1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mt6358.c -- mt6358 ALSA SoC audio codec driver 4 // 5 // Copyright (c) 2018 MediaTek Inc. 6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 8 #include <linux/platform_device.h> 9 #include <linux/module.h> 10 #include <linux/of_device.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/sched.h> 14 #include <linux/mfd/mt6397/core.h> 15 #include <linux/regulator/consumer.h> 16 17 #include <sound/soc.h> 18 #include <sound/tlv.h> 19 20 #include "mt6358.h" 21 22 enum { 23 AUDIO_ANALOG_VOLUME_HSOUTL, 24 AUDIO_ANALOG_VOLUME_HSOUTR, 25 AUDIO_ANALOG_VOLUME_HPOUTL, 26 AUDIO_ANALOG_VOLUME_HPOUTR, 27 AUDIO_ANALOG_VOLUME_LINEOUTL, 28 AUDIO_ANALOG_VOLUME_LINEOUTR, 29 AUDIO_ANALOG_VOLUME_MICAMP1, 30 AUDIO_ANALOG_VOLUME_MICAMP2, 31 AUDIO_ANALOG_VOLUME_TYPE_MAX 32 }; 33 34 enum { 35 MUX_ADC_L, 36 MUX_ADC_R, 37 MUX_PGA_L, 38 MUX_PGA_R, 39 MUX_MIC_TYPE, 40 MUX_HP_L, 41 MUX_HP_R, 42 MUX_NUM, 43 }; 44 45 enum { 46 DEVICE_HP, 47 DEVICE_LO, 48 DEVICE_RCV, 49 DEVICE_MIC1, 50 DEVICE_MIC2, 51 DEVICE_NUM 52 }; 53 54 /* Supply widget subseq */ 55 enum { 56 /* common */ 57 SUPPLY_SEQ_CLK_BUF, 58 SUPPLY_SEQ_AUD_GLB, 59 SUPPLY_SEQ_CLKSQ, 60 SUPPLY_SEQ_VOW_AUD_LPW, 61 SUPPLY_SEQ_AUD_VOW, 62 SUPPLY_SEQ_VOW_CLK, 63 SUPPLY_SEQ_VOW_LDO, 64 SUPPLY_SEQ_TOP_CK, 65 SUPPLY_SEQ_TOP_CK_LAST, 66 SUPPLY_SEQ_AUD_TOP, 67 SUPPLY_SEQ_AUD_TOP_LAST, 68 SUPPLY_SEQ_AFE, 69 /* capture */ 70 SUPPLY_SEQ_ADC_SUPPLY, 71 }; 72 73 enum { 74 CH_L = 0, 75 CH_R, 76 NUM_CH, 77 }; 78 79 #define REG_STRIDE 2 80 81 struct mt6358_priv { 82 struct device *dev; 83 struct regmap *regmap; 84 85 unsigned int dl_rate; 86 unsigned int ul_rate; 87 88 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX]; 89 unsigned int mux_select[MUX_NUM]; 90 91 int dev_counter[DEVICE_NUM]; 92 93 int mtkaif_protocol; 94 95 struct regulator *avdd_reg; 96 97 int wov_enabled; 98 }; 99 100 int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt, 101 int mtkaif_protocol) 102 { 103 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 104 105 priv->mtkaif_protocol = mtkaif_protocol; 106 return 0; 107 } 108 109 static void playback_gpio_set(struct mt6358_priv *priv) 110 { 111 /* set gpio mosi mode */ 112 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, 113 0x01f8, 0x01f8); 114 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET, 115 0xffff, 0x0249); 116 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, 117 0xffff, 0x0249); 118 } 119 120 static void playback_gpio_reset(struct mt6358_priv *priv) 121 { 122 /* set pad_aud_*_mosi to GPIO mode and dir input 123 * reason: 124 * pad_aud_dat_mosi*, because the pin is used as boot strap 125 * don't clean clk/sync, for mtkaif protocol 2 126 */ 127 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, 128 0x01f8, 0x01f8); 129 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, 130 0x01f8, 0x0000); 131 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, 132 0xf << 8, 0x0); 133 } 134 135 static void capture_gpio_set(struct mt6358_priv *priv) 136 { 137 /* set gpio miso mode */ 138 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, 139 0xffff, 0xffff); 140 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET, 141 0xffff, 0x0249); 142 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 143 0xffff, 0x0249); 144 } 145 146 static void capture_gpio_reset(struct mt6358_priv *priv) 147 { 148 /* set pad_aud_*_miso to GPIO mode and dir input 149 * reason: 150 * pad_aud_clk_miso, because when playback only the miso_clk 151 * will also have 26m, so will have power leak 152 * pad_aud_dat_miso*, because the pin is used as boot strap 153 */ 154 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, 155 0xffff, 0xffff); 156 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 157 0xffff, 0x0000); 158 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, 159 0xf << 12, 0x0); 160 } 161 162 /* use only when not govern by DAPM */ 163 static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable) 164 { 165 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 166 0x1 << RG_XO_AUDIO_EN_M_SFT, 167 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT); 168 return 0; 169 } 170 171 /* use only when not govern by DAPM */ 172 static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable) 173 { 174 /* audio clk source from internal dcxo */ 175 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, 176 RG_CLKSQ_IN_SEL_TEST_MASK_SFT, 177 0x0); 178 179 /* Enable/disable CLKSQ 26MHz */ 180 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, 181 RG_CLKSQ_EN_MASK_SFT, 182 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT); 183 return 0; 184 } 185 186 /* use only when not govern by DAPM */ 187 static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable) 188 { 189 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 190 RG_AUDGLB_PWRDN_VA28_MASK_SFT, 191 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT); 192 return 0; 193 } 194 195 /* use only when not govern by DAPM */ 196 static int mt6358_set_topck(struct mt6358_priv *priv, bool enable) 197 { 198 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, 199 0x0066, enable ? 0x0 : 0x66); 200 return 0; 201 } 202 203 static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv) 204 { 205 switch (priv->mtkaif_protocol) { 206 case MT6358_MTKAIF_PROTOCOL_2_CLK_P2: 207 /* MTKAIF TX format setting */ 208 regmap_update_bits(priv->regmap, 209 MT6358_AFE_ADDA_MTKAIF_CFG0, 210 0xffff, 0x0010); 211 /* enable aud_pad TX fifos */ 212 regmap_update_bits(priv->regmap, 213 MT6358_AFE_AUD_PAD_TOP, 214 0xff00, 0x3800); 215 regmap_update_bits(priv->regmap, 216 MT6358_AFE_AUD_PAD_TOP, 217 0xff00, 0x3900); 218 break; 219 case MT6358_MTKAIF_PROTOCOL_2: 220 /* MTKAIF TX format setting */ 221 regmap_update_bits(priv->regmap, 222 MT6358_AFE_ADDA_MTKAIF_CFG0, 223 0xffff, 0x0010); 224 /* enable aud_pad TX fifos */ 225 regmap_update_bits(priv->regmap, 226 MT6358_AFE_AUD_PAD_TOP, 227 0xff00, 0x3100); 228 break; 229 case MT6358_MTKAIF_PROTOCOL_1: 230 default: 231 /* MTKAIF TX format setting */ 232 regmap_update_bits(priv->regmap, 233 MT6358_AFE_ADDA_MTKAIF_CFG0, 234 0xffff, 0x0000); 235 /* enable aud_pad TX fifos */ 236 regmap_update_bits(priv->regmap, 237 MT6358_AFE_AUD_PAD_TOP, 238 0xff00, 0x3100); 239 break; 240 } 241 return 0; 242 } 243 244 static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv) 245 { 246 /* disable aud_pad TX fifos */ 247 regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP, 248 0xff00, 0x3000); 249 return 0; 250 } 251 252 int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt) 253 { 254 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 255 256 playback_gpio_set(priv); 257 capture_gpio_set(priv); 258 mt6358_mtkaif_tx_enable(priv); 259 260 mt6358_set_dcxo(priv, true); 261 mt6358_set_aud_global_bias(priv, true); 262 mt6358_set_clksq(priv, true); 263 mt6358_set_topck(priv, true); 264 265 /* set dat_miso_loopback on */ 266 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 267 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT, 268 1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT); 269 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 270 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT, 271 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); 272 return 0; 273 } 274 275 int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt) 276 { 277 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 278 279 /* set dat_miso_loopback off */ 280 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 281 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT, 282 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT); 283 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 284 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT, 285 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); 286 287 mt6358_set_topck(priv, false); 288 mt6358_set_clksq(priv, false); 289 mt6358_set_aud_global_bias(priv, false); 290 mt6358_set_dcxo(priv, false); 291 292 mt6358_mtkaif_tx_disable(priv); 293 playback_gpio_reset(priv); 294 capture_gpio_reset(priv); 295 return 0; 296 } 297 298 int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt, 299 int phase_1, int phase_2) 300 { 301 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 302 303 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 304 RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT, 305 phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT); 306 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 307 RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT, 308 phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT); 309 return 0; 310 } 311 312 /* dl pga gain */ 313 enum { 314 DL_GAIN_8DB = 0, 315 DL_GAIN_0DB = 8, 316 DL_GAIN_N_1DB = 9, 317 DL_GAIN_N_10DB = 18, 318 DL_GAIN_N_40DB = 0x1f, 319 }; 320 321 #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB) 322 #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB) 323 #define DL_GAIN_REG_MASK 0x0f9f 324 325 static void hp_zcd_disable(struct mt6358_priv *priv) 326 { 327 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000); 328 } 329 330 static void hp_main_output_ramp(struct mt6358_priv *priv, bool up) 331 { 332 int i = 0, stage = 0; 333 int target = 7; 334 335 /* Enable/Reduce HPL/R main output stage step by step */ 336 for (i = 0; i <= target; i++) { 337 stage = up ? i : target - i; 338 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 339 0x7 << 8, stage << 8); 340 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 341 0x7 << 11, stage << 11); 342 usleep_range(100, 150); 343 } 344 } 345 346 static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up) 347 { 348 int i = 0, stage = 0; 349 350 /* Reduce HP aux feedback loop gain step by step */ 351 for (i = 0; i <= 0xf; i++) { 352 stage = up ? i : 0xf - i; 353 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 354 0xf << 12, stage << 12); 355 usleep_range(100, 150); 356 } 357 } 358 359 static void hp_pull_down(struct mt6358_priv *priv, bool enable) 360 { 361 int i; 362 363 if (enable) { 364 for (i = 0x0; i <= 0x6; i++) { 365 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 366 0x7, i); 367 usleep_range(600, 700); 368 } 369 } else { 370 for (i = 0x6; i >= 0x1; i--) { 371 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 372 0x7, i); 373 usleep_range(600, 700); 374 } 375 } 376 } 377 378 static bool is_valid_hp_pga_idx(int reg_idx) 379 { 380 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) || 381 reg_idx == DL_GAIN_N_40DB; 382 } 383 384 static void headset_volume_ramp(struct mt6358_priv *priv, int from, int to) 385 { 386 int offset = 0, count = 0, reg_idx; 387 388 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to)) 389 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n", 390 __func__, from, to); 391 392 dev_info(priv->dev, "%s(), from %d, to %d\n", 393 __func__, from, to); 394 395 if (to > from) 396 offset = to - from; 397 else 398 offset = from - to; 399 400 while (offset >= 0) { 401 if (to > from) 402 reg_idx = from + count; 403 else 404 reg_idx = from - count; 405 406 if (is_valid_hp_pga_idx(reg_idx)) { 407 regmap_update_bits(priv->regmap, 408 MT6358_ZCD_CON2, 409 DL_GAIN_REG_MASK, 410 (reg_idx << 7) | reg_idx); 411 usleep_range(200, 300); 412 } 413 offset--; 414 count++; 415 } 416 } 417 418 static int mt6358_put_volsw(struct snd_kcontrol *kcontrol, 419 struct snd_ctl_elem_value *ucontrol) 420 { 421 struct snd_soc_component *component = 422 snd_soc_kcontrol_component(kcontrol); 423 struct mt6358_priv *priv = snd_soc_component_get_drvdata(component); 424 struct soc_mixer_control *mc = 425 (struct soc_mixer_control *)kcontrol->private_value; 426 unsigned int reg; 427 int ret; 428 429 ret = snd_soc_put_volsw(kcontrol, ucontrol); 430 if (ret < 0) 431 return ret; 432 433 switch (mc->reg) { 434 case MT6358_ZCD_CON2: 435 regmap_read(priv->regmap, MT6358_ZCD_CON2, ®); 436 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = 437 (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK; 438 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = 439 (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK; 440 break; 441 case MT6358_ZCD_CON1: 442 regmap_read(priv->regmap, MT6358_ZCD_CON1, ®); 443 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] = 444 (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK; 445 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] = 446 (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK; 447 break; 448 case MT6358_ZCD_CON3: 449 regmap_read(priv->regmap, MT6358_ZCD_CON3, ®); 450 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] = 451 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK; 452 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTR] = 453 (reg >> RG_AUDHSGAIN_SFT) & RG_AUDHSGAIN_MASK; 454 break; 455 case MT6358_AUDENC_ANA_CON0: 456 case MT6358_AUDENC_ANA_CON1: 457 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON0, ®); 458 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] = 459 (reg >> RG_AUDPREAMPLGAIN_SFT) & RG_AUDPREAMPLGAIN_MASK; 460 regmap_read(priv->regmap, MT6358_AUDENC_ANA_CON1, ®); 461 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] = 462 (reg >> RG_AUDPREAMPRGAIN_SFT) & RG_AUDPREAMPRGAIN_MASK; 463 break; 464 } 465 466 return ret; 467 } 468 469 static void mt6358_restore_pga(struct mt6358_priv *priv); 470 471 static int mt6358_enable_wov_phase2(struct mt6358_priv *priv) 472 { 473 /* analog */ 474 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 475 0xffff, 0x0000); 476 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); 477 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 478 0xffff, 0x0800); 479 mt6358_restore_pga(priv); 480 481 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9929); 482 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 483 0xffff, 0x0025); 484 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8, 485 0xffff, 0x0005); 486 487 /* digital */ 488 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, 489 0xffff, 0x0000); 490 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x0120); 491 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0xffff); 492 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0200); 493 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2424); 494 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xdbac); 495 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x029e); 496 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0000); 497 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, 498 0xffff, 0x0000); 499 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, 500 0xffff, 0x0451); 501 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0x68d1); 502 503 return 0; 504 } 505 506 static int mt6358_disable_wov_phase2(struct mt6358_priv *priv) 507 { 508 /* digital */ 509 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_TOP, 0xffff, 0xc000); 510 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_HPF_CFG0, 511 0xffff, 0x0450); 512 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_POSDIV_CFG0, 513 0xffff, 0x0c00); 514 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG5, 0xffff, 0x0100); 515 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG4, 0xffff, 0x006c); 516 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG3, 0xffff, 0xa879); 517 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG2, 0xffff, 0x2323); 518 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG1, 0xffff, 0x0400); 519 regmap_update_bits(priv->regmap, MT6358_AFE_VOW_CFG0, 0xffff, 0x0000); 520 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 0xffff, 0x02d8); 521 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, 522 0xffff, 0x0000); 523 524 /* analog */ 525 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON8, 526 0xffff, 0x0004); 527 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 528 0xffff, 0x0000); 529 regmap_update_bits(priv->regmap, MT6358_DCXO_CW13, 0xffff, 0x9829); 530 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 531 0xffff, 0x0000); 532 mt6358_restore_pga(priv); 533 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 0xffff, 0xa2b5); 534 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 535 0xffff, 0x0010); 536 537 return 0; 538 } 539 540 static int mt6358_get_wov(struct snd_kcontrol *kcontrol, 541 struct snd_ctl_elem_value *ucontrol) 542 { 543 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol); 544 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c); 545 546 ucontrol->value.integer.value[0] = priv->wov_enabled; 547 return 0; 548 } 549 550 static int mt6358_put_wov(struct snd_kcontrol *kcontrol, 551 struct snd_ctl_elem_value *ucontrol) 552 { 553 struct snd_soc_component *c = snd_soc_kcontrol_component(kcontrol); 554 struct mt6358_priv *priv = snd_soc_component_get_drvdata(c); 555 int enabled = ucontrol->value.integer.value[0]; 556 557 if (priv->wov_enabled != enabled) { 558 if (enabled) 559 mt6358_enable_wov_phase2(priv); 560 else 561 mt6358_disable_wov_phase2(priv); 562 563 priv->wov_enabled = enabled; 564 } 565 566 return 0; 567 } 568 569 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0); 570 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0); 571 572 static const struct snd_kcontrol_new mt6358_snd_controls[] = { 573 /* dl pga gain */ 574 SOC_DOUBLE_EXT_TLV("Headphone Volume", 575 MT6358_ZCD_CON2, 0, 7, 0x12, 1, 576 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv), 577 SOC_DOUBLE_EXT_TLV("Lineout Volume", 578 MT6358_ZCD_CON1, 0, 7, 0x12, 1, 579 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv), 580 SOC_SINGLE_EXT_TLV("Handset Volume", 581 MT6358_ZCD_CON3, 0, 0x12, 1, 582 snd_soc_get_volsw, mt6358_put_volsw, playback_tlv), 583 /* ul pga gain */ 584 SOC_DOUBLE_R_EXT_TLV("PGA Volume", 585 MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1, 586 8, 4, 0, 587 snd_soc_get_volsw, mt6358_put_volsw, pga_tlv), 588 589 SOC_SINGLE_BOOL_EXT("Wake-on-Voice Phase2 Switch", 0, 590 mt6358_get_wov, mt6358_put_wov), 591 }; 592 593 /* MUX */ 594 /* LOL MUX */ 595 static const char * const lo_in_mux_map[] = { 596 "Open", "Mute", "Playback", "Test Mode" 597 }; 598 599 static int lo_in_mux_map_value[] = { 600 0x0, 0x1, 0x2, 0x3, 601 }; 602 603 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum, 604 MT6358_AUDDEC_ANA_CON7, 605 RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT, 606 RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK, 607 lo_in_mux_map, 608 lo_in_mux_map_value); 609 610 static const struct snd_kcontrol_new lo_in_mux_control = 611 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum); 612 613 /*HP MUX */ 614 enum { 615 HP_MUX_OPEN = 0, 616 HP_MUX_HPSPK, 617 HP_MUX_HP, 618 HP_MUX_TEST_MODE, 619 HP_MUX_HP_IMPEDANCE, 620 HP_MUX_MASK = 0x7, 621 }; 622 623 static const char * const hp_in_mux_map[] = { 624 "Open", 625 "LoudSPK Playback", 626 "Audio Playback", 627 "Test Mode", 628 "HP Impedance", 629 "undefined1", 630 "undefined2", 631 "undefined3", 632 }; 633 634 static int hp_in_mux_map_value[] = { 635 HP_MUX_OPEN, 636 HP_MUX_HPSPK, 637 HP_MUX_HP, 638 HP_MUX_TEST_MODE, 639 HP_MUX_HP_IMPEDANCE, 640 HP_MUX_OPEN, 641 HP_MUX_OPEN, 642 HP_MUX_OPEN, 643 }; 644 645 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum, 646 SND_SOC_NOPM, 647 0, 648 HP_MUX_MASK, 649 hp_in_mux_map, 650 hp_in_mux_map_value); 651 652 static const struct snd_kcontrol_new hpl_in_mux_control = 653 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum); 654 655 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum, 656 SND_SOC_NOPM, 657 0, 658 HP_MUX_MASK, 659 hp_in_mux_map, 660 hp_in_mux_map_value); 661 662 static const struct snd_kcontrol_new hpr_in_mux_control = 663 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum); 664 665 /* RCV MUX */ 666 enum { 667 RCV_MUX_OPEN = 0, 668 RCV_MUX_MUTE, 669 RCV_MUX_VOICE_PLAYBACK, 670 RCV_MUX_TEST_MODE, 671 RCV_MUX_MASK = 0x3, 672 }; 673 674 static const char * const rcv_in_mux_map[] = { 675 "Open", "Mute", "Voice Playback", "Test Mode" 676 }; 677 678 static int rcv_in_mux_map_value[] = { 679 RCV_MUX_OPEN, 680 RCV_MUX_MUTE, 681 RCV_MUX_VOICE_PLAYBACK, 682 RCV_MUX_TEST_MODE, 683 }; 684 685 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum, 686 SND_SOC_NOPM, 687 0, 688 RCV_MUX_MASK, 689 rcv_in_mux_map, 690 rcv_in_mux_map_value); 691 692 static const struct snd_kcontrol_new rcv_in_mux_control = 693 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum); 694 695 /* DAC In MUX */ 696 static const char * const dac_in_mux_map[] = { 697 "Normal Path", "Sgen" 698 }; 699 700 static int dac_in_mux_map_value[] = { 701 0x0, 0x1, 702 }; 703 704 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum, 705 MT6358_AFE_TOP_CON0, 706 DL_SINE_ON_SFT, 707 DL_SINE_ON_MASK, 708 dac_in_mux_map, 709 dac_in_mux_map_value); 710 711 static const struct snd_kcontrol_new dac_in_mux_control = 712 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum); 713 714 /* AIF Out MUX */ 715 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum, 716 MT6358_AFE_TOP_CON0, 717 UL_SINE_ON_SFT, 718 UL_SINE_ON_MASK, 719 dac_in_mux_map, 720 dac_in_mux_map_value); 721 722 static const struct snd_kcontrol_new aif_out_mux_control = 723 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum); 724 725 /* Mic Type MUX */ 726 enum { 727 MIC_TYPE_MUX_IDLE = 0, 728 MIC_TYPE_MUX_ACC, 729 MIC_TYPE_MUX_DMIC, 730 MIC_TYPE_MUX_DCC, 731 MIC_TYPE_MUX_DCC_ECM_DIFF, 732 MIC_TYPE_MUX_DCC_ECM_SINGLE, 733 MIC_TYPE_MUX_MASK = 0x7, 734 }; 735 736 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \ 737 (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \ 738 (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE) 739 740 static const char * const mic_type_mux_map[] = { 741 "Idle", 742 "ACC", 743 "DMIC", 744 "DCC", 745 "DCC_ECM_DIFF", 746 "DCC_ECM_SINGLE", 747 }; 748 749 static int mic_type_mux_map_value[] = { 750 MIC_TYPE_MUX_IDLE, 751 MIC_TYPE_MUX_ACC, 752 MIC_TYPE_MUX_DMIC, 753 MIC_TYPE_MUX_DCC, 754 MIC_TYPE_MUX_DCC_ECM_DIFF, 755 MIC_TYPE_MUX_DCC_ECM_SINGLE, 756 }; 757 758 static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum, 759 SND_SOC_NOPM, 760 0, 761 MIC_TYPE_MUX_MASK, 762 mic_type_mux_map, 763 mic_type_mux_map_value); 764 765 static const struct snd_kcontrol_new mic_type_mux_control = 766 SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum); 767 768 /* ADC L MUX */ 769 enum { 770 ADC_MUX_IDLE = 0, 771 ADC_MUX_AIN0, 772 ADC_MUX_PREAMPLIFIER, 773 ADC_MUX_IDLE1, 774 ADC_MUX_MASK = 0x3, 775 }; 776 777 static const char * const adc_left_mux_map[] = { 778 "Idle", "AIN0", "Left Preamplifier", "Idle_1" 779 }; 780 781 static int adc_mux_map_value[] = { 782 ADC_MUX_IDLE, 783 ADC_MUX_AIN0, 784 ADC_MUX_PREAMPLIFIER, 785 ADC_MUX_IDLE1, 786 }; 787 788 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum, 789 SND_SOC_NOPM, 790 0, 791 ADC_MUX_MASK, 792 adc_left_mux_map, 793 adc_mux_map_value); 794 795 static const struct snd_kcontrol_new adc_left_mux_control = 796 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum); 797 798 /* ADC R MUX */ 799 static const char * const adc_right_mux_map[] = { 800 "Idle", "AIN0", "Right Preamplifier", "Idle_1" 801 }; 802 803 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum, 804 SND_SOC_NOPM, 805 0, 806 ADC_MUX_MASK, 807 adc_right_mux_map, 808 adc_mux_map_value); 809 810 static const struct snd_kcontrol_new adc_right_mux_control = 811 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum); 812 813 /* PGA L MUX */ 814 enum { 815 PGA_MUX_NONE = 0, 816 PGA_MUX_AIN0, 817 PGA_MUX_AIN1, 818 PGA_MUX_AIN2, 819 PGA_MUX_MASK = 0x3, 820 }; 821 822 static const char * const pga_mux_map[] = { 823 "None", "AIN0", "AIN1", "AIN2" 824 }; 825 826 static int pga_mux_map_value[] = { 827 PGA_MUX_NONE, 828 PGA_MUX_AIN0, 829 PGA_MUX_AIN1, 830 PGA_MUX_AIN2, 831 }; 832 833 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum, 834 SND_SOC_NOPM, 835 0, 836 PGA_MUX_MASK, 837 pga_mux_map, 838 pga_mux_map_value); 839 840 static const struct snd_kcontrol_new pga_left_mux_control = 841 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum); 842 843 /* PGA R MUX */ 844 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum, 845 SND_SOC_NOPM, 846 0, 847 PGA_MUX_MASK, 848 pga_mux_map, 849 pga_mux_map_value); 850 851 static const struct snd_kcontrol_new pga_right_mux_control = 852 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum); 853 854 static int mt_clksq_event(struct snd_soc_dapm_widget *w, 855 struct snd_kcontrol *kcontrol, 856 int event) 857 { 858 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 859 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 860 861 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 862 863 switch (event) { 864 case SND_SOC_DAPM_PRE_PMU: 865 /* audio clk source from internal dcxo */ 866 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, 867 RG_CLKSQ_IN_SEL_TEST_MASK_SFT, 868 0x0); 869 break; 870 default: 871 break; 872 } 873 874 return 0; 875 } 876 877 static int mt_sgen_event(struct snd_soc_dapm_widget *w, 878 struct snd_kcontrol *kcontrol, 879 int event) 880 { 881 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 882 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 883 884 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 885 886 switch (event) { 887 case SND_SOC_DAPM_PRE_PMU: 888 /* sdm audio fifo clock power on */ 889 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); 890 /* scrambler clock on enable */ 891 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); 892 /* sdm power on */ 893 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); 894 /* sdm fifo enable */ 895 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); 896 897 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0, 898 0xff3f, 899 0x0000); 900 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1, 901 0xffff, 902 0x0001); 903 break; 904 case SND_SOC_DAPM_POST_PMD: 905 /* DL scrambler disabling sequence */ 906 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); 907 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); 908 break; 909 default: 910 break; 911 } 912 913 return 0; 914 } 915 916 static int mt_aif_in_event(struct snd_soc_dapm_widget *w, 917 struct snd_kcontrol *kcontrol, 918 int event) 919 { 920 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 921 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 922 923 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n", 924 __func__, event, priv->dl_rate); 925 926 switch (event) { 927 case SND_SOC_DAPM_PRE_PMU: 928 playback_gpio_set(priv); 929 930 /* sdm audio fifo clock power on */ 931 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); 932 /* scrambler clock on enable */ 933 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); 934 /* sdm power on */ 935 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); 936 /* sdm fifo enable */ 937 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); 938 break; 939 case SND_SOC_DAPM_POST_PMD: 940 /* DL scrambler disabling sequence */ 941 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); 942 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); 943 944 playback_gpio_reset(priv); 945 break; 946 default: 947 break; 948 } 949 950 return 0; 951 } 952 953 static int mtk_hp_enable(struct mt6358_priv *priv) 954 { 955 /* Pull-down HPL/R to AVSS28_AUD */ 956 hp_pull_down(priv, true); 957 /* release HP CMFB gate rstb */ 958 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 959 0x1 << 6, 0x1 << 6); 960 961 /* Reduce ESD resistance of AU_REFN */ 962 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 963 964 /* Set HPR/HPL gain as minimum (~ -40dB) */ 965 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG); 966 967 /* Turn on DA_600K_NCP_VA18 */ 968 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 969 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 970 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 971 /* Toggle RG_DIVCKS_CHG */ 972 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 973 /* Set NCP soft start mode as default mode: 100us */ 974 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 975 /* Enable NCP */ 976 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 977 usleep_range(250, 270); 978 979 /* Enable cap-less LDOs (1.5V) */ 980 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 981 0x1055, 0x1055); 982 /* Enable NV regulator (-1.2V) */ 983 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 984 usleep_range(100, 120); 985 986 /* Disable AUD_ZCD */ 987 hp_zcd_disable(priv); 988 989 /* Disable headphone short-circuit protection */ 990 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); 991 992 /* Enable IBIST */ 993 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 994 995 /* Set HP DR bias current optimization, 010: 6uA */ 996 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 997 /* Set HP & ZCD bias current optimization */ 998 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 999 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1000 /* Set HPP/N STB enhance circuits */ 1001 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); 1002 1003 /* Enable HP aux output stage */ 1004 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c); 1005 /* Enable HP aux feedback loop */ 1006 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c); 1007 /* Enable HP aux CMFB loop */ 1008 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); 1009 /* Enable HP driver bias circuits */ 1010 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); 1011 /* Enable HP driver core circuits */ 1012 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); 1013 /* Short HP main output to HP aux output stage */ 1014 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc); 1015 1016 /* Enable HP main CMFB loop */ 1017 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); 1018 /* Disable HP aux CMFB loop */ 1019 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); 1020 1021 /* Select CMFB resistor bulk to AC mode */ 1022 /* Selec HS/LO cap size (6.5pF default) */ 1023 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 1024 1025 /* Enable HP main output stage */ 1026 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff); 1027 /* Enable HPR/L main output stage step by step */ 1028 hp_main_output_ramp(priv, true); 1029 1030 /* Reduce HP aux feedback loop gain */ 1031 hp_aux_feedback_loop_gain_ramp(priv, true); 1032 /* Disable HP aux feedback loop */ 1033 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 1034 1035 /* apply volume setting */ 1036 headset_volume_ramp(priv, 1037 DL_GAIN_N_10DB, 1038 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); 1039 1040 /* Disable HP aux output stage */ 1041 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 1042 /* Unshort HP main output to HP aux output stage */ 1043 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03); 1044 usleep_range(100, 120); 1045 1046 /* Enable AUD_CLK */ 1047 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); 1048 /* Enable Audio DAC */ 1049 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff); 1050 /* Enable low-noise mode of DAC */ 1051 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201); 1052 usleep_range(100, 120); 1053 1054 /* Switch HPL MUX to audio DAC */ 1055 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff); 1056 /* Switch HPR MUX to audio DAC */ 1057 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff); 1058 1059 /* Disable Pull-down HPL/R to AVSS28_AUD */ 1060 hp_pull_down(priv, false); 1061 1062 return 0; 1063 } 1064 1065 static int mtk_hp_disable(struct mt6358_priv *priv) 1066 { 1067 /* Pull-down HPL/R to AVSS28_AUD */ 1068 hp_pull_down(priv, true); 1069 1070 /* HPR/HPL mux to open */ 1071 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1072 0x0f00, 0x0000); 1073 1074 /* Disable low-noise mode of DAC */ 1075 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1076 0x0001, 0x0000); 1077 1078 /* Disable Audio DAC */ 1079 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1080 0x000f, 0x0000); 1081 1082 /* Disable AUD_CLK */ 1083 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); 1084 1085 /* Short HP main output to HP aux output stage */ 1086 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 1087 /* Enable HP aux output stage */ 1088 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 1089 1090 /* decrease HPL/R gain to normal gain step by step */ 1091 headset_volume_ramp(priv, 1092 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], 1093 DL_GAIN_N_40DB); 1094 1095 /* Enable HP aux feedback loop */ 1096 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); 1097 1098 /* Reduce HP aux feedback loop gain */ 1099 hp_aux_feedback_loop_gain_ramp(priv, false); 1100 1101 /* decrease HPR/L main output stage step by step */ 1102 hp_main_output_ramp(priv, false); 1103 1104 /* Disable HP main output stage */ 1105 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); 1106 1107 /* Enable HP aux CMFB loop */ 1108 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); 1109 1110 /* Disable HP main CMFB loop */ 1111 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); 1112 1113 /* Unshort HP main output to HP aux output stage */ 1114 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1115 0x3 << 6, 0x0); 1116 1117 /* Disable HP driver core circuits */ 1118 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1119 0x3 << 4, 0x0); 1120 1121 /* Disable HP driver bias circuits */ 1122 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1123 0x3 << 6, 0x0); 1124 1125 /* Disable HP aux CMFB loop */ 1126 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); 1127 1128 /* Disable HP aux feedback loop */ 1129 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1130 0x3 << 4, 0x0); 1131 1132 /* Disable HP aux output stage */ 1133 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1134 0x3 << 2, 0x0); 1135 1136 /* Disable IBIST */ 1137 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1138 0x1 << 8, 0x1 << 8); 1139 1140 /* Disable NV regulator (-1.2V) */ 1141 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); 1142 /* Disable cap-less LDOs (1.5V) */ 1143 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1144 0x1055, 0x0); 1145 /* Disable NCP */ 1146 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 1147 0x1, 0x1); 1148 1149 /* Increase ESD resistance of AU_REFN */ 1150 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2, 1151 0x1 << 14, 0x0); 1152 1153 /* Set HP CMFB gate rstb */ 1154 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1155 0x1 << 6, 0x0); 1156 /* disable Pull-down HPL/R to AVSS28_AUD */ 1157 hp_pull_down(priv, false); 1158 1159 return 0; 1160 } 1161 1162 static int mtk_hp_spk_enable(struct mt6358_priv *priv) 1163 { 1164 /* Pull-down HPL/R to AVSS28_AUD */ 1165 hp_pull_down(priv, true); 1166 /* release HP CMFB gate rstb */ 1167 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1168 0x1 << 6, 0x1 << 6); 1169 1170 /* Reduce ESD resistance of AU_REFN */ 1171 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 1172 1173 /* Set HPR/HPL gain to -10dB */ 1174 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG); 1175 1176 /* Turn on DA_600K_NCP_VA18 */ 1177 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 1178 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 1179 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 1180 /* Toggle RG_DIVCKS_CHG */ 1181 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 1182 /* Set NCP soft start mode as default mode: 100us */ 1183 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 1184 /* Enable NCP */ 1185 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 1186 usleep_range(250, 270); 1187 1188 /* Enable cap-less LDOs (1.5V) */ 1189 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1190 0x1055, 0x1055); 1191 /* Enable NV regulator (-1.2V) */ 1192 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 1193 usleep_range(100, 120); 1194 1195 /* Disable AUD_ZCD */ 1196 hp_zcd_disable(priv); 1197 1198 /* Disable headphone short-circuit protection */ 1199 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); 1200 1201 /* Enable IBIST */ 1202 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1203 1204 /* Set HP DR bias current optimization, 010: 6uA */ 1205 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 1206 /* Set HP & ZCD bias current optimization */ 1207 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1208 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1209 /* Set HPP/N STB enhance circuits */ 1210 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); 1211 1212 /* Disable Pull-down HPL/R to AVSS28_AUD */ 1213 hp_pull_down(priv, false); 1214 1215 /* Enable HP driver bias circuits */ 1216 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); 1217 /* Enable HP driver core circuits */ 1218 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); 1219 /* Enable HP main CMFB loop */ 1220 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); 1221 1222 /* Select CMFB resistor bulk to AC mode */ 1223 /* Selec HS/LO cap size (6.5pF default) */ 1224 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 1225 1226 /* Enable HP main output stage */ 1227 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003); 1228 /* Enable HPR/L main output stage step by step */ 1229 hp_main_output_ramp(priv, true); 1230 1231 /* Set LO gain as minimum (~ -40dB) */ 1232 regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG); 1233 /* apply volume setting */ 1234 headset_volume_ramp(priv, 1235 DL_GAIN_N_10DB, 1236 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); 1237 1238 /* Set LO STB enhance circuits */ 1239 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110); 1240 /* Enable LO driver bias circuits */ 1241 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112); 1242 /* Enable LO driver core circuits */ 1243 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113); 1244 1245 /* Set LOL gain to normal gain step by step */ 1246 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1247 RG_AUDLOLGAIN_MASK_SFT, 1248 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] << 1249 RG_AUDLOLGAIN_SFT); 1250 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1251 RG_AUDLORGAIN_MASK_SFT, 1252 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] << 1253 RG_AUDLORGAIN_SFT); 1254 1255 /* Enable AUD_CLK */ 1256 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); 1257 /* Enable Audio DAC */ 1258 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9); 1259 /* Enable low-noise mode of DAC */ 1260 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201); 1261 /* Switch LOL MUX to audio DAC */ 1262 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b); 1263 /* Switch HPL/R MUX to Line-out */ 1264 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9); 1265 1266 return 0; 1267 } 1268 1269 static int mtk_hp_spk_disable(struct mt6358_priv *priv) 1270 { 1271 /* HPR/HPL mux to open */ 1272 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1273 0x0f00, 0x0000); 1274 /* LOL mux to open */ 1275 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1276 0x3 << 2, 0x0000); 1277 1278 /* Disable Audio DAC */ 1279 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1280 0x000f, 0x0000); 1281 1282 /* Disable AUD_CLK */ 1283 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); 1284 1285 /* decrease HPL/R gain to normal gain step by step */ 1286 headset_volume_ramp(priv, 1287 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], 1288 DL_GAIN_N_40DB); 1289 1290 /* decrease LOL gain to minimum gain step by step */ 1291 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1292 DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG); 1293 1294 /* decrease HPR/L main output stage step by step */ 1295 hp_main_output_ramp(priv, false); 1296 1297 /* Disable HP main output stage */ 1298 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); 1299 1300 /* Short HP main output to HP aux output stage */ 1301 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 1302 /* Enable HP aux output stage */ 1303 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 1304 1305 /* Enable HP aux feedback loop */ 1306 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); 1307 1308 /* Reduce HP aux feedback loop gain */ 1309 hp_aux_feedback_loop_gain_ramp(priv, false); 1310 1311 /* Disable HP driver core circuits */ 1312 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1313 0x3 << 4, 0x0); 1314 /* Disable LO driver core circuits */ 1315 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1316 0x1, 0x0); 1317 1318 /* Disable HP driver bias circuits */ 1319 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1320 0x3 << 6, 0x0); 1321 /* Disable LO driver bias circuits */ 1322 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1323 0x1 << 1, 0x0); 1324 1325 /* Disable HP aux CMFB loop */ 1326 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1327 0xff << 8, 0x0000); 1328 1329 /* Disable IBIST */ 1330 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1331 0x1 << 8, 0x1 << 8); 1332 /* Disable NV regulator (-1.2V) */ 1333 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); 1334 /* Disable cap-less LDOs (1.5V) */ 1335 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0); 1336 /* Disable NCP */ 1337 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1); 1338 1339 /* Set HP CMFB gate rstb */ 1340 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1341 0x1 << 6, 0x0); 1342 /* disable Pull-down HPL/R to AVSS28_AUD */ 1343 hp_pull_down(priv, false); 1344 1345 return 0; 1346 } 1347 1348 static int mt_hp_event(struct snd_soc_dapm_widget *w, 1349 struct snd_kcontrol *kcontrol, 1350 int event) 1351 { 1352 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1353 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1354 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1355 int device = DEVICE_HP; 1356 1357 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", 1358 __func__, 1359 event, 1360 priv->dev_counter[device], 1361 mux); 1362 1363 switch (event) { 1364 case SND_SOC_DAPM_PRE_PMU: 1365 priv->dev_counter[device]++; 1366 if (priv->dev_counter[device] > 1) 1367 break; /* already enabled, do nothing */ 1368 else if (priv->dev_counter[device] <= 0) 1369 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n", 1370 __func__, 1371 priv->dev_counter[device]); 1372 1373 priv->mux_select[MUX_HP_L] = mux; 1374 1375 if (mux == HP_MUX_HP) 1376 mtk_hp_enable(priv); 1377 else if (mux == HP_MUX_HPSPK) 1378 mtk_hp_spk_enable(priv); 1379 break; 1380 case SND_SOC_DAPM_PRE_PMD: 1381 priv->dev_counter[device]--; 1382 if (priv->dev_counter[device] > 0) { 1383 break; /* still being used, don't close */ 1384 } else if (priv->dev_counter[device] < 0) { 1385 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n", 1386 __func__, 1387 priv->dev_counter[device]); 1388 priv->dev_counter[device] = 0; 1389 break; 1390 } 1391 1392 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP) 1393 mtk_hp_disable(priv); 1394 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK) 1395 mtk_hp_spk_disable(priv); 1396 1397 priv->mux_select[MUX_HP_L] = mux; 1398 break; 1399 default: 1400 break; 1401 } 1402 1403 return 0; 1404 } 1405 1406 static int mt_rcv_event(struct snd_soc_dapm_widget *w, 1407 struct snd_kcontrol *kcontrol, 1408 int event) 1409 { 1410 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1411 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1412 1413 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n", 1414 __func__, 1415 event, 1416 dapm_kcontrol_get_value(w->kcontrols[0])); 1417 1418 switch (event) { 1419 case SND_SOC_DAPM_PRE_PMU: 1420 /* Reduce ESD resistance of AU_REFN */ 1421 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 1422 1423 /* Turn on DA_600K_NCP_VA18 */ 1424 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 1425 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 1426 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 1427 /* Toggle RG_DIVCKS_CHG */ 1428 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 1429 /* Set NCP soft start mode as default mode: 100us */ 1430 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 1431 /* Enable NCP */ 1432 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 1433 usleep_range(250, 270); 1434 1435 /* Enable cap-less LDOs (1.5V) */ 1436 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1437 0x1055, 0x1055); 1438 /* Enable NV regulator (-1.2V) */ 1439 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 1440 usleep_range(100, 120); 1441 1442 /* Disable AUD_ZCD */ 1443 hp_zcd_disable(priv); 1444 1445 /* Disable handset short-circuit protection */ 1446 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010); 1447 1448 /* Enable IBIST */ 1449 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1450 /* Set HP DR bias current optimization, 010: 6uA */ 1451 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 1452 /* Set HP & ZCD bias current optimization */ 1453 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1454 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1455 /* Set HS STB enhance circuits */ 1456 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090); 1457 1458 /* Disable HP main CMFB loop */ 1459 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); 1460 /* Select CMFB resistor bulk to AC mode */ 1461 /* Selec HS/LO cap size (6.5pF default) */ 1462 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 1463 1464 /* Enable HS driver bias circuits */ 1465 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092); 1466 /* Enable HS driver core circuits */ 1467 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093); 1468 1469 /* Enable AUD_CLK */ 1470 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1471 0x1, 0x1); 1472 1473 /* Enable Audio DAC */ 1474 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009); 1475 /* Enable low-noise mode of DAC */ 1476 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001); 1477 /* Switch HS MUX to audio DAC */ 1478 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b); 1479 break; 1480 case SND_SOC_DAPM_PRE_PMD: 1481 /* HS mux to open */ 1482 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1483 RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT, 1484 RCV_MUX_OPEN); 1485 1486 /* Disable Audio DAC */ 1487 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1488 0x000f, 0x0000); 1489 1490 /* Disable AUD_CLK */ 1491 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1492 0x1, 0x0); 1493 1494 /* decrease HS gain to minimum gain step by step */ 1495 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB); 1496 1497 /* Disable HS driver core circuits */ 1498 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1499 0x1, 0x0); 1500 1501 /* Disable HS driver bias circuits */ 1502 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1503 0x1 << 1, 0x0000); 1504 1505 /* Disable HP aux CMFB loop */ 1506 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1507 0xff << 8, 0x0); 1508 1509 /* Enable HP main CMFB Switch */ 1510 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1511 0xff << 8, 0x2 << 8); 1512 1513 /* Disable IBIST */ 1514 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1515 0x1 << 8, 0x1 << 8); 1516 1517 /* Disable NV regulator (-1.2V) */ 1518 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 1519 0x1, 0x0); 1520 /* Disable cap-less LDOs (1.5V) */ 1521 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1522 0x1055, 0x0); 1523 /* Disable NCP */ 1524 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 1525 0x1, 0x1); 1526 break; 1527 default: 1528 break; 1529 } 1530 1531 return 0; 1532 } 1533 1534 static int mt_aif_out_event(struct snd_soc_dapm_widget *w, 1535 struct snd_kcontrol *kcontrol, 1536 int event) 1537 { 1538 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1539 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1540 1541 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", 1542 __func__, event, priv->ul_rate); 1543 1544 switch (event) { 1545 case SND_SOC_DAPM_PRE_PMU: 1546 capture_gpio_set(priv); 1547 break; 1548 case SND_SOC_DAPM_POST_PMD: 1549 capture_gpio_reset(priv); 1550 break; 1551 default: 1552 break; 1553 } 1554 1555 return 0; 1556 } 1557 1558 static int mt_adc_supply_event(struct snd_soc_dapm_widget *w, 1559 struct snd_kcontrol *kcontrol, 1560 int event) 1561 { 1562 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1563 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1564 1565 dev_dbg(priv->dev, "%s(), event 0x%x\n", 1566 __func__, event); 1567 1568 switch (event) { 1569 case SND_SOC_DAPM_PRE_PMU: 1570 /* Enable audio ADC CLKGEN */ 1571 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1572 0x1 << 5, 0x1 << 5); 1573 /* ADC CLK from CLKGEN (13MHz) */ 1574 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 1575 0x0000); 1576 /* Enable LCLDO_ENC 1P8V */ 1577 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1578 0x2500, 0x0100); 1579 /* LCLDO_ENC remote sense */ 1580 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1581 0x2500, 0x2500); 1582 break; 1583 case SND_SOC_DAPM_POST_PMD: 1584 /* LCLDO_ENC remote sense off */ 1585 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1586 0x2500, 0x0100); 1587 /* disable LCLDO_ENC 1P8V */ 1588 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1589 0x2500, 0x0000); 1590 1591 /* ADC CLK from CLKGEN (13MHz) */ 1592 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000); 1593 /* disable audio ADC CLKGEN */ 1594 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1595 0x1 << 5, 0x0 << 5); 1596 break; 1597 default: 1598 break; 1599 } 1600 1601 return 0; 1602 } 1603 1604 static int mt6358_amic_enable(struct mt6358_priv *priv) 1605 { 1606 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; 1607 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; 1608 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; 1609 1610 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", 1611 __func__, mic_type, mux_pga_l, mux_pga_r); 1612 1613 if (IS_DCC_BASE(mic_type)) { 1614 /* DCC 50k CLK (from 26M) */ 1615 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1616 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1617 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); 1618 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061); 1619 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100); 1620 } 1621 1622 /* mic bias 0 */ 1623 if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 || 1624 mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) { 1625 switch (mic_type) { 1626 case MIC_TYPE_MUX_DCC_ECM_DIFF: 1627 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1628 0xff00, 0x7700); 1629 break; 1630 case MIC_TYPE_MUX_DCC_ECM_SINGLE: 1631 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1632 0xff00, 0x1100); 1633 break; 1634 default: 1635 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1636 0xff00, 0x0000); 1637 break; 1638 } 1639 /* Enable MICBIAS0, MISBIAS0 = 1P9V */ 1640 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1641 0xff, 0x21); 1642 } 1643 1644 /* mic bias 1 */ 1645 if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) { 1646 /* Enable MICBIAS1, MISBIAS1 = 2P6V */ 1647 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE) 1648 regmap_write(priv->regmap, 1649 MT6358_AUDENC_ANA_CON10, 0x0161); 1650 else 1651 regmap_write(priv->regmap, 1652 MT6358_AUDENC_ANA_CON10, 0x0061); 1653 } 1654 1655 if (IS_DCC_BASE(mic_type)) { 1656 /* Audio L/R preamplifier DCC precharge */ 1657 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1658 0xf8ff, 0x0004); 1659 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1660 0xf8ff, 0x0004); 1661 } else { 1662 /* reset reg */ 1663 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1664 0xf8ff, 0x0000); 1665 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1666 0xf8ff, 0x0000); 1667 } 1668 1669 if (mux_pga_l != PGA_MUX_NONE) { 1670 /* L preamplifier input sel */ 1671 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1672 RG_AUDPREAMPLINPUTSEL_MASK_SFT, 1673 mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT); 1674 1675 /* L preamplifier enable */ 1676 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1677 RG_AUDPREAMPLON_MASK_SFT, 1678 0x1 << RG_AUDPREAMPLON_SFT); 1679 1680 if (IS_DCC_BASE(mic_type)) { 1681 /* L preamplifier DCCEN */ 1682 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1683 RG_AUDPREAMPLDCCEN_MASK_SFT, 1684 0x1 << RG_AUDPREAMPLDCCEN_SFT); 1685 } 1686 1687 /* L ADC input sel : L PGA. Enable audio L ADC */ 1688 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1689 RG_AUDADCLINPUTSEL_MASK_SFT, 1690 ADC_MUX_PREAMPLIFIER << 1691 RG_AUDADCLINPUTSEL_SFT); 1692 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1693 RG_AUDADCLPWRUP_MASK_SFT, 1694 0x1 << RG_AUDADCLPWRUP_SFT); 1695 } 1696 1697 if (mux_pga_r != PGA_MUX_NONE) { 1698 /* R preamplifier input sel */ 1699 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1700 RG_AUDPREAMPRINPUTSEL_MASK_SFT, 1701 mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT); 1702 1703 /* R preamplifier enable */ 1704 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1705 RG_AUDPREAMPRON_MASK_SFT, 1706 0x1 << RG_AUDPREAMPRON_SFT); 1707 1708 if (IS_DCC_BASE(mic_type)) { 1709 /* R preamplifier DCCEN */ 1710 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1711 RG_AUDPREAMPRDCCEN_MASK_SFT, 1712 0x1 << RG_AUDPREAMPRDCCEN_SFT); 1713 } 1714 1715 /* R ADC input sel : R PGA. Enable audio R ADC */ 1716 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1717 RG_AUDADCRINPUTSEL_MASK_SFT, 1718 ADC_MUX_PREAMPLIFIER << 1719 RG_AUDADCRINPUTSEL_SFT); 1720 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1721 RG_AUDADCRPWRUP_MASK_SFT, 1722 0x1 << RG_AUDADCRPWRUP_SFT); 1723 } 1724 1725 if (IS_DCC_BASE(mic_type)) { 1726 usleep_range(100, 150); 1727 /* Audio L preamplifier DCC precharge off */ 1728 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1729 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0); 1730 /* Audio R preamplifier DCC precharge off */ 1731 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1732 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0); 1733 1734 /* Short body to ground in PGA */ 1735 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3, 1736 0x1 << 12, 0x0); 1737 } 1738 1739 /* here to set digital part */ 1740 mt6358_mtkaif_tx_enable(priv); 1741 1742 /* UL dmic setting off */ 1743 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000); 1744 1745 /* UL turn on */ 1746 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001); 1747 1748 return 0; 1749 } 1750 1751 static void mt6358_amic_disable(struct mt6358_priv *priv) 1752 { 1753 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; 1754 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; 1755 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; 1756 1757 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", 1758 __func__, mic_type, mux_pga_l, mux_pga_r); 1759 1760 /* UL turn off */ 1761 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 1762 0x0001, 0x0000); 1763 1764 /* disable aud_pad TX fifos */ 1765 mt6358_mtkaif_tx_disable(priv); 1766 1767 /* L ADC input sel : off, disable L ADC */ 1768 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1769 0xf000, 0x0000); 1770 /* L preamplifier DCCEN */ 1771 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1772 0x1 << 1, 0x0); 1773 /* L preamplifier input sel : off, L PGA 0 dB gain */ 1774 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1775 0xfffb, 0x0000); 1776 1777 /* disable L preamplifier DCC precharge */ 1778 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1779 0x1 << 2, 0x0); 1780 1781 /* R ADC input sel : off, disable R ADC */ 1782 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1783 0xf000, 0x0000); 1784 /* R preamplifier DCCEN */ 1785 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1786 0x1 << 1, 0x0); 1787 /* R preamplifier input sel : off, R PGA 0 dB gain */ 1788 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1789 0x0ffb, 0x0000); 1790 1791 /* disable R preamplifier DCC precharge */ 1792 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1793 0x1 << 2, 0x0); 1794 1795 /* mic bias */ 1796 /* Disable MICBIAS0, MISBIAS0 = 1P7V */ 1797 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); 1798 1799 /* Disable MICBIAS1 */ 1800 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1801 0x0001, 0x0000); 1802 1803 if (IS_DCC_BASE(mic_type)) { 1804 /* dcclk_gen_on=1'b0 */ 1805 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); 1806 /* dcclk_pdn=1'b1 */ 1807 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1808 /* dcclk_ref_ck_sel=2'b00 */ 1809 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1810 /* dcclk_div=11'b00100000011 */ 1811 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1812 } 1813 } 1814 1815 static int mt6358_dmic_enable(struct mt6358_priv *priv) 1816 { 1817 dev_info(priv->dev, "%s()\n", __func__); 1818 1819 /* mic bias */ 1820 /* Enable MICBIAS0, MISBIAS0 = 1P9V */ 1821 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021); 1822 1823 /* RG_BANDGAPGEN=1'b0 */ 1824 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1825 0x1 << 12, 0x0); 1826 1827 /* DMIC enable */ 1828 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005); 1829 1830 /* here to set digital part */ 1831 mt6358_mtkaif_tx_enable(priv); 1832 1833 /* UL dmic setting */ 1834 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080); 1835 1836 /* UL turn on */ 1837 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003); 1838 1839 /* Prevent pop noise form dmic hw */ 1840 msleep(100); 1841 1842 return 0; 1843 } 1844 1845 static void mt6358_dmic_disable(struct mt6358_priv *priv) 1846 { 1847 dev_info(priv->dev, "%s()\n", __func__); 1848 1849 /* UL turn off */ 1850 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 1851 0x0003, 0x0000); 1852 1853 /* disable aud_pad TX fifos */ 1854 mt6358_mtkaif_tx_disable(priv); 1855 1856 /* DMIC disable */ 1857 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000); 1858 1859 /* mic bias */ 1860 /* MISBIAS0 = 1P7V */ 1861 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001); 1862 1863 /* RG_BANDGAPGEN=1'b0 */ 1864 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1865 0x1 << 12, 0x0); 1866 1867 /* MICBIA0 disable */ 1868 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); 1869 } 1870 1871 static void mt6358_restore_pga(struct mt6358_priv *priv) 1872 { 1873 unsigned int gain_l, gain_r; 1874 1875 gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1]; 1876 gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2]; 1877 1878 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1879 RG_AUDPREAMPLGAIN_MASK_SFT, 1880 gain_l << RG_AUDPREAMPLGAIN_SFT); 1881 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1882 RG_AUDPREAMPRGAIN_MASK_SFT, 1883 gain_r << RG_AUDPREAMPRGAIN_SFT); 1884 } 1885 1886 static int mt_mic_type_event(struct snd_soc_dapm_widget *w, 1887 struct snd_kcontrol *kcontrol, 1888 int event) 1889 { 1890 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1891 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1892 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1893 1894 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", 1895 __func__, event, mux); 1896 1897 switch (event) { 1898 case SND_SOC_DAPM_WILL_PMU: 1899 priv->mux_select[MUX_MIC_TYPE] = mux; 1900 break; 1901 case SND_SOC_DAPM_PRE_PMU: 1902 switch (mux) { 1903 case MIC_TYPE_MUX_DMIC: 1904 mt6358_dmic_enable(priv); 1905 break; 1906 default: 1907 mt6358_amic_enable(priv); 1908 break; 1909 } 1910 mt6358_restore_pga(priv); 1911 1912 break; 1913 case SND_SOC_DAPM_POST_PMD: 1914 switch (priv->mux_select[MUX_MIC_TYPE]) { 1915 case MIC_TYPE_MUX_DMIC: 1916 mt6358_dmic_disable(priv); 1917 break; 1918 default: 1919 mt6358_amic_disable(priv); 1920 break; 1921 } 1922 1923 priv->mux_select[MUX_MIC_TYPE] = mux; 1924 break; 1925 default: 1926 break; 1927 } 1928 1929 return 0; 1930 } 1931 1932 static int mt_adc_l_event(struct snd_soc_dapm_widget *w, 1933 struct snd_kcontrol *kcontrol, 1934 int event) 1935 { 1936 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1937 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1938 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1939 1940 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1941 __func__, event, mux); 1942 1943 priv->mux_select[MUX_ADC_L] = mux; 1944 1945 return 0; 1946 } 1947 1948 static int mt_adc_r_event(struct snd_soc_dapm_widget *w, 1949 struct snd_kcontrol *kcontrol, 1950 int event) 1951 { 1952 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1953 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1954 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1955 1956 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1957 __func__, event, mux); 1958 1959 priv->mux_select[MUX_ADC_R] = mux; 1960 1961 return 0; 1962 } 1963 1964 static int mt_pga_left_event(struct snd_soc_dapm_widget *w, 1965 struct snd_kcontrol *kcontrol, 1966 int event) 1967 { 1968 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1969 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1970 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1971 1972 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1973 __func__, event, mux); 1974 1975 priv->mux_select[MUX_PGA_L] = mux; 1976 1977 return 0; 1978 } 1979 1980 static int mt_pga_right_event(struct snd_soc_dapm_widget *w, 1981 struct snd_kcontrol *kcontrol, 1982 int event) 1983 { 1984 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1985 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1986 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1987 1988 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1989 __func__, event, mux); 1990 1991 priv->mux_select[MUX_PGA_R] = mux; 1992 1993 return 0; 1994 } 1995 1996 static int mt_delay_250_event(struct snd_soc_dapm_widget *w, 1997 struct snd_kcontrol *kcontrol, 1998 int event) 1999 { 2000 switch (event) { 2001 case SND_SOC_DAPM_POST_PMU: 2002 usleep_range(250, 270); 2003 break; 2004 case SND_SOC_DAPM_PRE_PMD: 2005 usleep_range(250, 270); 2006 break; 2007 default: 2008 break; 2009 } 2010 2011 return 0; 2012 } 2013 2014 /* DAPM Widgets */ 2015 static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = { 2016 /* Global Supply*/ 2017 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF, 2018 MT6358_DCXO_CW14, 2019 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0), 2020 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB, 2021 MT6358_AUDDEC_ANA_CON13, 2022 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0), 2023 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ, 2024 MT6358_AUDENC_ANA_CON6, 2025 RG_CLKSQ_EN_SFT, 0, 2026 mt_clksq_event, 2027 SND_SOC_DAPM_PRE_PMU), 2028 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK, 2029 MT6358_AUD_TOP_CKPDN_CON0, 2030 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0), 2031 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK, 2032 MT6358_AUD_TOP_CKPDN_CON0, 2033 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0), 2034 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST, 2035 MT6358_AUD_TOP_CKPDN_CON0, 2036 RG_AUD_CK_PDN_SFT, 1, 2037 mt_delay_250_event, 2038 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2039 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK, 2040 MT6358_AUD_TOP_CKPDN_CON0, 2041 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0), 2042 2043 /* Digital Clock */ 2044 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST, 2045 MT6358_AUDIO_TOP_CON0, 2046 PDN_AFE_CTL_SFT, 1, 2047 mt_delay_250_event, 2048 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 2049 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP, 2050 MT6358_AUDIO_TOP_CON0, 2051 PDN_DAC_CTL_SFT, 1, NULL, 0), 2052 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP, 2053 MT6358_AUDIO_TOP_CON0, 2054 PDN_ADC_CTL_SFT, 1, NULL, 0), 2055 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP, 2056 MT6358_AUDIO_TOP_CON0, 2057 PDN_I2S_DL_CTL_SFT, 1, NULL, 0), 2058 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP, 2059 MT6358_AUDIO_TOP_CON0, 2060 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0), 2061 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP, 2062 MT6358_AUDIO_TOP_CON0, 2063 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0), 2064 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP, 2065 MT6358_AUDIO_TOP_CON0, 2066 PDN_RESERVED_SFT, 1, NULL, 0), 2067 2068 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM, 2069 0, 0, NULL, 0), 2070 2071 /* AFE ON */ 2072 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE, 2073 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0, 2074 NULL, 0), 2075 2076 /* AIF Rx*/ 2077 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0, 2078 MT6358_AFE_DL_SRC2_CON0_L, 2079 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, 2080 mt_aif_in_event, 2081 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2082 2083 /* DL Supply */ 2084 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM, 2085 0, 0, NULL, 0), 2086 2087 /* DAC */ 2088 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control), 2089 2090 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 2091 2092 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 2093 2094 /* LOL */ 2095 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control), 2096 2097 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7, 2098 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0), 2099 2100 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7, 2101 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0), 2102 2103 /* Headphone */ 2104 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0, 2105 &hpl_in_mux_control, 2106 mt_hp_event, 2107 SND_SOC_DAPM_PRE_PMU | 2108 SND_SOC_DAPM_PRE_PMD), 2109 2110 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0, 2111 &hpr_in_mux_control, 2112 mt_hp_event, 2113 SND_SOC_DAPM_PRE_PMU | 2114 SND_SOC_DAPM_PRE_PMD), 2115 2116 /* Receiver */ 2117 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0, 2118 &rcv_in_mux_control, 2119 mt_rcv_event, 2120 SND_SOC_DAPM_PRE_PMU | 2121 SND_SOC_DAPM_PRE_PMD), 2122 2123 /* Outputs */ 2124 SND_SOC_DAPM_OUTPUT("Receiver"), 2125 SND_SOC_DAPM_OUTPUT("Headphone L"), 2126 SND_SOC_DAPM_OUTPUT("Headphone R"), 2127 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"), 2128 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"), 2129 SND_SOC_DAPM_OUTPUT("LINEOUT L"), 2130 SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"), 2131 2132 /* SGEN */ 2133 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0, 2134 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0), 2135 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0, 2136 SGEN_MUTE_SW_CTL_SFT, 1, 2137 mt_sgen_event, 2138 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2139 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L, 2140 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0), 2141 2142 SND_SOC_DAPM_INPUT("SGEN DL"), 2143 2144 /* Uplinks */ 2145 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0, 2146 SND_SOC_NOPM, 0, 0, 2147 mt_aif_out_event, 2148 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2149 2150 SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY, 2151 SND_SOC_NOPM, 0, 0, 2152 mt_adc_supply_event, 2153 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2154 2155 /* Uplinks MUX */ 2156 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0, 2157 &aif_out_mux_control), 2158 2159 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0, 2160 &mic_type_mux_control, 2161 mt_mic_type_event, 2162 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD | 2163 SND_SOC_DAPM_WILL_PMU), 2164 2165 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0, 2166 &adc_left_mux_control, 2167 mt_adc_l_event, 2168 SND_SOC_DAPM_WILL_PMU), 2169 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0, 2170 &adc_right_mux_control, 2171 mt_adc_r_event, 2172 SND_SOC_DAPM_WILL_PMU), 2173 2174 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2175 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2176 2177 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0, 2178 &pga_left_mux_control, 2179 mt_pga_left_event, 2180 SND_SOC_DAPM_WILL_PMU), 2181 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0, 2182 &pga_right_mux_control, 2183 mt_pga_right_event, 2184 SND_SOC_DAPM_WILL_PMU), 2185 2186 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0), 2187 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0), 2188 2189 /* UL input */ 2190 SND_SOC_DAPM_INPUT("AIN0"), 2191 SND_SOC_DAPM_INPUT("AIN1"), 2192 SND_SOC_DAPM_INPUT("AIN2"), 2193 }; 2194 2195 static const struct snd_soc_dapm_route mt6358_dapm_routes[] = { 2196 /* Capture */ 2197 {"AIF1TX", NULL, "AIF Out Mux"}, 2198 {"AIF1TX", NULL, "CLK_BUF"}, 2199 {"AIF1TX", NULL, "AUDGLB"}, 2200 {"AIF1TX", NULL, "CLKSQ Audio"}, 2201 2202 {"AIF1TX", NULL, "AUD_CK"}, 2203 {"AIF1TX", NULL, "AUDIF_CK"}, 2204 2205 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"}, 2206 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"}, 2207 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"}, 2208 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"}, 2209 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"}, 2210 2211 {"AIF1TX", NULL, "AFE_ON"}, 2212 2213 {"AIF Out Mux", NULL, "Mic Type Mux"}, 2214 2215 {"Mic Type Mux", "ACC", "ADC L"}, 2216 {"Mic Type Mux", "ACC", "ADC R"}, 2217 {"Mic Type Mux", "DCC", "ADC L"}, 2218 {"Mic Type Mux", "DCC", "ADC R"}, 2219 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"}, 2220 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"}, 2221 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"}, 2222 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"}, 2223 {"Mic Type Mux", "DMIC", "AIN0"}, 2224 {"Mic Type Mux", "DMIC", "AIN2"}, 2225 2226 {"ADC L", NULL, "ADC L Mux"}, 2227 {"ADC L", NULL, "ADC Supply"}, 2228 {"ADC R", NULL, "ADC R Mux"}, 2229 {"ADC R", NULL, "ADC Supply"}, 2230 2231 {"ADC L Mux", "Left Preamplifier", "PGA L"}, 2232 2233 {"ADC R Mux", "Right Preamplifier", "PGA R"}, 2234 2235 {"PGA L", NULL, "PGA L Mux"}, 2236 {"PGA R", NULL, "PGA R Mux"}, 2237 2238 {"PGA L Mux", "AIN0", "AIN0"}, 2239 {"PGA L Mux", "AIN1", "AIN1"}, 2240 {"PGA L Mux", "AIN2", "AIN2"}, 2241 2242 {"PGA R Mux", "AIN0", "AIN0"}, 2243 {"PGA R Mux", "AIN1", "AIN1"}, 2244 {"PGA R Mux", "AIN2", "AIN2"}, 2245 2246 /* DL Supply */ 2247 {"DL Power Supply", NULL, "CLK_BUF"}, 2248 {"DL Power Supply", NULL, "AUDGLB"}, 2249 {"DL Power Supply", NULL, "CLKSQ Audio"}, 2250 2251 {"DL Power Supply", NULL, "AUDNCP_CK"}, 2252 {"DL Power Supply", NULL, "ZCD13M_CK"}, 2253 {"DL Power Supply", NULL, "AUD_CK"}, 2254 {"DL Power Supply", NULL, "AUDIF_CK"}, 2255 2256 /* DL Digital Supply */ 2257 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"}, 2258 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"}, 2259 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"}, 2260 2261 {"DL Digital Clock", NULL, "AFE_ON"}, 2262 2263 {"AIF_RX", NULL, "DL Digital Clock"}, 2264 2265 /* DL Path */ 2266 {"DAC In Mux", "Normal Path", "AIF_RX"}, 2267 2268 {"DAC In Mux", "Sgen", "SGEN DL"}, 2269 {"SGEN DL", NULL, "SGEN DL SRC"}, 2270 {"SGEN DL", NULL, "SGEN MUTE"}, 2271 {"SGEN DL", NULL, "SGEN DL Enable"}, 2272 {"SGEN DL", NULL, "DL Digital Clock"}, 2273 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"}, 2274 2275 {"DACL", NULL, "DAC In Mux"}, 2276 {"DACL", NULL, "DL Power Supply"}, 2277 2278 {"DACR", NULL, "DAC In Mux"}, 2279 {"DACR", NULL, "DL Power Supply"}, 2280 2281 /* Lineout Path */ 2282 {"LOL Mux", "Playback", "DACL"}, 2283 2284 {"LOL Buffer", NULL, "LOL Mux"}, 2285 {"LOL Buffer", NULL, "LO Stability Enh"}, 2286 2287 {"LINEOUT L", NULL, "LOL Buffer"}, 2288 2289 /* Headphone Path */ 2290 {"HPL Mux", "Audio Playback", "DACL"}, 2291 {"HPR Mux", "Audio Playback", "DACR"}, 2292 {"HPL Mux", "HP Impedance", "DACL"}, 2293 {"HPR Mux", "HP Impedance", "DACR"}, 2294 {"HPL Mux", "LoudSPK Playback", "DACL"}, 2295 {"HPR Mux", "LoudSPK Playback", "DACR"}, 2296 2297 {"Headphone L", NULL, "HPL Mux"}, 2298 {"Headphone R", NULL, "HPR Mux"}, 2299 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"}, 2300 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"}, 2301 {"LINEOUT L HSSPK", NULL, "HPL Mux"}, 2302 2303 /* Receiver Path */ 2304 {"RCV Mux", "Voice Playback", "DACL"}, 2305 {"Receiver", NULL, "RCV Mux"}, 2306 }; 2307 2308 static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream, 2309 struct snd_pcm_hw_params *params, 2310 struct snd_soc_dai *dai) 2311 { 2312 struct snd_soc_component *cmpnt = dai->component; 2313 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2314 unsigned int rate = params_rate(params); 2315 2316 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n", 2317 __func__, 2318 substream->stream, 2319 rate, 2320 substream->number); 2321 2322 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2323 priv->dl_rate = rate; 2324 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2325 priv->ul_rate = rate; 2326 2327 return 0; 2328 } 2329 2330 static const struct snd_soc_dai_ops mt6358_codec_dai_ops = { 2331 .hw_params = mt6358_codec_dai_hw_params, 2332 }; 2333 2334 #define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\ 2335 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\ 2336 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\ 2337 SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\ 2338 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\ 2339 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE) 2340 2341 static struct snd_soc_dai_driver mt6358_dai_driver[] = { 2342 { 2343 .name = "mt6358-snd-codec-aif1", 2344 .playback = { 2345 .stream_name = "AIF1 Playback", 2346 .channels_min = 1, 2347 .channels_max = 2, 2348 .rates = SNDRV_PCM_RATE_8000_48000 | 2349 SNDRV_PCM_RATE_96000 | 2350 SNDRV_PCM_RATE_192000, 2351 .formats = MT6358_FORMATS, 2352 }, 2353 .capture = { 2354 .stream_name = "AIF1 Capture", 2355 .channels_min = 1, 2356 .channels_max = 2, 2357 .rates = SNDRV_PCM_RATE_8000 | 2358 SNDRV_PCM_RATE_16000 | 2359 SNDRV_PCM_RATE_32000 | 2360 SNDRV_PCM_RATE_48000, 2361 .formats = MT6358_FORMATS, 2362 }, 2363 .ops = &mt6358_codec_dai_ops, 2364 }, 2365 }; 2366 2367 static void mt6358_codec_init_reg(struct mt6358_priv *priv) 2368 { 2369 /* Disable HeadphoneL/HeadphoneR short circuit protection */ 2370 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 2371 RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT, 2372 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT); 2373 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 2374 RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT, 2375 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT); 2376 /* Disable voice short circuit protection */ 2377 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 2378 RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT, 2379 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT); 2380 /* disable LO buffer left short circuit protection */ 2381 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 2382 RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT, 2383 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT); 2384 2385 /* accdet s/w enable */ 2386 regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13, 2387 0xFFFF, 0x700E); 2388 2389 /* gpio miso driving set to 4mA */ 2390 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888); 2391 2392 /* set gpio */ 2393 playback_gpio_reset(priv); 2394 capture_gpio_reset(priv); 2395 } 2396 2397 static int mt6358_codec_probe(struct snd_soc_component *cmpnt) 2398 { 2399 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2400 int ret; 2401 2402 snd_soc_component_init_regmap(cmpnt, priv->regmap); 2403 2404 mt6358_codec_init_reg(priv); 2405 2406 priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd"); 2407 if (IS_ERR(priv->avdd_reg)) { 2408 dev_err(priv->dev, "%s() have no Avdd supply", __func__); 2409 return PTR_ERR(priv->avdd_reg); 2410 } 2411 2412 ret = regulator_enable(priv->avdd_reg); 2413 if (ret) 2414 return ret; 2415 2416 return 0; 2417 } 2418 2419 static const struct snd_soc_component_driver mt6358_soc_component_driver = { 2420 .probe = mt6358_codec_probe, 2421 .controls = mt6358_snd_controls, 2422 .num_controls = ARRAY_SIZE(mt6358_snd_controls), 2423 .dapm_widgets = mt6358_dapm_widgets, 2424 .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets), 2425 .dapm_routes = mt6358_dapm_routes, 2426 .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes), 2427 }; 2428 2429 static int mt6358_platform_driver_probe(struct platform_device *pdev) 2430 { 2431 struct mt6358_priv *priv; 2432 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); 2433 2434 priv = devm_kzalloc(&pdev->dev, 2435 sizeof(struct mt6358_priv), 2436 GFP_KERNEL); 2437 if (!priv) 2438 return -ENOMEM; 2439 2440 dev_set_drvdata(&pdev->dev, priv); 2441 2442 priv->dev = &pdev->dev; 2443 2444 priv->regmap = mt6397->regmap; 2445 if (IS_ERR(priv->regmap)) 2446 return PTR_ERR(priv->regmap); 2447 2448 dev_info(priv->dev, "%s(), dev name %s\n", 2449 __func__, dev_name(&pdev->dev)); 2450 2451 return devm_snd_soc_register_component(&pdev->dev, 2452 &mt6358_soc_component_driver, 2453 mt6358_dai_driver, 2454 ARRAY_SIZE(mt6358_dai_driver)); 2455 } 2456 2457 static const struct of_device_id mt6358_of_match[] = { 2458 {.compatible = "mediatek,mt6358-sound",}, 2459 {} 2460 }; 2461 MODULE_DEVICE_TABLE(of, mt6358_of_match); 2462 2463 static struct platform_driver mt6358_platform_driver = { 2464 .driver = { 2465 .name = "mt6358-sound", 2466 .of_match_table = mt6358_of_match, 2467 }, 2468 .probe = mt6358_platform_driver_probe, 2469 }; 2470 2471 module_platform_driver(mt6358_platform_driver) 2472 2473 /* Module information */ 2474 MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver"); 2475 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>"); 2476 MODULE_LICENSE("GPL v2"); 2477