1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // mt6358.c -- mt6358 ALSA SoC audio codec driver 4 // 5 // Copyright (c) 2018 MediaTek Inc. 6 // Author: KaiChieh Chuang <kaichieh.chuang@mediatek.com> 7 8 #include <linux/platform_device.h> 9 #include <linux/module.h> 10 #include <linux/of_device.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/sched.h> 14 #include <linux/mfd/mt6397/core.h> 15 #include <linux/regulator/consumer.h> 16 17 #include <sound/soc.h> 18 #include <sound/tlv.h> 19 20 #include "mt6358.h" 21 22 enum { 23 AUDIO_ANALOG_VOLUME_HSOUTL, 24 AUDIO_ANALOG_VOLUME_HSOUTR, 25 AUDIO_ANALOG_VOLUME_HPOUTL, 26 AUDIO_ANALOG_VOLUME_HPOUTR, 27 AUDIO_ANALOG_VOLUME_LINEOUTL, 28 AUDIO_ANALOG_VOLUME_LINEOUTR, 29 AUDIO_ANALOG_VOLUME_MICAMP1, 30 AUDIO_ANALOG_VOLUME_MICAMP2, 31 AUDIO_ANALOG_VOLUME_TYPE_MAX 32 }; 33 34 enum { 35 MUX_ADC_L, 36 MUX_ADC_R, 37 MUX_PGA_L, 38 MUX_PGA_R, 39 MUX_MIC_TYPE, 40 MUX_HP_L, 41 MUX_HP_R, 42 MUX_NUM, 43 }; 44 45 enum { 46 DEVICE_HP, 47 DEVICE_LO, 48 DEVICE_RCV, 49 DEVICE_MIC1, 50 DEVICE_MIC2, 51 DEVICE_NUM 52 }; 53 54 /* Supply widget subseq */ 55 enum { 56 /* common */ 57 SUPPLY_SEQ_CLK_BUF, 58 SUPPLY_SEQ_AUD_GLB, 59 SUPPLY_SEQ_CLKSQ, 60 SUPPLY_SEQ_VOW_AUD_LPW, 61 SUPPLY_SEQ_AUD_VOW, 62 SUPPLY_SEQ_VOW_CLK, 63 SUPPLY_SEQ_VOW_LDO, 64 SUPPLY_SEQ_TOP_CK, 65 SUPPLY_SEQ_TOP_CK_LAST, 66 SUPPLY_SEQ_AUD_TOP, 67 SUPPLY_SEQ_AUD_TOP_LAST, 68 SUPPLY_SEQ_AFE, 69 /* capture */ 70 SUPPLY_SEQ_ADC_SUPPLY, 71 }; 72 73 enum { 74 CH_L = 0, 75 CH_R, 76 NUM_CH, 77 }; 78 79 #define REG_STRIDE 2 80 81 struct mt6358_priv { 82 struct device *dev; 83 struct regmap *regmap; 84 85 unsigned int dl_rate; 86 unsigned int ul_rate; 87 88 int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX]; 89 unsigned int mux_select[MUX_NUM]; 90 91 int dev_counter[DEVICE_NUM]; 92 93 int mtkaif_protocol; 94 95 struct regulator *avdd_reg; 96 }; 97 98 int mt6358_set_mtkaif_protocol(struct snd_soc_component *cmpnt, 99 int mtkaif_protocol) 100 { 101 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 102 103 priv->mtkaif_protocol = mtkaif_protocol; 104 return 0; 105 } 106 107 static void playback_gpio_set(struct mt6358_priv *priv) 108 { 109 /* set gpio mosi mode */ 110 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, 111 0x01f8, 0x01f8); 112 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_SET, 113 0xffff, 0x0249); 114 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, 115 0xffff, 0x0249); 116 } 117 118 static void playback_gpio_reset(struct mt6358_priv *priv) 119 { 120 /* set pad_aud_*_mosi to GPIO mode and dir input 121 * reason: 122 * pad_aud_dat_mosi*, because the pin is used as boot strap 123 * don't clean clk/sync, for mtkaif protocol 2 124 */ 125 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2_CLR, 126 0x01f8, 0x01f8); 127 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE2, 128 0x01f8, 0x0000); 129 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, 130 0xf << 8, 0x0); 131 } 132 133 static void capture_gpio_set(struct mt6358_priv *priv) 134 { 135 /* set gpio miso mode */ 136 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, 137 0xffff, 0xffff); 138 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_SET, 139 0xffff, 0x0249); 140 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 141 0xffff, 0x0249); 142 } 143 144 static void capture_gpio_reset(struct mt6358_priv *priv) 145 { 146 /* set pad_aud_*_miso to GPIO mode and dir input 147 * reason: 148 * pad_aud_clk_miso, because when playback only the miso_clk 149 * will also have 26m, so will have power leak 150 * pad_aud_dat_miso*, because the pin is used as boot strap 151 */ 152 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3_CLR, 153 0xffff, 0xffff); 154 regmap_update_bits(priv->regmap, MT6358_GPIO_MODE3, 155 0xffff, 0x0000); 156 regmap_update_bits(priv->regmap, MT6358_GPIO_DIR0, 157 0xf << 12, 0x0); 158 } 159 160 /* use only when not govern by DAPM */ 161 static int mt6358_set_dcxo(struct mt6358_priv *priv, bool enable) 162 { 163 regmap_update_bits(priv->regmap, MT6358_DCXO_CW14, 164 0x1 << RG_XO_AUDIO_EN_M_SFT, 165 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT); 166 return 0; 167 } 168 169 /* use only when not govern by DAPM */ 170 static int mt6358_set_clksq(struct mt6358_priv *priv, bool enable) 171 { 172 /* audio clk source from internal dcxo */ 173 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, 174 RG_CLKSQ_IN_SEL_TEST_MASK_SFT, 175 0x0); 176 177 /* Enable/disable CLKSQ 26MHz */ 178 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, 179 RG_CLKSQ_EN_MASK_SFT, 180 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT); 181 return 0; 182 } 183 184 /* use only when not govern by DAPM */ 185 static int mt6358_set_aud_global_bias(struct mt6358_priv *priv, bool enable) 186 { 187 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 188 RG_AUDGLB_PWRDN_VA28_MASK_SFT, 189 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA28_SFT); 190 return 0; 191 } 192 193 /* use only when not govern by DAPM */ 194 static int mt6358_set_topck(struct mt6358_priv *priv, bool enable) 195 { 196 regmap_update_bits(priv->regmap, MT6358_AUD_TOP_CKPDN_CON0, 197 0x0066, enable ? 0x0 : 0x66); 198 return 0; 199 } 200 201 static int mt6358_mtkaif_tx_enable(struct mt6358_priv *priv) 202 { 203 switch (priv->mtkaif_protocol) { 204 case MT6358_MTKAIF_PROTOCOL_2_CLK_P2: 205 /* MTKAIF TX format setting */ 206 regmap_update_bits(priv->regmap, 207 MT6358_AFE_ADDA_MTKAIF_CFG0, 208 0xffff, 0x0010); 209 /* enable aud_pad TX fifos */ 210 regmap_update_bits(priv->regmap, 211 MT6358_AFE_AUD_PAD_TOP, 212 0xff00, 0x3800); 213 regmap_update_bits(priv->regmap, 214 MT6358_AFE_AUD_PAD_TOP, 215 0xff00, 0x3900); 216 break; 217 case MT6358_MTKAIF_PROTOCOL_2: 218 /* MTKAIF TX format setting */ 219 regmap_update_bits(priv->regmap, 220 MT6358_AFE_ADDA_MTKAIF_CFG0, 221 0xffff, 0x0010); 222 /* enable aud_pad TX fifos */ 223 regmap_update_bits(priv->regmap, 224 MT6358_AFE_AUD_PAD_TOP, 225 0xff00, 0x3100); 226 break; 227 case MT6358_MTKAIF_PROTOCOL_1: 228 default: 229 /* MTKAIF TX format setting */ 230 regmap_update_bits(priv->regmap, 231 MT6358_AFE_ADDA_MTKAIF_CFG0, 232 0xffff, 0x0000); 233 /* enable aud_pad TX fifos */ 234 regmap_update_bits(priv->regmap, 235 MT6358_AFE_AUD_PAD_TOP, 236 0xff00, 0x3100); 237 break; 238 } 239 return 0; 240 } 241 242 static int mt6358_mtkaif_tx_disable(struct mt6358_priv *priv) 243 { 244 /* disable aud_pad TX fifos */ 245 regmap_update_bits(priv->regmap, MT6358_AFE_AUD_PAD_TOP, 246 0xff00, 0x3000); 247 return 0; 248 } 249 250 int mt6358_mtkaif_calibration_enable(struct snd_soc_component *cmpnt) 251 { 252 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 253 254 playback_gpio_set(priv); 255 capture_gpio_set(priv); 256 mt6358_mtkaif_tx_enable(priv); 257 258 mt6358_set_dcxo(priv, true); 259 mt6358_set_aud_global_bias(priv, true); 260 mt6358_set_clksq(priv, true); 261 mt6358_set_topck(priv, true); 262 263 /* set dat_miso_loopback on */ 264 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 265 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT, 266 1 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT); 267 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 268 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT, 269 1 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); 270 return 0; 271 } 272 273 int mt6358_mtkaif_calibration_disable(struct snd_soc_component *cmpnt) 274 { 275 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 276 277 /* set dat_miso_loopback off */ 278 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 279 RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT, 280 0 << RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT); 281 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 282 RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT, 283 0 << RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT); 284 285 mt6358_set_topck(priv, false); 286 mt6358_set_clksq(priv, false); 287 mt6358_set_aud_global_bias(priv, false); 288 mt6358_set_dcxo(priv, false); 289 290 mt6358_mtkaif_tx_disable(priv); 291 playback_gpio_reset(priv); 292 capture_gpio_reset(priv); 293 return 0; 294 } 295 296 int mt6358_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt, 297 int phase_1, int phase_2) 298 { 299 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 300 301 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 302 RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT, 303 phase_1 << RG_AUD_PAD_TOP_PHASE_MODE_SFT); 304 regmap_update_bits(priv->regmap, MT6358_AUDIO_DIG_CFG, 305 RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT, 306 phase_2 << RG_AUD_PAD_TOP_PHASE_MODE2_SFT); 307 return 0; 308 } 309 310 /* dl pga gain */ 311 enum { 312 DL_GAIN_8DB = 0, 313 DL_GAIN_0DB = 8, 314 DL_GAIN_N_1DB = 9, 315 DL_GAIN_N_10DB = 18, 316 DL_GAIN_N_40DB = 0x1f, 317 }; 318 319 #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB) 320 #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB) 321 #define DL_GAIN_REG_MASK 0x0f9f 322 323 static void lo_store_gain(struct mt6358_priv *priv) 324 { 325 unsigned int reg; 326 unsigned int gain_l, gain_r; 327 328 regmap_read(priv->regmap, MT6358_ZCD_CON1, ®); 329 gain_l = (reg >> RG_AUDLOLGAIN_SFT) & RG_AUDLOLGAIN_MASK; 330 gain_r = (reg >> RG_AUDLORGAIN_SFT) & RG_AUDLORGAIN_MASK; 331 332 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] = gain_l; 333 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] = gain_r; 334 } 335 336 static void hp_store_gain(struct mt6358_priv *priv) 337 { 338 unsigned int reg; 339 unsigned int gain_l, gain_r; 340 341 regmap_read(priv->regmap, MT6358_ZCD_CON2, ®); 342 gain_l = (reg >> RG_AUDHPLGAIN_SFT) & RG_AUDHPLGAIN_MASK; 343 gain_r = (reg >> RG_AUDHPRGAIN_SFT) & RG_AUDHPRGAIN_MASK; 344 345 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] = gain_l; 346 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] = gain_r; 347 } 348 349 static void hp_zcd_disable(struct mt6358_priv *priv) 350 { 351 regmap_write(priv->regmap, MT6358_ZCD_CON0, 0x0000); 352 } 353 354 static void hp_main_output_ramp(struct mt6358_priv *priv, bool up) 355 { 356 int i = 0, stage = 0; 357 int target = 7; 358 359 /* Enable/Reduce HPL/R main output stage step by step */ 360 for (i = 0; i <= target; i++) { 361 stage = up ? i : target - i; 362 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 363 0x7 << 8, stage << 8); 364 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 365 0x7 << 11, stage << 11); 366 usleep_range(100, 150); 367 } 368 } 369 370 static void hp_aux_feedback_loop_gain_ramp(struct mt6358_priv *priv, bool up) 371 { 372 int i = 0, stage = 0; 373 374 /* Reduce HP aux feedback loop gain step by step */ 375 for (i = 0; i <= 0xf; i++) { 376 stage = up ? i : 0xf - i; 377 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 378 0xf << 12, stage << 12); 379 usleep_range(100, 150); 380 } 381 } 382 383 static void hp_pull_down(struct mt6358_priv *priv, bool enable) 384 { 385 int i; 386 387 if (enable) { 388 for (i = 0x0; i <= 0x6; i++) { 389 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 390 0x7, i); 391 usleep_range(600, 700); 392 } 393 } else { 394 for (i = 0x6; i >= 0x1; i--) { 395 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 396 0x7, i); 397 usleep_range(600, 700); 398 } 399 } 400 } 401 402 static bool is_valid_hp_pga_idx(int reg_idx) 403 { 404 return (reg_idx >= DL_GAIN_8DB && reg_idx <= DL_GAIN_N_10DB) || 405 reg_idx == DL_GAIN_N_40DB; 406 } 407 408 static void headset_volume_ramp(struct mt6358_priv *priv, 409 int from, int to) 410 { 411 int offset = 0, count = 1, reg_idx; 412 413 if (!is_valid_hp_pga_idx(from) || !is_valid_hp_pga_idx(to)) 414 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n", 415 __func__, from, to); 416 417 dev_info(priv->dev, "%s(), from %d, to %d\n", 418 __func__, from, to); 419 420 if (to > from) 421 offset = to - from; 422 else 423 offset = from - to; 424 425 while (offset > 0) { 426 if (to > from) 427 reg_idx = from + count; 428 else 429 reg_idx = from - count; 430 431 if (is_valid_hp_pga_idx(reg_idx)) { 432 regmap_update_bits(priv->regmap, 433 MT6358_ZCD_CON2, 434 DL_GAIN_REG_MASK, 435 (reg_idx << 7) | reg_idx); 436 usleep_range(200, 300); 437 } 438 offset--; 439 count++; 440 } 441 } 442 443 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0); 444 static const DECLARE_TLV_DB_SCALE(pga_tlv, 0, 600, 0); 445 446 static const struct snd_kcontrol_new mt6358_snd_controls[] = { 447 /* dl pga gain */ 448 SOC_DOUBLE_TLV("Headphone Volume", 449 MT6358_ZCD_CON2, 0, 7, 0x12, 1, 450 playback_tlv), 451 SOC_DOUBLE_TLV("Lineout Volume", 452 MT6358_ZCD_CON1, 0, 7, 0x12, 1, 453 playback_tlv), 454 SOC_SINGLE_TLV("Handset Volume", 455 MT6358_ZCD_CON3, 0, 0x12, 1, 456 playback_tlv), 457 /* ul pga gain */ 458 SOC_DOUBLE_R_TLV("PGA Volume", 459 MT6358_AUDENC_ANA_CON0, MT6358_AUDENC_ANA_CON1, 460 8, 4, 0, 461 pga_tlv), 462 }; 463 464 /* MUX */ 465 /* LOL MUX */ 466 static const char * const lo_in_mux_map[] = { 467 "Open", "Mute", "Playback", "Test Mode" 468 }; 469 470 static int lo_in_mux_map_value[] = { 471 0x0, 0x1, 0x2, 0x3, 472 }; 473 474 static SOC_VALUE_ENUM_SINGLE_DECL(lo_in_mux_map_enum, 475 MT6358_AUDDEC_ANA_CON7, 476 RG_AUDLOLMUXINPUTSEL_VAUDP15_SFT, 477 RG_AUDLOLMUXINPUTSEL_VAUDP15_MASK, 478 lo_in_mux_map, 479 lo_in_mux_map_value); 480 481 static const struct snd_kcontrol_new lo_in_mux_control = 482 SOC_DAPM_ENUM("In Select", lo_in_mux_map_enum); 483 484 /*HP MUX */ 485 enum { 486 HP_MUX_OPEN = 0, 487 HP_MUX_HPSPK, 488 HP_MUX_HP, 489 HP_MUX_TEST_MODE, 490 HP_MUX_HP_IMPEDANCE, 491 HP_MUX_MASK = 0x7, 492 }; 493 494 static const char * const hp_in_mux_map[] = { 495 "Open", 496 "LoudSPK Playback", 497 "Audio Playback", 498 "Test Mode", 499 "HP Impedance", 500 "undefined1", 501 "undefined2", 502 "undefined3", 503 }; 504 505 static int hp_in_mux_map_value[] = { 506 HP_MUX_OPEN, 507 HP_MUX_HPSPK, 508 HP_MUX_HP, 509 HP_MUX_TEST_MODE, 510 HP_MUX_HP_IMPEDANCE, 511 HP_MUX_OPEN, 512 HP_MUX_OPEN, 513 HP_MUX_OPEN, 514 }; 515 516 static SOC_VALUE_ENUM_SINGLE_DECL(hpl_in_mux_map_enum, 517 SND_SOC_NOPM, 518 0, 519 HP_MUX_MASK, 520 hp_in_mux_map, 521 hp_in_mux_map_value); 522 523 static const struct snd_kcontrol_new hpl_in_mux_control = 524 SOC_DAPM_ENUM("HPL Select", hpl_in_mux_map_enum); 525 526 static SOC_VALUE_ENUM_SINGLE_DECL(hpr_in_mux_map_enum, 527 SND_SOC_NOPM, 528 0, 529 HP_MUX_MASK, 530 hp_in_mux_map, 531 hp_in_mux_map_value); 532 533 static const struct snd_kcontrol_new hpr_in_mux_control = 534 SOC_DAPM_ENUM("HPR Select", hpr_in_mux_map_enum); 535 536 /* RCV MUX */ 537 enum { 538 RCV_MUX_OPEN = 0, 539 RCV_MUX_MUTE, 540 RCV_MUX_VOICE_PLAYBACK, 541 RCV_MUX_TEST_MODE, 542 RCV_MUX_MASK = 0x3, 543 }; 544 545 static const char * const rcv_in_mux_map[] = { 546 "Open", "Mute", "Voice Playback", "Test Mode" 547 }; 548 549 static int rcv_in_mux_map_value[] = { 550 RCV_MUX_OPEN, 551 RCV_MUX_MUTE, 552 RCV_MUX_VOICE_PLAYBACK, 553 RCV_MUX_TEST_MODE, 554 }; 555 556 static SOC_VALUE_ENUM_SINGLE_DECL(rcv_in_mux_map_enum, 557 SND_SOC_NOPM, 558 0, 559 RCV_MUX_MASK, 560 rcv_in_mux_map, 561 rcv_in_mux_map_value); 562 563 static const struct snd_kcontrol_new rcv_in_mux_control = 564 SOC_DAPM_ENUM("RCV Select", rcv_in_mux_map_enum); 565 566 /* DAC In MUX */ 567 static const char * const dac_in_mux_map[] = { 568 "Normal Path", "Sgen" 569 }; 570 571 static int dac_in_mux_map_value[] = { 572 0x0, 0x1, 573 }; 574 575 static SOC_VALUE_ENUM_SINGLE_DECL(dac_in_mux_map_enum, 576 MT6358_AFE_TOP_CON0, 577 DL_SINE_ON_SFT, 578 DL_SINE_ON_MASK, 579 dac_in_mux_map, 580 dac_in_mux_map_value); 581 582 static const struct snd_kcontrol_new dac_in_mux_control = 583 SOC_DAPM_ENUM("DAC Select", dac_in_mux_map_enum); 584 585 /* AIF Out MUX */ 586 static SOC_VALUE_ENUM_SINGLE_DECL(aif_out_mux_map_enum, 587 MT6358_AFE_TOP_CON0, 588 UL_SINE_ON_SFT, 589 UL_SINE_ON_MASK, 590 dac_in_mux_map, 591 dac_in_mux_map_value); 592 593 static const struct snd_kcontrol_new aif_out_mux_control = 594 SOC_DAPM_ENUM("AIF Out Select", aif_out_mux_map_enum); 595 596 /* Mic Type MUX */ 597 enum { 598 MIC_TYPE_MUX_IDLE = 0, 599 MIC_TYPE_MUX_ACC, 600 MIC_TYPE_MUX_DMIC, 601 MIC_TYPE_MUX_DCC, 602 MIC_TYPE_MUX_DCC_ECM_DIFF, 603 MIC_TYPE_MUX_DCC_ECM_SINGLE, 604 MIC_TYPE_MUX_MASK = 0x7, 605 }; 606 607 #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \ 608 (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \ 609 (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE) 610 611 static const char * const mic_type_mux_map[] = { 612 "Idle", 613 "ACC", 614 "DMIC", 615 "DCC", 616 "DCC_ECM_DIFF", 617 "DCC_ECM_SINGLE", 618 }; 619 620 static int mic_type_mux_map_value[] = { 621 MIC_TYPE_MUX_IDLE, 622 MIC_TYPE_MUX_ACC, 623 MIC_TYPE_MUX_DMIC, 624 MIC_TYPE_MUX_DCC, 625 MIC_TYPE_MUX_DCC_ECM_DIFF, 626 MIC_TYPE_MUX_DCC_ECM_SINGLE, 627 }; 628 629 static SOC_VALUE_ENUM_SINGLE_DECL(mic_type_mux_map_enum, 630 SND_SOC_NOPM, 631 0, 632 MIC_TYPE_MUX_MASK, 633 mic_type_mux_map, 634 mic_type_mux_map_value); 635 636 static const struct snd_kcontrol_new mic_type_mux_control = 637 SOC_DAPM_ENUM("Mic Type Select", mic_type_mux_map_enum); 638 639 /* ADC L MUX */ 640 enum { 641 ADC_MUX_IDLE = 0, 642 ADC_MUX_AIN0, 643 ADC_MUX_PREAMPLIFIER, 644 ADC_MUX_IDLE1, 645 ADC_MUX_MASK = 0x3, 646 }; 647 648 static const char * const adc_left_mux_map[] = { 649 "Idle", "AIN0", "Left Preamplifier", "Idle_1" 650 }; 651 652 static int adc_mux_map_value[] = { 653 ADC_MUX_IDLE, 654 ADC_MUX_AIN0, 655 ADC_MUX_PREAMPLIFIER, 656 ADC_MUX_IDLE1, 657 }; 658 659 static SOC_VALUE_ENUM_SINGLE_DECL(adc_left_mux_map_enum, 660 SND_SOC_NOPM, 661 0, 662 ADC_MUX_MASK, 663 adc_left_mux_map, 664 adc_mux_map_value); 665 666 static const struct snd_kcontrol_new adc_left_mux_control = 667 SOC_DAPM_ENUM("ADC L Select", adc_left_mux_map_enum); 668 669 /* ADC R MUX */ 670 static const char * const adc_right_mux_map[] = { 671 "Idle", "AIN0", "Right Preamplifier", "Idle_1" 672 }; 673 674 static SOC_VALUE_ENUM_SINGLE_DECL(adc_right_mux_map_enum, 675 SND_SOC_NOPM, 676 0, 677 ADC_MUX_MASK, 678 adc_right_mux_map, 679 adc_mux_map_value); 680 681 static const struct snd_kcontrol_new adc_right_mux_control = 682 SOC_DAPM_ENUM("ADC R Select", adc_right_mux_map_enum); 683 684 /* PGA L MUX */ 685 enum { 686 PGA_MUX_NONE = 0, 687 PGA_MUX_AIN0, 688 PGA_MUX_AIN1, 689 PGA_MUX_AIN2, 690 PGA_MUX_MASK = 0x3, 691 }; 692 693 static const char * const pga_mux_map[] = { 694 "None", "AIN0", "AIN1", "AIN2" 695 }; 696 697 static int pga_mux_map_value[] = { 698 PGA_MUX_NONE, 699 PGA_MUX_AIN0, 700 PGA_MUX_AIN1, 701 PGA_MUX_AIN2, 702 }; 703 704 static SOC_VALUE_ENUM_SINGLE_DECL(pga_left_mux_map_enum, 705 SND_SOC_NOPM, 706 0, 707 PGA_MUX_MASK, 708 pga_mux_map, 709 pga_mux_map_value); 710 711 static const struct snd_kcontrol_new pga_left_mux_control = 712 SOC_DAPM_ENUM("PGA L Select", pga_left_mux_map_enum); 713 714 /* PGA R MUX */ 715 static SOC_VALUE_ENUM_SINGLE_DECL(pga_right_mux_map_enum, 716 SND_SOC_NOPM, 717 0, 718 PGA_MUX_MASK, 719 pga_mux_map, 720 pga_mux_map_value); 721 722 static const struct snd_kcontrol_new pga_right_mux_control = 723 SOC_DAPM_ENUM("PGA R Select", pga_right_mux_map_enum); 724 725 static int mt_clksq_event(struct snd_soc_dapm_widget *w, 726 struct snd_kcontrol *kcontrol, 727 int event) 728 { 729 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 730 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 731 732 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 733 734 switch (event) { 735 case SND_SOC_DAPM_PRE_PMU: 736 /* audio clk source from internal dcxo */ 737 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON6, 738 RG_CLKSQ_IN_SEL_TEST_MASK_SFT, 739 0x0); 740 break; 741 default: 742 break; 743 } 744 745 return 0; 746 } 747 748 static int mt_sgen_event(struct snd_soc_dapm_widget *w, 749 struct snd_kcontrol *kcontrol, 750 int event) 751 { 752 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 753 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 754 755 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event); 756 757 switch (event) { 758 case SND_SOC_DAPM_PRE_PMU: 759 /* sdm audio fifo clock power on */ 760 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); 761 /* scrambler clock on enable */ 762 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); 763 /* sdm power on */ 764 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); 765 /* sdm fifo enable */ 766 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); 767 768 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG0, 769 0xff3f, 770 0x0000); 771 regmap_update_bits(priv->regmap, MT6358_AFE_SGEN_CFG1, 772 0xffff, 773 0x0001); 774 break; 775 case SND_SOC_DAPM_POST_PMD: 776 /* DL scrambler disabling sequence */ 777 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); 778 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); 779 break; 780 default: 781 break; 782 } 783 784 return 0; 785 } 786 787 static int mt_aif_in_event(struct snd_soc_dapm_widget *w, 788 struct snd_kcontrol *kcontrol, 789 int event) 790 { 791 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 792 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 793 794 dev_info(priv->dev, "%s(), event 0x%x, rate %d\n", 795 __func__, event, priv->dl_rate); 796 797 switch (event) { 798 case SND_SOC_DAPM_PRE_PMU: 799 playback_gpio_set(priv); 800 801 /* sdm audio fifo clock power on */ 802 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0006); 803 /* scrambler clock on enable */ 804 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xCBA1); 805 /* sdm power on */ 806 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0003); 807 /* sdm fifo enable */ 808 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x000B); 809 break; 810 case SND_SOC_DAPM_POST_PMD: 811 /* DL scrambler disabling sequence */ 812 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON2, 0x0000); 813 regmap_write(priv->regmap, MT6358_AFUNC_AUD_CON0, 0xcba0); 814 815 playback_gpio_reset(priv); 816 break; 817 default: 818 break; 819 } 820 821 return 0; 822 } 823 824 static int mtk_hp_enable(struct mt6358_priv *priv) 825 { 826 /* Pull-down HPL/R to AVSS28_AUD */ 827 hp_pull_down(priv, true); 828 /* release HP CMFB gate rstb */ 829 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 830 0x1 << 6, 0x1 << 6); 831 832 /* Reduce ESD resistance of AU_REFN */ 833 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 834 835 /* save target gain to restore after hardware open complete */ 836 hp_store_gain(priv); 837 /* Set HPR/HPL gain as minimum (~ -40dB) */ 838 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_40DB_REG); 839 840 /* Turn on DA_600K_NCP_VA18 */ 841 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 842 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 843 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 844 /* Toggle RG_DIVCKS_CHG */ 845 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 846 /* Set NCP soft start mode as default mode: 100us */ 847 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 848 /* Enable NCP */ 849 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 850 usleep_range(250, 270); 851 852 /* Enable cap-less LDOs (1.5V) */ 853 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 854 0x1055, 0x1055); 855 /* Enable NV regulator (-1.2V) */ 856 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 857 usleep_range(100, 120); 858 859 /* Disable AUD_ZCD */ 860 hp_zcd_disable(priv); 861 862 /* Disable headphone short-circuit protection */ 863 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); 864 865 /* Enable IBIST */ 866 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 867 868 /* Set HP DR bias current optimization, 010: 6uA */ 869 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 870 /* Set HP & ZCD bias current optimization */ 871 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 872 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 873 /* Set HPP/N STB enhance circuits */ 874 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); 875 876 /* Enable HP aux output stage */ 877 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x000c); 878 /* Enable HP aux feedback loop */ 879 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x003c); 880 /* Enable HP aux CMFB loop */ 881 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); 882 /* Enable HP driver bias circuits */ 883 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); 884 /* Enable HP driver core circuits */ 885 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); 886 /* Short HP main output to HP aux output stage */ 887 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00fc); 888 889 /* Enable HP main CMFB loop */ 890 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); 891 /* Disable HP aux CMFB loop */ 892 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); 893 894 /* Select CMFB resistor bulk to AC mode */ 895 /* Selec HS/LO cap size (6.5pF default) */ 896 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 897 898 /* Enable HP main output stage */ 899 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x00ff); 900 /* Enable HPR/L main output stage step by step */ 901 hp_main_output_ramp(priv, true); 902 903 /* Reduce HP aux feedback loop gain */ 904 hp_aux_feedback_loop_gain_ramp(priv, true); 905 /* Disable HP aux feedback loop */ 906 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 907 908 /* apply volume setting */ 909 headset_volume_ramp(priv, 910 DL_GAIN_N_10DB, 911 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); 912 913 /* Disable HP aux output stage */ 914 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 915 /* Unshort HP main output to HP aux output stage */ 916 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3f03); 917 usleep_range(100, 120); 918 919 /* Enable AUD_CLK */ 920 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); 921 /* Enable Audio DAC */ 922 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30ff); 923 /* Enable low-noise mode of DAC */ 924 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0xf201); 925 usleep_range(100, 120); 926 927 /* Switch HPL MUX to audio DAC */ 928 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x32ff); 929 /* Switch HPR MUX to audio DAC */ 930 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3aff); 931 932 /* Disable Pull-down HPL/R to AVSS28_AUD */ 933 hp_pull_down(priv, false); 934 935 return 0; 936 } 937 938 static int mtk_hp_disable(struct mt6358_priv *priv) 939 { 940 /* Pull-down HPL/R to AVSS28_AUD */ 941 hp_pull_down(priv, true); 942 943 /* HPR/HPL mux to open */ 944 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 945 0x0f00, 0x0000); 946 947 /* Disable low-noise mode of DAC */ 948 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 949 0x0001, 0x0000); 950 951 /* Disable Audio DAC */ 952 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 953 0x000f, 0x0000); 954 955 /* Disable AUD_CLK */ 956 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); 957 958 /* Short HP main output to HP aux output stage */ 959 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 960 /* Enable HP aux output stage */ 961 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 962 963 /* decrease HPL/R gain to normal gain step by step */ 964 headset_volume_ramp(priv, 965 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], 966 DL_GAIN_N_40DB); 967 968 /* Enable HP aux feedback loop */ 969 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); 970 971 /* Reduce HP aux feedback loop gain */ 972 hp_aux_feedback_loop_gain_ramp(priv, false); 973 974 /* decrease HPR/L main output stage step by step */ 975 hp_main_output_ramp(priv, false); 976 977 /* Disable HP main output stage */ 978 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); 979 980 /* Enable HP aux CMFB loop */ 981 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0e00); 982 983 /* Disable HP main CMFB loop */ 984 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0c00); 985 986 /* Unshort HP main output to HP aux output stage */ 987 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 988 0x3 << 6, 0x0); 989 990 /* Disable HP driver core circuits */ 991 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 992 0x3 << 4, 0x0); 993 994 /* Disable HP driver bias circuits */ 995 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 996 0x3 << 6, 0x0); 997 998 /* Disable HP aux CMFB loop */ 999 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); 1000 1001 /* Disable HP aux feedback loop */ 1002 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1003 0x3 << 4, 0x0); 1004 1005 /* Disable HP aux output stage */ 1006 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 1007 0x3 << 2, 0x0); 1008 1009 /* Disable IBIST */ 1010 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1011 0x1 << 8, 0x1 << 8); 1012 1013 /* Disable NV regulator (-1.2V) */ 1014 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); 1015 /* Disable cap-less LDOs (1.5V) */ 1016 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1017 0x1055, 0x0); 1018 /* Disable NCP */ 1019 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 1020 0x1, 0x1); 1021 1022 /* Increase ESD resistance of AU_REFN */ 1023 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON2, 1024 0x1 << 14, 0x0); 1025 1026 /* Set HP CMFB gate rstb */ 1027 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1028 0x1 << 6, 0x0); 1029 /* disable Pull-down HPL/R to AVSS28_AUD */ 1030 hp_pull_down(priv, false); 1031 1032 return 0; 1033 } 1034 1035 static int mtk_hp_spk_enable(struct mt6358_priv *priv) 1036 { 1037 /* Pull-down HPL/R to AVSS28_AUD */ 1038 hp_pull_down(priv, true); 1039 /* release HP CMFB gate rstb */ 1040 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1041 0x1 << 6, 0x1 << 6); 1042 1043 /* Reduce ESD resistance of AU_REFN */ 1044 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 1045 1046 /* save target gain to restore after hardware open complete */ 1047 hp_store_gain(priv); 1048 /* Set HPR/HPL gain to -10dB */ 1049 regmap_write(priv->regmap, MT6358_ZCD_CON2, DL_GAIN_N_10DB_REG); 1050 1051 /* Turn on DA_600K_NCP_VA18 */ 1052 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 1053 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 1054 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 1055 /* Toggle RG_DIVCKS_CHG */ 1056 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 1057 /* Set NCP soft start mode as default mode: 100us */ 1058 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 1059 /* Enable NCP */ 1060 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 1061 usleep_range(250, 270); 1062 1063 /* Enable cap-less LDOs (1.5V) */ 1064 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1065 0x1055, 0x1055); 1066 /* Enable NV regulator (-1.2V) */ 1067 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 1068 usleep_range(100, 120); 1069 1070 /* Disable AUD_ZCD */ 1071 hp_zcd_disable(priv); 1072 1073 /* Disable headphone short-circuit protection */ 1074 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x3000); 1075 1076 /* Enable IBIST */ 1077 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1078 1079 /* Set HP DR bias current optimization, 010: 6uA */ 1080 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 1081 /* Set HP & ZCD bias current optimization */ 1082 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1083 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1084 /* Set HPP/N STB enhance circuits */ 1085 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4033); 1086 1087 /* Disable Pull-down HPL/R to AVSS28_AUD */ 1088 hp_pull_down(priv, false); 1089 1090 /* Enable HP driver bias circuits */ 1091 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30c0); 1092 /* Enable HP driver core circuits */ 1093 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f0); 1094 /* Enable HP main CMFB loop */ 1095 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0200); 1096 1097 /* Select CMFB resistor bulk to AC mode */ 1098 /* Selec HS/LO cap size (6.5pF default) */ 1099 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 1100 1101 /* Enable HP main output stage */ 1102 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x0003); 1103 /* Enable HPR/L main output stage step by step */ 1104 hp_main_output_ramp(priv, true); 1105 1106 /* Set LO gain as minimum (~ -40dB) */ 1107 lo_store_gain(priv); 1108 regmap_write(priv->regmap, MT6358_ZCD_CON1, DL_GAIN_N_40DB_REG); 1109 /* apply volume setting */ 1110 headset_volume_ramp(priv, 1111 DL_GAIN_N_10DB, 1112 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]); 1113 1114 /* Set LO STB enhance circuits */ 1115 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0110); 1116 /* Enable LO driver bias circuits */ 1117 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0112); 1118 /* Enable LO driver core circuits */ 1119 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x0113); 1120 1121 /* Set LOL gain to normal gain step by step */ 1122 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1123 RG_AUDLOLGAIN_MASK_SFT, 1124 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] << 1125 RG_AUDLOLGAIN_SFT); 1126 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1127 RG_AUDLORGAIN_MASK_SFT, 1128 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] << 1129 RG_AUDLORGAIN_SFT); 1130 1131 /* Enable AUD_CLK */ 1132 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x1); 1133 /* Enable Audio DAC */ 1134 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x30f9); 1135 /* Enable low-noise mode of DAC */ 1136 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0201); 1137 /* Switch LOL MUX to audio DAC */ 1138 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON7, 0x011b); 1139 /* Switch HPL/R MUX to Line-out */ 1140 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x35f9); 1141 1142 return 0; 1143 } 1144 1145 static int mtk_hp_spk_disable(struct mt6358_priv *priv) 1146 { 1147 /* HPR/HPL mux to open */ 1148 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1149 0x0f00, 0x0000); 1150 /* LOL mux to open */ 1151 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1152 0x3 << 2, 0x0000); 1153 1154 /* Disable Audio DAC */ 1155 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1156 0x000f, 0x0000); 1157 1158 /* Disable AUD_CLK */ 1159 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 0x1, 0x0); 1160 1161 /* decrease HPL/R gain to normal gain step by step */ 1162 headset_volume_ramp(priv, 1163 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL], 1164 DL_GAIN_N_40DB); 1165 1166 /* decrease LOL gain to minimum gain step by step */ 1167 regmap_update_bits(priv->regmap, MT6358_ZCD_CON1, 1168 DL_GAIN_REG_MASK, DL_GAIN_N_40DB_REG); 1169 1170 /* decrease HPR/L main output stage step by step */ 1171 hp_main_output_ramp(priv, false); 1172 1173 /* Disable HP main output stage */ 1174 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3, 0x0); 1175 1176 /* Short HP main output to HP aux output stage */ 1177 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fc3); 1178 /* Enable HP aux output stage */ 1179 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fcf); 1180 1181 /* Enable HP aux feedback loop */ 1182 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON1, 0x3fff); 1183 1184 /* Reduce HP aux feedback loop gain */ 1185 hp_aux_feedback_loop_gain_ramp(priv, false); 1186 1187 /* Disable HP driver core circuits */ 1188 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1189 0x3 << 4, 0x0); 1190 /* Disable LO driver core circuits */ 1191 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1192 0x1, 0x0); 1193 1194 /* Disable HP driver bias circuits */ 1195 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1196 0x3 << 6, 0x0); 1197 /* Disable LO driver bias circuits */ 1198 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 1199 0x1 << 1, 0x0); 1200 1201 /* Disable HP aux CMFB loop */ 1202 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1203 0xff << 8, 0x0000); 1204 1205 /* Disable IBIST */ 1206 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1207 0x1 << 8, 0x1 << 8); 1208 /* Disable NV regulator (-1.2V) */ 1209 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x1, 0x0); 1210 /* Disable cap-less LDOs (1.5V) */ 1211 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 0x1055, 0x0); 1212 /* Disable NCP */ 1213 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x1, 0x1); 1214 1215 /* Set HP CMFB gate rstb */ 1216 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON4, 1217 0x1 << 6, 0x0); 1218 /* disable Pull-down HPL/R to AVSS28_AUD */ 1219 hp_pull_down(priv, false); 1220 1221 return 0; 1222 } 1223 1224 static int mt_hp_event(struct snd_soc_dapm_widget *w, 1225 struct snd_kcontrol *kcontrol, 1226 int event) 1227 { 1228 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1229 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1230 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1231 int device = DEVICE_HP; 1232 1233 dev_info(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n", 1234 __func__, 1235 event, 1236 priv->dev_counter[device], 1237 mux); 1238 1239 switch (event) { 1240 case SND_SOC_DAPM_PRE_PMU: 1241 priv->dev_counter[device]++; 1242 if (priv->dev_counter[device] > 1) 1243 break; /* already enabled, do nothing */ 1244 else if (priv->dev_counter[device] <= 0) 1245 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d <= 0\n", 1246 __func__, 1247 priv->dev_counter[device]); 1248 1249 priv->mux_select[MUX_HP_L] = mux; 1250 1251 if (mux == HP_MUX_HP) 1252 mtk_hp_enable(priv); 1253 else if (mux == HP_MUX_HPSPK) 1254 mtk_hp_spk_enable(priv); 1255 break; 1256 case SND_SOC_DAPM_PRE_PMD: 1257 priv->dev_counter[device]--; 1258 if (priv->dev_counter[device] > 0) { 1259 break; /* still being used, don't close */ 1260 } else if (priv->dev_counter[device] < 0) { 1261 dev_warn(priv->dev, "%s(), dev_counter[DEV_HP] %d < 0\n", 1262 __func__, 1263 priv->dev_counter[device]); 1264 priv->dev_counter[device] = 0; 1265 break; 1266 } 1267 1268 if (priv->mux_select[MUX_HP_L] == HP_MUX_HP) 1269 mtk_hp_disable(priv); 1270 else if (priv->mux_select[MUX_HP_L] == HP_MUX_HPSPK) 1271 mtk_hp_spk_disable(priv); 1272 1273 priv->mux_select[MUX_HP_L] = mux; 1274 break; 1275 default: 1276 break; 1277 } 1278 1279 return 0; 1280 } 1281 1282 static int mt_rcv_event(struct snd_soc_dapm_widget *w, 1283 struct snd_kcontrol *kcontrol, 1284 int event) 1285 { 1286 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1287 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1288 1289 dev_info(priv->dev, "%s(), event 0x%x, mux %u\n", 1290 __func__, 1291 event, 1292 dapm_kcontrol_get_value(w->kcontrols[0])); 1293 1294 switch (event) { 1295 case SND_SOC_DAPM_PRE_PMU: 1296 /* Reduce ESD resistance of AU_REFN */ 1297 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON2, 0x4000); 1298 1299 /* Turn on DA_600K_NCP_VA18 */ 1300 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON1, 0x0001); 1301 /* Set NCP clock as 604kHz // 26MHz/43 = 604KHz */ 1302 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON2, 0x002c); 1303 /* Toggle RG_DIVCKS_CHG */ 1304 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON0, 0x0001); 1305 /* Set NCP soft start mode as default mode: 100us */ 1306 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON4, 0x0003); 1307 /* Enable NCP */ 1308 regmap_write(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 0x0000); 1309 usleep_range(250, 270); 1310 1311 /* Enable cap-less LDOs (1.5V) */ 1312 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1313 0x1055, 0x1055); 1314 /* Enable NV regulator (-1.2V) */ 1315 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON15, 0x0001); 1316 usleep_range(100, 120); 1317 1318 /* Disable AUD_ZCD */ 1319 hp_zcd_disable(priv); 1320 1321 /* Disable handset short-circuit protection */ 1322 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0010); 1323 1324 /* Enable IBIST */ 1325 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1326 /* Set HP DR bias current optimization, 010: 6uA */ 1327 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON11, 0x4900); 1328 /* Set HP & ZCD bias current optimization */ 1329 /* 01: ZCD: 4uA, HP/HS/LO: 5uA */ 1330 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON12, 0x0055); 1331 /* Set HS STB enhance circuits */ 1332 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0090); 1333 1334 /* Disable HP main CMFB loop */ 1335 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0000); 1336 /* Select CMFB resistor bulk to AC mode */ 1337 /* Selec HS/LO cap size (6.5pF default) */ 1338 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON10, 0x0000); 1339 1340 /* Enable HS driver bias circuits */ 1341 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0092); 1342 /* Enable HS driver core circuits */ 1343 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x0093); 1344 1345 /* Enable AUD_CLK */ 1346 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1347 0x1, 0x1); 1348 1349 /* Enable Audio DAC */ 1350 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON0, 0x0009); 1351 /* Enable low-noise mode of DAC */ 1352 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON9, 0x0001); 1353 /* Switch HS MUX to audio DAC */ 1354 regmap_write(priv->regmap, MT6358_AUDDEC_ANA_CON6, 0x009b); 1355 break; 1356 case SND_SOC_DAPM_PRE_PMD: 1357 /* HS mux to open */ 1358 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1359 RG_AUDHSMUXINPUTSEL_VAUDP15_MASK_SFT, 1360 RCV_MUX_OPEN); 1361 1362 /* Disable Audio DAC */ 1363 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 1364 0x000f, 0x0000); 1365 1366 /* Disable AUD_CLK */ 1367 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1368 0x1, 0x0); 1369 1370 /* decrease HS gain to minimum gain step by step */ 1371 regmap_write(priv->regmap, MT6358_ZCD_CON3, DL_GAIN_N_40DB); 1372 1373 /* Disable HS driver core circuits */ 1374 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1375 0x1, 0x0); 1376 1377 /* Disable HS driver bias circuits */ 1378 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 1379 0x1 << 1, 0x0000); 1380 1381 /* Disable HP aux CMFB loop */ 1382 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1383 0xff << 8, 0x0); 1384 1385 /* Enable HP main CMFB Switch */ 1386 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON9, 1387 0xff << 8, 0x2 << 8); 1388 1389 /* Disable IBIST */ 1390 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON12, 1391 0x1 << 8, 0x1 << 8); 1392 1393 /* Disable NV regulator (-1.2V) */ 1394 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON15, 1395 0x1, 0x0); 1396 /* Disable cap-less LDOs (1.5V) */ 1397 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1398 0x1055, 0x0); 1399 /* Disable NCP */ 1400 regmap_update_bits(priv->regmap, MT6358_AUDNCP_CLKDIV_CON3, 1401 0x1, 0x1); 1402 break; 1403 default: 1404 break; 1405 } 1406 1407 return 0; 1408 } 1409 1410 static int mt_aif_out_event(struct snd_soc_dapm_widget *w, 1411 struct snd_kcontrol *kcontrol, 1412 int event) 1413 { 1414 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1415 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1416 1417 dev_dbg(priv->dev, "%s(), event 0x%x, rate %d\n", 1418 __func__, event, priv->ul_rate); 1419 1420 switch (event) { 1421 case SND_SOC_DAPM_PRE_PMU: 1422 capture_gpio_set(priv); 1423 break; 1424 case SND_SOC_DAPM_POST_PMD: 1425 capture_gpio_reset(priv); 1426 break; 1427 default: 1428 break; 1429 } 1430 1431 return 0; 1432 } 1433 1434 static int mt_adc_supply_event(struct snd_soc_dapm_widget *w, 1435 struct snd_kcontrol *kcontrol, 1436 int event) 1437 { 1438 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1439 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1440 1441 dev_dbg(priv->dev, "%s(), event 0x%x\n", 1442 __func__, event); 1443 1444 switch (event) { 1445 case SND_SOC_DAPM_PRE_PMU: 1446 /* Enable audio ADC CLKGEN */ 1447 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1448 0x1 << 5, 0x1 << 5); 1449 /* ADC CLK from CLKGEN (13MHz) */ 1450 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 1451 0x0000); 1452 /* Enable LCLDO_ENC 1P8V */ 1453 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1454 0x2500, 0x0100); 1455 /* LCLDO_ENC remote sense */ 1456 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1457 0x2500, 0x2500); 1458 break; 1459 case SND_SOC_DAPM_POST_PMD: 1460 /* LCLDO_ENC remote sense off */ 1461 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1462 0x2500, 0x0100); 1463 /* disable LCLDO_ENC 1P8V */ 1464 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON14, 1465 0x2500, 0x0000); 1466 1467 /* ADC CLK from CLKGEN (13MHz) */ 1468 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON3, 0x0000); 1469 /* disable audio ADC CLKGEN */ 1470 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON13, 1471 0x1 << 5, 0x0 << 5); 1472 break; 1473 default: 1474 break; 1475 } 1476 1477 return 0; 1478 } 1479 1480 static int mt6358_amic_enable(struct mt6358_priv *priv) 1481 { 1482 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; 1483 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; 1484 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; 1485 1486 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", 1487 __func__, mic_type, mux_pga_l, mux_pga_r); 1488 1489 if (IS_DCC_BASE(mic_type)) { 1490 /* DCC 50k CLK (from 26M) */ 1491 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1492 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1493 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); 1494 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2061); 1495 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG1, 0x0100); 1496 } 1497 1498 /* mic bias 0 */ 1499 if (mux_pga_l == PGA_MUX_AIN0 || mux_pga_l == PGA_MUX_AIN2 || 1500 mux_pga_r == PGA_MUX_AIN0 || mux_pga_r == PGA_MUX_AIN2) { 1501 switch (mic_type) { 1502 case MIC_TYPE_MUX_DCC_ECM_DIFF: 1503 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1504 0xff00, 0x7700); 1505 break; 1506 case MIC_TYPE_MUX_DCC_ECM_SINGLE: 1507 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1508 0xff00, 0x1100); 1509 break; 1510 default: 1511 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1512 0xff00, 0x0000); 1513 break; 1514 } 1515 /* Enable MICBIAS0, MISBIAS0 = 1P9V */ 1516 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON9, 1517 0xff, 0x21); 1518 } 1519 1520 /* mic bias 1 */ 1521 if (mux_pga_l == PGA_MUX_AIN1 || mux_pga_r == PGA_MUX_AIN1) { 1522 /* Enable MICBIAS1, MISBIAS1 = 2P6V */ 1523 if (mic_type == MIC_TYPE_MUX_DCC_ECM_SINGLE) 1524 regmap_write(priv->regmap, 1525 MT6358_AUDENC_ANA_CON10, 0x0161); 1526 else 1527 regmap_write(priv->regmap, 1528 MT6358_AUDENC_ANA_CON10, 0x0061); 1529 } 1530 1531 if (IS_DCC_BASE(mic_type)) { 1532 /* Audio L/R preamplifier DCC precharge */ 1533 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1534 0xf8ff, 0x0004); 1535 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1536 0xf8ff, 0x0004); 1537 } else { 1538 /* reset reg */ 1539 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1540 0xf8ff, 0x0000); 1541 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1542 0xf8ff, 0x0000); 1543 } 1544 1545 if (mux_pga_l != PGA_MUX_NONE) { 1546 /* L preamplifier input sel */ 1547 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1548 RG_AUDPREAMPLINPUTSEL_MASK_SFT, 1549 mux_pga_l << RG_AUDPREAMPLINPUTSEL_SFT); 1550 1551 /* L preamplifier enable */ 1552 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1553 RG_AUDPREAMPLON_MASK_SFT, 1554 0x1 << RG_AUDPREAMPLON_SFT); 1555 1556 if (IS_DCC_BASE(mic_type)) { 1557 /* L preamplifier DCCEN */ 1558 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1559 RG_AUDPREAMPLDCCEN_MASK_SFT, 1560 0x1 << RG_AUDPREAMPLDCCEN_SFT); 1561 } 1562 1563 /* L ADC input sel : L PGA. Enable audio L ADC */ 1564 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1565 RG_AUDADCLINPUTSEL_MASK_SFT, 1566 ADC_MUX_PREAMPLIFIER << 1567 RG_AUDADCLINPUTSEL_SFT); 1568 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1569 RG_AUDADCLPWRUP_MASK_SFT, 1570 0x1 << RG_AUDADCLPWRUP_SFT); 1571 } 1572 1573 if (mux_pga_r != PGA_MUX_NONE) { 1574 /* R preamplifier input sel */ 1575 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1576 RG_AUDPREAMPRINPUTSEL_MASK_SFT, 1577 mux_pga_r << RG_AUDPREAMPRINPUTSEL_SFT); 1578 1579 /* R preamplifier enable */ 1580 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1581 RG_AUDPREAMPRON_MASK_SFT, 1582 0x1 << RG_AUDPREAMPRON_SFT); 1583 1584 if (IS_DCC_BASE(mic_type)) { 1585 /* R preamplifier DCCEN */ 1586 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1587 RG_AUDPREAMPRDCCEN_MASK_SFT, 1588 0x1 << RG_AUDPREAMPRDCCEN_SFT); 1589 } 1590 1591 /* R ADC input sel : R PGA. Enable audio R ADC */ 1592 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1593 RG_AUDADCRINPUTSEL_MASK_SFT, 1594 ADC_MUX_PREAMPLIFIER << 1595 RG_AUDADCRINPUTSEL_SFT); 1596 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1597 RG_AUDADCRPWRUP_MASK_SFT, 1598 0x1 << RG_AUDADCRPWRUP_SFT); 1599 } 1600 1601 if (IS_DCC_BASE(mic_type)) { 1602 usleep_range(100, 150); 1603 /* Audio L preamplifier DCC precharge off */ 1604 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1605 RG_AUDPREAMPLDCPRECHARGE_MASK_SFT, 0x0); 1606 /* Audio R preamplifier DCC precharge off */ 1607 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1608 RG_AUDPREAMPRDCPRECHARGE_MASK_SFT, 0x0); 1609 1610 /* Short body to ground in PGA */ 1611 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON3, 1612 0x1 << 12, 0x0); 1613 } 1614 1615 /* here to set digital part */ 1616 mt6358_mtkaif_tx_enable(priv); 1617 1618 /* UL dmic setting off */ 1619 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0000); 1620 1621 /* UL turn on */ 1622 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0001); 1623 1624 return 0; 1625 } 1626 1627 static void mt6358_amic_disable(struct mt6358_priv *priv) 1628 { 1629 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE]; 1630 unsigned int mux_pga_l = priv->mux_select[MUX_PGA_L]; 1631 unsigned int mux_pga_r = priv->mux_select[MUX_PGA_R]; 1632 1633 dev_info(priv->dev, "%s(), mux, mic %u, pga l %u, pga r %u\n", 1634 __func__, mic_type, mux_pga_l, mux_pga_r); 1635 1636 /* UL turn off */ 1637 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 1638 0x0001, 0x0000); 1639 1640 /* disable aud_pad TX fifos */ 1641 mt6358_mtkaif_tx_disable(priv); 1642 1643 /* L ADC input sel : off, disable L ADC */ 1644 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1645 0xf000, 0x0000); 1646 /* L preamplifier DCCEN */ 1647 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1648 0x1 << 1, 0x0); 1649 /* L preamplifier input sel : off, L PGA 0 dB gain */ 1650 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1651 0xfffb, 0x0000); 1652 1653 /* disable L preamplifier DCC precharge */ 1654 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON0, 1655 0x1 << 2, 0x0); 1656 1657 /* R ADC input sel : off, disable R ADC */ 1658 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1659 0xf000, 0x0000); 1660 /* R preamplifier DCCEN */ 1661 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1662 0x1 << 1, 0x0); 1663 /* R preamplifier input sel : off, R PGA 0 dB gain */ 1664 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1665 0x0ffb, 0x0000); 1666 1667 /* disable R preamplifier DCC precharge */ 1668 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON1, 1669 0x1 << 2, 0x0); 1670 1671 /* mic bias */ 1672 /* Disable MICBIAS0, MISBIAS0 = 1P7V */ 1673 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); 1674 1675 /* Disable MICBIAS1 */ 1676 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1677 0x0001, 0x0000); 1678 1679 if (IS_DCC_BASE(mic_type)) { 1680 /* dcclk_gen_on=1'b0 */ 1681 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2060); 1682 /* dcclk_pdn=1'b1 */ 1683 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1684 /* dcclk_ref_ck_sel=2'b00 */ 1685 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1686 /* dcclk_div=11'b00100000011 */ 1687 regmap_write(priv->regmap, MT6358_AFE_DCCLK_CFG0, 0x2062); 1688 } 1689 } 1690 1691 static int mt6358_dmic_enable(struct mt6358_priv *priv) 1692 { 1693 dev_info(priv->dev, "%s()\n", __func__); 1694 1695 /* mic bias */ 1696 /* Enable MICBIAS0, MISBIAS0 = 1P9V */ 1697 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0021); 1698 1699 /* RG_BANDGAPGEN=1'b0 */ 1700 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1701 0x1 << 12, 0x0); 1702 1703 /* DMIC enable */ 1704 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0005); 1705 1706 /* here to set digital part */ 1707 mt6358_mtkaif_tx_enable(priv); 1708 1709 /* UL dmic setting */ 1710 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_H, 0x0080); 1711 1712 /* UL turn on */ 1713 regmap_write(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 0x0003); 1714 return 0; 1715 } 1716 1717 static void mt6358_dmic_disable(struct mt6358_priv *priv) 1718 { 1719 dev_info(priv->dev, "%s()\n", __func__); 1720 1721 /* UL turn off */ 1722 regmap_update_bits(priv->regmap, MT6358_AFE_UL_SRC_CON0_L, 1723 0x0003, 0x0000); 1724 1725 /* disable aud_pad TX fifos */ 1726 mt6358_mtkaif_tx_disable(priv); 1727 1728 /* DMIC disable */ 1729 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON8, 0x0000); 1730 1731 /* mic bias */ 1732 /* MISBIAS0 = 1P7V */ 1733 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0001); 1734 1735 /* RG_BANDGAPGEN=1'b0 */ 1736 regmap_update_bits(priv->regmap, MT6358_AUDENC_ANA_CON10, 1737 0x1 << 12, 0x0); 1738 1739 /* MICBIA0 disable */ 1740 regmap_write(priv->regmap, MT6358_AUDENC_ANA_CON9, 0x0000); 1741 } 1742 1743 static int mt_mic_type_event(struct snd_soc_dapm_widget *w, 1744 struct snd_kcontrol *kcontrol, 1745 int event) 1746 { 1747 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1748 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1749 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1750 1751 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n", 1752 __func__, event, mux); 1753 1754 switch (event) { 1755 case SND_SOC_DAPM_WILL_PMU: 1756 priv->mux_select[MUX_MIC_TYPE] = mux; 1757 break; 1758 case SND_SOC_DAPM_PRE_PMU: 1759 switch (mux) { 1760 case MIC_TYPE_MUX_DMIC: 1761 mt6358_dmic_enable(priv); 1762 break; 1763 default: 1764 mt6358_amic_enable(priv); 1765 break; 1766 } 1767 1768 break; 1769 case SND_SOC_DAPM_POST_PMD: 1770 switch (priv->mux_select[MUX_MIC_TYPE]) { 1771 case MIC_TYPE_MUX_DMIC: 1772 mt6358_dmic_disable(priv); 1773 break; 1774 default: 1775 mt6358_amic_disable(priv); 1776 break; 1777 } 1778 1779 priv->mux_select[MUX_MIC_TYPE] = mux; 1780 break; 1781 default: 1782 break; 1783 } 1784 1785 return 0; 1786 } 1787 1788 static int mt_adc_l_event(struct snd_soc_dapm_widget *w, 1789 struct snd_kcontrol *kcontrol, 1790 int event) 1791 { 1792 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1793 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1794 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1795 1796 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1797 __func__, event, mux); 1798 1799 priv->mux_select[MUX_ADC_L] = mux; 1800 1801 return 0; 1802 } 1803 1804 static int mt_adc_r_event(struct snd_soc_dapm_widget *w, 1805 struct snd_kcontrol *kcontrol, 1806 int event) 1807 { 1808 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1809 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1810 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1811 1812 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1813 __func__, event, mux); 1814 1815 priv->mux_select[MUX_ADC_R] = mux; 1816 1817 return 0; 1818 } 1819 1820 static int mt_pga_left_event(struct snd_soc_dapm_widget *w, 1821 struct snd_kcontrol *kcontrol, 1822 int event) 1823 { 1824 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1825 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1826 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1827 1828 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1829 __func__, event, mux); 1830 1831 priv->mux_select[MUX_PGA_L] = mux; 1832 1833 return 0; 1834 } 1835 1836 static int mt_pga_right_event(struct snd_soc_dapm_widget *w, 1837 struct snd_kcontrol *kcontrol, 1838 int event) 1839 { 1840 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 1841 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 1842 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]); 1843 1844 dev_dbg(priv->dev, "%s(), event = 0x%x, mux %u\n", 1845 __func__, event, mux); 1846 1847 priv->mux_select[MUX_PGA_R] = mux; 1848 1849 return 0; 1850 } 1851 1852 static int mt_delay_250_event(struct snd_soc_dapm_widget *w, 1853 struct snd_kcontrol *kcontrol, 1854 int event) 1855 { 1856 switch (event) { 1857 case SND_SOC_DAPM_POST_PMU: 1858 usleep_range(250, 270); 1859 break; 1860 case SND_SOC_DAPM_PRE_PMD: 1861 usleep_range(250, 270); 1862 break; 1863 default: 1864 break; 1865 } 1866 1867 return 0; 1868 } 1869 1870 /* DAPM Widgets */ 1871 static const struct snd_soc_dapm_widget mt6358_dapm_widgets[] = { 1872 /* Global Supply*/ 1873 SND_SOC_DAPM_SUPPLY_S("CLK_BUF", SUPPLY_SEQ_CLK_BUF, 1874 MT6358_DCXO_CW14, 1875 RG_XO_AUDIO_EN_M_SFT, 0, NULL, 0), 1876 SND_SOC_DAPM_SUPPLY_S("AUDGLB", SUPPLY_SEQ_AUD_GLB, 1877 MT6358_AUDDEC_ANA_CON13, 1878 RG_AUDGLB_PWRDN_VA28_SFT, 1, NULL, 0), 1879 SND_SOC_DAPM_SUPPLY_S("CLKSQ Audio", SUPPLY_SEQ_CLKSQ, 1880 MT6358_AUDENC_ANA_CON6, 1881 RG_CLKSQ_EN_SFT, 0, 1882 mt_clksq_event, 1883 SND_SOC_DAPM_PRE_PMU), 1884 SND_SOC_DAPM_SUPPLY_S("AUDNCP_CK", SUPPLY_SEQ_TOP_CK, 1885 MT6358_AUD_TOP_CKPDN_CON0, 1886 RG_AUDNCP_CK_PDN_SFT, 1, NULL, 0), 1887 SND_SOC_DAPM_SUPPLY_S("ZCD13M_CK", SUPPLY_SEQ_TOP_CK, 1888 MT6358_AUD_TOP_CKPDN_CON0, 1889 RG_ZCD13M_CK_PDN_SFT, 1, NULL, 0), 1890 SND_SOC_DAPM_SUPPLY_S("AUD_CK", SUPPLY_SEQ_TOP_CK_LAST, 1891 MT6358_AUD_TOP_CKPDN_CON0, 1892 RG_AUD_CK_PDN_SFT, 1, 1893 mt_delay_250_event, 1894 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1895 SND_SOC_DAPM_SUPPLY_S("AUDIF_CK", SUPPLY_SEQ_TOP_CK, 1896 MT6358_AUD_TOP_CKPDN_CON0, 1897 RG_AUDIF_CK_PDN_SFT, 1, NULL, 0), 1898 1899 /* Digital Clock */ 1900 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_AFE_CTL", SUPPLY_SEQ_AUD_TOP_LAST, 1901 MT6358_AUDIO_TOP_CON0, 1902 PDN_AFE_CTL_SFT, 1, 1903 mt_delay_250_event, 1904 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 1905 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_DAC_CTL", SUPPLY_SEQ_AUD_TOP, 1906 MT6358_AUDIO_TOP_CON0, 1907 PDN_DAC_CTL_SFT, 1, NULL, 0), 1908 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_ADC_CTL", SUPPLY_SEQ_AUD_TOP, 1909 MT6358_AUDIO_TOP_CON0, 1910 PDN_ADC_CTL_SFT, 1, NULL, 0), 1911 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_I2S_DL", SUPPLY_SEQ_AUD_TOP, 1912 MT6358_AUDIO_TOP_CON0, 1913 PDN_I2S_DL_CTL_SFT, 1, NULL, 0), 1914 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PWR_CLK", SUPPLY_SEQ_AUD_TOP, 1915 MT6358_AUDIO_TOP_CON0, 1916 PWR_CLK_DIS_CTL_SFT, 1, NULL, 0), 1917 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_AFE_TESTMODEL", SUPPLY_SEQ_AUD_TOP, 1918 MT6358_AUDIO_TOP_CON0, 1919 PDN_AFE_TESTMODEL_CTL_SFT, 1, NULL, 0), 1920 SND_SOC_DAPM_SUPPLY_S("AUDIO_TOP_PDN_RESERVED", SUPPLY_SEQ_AUD_TOP, 1921 MT6358_AUDIO_TOP_CON0, 1922 PDN_RESERVED_SFT, 1, NULL, 0), 1923 1924 SND_SOC_DAPM_SUPPLY("DL Digital Clock", SND_SOC_NOPM, 1925 0, 0, NULL, 0), 1926 1927 /* AFE ON */ 1928 SND_SOC_DAPM_SUPPLY_S("AFE_ON", SUPPLY_SEQ_AFE, 1929 MT6358_AFE_UL_DL_CON0, AFE_ON_SFT, 0, 1930 NULL, 0), 1931 1932 /* AIF Rx*/ 1933 SND_SOC_DAPM_AIF_IN_E("AIF_RX", "AIF1 Playback", 0, 1934 MT6358_AFE_DL_SRC2_CON0_L, 1935 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, 1936 mt_aif_in_event, 1937 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1938 1939 /* DL Supply */ 1940 SND_SOC_DAPM_SUPPLY("DL Power Supply", SND_SOC_NOPM, 1941 0, 0, NULL, 0), 1942 1943 /* DAC */ 1944 SND_SOC_DAPM_MUX("DAC In Mux", SND_SOC_NOPM, 0, 0, &dac_in_mux_control), 1945 1946 SND_SOC_DAPM_DAC("DACL", NULL, SND_SOC_NOPM, 0, 0), 1947 1948 SND_SOC_DAPM_DAC("DACR", NULL, SND_SOC_NOPM, 0, 0), 1949 1950 /* LOL */ 1951 SND_SOC_DAPM_MUX("LOL Mux", SND_SOC_NOPM, 0, 0, &lo_in_mux_control), 1952 1953 SND_SOC_DAPM_SUPPLY("LO Stability Enh", MT6358_AUDDEC_ANA_CON7, 1954 RG_LOOUTPUTSTBENH_VAUDP15_SFT, 0, NULL, 0), 1955 1956 SND_SOC_DAPM_OUT_DRV("LOL Buffer", MT6358_AUDDEC_ANA_CON7, 1957 RG_AUDLOLPWRUP_VAUDP15_SFT, 0, NULL, 0), 1958 1959 /* Headphone */ 1960 SND_SOC_DAPM_MUX_E("HPL Mux", SND_SOC_NOPM, 0, 0, 1961 &hpl_in_mux_control, 1962 mt_hp_event, 1963 SND_SOC_DAPM_PRE_PMU | 1964 SND_SOC_DAPM_PRE_PMD), 1965 1966 SND_SOC_DAPM_MUX_E("HPR Mux", SND_SOC_NOPM, 0, 0, 1967 &hpr_in_mux_control, 1968 mt_hp_event, 1969 SND_SOC_DAPM_PRE_PMU | 1970 SND_SOC_DAPM_PRE_PMD), 1971 1972 /* Receiver */ 1973 SND_SOC_DAPM_MUX_E("RCV Mux", SND_SOC_NOPM, 0, 0, 1974 &rcv_in_mux_control, 1975 mt_rcv_event, 1976 SND_SOC_DAPM_PRE_PMU | 1977 SND_SOC_DAPM_PRE_PMD), 1978 1979 /* Outputs */ 1980 SND_SOC_DAPM_OUTPUT("Receiver"), 1981 SND_SOC_DAPM_OUTPUT("Headphone L"), 1982 SND_SOC_DAPM_OUTPUT("Headphone R"), 1983 SND_SOC_DAPM_OUTPUT("Headphone L Ext Spk Amp"), 1984 SND_SOC_DAPM_OUTPUT("Headphone R Ext Spk Amp"), 1985 SND_SOC_DAPM_OUTPUT("LINEOUT L"), 1986 SND_SOC_DAPM_OUTPUT("LINEOUT L HSSPK"), 1987 1988 /* SGEN */ 1989 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6358_AFE_SGEN_CFG0, 1990 SGEN_DAC_EN_CTL_SFT, 0, NULL, 0), 1991 SND_SOC_DAPM_SUPPLY("SGEN MUTE", MT6358_AFE_SGEN_CFG0, 1992 SGEN_MUTE_SW_CTL_SFT, 1, 1993 mt_sgen_event, 1994 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1995 SND_SOC_DAPM_SUPPLY("SGEN DL SRC", MT6358_AFE_DL_SRC2_CON0_L, 1996 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, NULL, 0), 1997 1998 SND_SOC_DAPM_INPUT("SGEN DL"), 1999 2000 /* Uplinks */ 2001 SND_SOC_DAPM_AIF_OUT_E("AIF1TX", "AIF1 Capture", 0, 2002 SND_SOC_NOPM, 0, 0, 2003 mt_aif_out_event, 2004 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2005 2006 SND_SOC_DAPM_SUPPLY_S("ADC Supply", SUPPLY_SEQ_ADC_SUPPLY, 2007 SND_SOC_NOPM, 0, 0, 2008 mt_adc_supply_event, 2009 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2010 2011 /* Uplinks MUX */ 2012 SND_SOC_DAPM_MUX("AIF Out Mux", SND_SOC_NOPM, 0, 0, 2013 &aif_out_mux_control), 2014 2015 SND_SOC_DAPM_MUX_E("Mic Type Mux", SND_SOC_NOPM, 0, 0, 2016 &mic_type_mux_control, 2017 mt_mic_type_event, 2018 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD | 2019 SND_SOC_DAPM_WILL_PMU), 2020 2021 SND_SOC_DAPM_MUX_E("ADC L Mux", SND_SOC_NOPM, 0, 0, 2022 &adc_left_mux_control, 2023 mt_adc_l_event, 2024 SND_SOC_DAPM_WILL_PMU), 2025 SND_SOC_DAPM_MUX_E("ADC R Mux", SND_SOC_NOPM, 0, 0, 2026 &adc_right_mux_control, 2027 mt_adc_r_event, 2028 SND_SOC_DAPM_WILL_PMU), 2029 2030 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0), 2031 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0), 2032 2033 SND_SOC_DAPM_MUX_E("PGA L Mux", SND_SOC_NOPM, 0, 0, 2034 &pga_left_mux_control, 2035 mt_pga_left_event, 2036 SND_SOC_DAPM_WILL_PMU), 2037 SND_SOC_DAPM_MUX_E("PGA R Mux", SND_SOC_NOPM, 0, 0, 2038 &pga_right_mux_control, 2039 mt_pga_right_event, 2040 SND_SOC_DAPM_WILL_PMU), 2041 2042 SND_SOC_DAPM_PGA("PGA L", SND_SOC_NOPM, 0, 0, NULL, 0), 2043 SND_SOC_DAPM_PGA("PGA R", SND_SOC_NOPM, 0, 0, NULL, 0), 2044 2045 /* UL input */ 2046 SND_SOC_DAPM_INPUT("AIN0"), 2047 SND_SOC_DAPM_INPUT("AIN1"), 2048 SND_SOC_DAPM_INPUT("AIN2"), 2049 }; 2050 2051 static const struct snd_soc_dapm_route mt6358_dapm_routes[] = { 2052 /* Capture */ 2053 {"AIF1TX", NULL, "AIF Out Mux"}, 2054 {"AIF1TX", NULL, "CLK_BUF"}, 2055 {"AIF1TX", NULL, "AUDGLB"}, 2056 {"AIF1TX", NULL, "CLKSQ Audio"}, 2057 2058 {"AIF1TX", NULL, "AUD_CK"}, 2059 {"AIF1TX", NULL, "AUDIF_CK"}, 2060 2061 {"AIF1TX", NULL, "AUDIO_TOP_AFE_CTL"}, 2062 {"AIF1TX", NULL, "AUDIO_TOP_ADC_CTL"}, 2063 {"AIF1TX", NULL, "AUDIO_TOP_PWR_CLK"}, 2064 {"AIF1TX", NULL, "AUDIO_TOP_PDN_RESERVED"}, 2065 {"AIF1TX", NULL, "AUDIO_TOP_I2S_DL"}, 2066 2067 {"AIF1TX", NULL, "AFE_ON"}, 2068 2069 {"AIF Out Mux", NULL, "Mic Type Mux"}, 2070 2071 {"Mic Type Mux", "ACC", "ADC L"}, 2072 {"Mic Type Mux", "ACC", "ADC R"}, 2073 {"Mic Type Mux", "DCC", "ADC L"}, 2074 {"Mic Type Mux", "DCC", "ADC R"}, 2075 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC L"}, 2076 {"Mic Type Mux", "DCC_ECM_DIFF", "ADC R"}, 2077 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC L"}, 2078 {"Mic Type Mux", "DCC_ECM_SINGLE", "ADC R"}, 2079 {"Mic Type Mux", "DMIC", "AIN0"}, 2080 {"Mic Type Mux", "DMIC", "AIN2"}, 2081 2082 {"ADC L", NULL, "ADC L Mux"}, 2083 {"ADC L", NULL, "ADC Supply"}, 2084 {"ADC R", NULL, "ADC R Mux"}, 2085 {"ADC R", NULL, "ADC Supply"}, 2086 2087 {"ADC L Mux", "Left Preamplifier", "PGA L"}, 2088 2089 {"ADC R Mux", "Right Preamplifier", "PGA R"}, 2090 2091 {"PGA L", NULL, "PGA L Mux"}, 2092 {"PGA R", NULL, "PGA R Mux"}, 2093 2094 {"PGA L Mux", "AIN0", "AIN0"}, 2095 {"PGA L Mux", "AIN1", "AIN1"}, 2096 {"PGA L Mux", "AIN2", "AIN2"}, 2097 2098 {"PGA R Mux", "AIN0", "AIN0"}, 2099 {"PGA R Mux", "AIN1", "AIN1"}, 2100 {"PGA R Mux", "AIN2", "AIN2"}, 2101 2102 /* DL Supply */ 2103 {"DL Power Supply", NULL, "CLK_BUF"}, 2104 {"DL Power Supply", NULL, "AUDGLB"}, 2105 {"DL Power Supply", NULL, "CLKSQ Audio"}, 2106 2107 {"DL Power Supply", NULL, "AUDNCP_CK"}, 2108 {"DL Power Supply", NULL, "ZCD13M_CK"}, 2109 {"DL Power Supply", NULL, "AUD_CK"}, 2110 {"DL Power Supply", NULL, "AUDIF_CK"}, 2111 2112 /* DL Digital Supply */ 2113 {"DL Digital Clock", NULL, "AUDIO_TOP_AFE_CTL"}, 2114 {"DL Digital Clock", NULL, "AUDIO_TOP_DAC_CTL"}, 2115 {"DL Digital Clock", NULL, "AUDIO_TOP_PWR_CLK"}, 2116 2117 {"DL Digital Clock", NULL, "AFE_ON"}, 2118 2119 {"AIF_RX", NULL, "DL Digital Clock"}, 2120 2121 /* DL Path */ 2122 {"DAC In Mux", "Normal Path", "AIF_RX"}, 2123 2124 {"DAC In Mux", "Sgen", "SGEN DL"}, 2125 {"SGEN DL", NULL, "SGEN DL SRC"}, 2126 {"SGEN DL", NULL, "SGEN MUTE"}, 2127 {"SGEN DL", NULL, "SGEN DL Enable"}, 2128 {"SGEN DL", NULL, "DL Digital Clock"}, 2129 {"SGEN DL", NULL, "AUDIO_TOP_PDN_AFE_TESTMODEL"}, 2130 2131 {"DACL", NULL, "DAC In Mux"}, 2132 {"DACL", NULL, "DL Power Supply"}, 2133 2134 {"DACR", NULL, "DAC In Mux"}, 2135 {"DACR", NULL, "DL Power Supply"}, 2136 2137 /* Lineout Path */ 2138 {"LOL Mux", "Playback", "DACL"}, 2139 2140 {"LOL Buffer", NULL, "LOL Mux"}, 2141 {"LOL Buffer", NULL, "LO Stability Enh"}, 2142 2143 {"LINEOUT L", NULL, "LOL Buffer"}, 2144 2145 /* Headphone Path */ 2146 {"HPL Mux", "Audio Playback", "DACL"}, 2147 {"HPR Mux", "Audio Playback", "DACR"}, 2148 {"HPL Mux", "HP Impedance", "DACL"}, 2149 {"HPR Mux", "HP Impedance", "DACR"}, 2150 {"HPL Mux", "LoudSPK Playback", "DACL"}, 2151 {"HPR Mux", "LoudSPK Playback", "DACR"}, 2152 2153 {"Headphone L", NULL, "HPL Mux"}, 2154 {"Headphone R", NULL, "HPR Mux"}, 2155 {"Headphone L Ext Spk Amp", NULL, "HPL Mux"}, 2156 {"Headphone R Ext Spk Amp", NULL, "HPR Mux"}, 2157 {"LINEOUT L HSSPK", NULL, "HPL Mux"}, 2158 2159 /* Receiver Path */ 2160 {"RCV Mux", "Voice Playback", "DACL"}, 2161 {"Receiver", NULL, "RCV Mux"}, 2162 }; 2163 2164 static int mt6358_codec_dai_hw_params(struct snd_pcm_substream *substream, 2165 struct snd_pcm_hw_params *params, 2166 struct snd_soc_dai *dai) 2167 { 2168 struct snd_soc_component *cmpnt = dai->component; 2169 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2170 unsigned int rate = params_rate(params); 2171 2172 dev_info(priv->dev, "%s(), substream->stream %d, rate %d, number %d\n", 2173 __func__, 2174 substream->stream, 2175 rate, 2176 substream->number); 2177 2178 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 2179 priv->dl_rate = rate; 2180 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 2181 priv->ul_rate = rate; 2182 2183 return 0; 2184 } 2185 2186 static const struct snd_soc_dai_ops mt6358_codec_dai_ops = { 2187 .hw_params = mt6358_codec_dai_hw_params, 2188 }; 2189 2190 #define MT6358_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |\ 2191 SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE |\ 2192 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_BE |\ 2193 SNDRV_PCM_FMTBIT_U24_LE | SNDRV_PCM_FMTBIT_U24_BE |\ 2194 SNDRV_PCM_FMTBIT_S32_LE | SNDRV_PCM_FMTBIT_S32_BE |\ 2195 SNDRV_PCM_FMTBIT_U32_LE | SNDRV_PCM_FMTBIT_U32_BE) 2196 2197 static struct snd_soc_dai_driver mt6358_dai_driver[] = { 2198 { 2199 .name = "mt6358-snd-codec-aif1", 2200 .playback = { 2201 .stream_name = "AIF1 Playback", 2202 .channels_min = 1, 2203 .channels_max = 2, 2204 .rates = SNDRV_PCM_RATE_8000_48000 | 2205 SNDRV_PCM_RATE_96000 | 2206 SNDRV_PCM_RATE_192000, 2207 .formats = MT6358_FORMATS, 2208 }, 2209 .capture = { 2210 .stream_name = "AIF1 Capture", 2211 .channels_min = 1, 2212 .channels_max = 2, 2213 .rates = SNDRV_PCM_RATE_8000 | 2214 SNDRV_PCM_RATE_16000 | 2215 SNDRV_PCM_RATE_32000 | 2216 SNDRV_PCM_RATE_48000, 2217 .formats = MT6358_FORMATS, 2218 }, 2219 .ops = &mt6358_codec_dai_ops, 2220 }, 2221 }; 2222 2223 static int mt6358_codec_init_reg(struct mt6358_priv *priv) 2224 { 2225 int ret = 0; 2226 2227 /* Disable HeadphoneL/HeadphoneR short circuit protection */ 2228 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 2229 RG_AUDHPLSCDISABLE_VAUDP15_MASK_SFT, 2230 0x1 << RG_AUDHPLSCDISABLE_VAUDP15_SFT); 2231 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON0, 2232 RG_AUDHPRSCDISABLE_VAUDP15_MASK_SFT, 2233 0x1 << RG_AUDHPRSCDISABLE_VAUDP15_SFT); 2234 /* Disable voice short circuit protection */ 2235 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON6, 2236 RG_AUDHSSCDISABLE_VAUDP15_MASK_SFT, 2237 0x1 << RG_AUDHSSCDISABLE_VAUDP15_SFT); 2238 /* disable LO buffer left short circuit protection */ 2239 regmap_update_bits(priv->regmap, MT6358_AUDDEC_ANA_CON7, 2240 RG_AUDLOLSCDISABLE_VAUDP15_MASK_SFT, 2241 0x1 << RG_AUDLOLSCDISABLE_VAUDP15_SFT); 2242 2243 /* accdet s/w enable */ 2244 regmap_update_bits(priv->regmap, MT6358_ACCDET_CON13, 2245 0xFFFF, 0x700E); 2246 2247 /* gpio miso driving set to 4mA */ 2248 regmap_write(priv->regmap, MT6358_DRV_CON3, 0x8888); 2249 2250 /* set gpio */ 2251 playback_gpio_reset(priv); 2252 capture_gpio_reset(priv); 2253 2254 return ret; 2255 } 2256 2257 static int mt6358_codec_probe(struct snd_soc_component *cmpnt) 2258 { 2259 struct mt6358_priv *priv = snd_soc_component_get_drvdata(cmpnt); 2260 int ret; 2261 2262 snd_soc_component_init_regmap(cmpnt, priv->regmap); 2263 2264 mt6358_codec_init_reg(priv); 2265 2266 priv->avdd_reg = devm_regulator_get(priv->dev, "Avdd"); 2267 if (IS_ERR(priv->avdd_reg)) { 2268 dev_err(priv->dev, "%s() have no Avdd supply", __func__); 2269 return PTR_ERR(priv->avdd_reg); 2270 } 2271 2272 ret = regulator_enable(priv->avdd_reg); 2273 if (ret) 2274 return ret; 2275 2276 return 0; 2277 } 2278 2279 static const struct snd_soc_component_driver mt6358_soc_component_driver = { 2280 .probe = mt6358_codec_probe, 2281 .controls = mt6358_snd_controls, 2282 .num_controls = ARRAY_SIZE(mt6358_snd_controls), 2283 .dapm_widgets = mt6358_dapm_widgets, 2284 .num_dapm_widgets = ARRAY_SIZE(mt6358_dapm_widgets), 2285 .dapm_routes = mt6358_dapm_routes, 2286 .num_dapm_routes = ARRAY_SIZE(mt6358_dapm_routes), 2287 }; 2288 2289 static int mt6358_platform_driver_probe(struct platform_device *pdev) 2290 { 2291 struct mt6358_priv *priv; 2292 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent); 2293 2294 priv = devm_kzalloc(&pdev->dev, 2295 sizeof(struct mt6358_priv), 2296 GFP_KERNEL); 2297 if (!priv) 2298 return -ENOMEM; 2299 2300 dev_set_drvdata(&pdev->dev, priv); 2301 2302 priv->dev = &pdev->dev; 2303 2304 priv->regmap = mt6397->regmap; 2305 if (IS_ERR(priv->regmap)) 2306 return PTR_ERR(priv->regmap); 2307 2308 dev_info(priv->dev, "%s(), dev name %s\n", 2309 __func__, dev_name(&pdev->dev)); 2310 2311 return devm_snd_soc_register_component(&pdev->dev, 2312 &mt6358_soc_component_driver, 2313 mt6358_dai_driver, 2314 ARRAY_SIZE(mt6358_dai_driver)); 2315 } 2316 2317 static const struct of_device_id mt6358_of_match[] = { 2318 {.compatible = "mediatek,mt6358-sound",}, 2319 {} 2320 }; 2321 MODULE_DEVICE_TABLE(of, mt6358_of_match); 2322 2323 static struct platform_driver mt6358_platform_driver = { 2324 .driver = { 2325 .name = "mt6358-sound", 2326 .of_match_table = mt6358_of_match, 2327 }, 2328 .probe = mt6358_platform_driver_probe, 2329 }; 2330 2331 module_platform_driver(mt6358_platform_driver) 2332 2333 /* Module information */ 2334 MODULE_DESCRIPTION("MT6358 ALSA SoC codec driver"); 2335 MODULE_AUTHOR("KaiChieh Chuang <kaichieh.chuang@mediatek.com>"); 2336 MODULE_LICENSE("GPL v2"); 2337