1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2016, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/err.h> 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/regulator/consumer.h> 9 #include <linux/types.h> 10 #include <linux/clk.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <sound/soc.h> 15 #include <sound/pcm.h> 16 #include <sound/pcm_params.h> 17 #include <sound/tlv.h> 18 #include <sound/jack.h> 19 20 #define CDC_D_REVISION1 (0xf000) 21 #define CDC_D_PERPH_SUBTYPE (0xf005) 22 #define CDC_D_INT_EN_SET (0x015) 23 #define CDC_D_INT_EN_CLR (0x016) 24 #define MBHC_SWITCH_INT BIT(7) 25 #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6) 26 #define MBHC_BUTTON_PRESS_DET BIT(5) 27 #define MBHC_BUTTON_RELEASE_DET BIT(4) 28 #define CDC_D_CDC_RST_CTL (0xf046) 29 #define RST_CTL_DIG_SW_RST_N_MASK BIT(7) 30 #define RST_CTL_DIG_SW_RST_N_RESET 0 31 #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7) 32 33 #define CDC_D_CDC_TOP_CLK_CTL (0xf048) 34 #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3)) 35 #define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2) 36 #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3) 37 38 #define CDC_D_CDC_ANA_CLK_CTL (0xf049) 39 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0) 40 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0) 41 #define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1) 42 #define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4) 43 #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4) 44 #define ANA_CLK_CTL_TXA_CLK25_EN BIT(5) 45 46 #define CDC_D_CDC_DIG_CLK_CTL (0xf04A) 47 #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0) 48 #define DIG_CLK_CTL_RXD2_CLK_EN BIT(1) 49 #define DIG_CLK_CTL_RXD3_CLK_EN BIT(2) 50 #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3) 51 #define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3) 52 #define DIG_CLK_CTL_TXD_CLK_EN BIT(4) 53 #define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6) 54 #define DIG_CLK_CTL_NCP_CLK_EN BIT(6) 55 #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7) 56 #define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7) 57 58 #define CDC_D_CDC_CONN_TX1_CTL (0xf050) 59 #define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0) 60 #define CONN_TX1_SERIAL_TX1_ADC_1 0x0 61 #define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1 62 #define CONN_TX1_SERIAL_TX1_ZERO 0x2 63 64 #define CDC_D_CDC_CONN_TX2_CTL (0xf051) 65 #define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0) 66 #define CONN_TX2_SERIAL_TX2_ADC_2 0x0 67 #define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1 68 #define CONN_TX2_SERIAL_TX2_ZERO 0x2 69 #define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052) 70 #define CDC_D_CDC_CONN_RX1_CTL (0xf053) 71 #define CDC_D_CDC_CONN_RX2_CTL (0xf054) 72 #define CDC_D_CDC_CONN_RX3_CTL (0xf055) 73 #define CDC_D_CDC_CONN_RX_LB_CTL (0xf056) 74 #define CDC_D_SEC_ACCESS (0xf0D0) 75 #define CDC_D_PERPH_RESET_CTL3 (0xf0DA) 76 #define CDC_D_PERPH_RESET_CTL4 (0xf0DB) 77 #define CDC_A_REVISION1 (0xf100) 78 #define CDC_A_REVISION2 (0xf101) 79 #define CDC_A_REVISION3 (0xf102) 80 #define CDC_A_REVISION4 (0xf103) 81 #define CDC_A_PERPH_TYPE (0xf104) 82 #define CDC_A_PERPH_SUBTYPE (0xf105) 83 #define CDC_A_INT_RT_STS (0xf110) 84 #define CDC_A_INT_SET_TYPE (0xf111) 85 #define CDC_A_INT_POLARITY_HIGH (0xf112) 86 #define CDC_A_INT_POLARITY_LOW (0xf113) 87 #define CDC_A_INT_LATCHED_CLR (0xf114) 88 #define CDC_A_INT_EN_SET (0xf115) 89 #define CDC_A_INT_EN_CLR (0xf116) 90 #define CDC_A_INT_LATCHED_STS (0xf118) 91 #define CDC_A_INT_PENDING_STS (0xf119) 92 #define CDC_A_INT_MID_SEL (0xf11A) 93 #define CDC_A_INT_PRIORITY (0xf11B) 94 #define CDC_A_MICB_1_EN (0xf140) 95 #define MICB_1_EN_MICB_ENABLE BIT(7) 96 #define MICB_1_EN_BYP_CAP_MASK BIT(6) 97 #define MICB_1_EN_NO_EXT_BYP_CAP BIT(6) 98 #define MICB_1_EN_EXT_BYP_CAP 0 99 #define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5) 100 #define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5) 101 #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1) 102 #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4) 103 #define MICB_1_EN_PULL_UP_EN_MASK BIT(4) 104 #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0) 105 #define MICB_1_EN_TX3_GND_SEL_TX_GND 0 106 107 #define CDC_A_MICB_1_VAL (0xf141) 108 #define MICB_MIN_VAL 1600 109 #define MICB_STEP_SIZE 50 110 #define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3) 111 #define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3) 112 #define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3) 113 #define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3) 114 #define CDC_A_MICB_1_CTL (0xf142) 115 116 #define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1) 117 #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1) 118 #define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5) 119 #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5) 120 #define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6) 121 #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6) 122 123 #define CDC_A_MICB_1_INT_RBIAS (0xf143) 124 #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7) 125 #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7) 126 #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0 127 128 #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6) 129 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6) 130 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0 131 132 #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4) 133 #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4) 134 #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0 135 #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3) 136 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3) 137 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0 138 139 #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1) 140 #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1) 141 #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0 142 #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0) 143 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0) 144 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0 145 146 #define CDC_A_MICB_2_EN (0xf144) 147 #define CDC_A_MICB_2_EN_ENABLE BIT(7) 148 #define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5) 149 #define CDC_A_MICB_2_PULL_DOWN_EN BIT(5) 150 #define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145) 151 #define CDC_A_MASTER_BIAS_CTL (0xf146) 152 #define CDC_A_MBHC_DET_CTL_1 (0xf147) 153 #define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7) 154 #define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6) 155 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5) 156 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0) 157 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5) 158 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5) 159 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4) 160 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3) 161 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3) 162 #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2) 163 #define CDC_A_MBHC_DET_CTL_2 (0xf150) 164 #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6)) 165 #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5) 166 #define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3) 167 #define CDC_A_HPHL_PLUG_TYPE_NO BIT(4) 168 #define CDC_A_GND_PLUG_TYPE_NO BIT(3) 169 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0) 170 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0) 171 #define CDC_A_MBHC_FSM_CTL (0xf151) 172 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7) 173 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7) 174 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4) 175 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4) 176 #define CDC_A_MBHC_DBNC_TIMER (0xf152) 177 #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3) 178 #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4) 179 #define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153) 180 #define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154) 181 #define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155) 182 #define CDC_A_MBHC_BTN3_CTL (0xf156) 183 #define CDC_A_MBHC_BTN4_CTL (0xf157) 184 #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2) 185 #define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2) 186 #define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5) 187 #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5) 188 #define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \ 189 CDC_A_MBHC_BTN_VREF_FINE_MASK) 190 #define CDC_A_MBHC_RESULT_1 (0xf158) 191 #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0) 192 #define CDC_A_TX_1_EN (0xf160) 193 #define CDC_A_TX_2_EN (0xf161) 194 #define CDC_A_TX_1_2_TEST_CTL_1 (0xf162) 195 #define CDC_A_TX_1_2_TEST_CTL_2 (0xf163) 196 #define CDC_A_TX_1_2_ATEST_CTL (0xf164) 197 #define CDC_A_TX_1_2_OPAMP_BIAS (0xf165) 198 #define CDC_A_TX_3_EN (0xf167) 199 #define CDC_A_NCP_EN (0xf180) 200 #define CDC_A_NCP_CLK (0xf181) 201 #define CDC_A_NCP_FBCTRL (0xf183) 202 #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5) 203 #define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5) 204 #define CDC_A_NCP_BIAS (0xf184) 205 #define CDC_A_NCP_VCTRL (0xf185) 206 #define CDC_A_NCP_TEST (0xf186) 207 #define CDC_A_NCP_CLIM_ADDR (0xf187) 208 #define CDC_A_RX_CLOCK_DIVIDER (0xf190) 209 #define CDC_A_RX_COM_OCP_CTL (0xf191) 210 #define CDC_A_RX_COM_OCP_COUNT (0xf192) 211 #define CDC_A_RX_COM_BIAS_DAC (0xf193) 212 #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7) 213 #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7) 214 #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0) 215 #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0) 216 217 #define CDC_A_RX_HPH_BIAS_PA (0xf194) 218 #define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195) 219 #define CDC_A_RX_HPH_BIAS_CNP (0xf196) 220 #define CDC_A_RX_HPH_CNP_EN (0xf197) 221 #define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B) 222 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1) 223 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1) 224 #define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D) 225 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1) 226 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1) 227 228 #define CDC_A_RX_EAR_CTL (0xf19E) 229 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0) 230 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0) 231 #define RX_EAR_CTL_PA_EAR_PA_EN_MASK BIT(6) 232 #define RX_EAR_CTL_PA_EAR_PA_EN_ENABLE BIT(6) 233 #define RX_EAR_CTL_PA_SEL_MASK BIT(7) 234 #define RX_EAR_CTL_PA_SEL BIT(7) 235 236 #define CDC_A_SPKR_DAC_CTL (0xf1B0) 237 #define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4) 238 #define SPKR_DAC_CTL_DAC_RESET_NORMAL 0 239 240 #define CDC_A_SPKR_DRV_CTL (0xf1B2) 241 #define SPKR_DRV_CTL_DEF_MASK 0xEF 242 #define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7) 243 #define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7) 244 #define SPKR_DRV_CAL_EN BIT(6) 245 #define SPKR_DRV_SETTLE_EN BIT(5) 246 #define SPKR_DRV_FW_EN BIT(3) 247 #define SPKR_DRV_BOOST_SET BIT(2) 248 #define SPKR_DRV_CMFB_SET BIT(1) 249 #define SPKR_DRV_GAIN_SET BIT(0) 250 #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \ 251 SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \ 252 SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \ 253 SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET) 254 #define CDC_A_SPKR_OCP_CTL (0xf1B4) 255 #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5) 256 #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0) 257 #define SPKR_PWRSTG_CTL_DAC_EN BIT(0) 258 #define SPKR_PWRSTG_CTL_MASK 0xE0 259 #define SPKR_PWRSTG_CTL_BBM_MASK BIT(7) 260 #define SPKR_PWRSTG_CTL_BBM_EN BIT(7) 261 #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6) 262 #define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6) 263 #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5) 264 #define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5) 265 266 #define CDC_A_SPKR_DRV_DBG (0xf1B7) 267 #define CDC_A_CURRENT_LIMIT (0xf1C0) 268 #define CDC_A_BOOST_EN_CTL (0xf1C3) 269 #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4) 270 #define CDC_A_SEC_ACCESS (0xf1D0) 271 #define CDC_A_PERPH_RESET_CTL3 (0xf1DA) 272 #define CDC_A_PERPH_RESET_CTL4 (0xf1DB) 273 274 #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 275 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) 276 #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 277 SNDRV_PCM_FMTBIT_S32_LE) 278 279 static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | 280 SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4; 281 static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET; 282 283 static const char * const supply_names[] = { 284 "vdd-cdc-io", 285 "vdd-cdc-tx-rx-cx", 286 }; 287 288 #define MBHC_MAX_BUTTONS (5) 289 290 struct pm8916_wcd_analog_priv { 291 u16 pmic_rev; 292 u16 codec_version; 293 bool mbhc_btn_enabled; 294 /* special event to detect accessory type */ 295 int mbhc_btn0_released; 296 bool detect_accessory_type; 297 struct clk *mclk; 298 struct snd_soc_component *component; 299 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; 300 struct snd_soc_jack *jack; 301 bool hphl_jack_type_normally_open; 302 bool gnd_jack_type_normally_open; 303 /* Voltage threshold when internal current source of 100uA is used */ 304 u32 vref_btn_cs[MBHC_MAX_BUTTONS]; 305 /* Voltage threshold when microphone bias is ON */ 306 u32 vref_btn_micb[MBHC_MAX_BUTTONS]; 307 unsigned int micbias1_cap_mode; 308 unsigned int micbias2_cap_mode; 309 unsigned int micbias_mv; 310 }; 311 312 static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" }; 313 static const char *const rdac2_mux_text[] = { "RX1", "RX2" }; 314 static const char *const hph_text[] = { "ZERO", "Switch", }; 315 316 static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT( 317 ARRAY_SIZE(hph_text), hph_text); 318 319 static const struct snd_kcontrol_new ear_mux = SOC_DAPM_ENUM("EAR_S", hph_enum); 320 static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum); 321 static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum); 322 323 /* ADC2 MUX */ 324 static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT( 325 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 326 327 /* RDAC2 MUX */ 328 static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE( 329 CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text); 330 331 static const struct snd_kcontrol_new spkr_switch[] = { 332 SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0) 333 }; 334 335 static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM( 336 "RDAC2 MUX Mux", rdac2_mux_enum); 337 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM( 338 "ADC2 MUX Mux", adc2_enum); 339 340 /* Analog Gain control 0 dB to +24 dB in 6 dB steps */ 341 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0); 342 343 static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = { 344 SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain), 345 SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain), 346 SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain), 347 }; 348 349 static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component) 350 { 351 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 352 353 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 354 MICB_1_CTL_EXT_PRECHARG_EN_MASK | 355 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 356 MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL 357 | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE); 358 359 if (wcd->micbias_mv) { 360 snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL, 361 MICB_1_VAL_MICB_OUT_VAL_MASK, 362 MICB_VOLTAGE_REGVAL(wcd->micbias_mv)); 363 /* 364 * Special headset needs MICBIAS as 2.7V so wait for 365 * 50 msec for the MICBIAS to reach 2.7 volts. 366 */ 367 if (wcd->micbias_mv >= 2700) 368 msleep(50); 369 } 370 371 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 372 MICB_1_CTL_EXT_PRECHARG_EN_MASK | 373 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0); 374 375 } 376 377 static int pm8916_wcd_analog_enable_micbias_ext(struct snd_soc_component 378 *component, int event, 379 int reg, unsigned int cap_mode) 380 { 381 switch (event) { 382 case SND_SOC_DAPM_POST_PMU: 383 pm8916_wcd_analog_micbias_enable(component); 384 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, 385 MICB_1_EN_BYP_CAP_MASK, cap_mode); 386 break; 387 } 388 389 return 0; 390 } 391 392 static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_component 393 *component, int event, 394 int reg, u32 cap_mode) 395 { 396 397 switch (event) { 398 case SND_SOC_DAPM_PRE_PMU: 399 snd_soc_component_update_bits(component, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0); 400 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, 401 MICB_1_EN_OPA_STG2_TAIL_CURR_MASK, 402 MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA); 403 404 break; 405 case SND_SOC_DAPM_POST_PMU: 406 pm8916_wcd_analog_micbias_enable(component); 407 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, 408 MICB_1_EN_BYP_CAP_MASK, cap_mode); 409 break; 410 } 411 412 return 0; 413 } 414 415 static int pm8916_wcd_analog_enable_micbias_ext1(struct 416 snd_soc_dapm_widget 417 *w, struct snd_kcontrol 418 *kcontrol, int event) 419 { 420 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 421 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 422 423 return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg, 424 wcd->micbias1_cap_mode); 425 } 426 427 static int pm8916_wcd_analog_enable_micbias_ext2(struct 428 snd_soc_dapm_widget 429 *w, struct snd_kcontrol 430 *kcontrol, int event) 431 { 432 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 433 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 434 435 return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg, 436 wcd->micbias2_cap_mode); 437 438 } 439 440 static int pm8916_wcd_analog_enable_micbias_int1(struct 441 snd_soc_dapm_widget 442 *w, struct snd_kcontrol 443 *kcontrol, int event) 444 { 445 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 446 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 447 448 switch (event) { 449 case SND_SOC_DAPM_PRE_PMU: 450 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS, 451 MICB_1_INT_TX1_INT_RBIAS_EN_MASK, 452 MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE); 453 break; 454 } 455 456 return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg, 457 wcd->micbias1_cap_mode); 458 } 459 460 static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv, 461 bool micbias2_enabled) 462 { 463 struct snd_soc_component *component = priv->component; 464 u32 coarse, fine, reg_val, reg_addr; 465 int *vrefs, i; 466 467 if (!micbias2_enabled) { /* use internal 100uA Current source */ 468 /* Enable internal 2.2k Internal Rbias Resistor */ 469 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS, 470 MICB_1_INT_TX2_INT_RBIAS_EN_MASK, 471 MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); 472 /* Remove pull down on MIC BIAS2 */ 473 snd_soc_component_update_bits(component, CDC_A_MICB_2_EN, 474 CDC_A_MICB_2_PULL_DOWN_EN_MASK, 475 0); 476 /* enable 100uA internal current source */ 477 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL, 478 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK, 479 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA); 480 } 481 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL, 482 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK, 483 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN); 484 485 if (micbias2_enabled) 486 vrefs = &priv->vref_btn_micb[0]; 487 else 488 vrefs = &priv->vref_btn_cs[0]; 489 490 /* program vref ranges for all the buttons */ 491 reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0; 492 for (i = 0; i < MBHC_MAX_BUTTONS; i++) { 493 /* split mv in to coarse parts of 100mv & fine parts of 12mv */ 494 coarse = (vrefs[i] / 100); 495 fine = ((vrefs[i] % 100) / 12); 496 reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) | 497 (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT); 498 snd_soc_component_update_bits(component, reg_addr, 499 CDC_A_MBHC_BTN_VREF_MASK, 500 reg_val); 501 reg_addr++; 502 } 503 504 return 0; 505 } 506 507 static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd) 508 { 509 struct snd_soc_component *component = wcd->component; 510 bool micbias_enabled = false; 511 u32 plug_type = 0; 512 u32 int_en_mask; 513 514 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1, 515 CDC_A_MBHC_DET_CTL_L_DET_EN | 516 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION | 517 CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO | 518 CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN); 519 520 if (wcd->hphl_jack_type_normally_open) 521 plug_type |= CDC_A_HPHL_PLUG_TYPE_NO; 522 523 if (wcd->gnd_jack_type_normally_open) 524 plug_type |= CDC_A_GND_PLUG_TYPE_NO; 525 526 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2, 527 CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 | 528 CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD | 529 plug_type | 530 CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN); 531 532 533 snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER, 534 CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS | 535 CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS); 536 537 /* enable MBHC clock */ 538 snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL, 539 DIG_CLK_CTL_D_MBHC_CLK_EN_MASK, 540 DIG_CLK_CTL_D_MBHC_CLK_EN); 541 542 if (snd_soc_component_read32(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE) 543 micbias_enabled = true; 544 545 pm8916_mbhc_configure_bias(wcd, micbias_enabled); 546 547 int_en_mask = MBHC_SWITCH_INT; 548 if (wcd->mbhc_btn_enabled) 549 int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET; 550 551 snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0); 552 snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask); 553 wcd->mbhc_btn0_released = false; 554 wcd->detect_accessory_type = true; 555 } 556 557 static int pm8916_wcd_analog_enable_micbias_int2(struct 558 snd_soc_dapm_widget 559 *w, struct snd_kcontrol 560 *kcontrol, int event) 561 { 562 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 563 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 564 565 switch (event) { 566 case SND_SOC_DAPM_PRE_PMU: 567 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS, 568 MICB_1_INT_TX2_INT_RBIAS_EN_MASK, 569 MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); 570 break; 571 case SND_SOC_DAPM_POST_PMU: 572 pm8916_mbhc_configure_bias(wcd, true); 573 break; 574 case SND_SOC_DAPM_POST_PMD: 575 pm8916_mbhc_configure_bias(wcd, false); 576 break; 577 } 578 579 return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg, 580 wcd->micbias2_cap_mode); 581 } 582 583 static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w, 584 struct snd_kcontrol *kcontrol, 585 int event) 586 { 587 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 588 u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2; 589 u8 init_bit_shift; 590 591 if (w->reg == CDC_A_TX_1_EN) 592 init_bit_shift = 5; 593 else 594 init_bit_shift = 4; 595 596 switch (event) { 597 case SND_SOC_DAPM_PRE_PMU: 598 if (w->reg == CDC_A_TX_2_EN) 599 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 600 MICB_1_CTL_CFILT_REF_SEL_MASK, 601 MICB_1_CTL_CFILT_REF_SEL_HPF_REF); 602 /* 603 * Add delay of 10 ms to give sufficient time for the voltage 604 * to shoot up and settle so that the txfe init does not 605 * happen when the input voltage is changing too much. 606 */ 607 usleep_range(10000, 10010); 608 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 609 1 << init_bit_shift); 610 switch (w->reg) { 611 case CDC_A_TX_1_EN: 612 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL, 613 CONN_TX1_SERIAL_TX1_MUX, 614 CONN_TX1_SERIAL_TX1_ADC_1); 615 break; 616 case CDC_A_TX_2_EN: 617 case CDC_A_TX_3_EN: 618 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL, 619 CONN_TX2_SERIAL_TX2_MUX, 620 CONN_TX2_SERIAL_TX2_ADC_2); 621 break; 622 } 623 break; 624 case SND_SOC_DAPM_POST_PMU: 625 /* 626 * Add delay of 12 ms before deasserting the init 627 * to reduce the tx pop 628 */ 629 usleep_range(12000, 12010); 630 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00); 631 break; 632 case SND_SOC_DAPM_POST_PMD: 633 switch (w->reg) { 634 case CDC_A_TX_1_EN: 635 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL, 636 CONN_TX1_SERIAL_TX1_MUX, 637 CONN_TX1_SERIAL_TX1_ZERO); 638 break; 639 case CDC_A_TX_2_EN: 640 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 641 MICB_1_CTL_CFILT_REF_SEL_MASK, 0); 642 /* fall through */ 643 case CDC_A_TX_3_EN: 644 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL, 645 CONN_TX2_SERIAL_TX2_MUX, 646 CONN_TX2_SERIAL_TX2_ZERO); 647 break; 648 } 649 650 651 break; 652 } 653 return 0; 654 } 655 656 static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w, 657 struct snd_kcontrol *kcontrol, 658 int event) 659 { 660 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 661 662 switch (event) { 663 case SND_SOC_DAPM_PRE_PMU: 664 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL, 665 SPKR_PWRSTG_CTL_DAC_EN_MASK | 666 SPKR_PWRSTG_CTL_BBM_MASK | 667 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | 668 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 669 SPKR_PWRSTG_CTL_DAC_EN| 670 SPKR_PWRSTG_CTL_BBM_EN | 671 SPKR_PWRSTG_CTL_HBRDGE_EN | 672 SPKR_PWRSTG_CTL_CLAMP_EN); 673 674 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 675 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 676 RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE); 677 break; 678 case SND_SOC_DAPM_POST_PMU: 679 snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL, 680 SPKR_DRV_CTL_DEF_MASK, 681 SPKR_DRV_CTL_DEF_VAL); 682 snd_soc_component_update_bits(component, w->reg, 683 SPKR_DRV_CLASSD_PA_EN_MASK, 684 SPKR_DRV_CLASSD_PA_EN_ENABLE); 685 break; 686 case SND_SOC_DAPM_POST_PMD: 687 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL, 688 SPKR_PWRSTG_CTL_DAC_EN_MASK| 689 SPKR_PWRSTG_CTL_BBM_MASK | 690 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | 691 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0); 692 693 snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL, 694 SPKR_DAC_CTL_DAC_RESET_MASK, 695 SPKR_DAC_CTL_DAC_RESET_NORMAL); 696 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 697 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0); 698 break; 699 } 700 return 0; 701 } 702 703 static int pm8916_wcd_analog_enable_ear_pa(struct snd_soc_dapm_widget *w, 704 struct snd_kcontrol *kcontrol, 705 int event) 706 { 707 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 708 709 switch (event) { 710 case SND_SOC_DAPM_PRE_PMU: 711 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 712 RX_EAR_CTL_PA_SEL_MASK, RX_EAR_CTL_PA_SEL); 713 break; 714 case SND_SOC_DAPM_POST_PMU: 715 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 716 RX_EAR_CTL_PA_EAR_PA_EN_MASK, 717 RX_EAR_CTL_PA_EAR_PA_EN_ENABLE); 718 break; 719 case SND_SOC_DAPM_POST_PMD: 720 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 721 RX_EAR_CTL_PA_EAR_PA_EN_MASK, 0); 722 /* Delay to reduce ear turn off pop */ 723 usleep_range(7000, 7100); 724 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 725 RX_EAR_CTL_PA_SEL_MASK, 0); 726 break; 727 } 728 return 0; 729 } 730 731 static const struct reg_default wcd_reg_defaults_2_0[] = { 732 {CDC_A_RX_COM_OCP_CTL, 0xD1}, 733 {CDC_A_RX_COM_OCP_COUNT, 0xFF}, 734 {CDC_D_SEC_ACCESS, 0xA5}, 735 {CDC_D_PERPH_RESET_CTL3, 0x0F}, 736 {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F}, 737 {CDC_A_NCP_FBCTRL, 0x28}, 738 {CDC_A_SPKR_DRV_CTL, 0x69}, 739 {CDC_A_SPKR_DRV_DBG, 0x01}, 740 {CDC_A_BOOST_EN_CTL, 0x5F}, 741 {CDC_A_SLOPE_COMP_IP_ZERO, 0x88}, 742 {CDC_A_SEC_ACCESS, 0xA5}, 743 {CDC_A_PERPH_RESET_CTL3, 0x0F}, 744 {CDC_A_CURRENT_LIMIT, 0x82}, 745 {CDC_A_SPKR_DAC_CTL, 0x03}, 746 {CDC_A_SPKR_OCP_CTL, 0xE1}, 747 {CDC_A_MASTER_BIAS_CTL, 0x30}, 748 }; 749 750 static int pm8916_wcd_analog_probe(struct snd_soc_component *component) 751 { 752 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); 753 int err, reg; 754 755 err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 756 if (err != 0) { 757 dev_err(component->dev, "failed to enable regulators (%d)\n", err); 758 return err; 759 } 760 761 snd_soc_component_init_regmap(component, 762 dev_get_regmap(component->dev->parent, NULL)); 763 snd_soc_component_set_drvdata(component, priv); 764 priv->pmic_rev = snd_soc_component_read32(component, CDC_D_REVISION1); 765 priv->codec_version = snd_soc_component_read32(component, CDC_D_PERPH_SUBTYPE); 766 767 dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n", 768 priv->pmic_rev, priv->codec_version); 769 770 snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01); 771 snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01); 772 773 for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++) 774 snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg, 775 wcd_reg_defaults_2_0[reg].def); 776 777 priv->component = component; 778 779 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL, 780 RST_CTL_DIG_SW_RST_N_MASK, 781 RST_CTL_DIG_SW_RST_N_REMOVE_RESET); 782 783 pm8916_wcd_setup_mbhc(priv); 784 785 return 0; 786 } 787 788 static void pm8916_wcd_analog_remove(struct snd_soc_component *component) 789 { 790 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); 791 792 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL, 793 RST_CTL_DIG_SW_RST_N_MASK, 0); 794 795 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 796 priv->supplies); 797 } 798 799 static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = { 800 801 {"PDM_RX1", NULL, "PDM Playback"}, 802 {"PDM_RX2", NULL, "PDM Playback"}, 803 {"PDM_RX3", NULL, "PDM Playback"}, 804 {"PDM Capture", NULL, "PDM_TX"}, 805 806 /* ADC Connections */ 807 {"PDM_TX", NULL, "ADC2"}, 808 {"PDM_TX", NULL, "ADC3"}, 809 {"ADC2", NULL, "ADC2 MUX"}, 810 {"ADC3", NULL, "ADC2 MUX"}, 811 {"ADC2 MUX", "INP2", "ADC2_INP2"}, 812 {"ADC2 MUX", "INP3", "ADC2_INP3"}, 813 814 {"PDM_TX", NULL, "ADC1"}, 815 {"ADC1", NULL, "AMIC1"}, 816 {"ADC2_INP2", NULL, "AMIC2"}, 817 {"ADC2_INP3", NULL, "AMIC3"}, 818 819 /* RDAC Connections */ 820 {"HPHR DAC", NULL, "RDAC2 MUX"}, 821 {"RDAC2 MUX", "RX1", "PDM_RX1"}, 822 {"RDAC2 MUX", "RX2", "PDM_RX2"}, 823 {"HPHL DAC", NULL, "PDM_RX1"}, 824 {"PDM_RX1", NULL, "RXD1_CLK"}, 825 {"PDM_RX2", NULL, "RXD2_CLK"}, 826 {"PDM_RX3", NULL, "RXD3_CLK"}, 827 828 {"PDM_RX1", NULL, "RXD_PDM_CLK"}, 829 {"PDM_RX2", NULL, "RXD_PDM_CLK"}, 830 {"PDM_RX3", NULL, "RXD_PDM_CLK"}, 831 832 {"ADC1", NULL, "TXD_CLK"}, 833 {"ADC2", NULL, "TXD_CLK"}, 834 {"ADC3", NULL, "TXD_CLK"}, 835 836 {"ADC1", NULL, "TXA_CLK25"}, 837 {"ADC2", NULL, "TXA_CLK25"}, 838 {"ADC3", NULL, "TXA_CLK25"}, 839 840 {"PDM_RX1", NULL, "A_MCLK2"}, 841 {"PDM_RX2", NULL, "A_MCLK2"}, 842 {"PDM_RX3", NULL, "A_MCLK2"}, 843 844 {"PDM_TX", NULL, "A_MCLK2"}, 845 {"A_MCLK2", NULL, "A_MCLK"}, 846 847 /* Earpiece (RX MIX1) */ 848 {"EAR", NULL, "EAR_S"}, 849 {"EAR_S", "Switch", "EAR PA"}, 850 {"EAR PA", NULL, "RX_BIAS"}, 851 {"EAR PA", NULL, "HPHL DAC"}, 852 {"EAR PA", NULL, "HPHR DAC"}, 853 {"EAR PA", NULL, "EAR CP"}, 854 855 /* Headset (RX MIX1 and RX MIX2) */ 856 {"HEADPHONE", NULL, "HPHL PA"}, 857 {"HEADPHONE", NULL, "HPHR PA"}, 858 859 {"HPHL DAC", NULL, "EAR_HPHL_CLK"}, 860 {"HPHR DAC", NULL, "EAR_HPHR_CLK"}, 861 862 {"CP", NULL, "NCP_CLK"}, 863 864 {"HPHL PA", NULL, "HPHL"}, 865 {"HPHR PA", NULL, "HPHR"}, 866 {"HPHL PA", NULL, "CP"}, 867 {"HPHL PA", NULL, "RX_BIAS"}, 868 {"HPHR PA", NULL, "CP"}, 869 {"HPHR PA", NULL, "RX_BIAS"}, 870 {"HPHL", "Switch", "HPHL DAC"}, 871 {"HPHR", "Switch", "HPHR DAC"}, 872 873 {"RX_BIAS", NULL, "DAC_REF"}, 874 875 {"SPK_OUT", NULL, "SPK PA"}, 876 {"SPK PA", NULL, "RX_BIAS"}, 877 {"SPK PA", NULL, "SPKR_CLK"}, 878 {"SPK PA", NULL, "SPK DAC"}, 879 {"SPK DAC", "Switch", "PDM_RX3"}, 880 881 {"MIC BIAS Internal1", NULL, "INT_LDO_H"}, 882 {"MIC BIAS Internal2", NULL, "INT_LDO_H"}, 883 {"MIC BIAS External1", NULL, "INT_LDO_H"}, 884 {"MIC BIAS External2", NULL, "INT_LDO_H"}, 885 {"MIC BIAS Internal1", NULL, "vdd-micbias"}, 886 {"MIC BIAS Internal2", NULL, "vdd-micbias"}, 887 {"MIC BIAS External1", NULL, "vdd-micbias"}, 888 {"MIC BIAS External2", NULL, "vdd-micbias"}, 889 }; 890 891 static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = { 892 893 SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 894 SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0), 895 SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0), 896 SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0), 897 898 SND_SOC_DAPM_INPUT("AMIC1"), 899 SND_SOC_DAPM_INPUT("AMIC3"), 900 SND_SOC_DAPM_INPUT("AMIC2"), 901 SND_SOC_DAPM_OUTPUT("EAR"), 902 SND_SOC_DAPM_OUTPUT("HEADPHONE"), 903 904 /* RX stuff */ 905 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0), 906 907 SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM, 908 0, 0, NULL, 0, 909 pm8916_wcd_analog_enable_ear_pa, 910 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 911 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 912 SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, &ear_mux), 913 SND_SOC_DAPM_SUPPLY("EAR CP", CDC_A_NCP_EN, 4, 0, NULL, 0), 914 915 SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0), 916 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux), 917 SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL, 918 0), 919 SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0), 920 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux), 921 SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL, 922 0), 923 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0, 924 spkr_switch, ARRAY_SIZE(spkr_switch)), 925 926 /* Speaker */ 927 SND_SOC_DAPM_OUTPUT("SPK_OUT"), 928 SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL, 929 6, 0, NULL, 0, 930 pm8916_wcd_analog_enable_spk_pa, 931 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 932 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 933 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0), 934 SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0), 935 936 SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0), 937 SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0), 938 939 /* TX */ 940 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_EN, 7, 0, 941 pm8916_wcd_analog_enable_micbias_int1, 942 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 943 SND_SOC_DAPM_POST_PMD), 944 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_2_EN, 7, 0, 945 pm8916_wcd_analog_enable_micbias_int2, 946 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 947 SND_SOC_DAPM_POST_PMD), 948 949 SND_SOC_DAPM_SUPPLY("MIC BIAS External1", CDC_A_MICB_1_EN, 7, 0, 950 pm8916_wcd_analog_enable_micbias_ext1, 951 SND_SOC_DAPM_POST_PMU), 952 SND_SOC_DAPM_SUPPLY("MIC BIAS External2", CDC_A_MICB_2_EN, 7, 0, 953 pm8916_wcd_analog_enable_micbias_ext2, 954 SND_SOC_DAPM_POST_PMU), 955 956 SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0, 957 pm8916_wcd_analog_enable_adc, 958 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 959 SND_SOC_DAPM_POST_PMD), 960 SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0, 961 pm8916_wcd_analog_enable_adc, 962 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 963 SND_SOC_DAPM_POST_PMD), 964 SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0, 965 pm8916_wcd_analog_enable_adc, 966 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 967 SND_SOC_DAPM_POST_PMD), 968 969 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 970 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 971 972 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 973 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux), 974 975 /* Analog path clocks */ 976 SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL, 977 0), 978 SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL, 979 0), 980 SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0), 981 SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0), 982 983 /* Digital path clocks */ 984 985 SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0), 986 SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0), 987 SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0), 988 989 SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0), 990 SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0), 991 SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL, 992 0), 993 994 /* System Clock source */ 995 SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0), 996 /* TX ADC and RX DAC Clock source. */ 997 SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0), 998 }; 999 1000 static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component, 1001 struct snd_soc_jack *jack, 1002 void *data) 1003 { 1004 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 1005 1006 wcd->jack = jack; 1007 1008 return 0; 1009 } 1010 1011 static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg) 1012 { 1013 struct pm8916_wcd_analog_priv *priv = arg; 1014 1015 if (priv->detect_accessory_type) { 1016 struct snd_soc_component *component = priv->component; 1017 u32 val = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1); 1018 1019 /* check if its BTN0 thats released */ 1020 if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK)) 1021 priv->mbhc_btn0_released = true; 1022 1023 } else { 1024 snd_soc_jack_report(priv->jack, 0, btn_mask); 1025 } 1026 1027 return IRQ_HANDLED; 1028 } 1029 1030 static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg) 1031 { 1032 struct pm8916_wcd_analog_priv *priv = arg; 1033 struct snd_soc_component *component = priv->component; 1034 u32 btn_result; 1035 1036 btn_result = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1) & 1037 CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK; 1038 1039 switch (btn_result) { 1040 case 0xf: 1041 snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask); 1042 break; 1043 case 0x7: 1044 snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask); 1045 break; 1046 case 0x3: 1047 snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask); 1048 break; 1049 case 0x1: 1050 snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask); 1051 break; 1052 case 0x0: 1053 /* handle BTN_0 specially for type detection */ 1054 if (!priv->detect_accessory_type) 1055 snd_soc_jack_report(priv->jack, 1056 SND_JACK_BTN_0, btn_mask); 1057 break; 1058 default: 1059 dev_err(component->dev, 1060 "Unexpected button press result (%x)", btn_result); 1061 break; 1062 } 1063 1064 return IRQ_HANDLED; 1065 } 1066 1067 static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg) 1068 { 1069 struct pm8916_wcd_analog_priv *priv = arg; 1070 struct snd_soc_component *component = priv->component; 1071 bool ins = false; 1072 1073 if (snd_soc_component_read32(component, CDC_A_MBHC_DET_CTL_1) & 1074 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK) 1075 ins = true; 1076 1077 /* Set the detection type appropriately */ 1078 snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1, 1079 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK, 1080 (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT)); 1081 1082 1083 if (ins) { /* hs insertion */ 1084 bool micbias_enabled = false; 1085 1086 if (snd_soc_component_read32(component, CDC_A_MICB_2_EN) & 1087 CDC_A_MICB_2_EN_ENABLE) 1088 micbias_enabled = true; 1089 1090 pm8916_mbhc_configure_bias(priv, micbias_enabled); 1091 1092 /* 1093 * if only a btn0 press event is receive just before 1094 * insert event then its a 3 pole headphone else if 1095 * both press and release event received then its 1096 * a headset. 1097 */ 1098 if (priv->mbhc_btn0_released) 1099 snd_soc_jack_report(priv->jack, 1100 SND_JACK_HEADSET, hs_jack_mask); 1101 else 1102 snd_soc_jack_report(priv->jack, 1103 SND_JACK_HEADPHONE, hs_jack_mask); 1104 1105 priv->detect_accessory_type = false; 1106 1107 } else { /* removal */ 1108 snd_soc_jack_report(priv->jack, 0, hs_jack_mask); 1109 priv->detect_accessory_type = true; 1110 priv->mbhc_btn0_released = false; 1111 } 1112 1113 return IRQ_HANDLED; 1114 } 1115 1116 static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = { 1117 [0] = { 1118 .name = "pm8916_wcd_analog_pdm_rx", 1119 .id = 0, 1120 .playback = { 1121 .stream_name = "PDM Playback", 1122 .rates = MSM8916_WCD_ANALOG_RATES, 1123 .formats = MSM8916_WCD_ANALOG_FORMATS, 1124 .channels_min = 1, 1125 .channels_max = 3, 1126 }, 1127 }, 1128 [1] = { 1129 .name = "pm8916_wcd_analog_pdm_tx", 1130 .id = 1, 1131 .capture = { 1132 .stream_name = "PDM Capture", 1133 .rates = MSM8916_WCD_ANALOG_RATES, 1134 .formats = MSM8916_WCD_ANALOG_FORMATS, 1135 .channels_min = 1, 1136 .channels_max = 4, 1137 }, 1138 }, 1139 }; 1140 1141 static const struct snd_soc_component_driver pm8916_wcd_analog = { 1142 .probe = pm8916_wcd_analog_probe, 1143 .remove = pm8916_wcd_analog_remove, 1144 .set_jack = pm8916_wcd_analog_set_jack, 1145 .controls = pm8916_wcd_analog_snd_controls, 1146 .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls), 1147 .dapm_widgets = pm8916_wcd_analog_dapm_widgets, 1148 .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets), 1149 .dapm_routes = pm8916_wcd_analog_audio_map, 1150 .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map), 1151 .idle_bias_on = 1, 1152 .use_pmdown_time = 1, 1153 .endianness = 1, 1154 .non_legacy_dai_naming = 1, 1155 }; 1156 1157 static int pm8916_wcd_analog_parse_dt(struct device *dev, 1158 struct pm8916_wcd_analog_priv *priv) 1159 { 1160 int rval; 1161 1162 if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap")) 1163 priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP; 1164 else 1165 priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; 1166 1167 if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap")) 1168 priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP; 1169 else 1170 priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; 1171 1172 of_property_read_u32(dev->of_node, "qcom,micbias-lvl", 1173 &priv->micbias_mv); 1174 1175 if (of_property_read_bool(dev->of_node, 1176 "qcom,hphl-jack-type-normally-open")) 1177 priv->hphl_jack_type_normally_open = true; 1178 else 1179 priv->hphl_jack_type_normally_open = false; 1180 1181 if (of_property_read_bool(dev->of_node, 1182 "qcom,gnd-jack-type-normally-open")) 1183 priv->gnd_jack_type_normally_open = true; 1184 else 1185 priv->gnd_jack_type_normally_open = false; 1186 1187 priv->mbhc_btn_enabled = true; 1188 rval = of_property_read_u32_array(dev->of_node, 1189 "qcom,mbhc-vthreshold-low", 1190 &priv->vref_btn_cs[0], 1191 MBHC_MAX_BUTTONS); 1192 if (rval < 0) { 1193 priv->mbhc_btn_enabled = false; 1194 } else { 1195 rval = of_property_read_u32_array(dev->of_node, 1196 "qcom,mbhc-vthreshold-high", 1197 &priv->vref_btn_micb[0], 1198 MBHC_MAX_BUTTONS); 1199 if (rval < 0) 1200 priv->mbhc_btn_enabled = false; 1201 } 1202 1203 if (!priv->mbhc_btn_enabled) 1204 dev_err(dev, 1205 "DT property missing, MBHC btn detection disabled\n"); 1206 1207 1208 return 0; 1209 } 1210 1211 static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev) 1212 { 1213 struct pm8916_wcd_analog_priv *priv; 1214 struct device *dev = &pdev->dev; 1215 int ret, i, irq; 1216 1217 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1218 if (!priv) 1219 return -ENOMEM; 1220 1221 ret = pm8916_wcd_analog_parse_dt(dev, priv); 1222 if (ret < 0) 1223 return ret; 1224 1225 priv->mclk = devm_clk_get(dev, "mclk"); 1226 if (IS_ERR(priv->mclk)) { 1227 dev_err(dev, "failed to get mclk\n"); 1228 return PTR_ERR(priv->mclk); 1229 } 1230 1231 for (i = 0; i < ARRAY_SIZE(supply_names); i++) 1232 priv->supplies[i].supply = supply_names[i]; 1233 1234 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies), 1235 priv->supplies); 1236 if (ret) { 1237 dev_err(dev, "Failed to get regulator supplies %d\n", ret); 1238 return ret; 1239 } 1240 1241 ret = clk_prepare_enable(priv->mclk); 1242 if (ret < 0) { 1243 dev_err(dev, "failed to enable mclk %d\n", ret); 1244 return ret; 1245 } 1246 1247 irq = platform_get_irq_byname(pdev, "mbhc_switch_int"); 1248 if (irq < 0) 1249 return irq; 1250 1251 ret = devm_request_threaded_irq(dev, irq, NULL, 1252 pm8916_mbhc_switch_irq_handler, 1253 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | 1254 IRQF_ONESHOT, 1255 "mbhc switch irq", priv); 1256 if (ret) 1257 dev_err(dev, "cannot request mbhc switch irq\n"); 1258 1259 if (priv->mbhc_btn_enabled) { 1260 irq = platform_get_irq_byname(pdev, "mbhc_but_press_det"); 1261 if (irq < 0) 1262 return irq; 1263 1264 ret = devm_request_threaded_irq(dev, irq, NULL, 1265 mbhc_btn_press_irq_handler, 1266 IRQF_TRIGGER_RISING | 1267 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1268 "mbhc btn press irq", priv); 1269 if (ret) 1270 dev_err(dev, "cannot request mbhc button press irq\n"); 1271 1272 irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det"); 1273 if (irq < 0) 1274 return irq; 1275 1276 ret = devm_request_threaded_irq(dev, irq, NULL, 1277 mbhc_btn_release_irq_handler, 1278 IRQF_TRIGGER_RISING | 1279 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1280 "mbhc btn release irq", priv); 1281 if (ret) 1282 dev_err(dev, "cannot request mbhc button release irq\n"); 1283 1284 } 1285 1286 dev_set_drvdata(dev, priv); 1287 1288 return devm_snd_soc_register_component(dev, &pm8916_wcd_analog, 1289 pm8916_wcd_analog_dai, 1290 ARRAY_SIZE(pm8916_wcd_analog_dai)); 1291 } 1292 1293 static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev) 1294 { 1295 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev); 1296 1297 clk_disable_unprepare(priv->mclk); 1298 1299 return 0; 1300 } 1301 1302 static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = { 1303 { .compatible = "qcom,pm8916-wcd-analog-codec", }, 1304 { } 1305 }; 1306 1307 MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table); 1308 1309 static struct platform_driver pm8916_wcd_analog_spmi_driver = { 1310 .driver = { 1311 .name = "qcom,pm8916-wcd-spmi-codec", 1312 .of_match_table = pm8916_wcd_analog_spmi_match_table, 1313 }, 1314 .probe = pm8916_wcd_analog_spmi_probe, 1315 .remove = pm8916_wcd_analog_spmi_remove, 1316 }; 1317 1318 module_platform_driver(pm8916_wcd_analog_spmi_driver); 1319 1320 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>"); 1321 MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver"); 1322 MODULE_LICENSE("GPL v2"); 1323