1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2016, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/err.h> 6 #include <linux/kernel.h> 7 #include <linux/delay.h> 8 #include <linux/regulator/consumer.h> 9 #include <linux/types.h> 10 #include <linux/clk.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 #include <sound/soc.h> 15 #include <sound/pcm.h> 16 #include <sound/pcm_params.h> 17 #include <sound/tlv.h> 18 #include <sound/jack.h> 19 20 #define CDC_D_REVISION1 (0xf000) 21 #define CDC_D_PERPH_SUBTYPE (0xf005) 22 #define CDC_D_INT_EN_SET (0x015) 23 #define CDC_D_INT_EN_CLR (0x016) 24 #define MBHC_SWITCH_INT BIT(7) 25 #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6) 26 #define MBHC_BUTTON_PRESS_DET BIT(5) 27 #define MBHC_BUTTON_RELEASE_DET BIT(4) 28 #define CDC_D_CDC_RST_CTL (0xf046) 29 #define RST_CTL_DIG_SW_RST_N_MASK BIT(7) 30 #define RST_CTL_DIG_SW_RST_N_RESET 0 31 #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7) 32 33 #define CDC_D_CDC_TOP_CLK_CTL (0xf048) 34 #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3)) 35 #define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2) 36 #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3) 37 38 #define CDC_D_CDC_ANA_CLK_CTL (0xf049) 39 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0) 40 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0) 41 #define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1) 42 #define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4) 43 #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4) 44 #define ANA_CLK_CTL_TXA_CLK25_EN BIT(5) 45 46 #define CDC_D_CDC_DIG_CLK_CTL (0xf04A) 47 #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0) 48 #define DIG_CLK_CTL_RXD2_CLK_EN BIT(1) 49 #define DIG_CLK_CTL_RXD3_CLK_EN BIT(2) 50 #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3) 51 #define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3) 52 #define DIG_CLK_CTL_TXD_CLK_EN BIT(4) 53 #define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6) 54 #define DIG_CLK_CTL_NCP_CLK_EN BIT(6) 55 #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7) 56 #define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7) 57 58 #define CDC_D_CDC_CONN_TX1_CTL (0xf050) 59 #define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0) 60 #define CONN_TX1_SERIAL_TX1_ADC_1 0x0 61 #define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1 62 #define CONN_TX1_SERIAL_TX1_ZERO 0x2 63 64 #define CDC_D_CDC_CONN_TX2_CTL (0xf051) 65 #define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0) 66 #define CONN_TX2_SERIAL_TX2_ADC_2 0x0 67 #define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1 68 #define CONN_TX2_SERIAL_TX2_ZERO 0x2 69 #define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052) 70 #define CDC_D_CDC_CONN_RX1_CTL (0xf053) 71 #define CDC_D_CDC_CONN_RX2_CTL (0xf054) 72 #define CDC_D_CDC_CONN_RX3_CTL (0xf055) 73 #define CDC_D_CDC_CONN_RX_LB_CTL (0xf056) 74 #define CDC_D_SEC_ACCESS (0xf0D0) 75 #define CDC_D_PERPH_RESET_CTL3 (0xf0DA) 76 #define CDC_D_PERPH_RESET_CTL4 (0xf0DB) 77 #define CDC_A_REVISION1 (0xf100) 78 #define CDC_A_REVISION2 (0xf101) 79 #define CDC_A_REVISION3 (0xf102) 80 #define CDC_A_REVISION4 (0xf103) 81 #define CDC_A_PERPH_TYPE (0xf104) 82 #define CDC_A_PERPH_SUBTYPE (0xf105) 83 #define CDC_A_INT_RT_STS (0xf110) 84 #define CDC_A_INT_SET_TYPE (0xf111) 85 #define CDC_A_INT_POLARITY_HIGH (0xf112) 86 #define CDC_A_INT_POLARITY_LOW (0xf113) 87 #define CDC_A_INT_LATCHED_CLR (0xf114) 88 #define CDC_A_INT_EN_SET (0xf115) 89 #define CDC_A_INT_EN_CLR (0xf116) 90 #define CDC_A_INT_LATCHED_STS (0xf118) 91 #define CDC_A_INT_PENDING_STS (0xf119) 92 #define CDC_A_INT_MID_SEL (0xf11A) 93 #define CDC_A_INT_PRIORITY (0xf11B) 94 #define CDC_A_MICB_1_EN (0xf140) 95 #define MICB_1_EN_MICB_ENABLE BIT(7) 96 #define MICB_1_EN_BYP_CAP_MASK BIT(6) 97 #define MICB_1_EN_NO_EXT_BYP_CAP BIT(6) 98 #define MICB_1_EN_EXT_BYP_CAP 0 99 #define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5) 100 #define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5) 101 #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1) 102 #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4) 103 #define MICB_1_EN_PULL_UP_EN_MASK BIT(4) 104 #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0) 105 #define MICB_1_EN_TX3_GND_SEL_TX_GND 0 106 107 #define CDC_A_MICB_1_VAL (0xf141) 108 #define MICB_MIN_VAL 1600 109 #define MICB_STEP_SIZE 50 110 #define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3) 111 #define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3) 112 #define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3) 113 #define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3) 114 #define CDC_A_MICB_1_CTL (0xf142) 115 116 #define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1) 117 #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1) 118 #define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5) 119 #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5) 120 #define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6) 121 #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6) 122 123 #define CDC_A_MICB_1_INT_RBIAS (0xf143) 124 #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7) 125 #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7) 126 #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0 127 128 #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6) 129 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6) 130 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0 131 132 #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4) 133 #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4) 134 #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0 135 #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3) 136 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3) 137 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0 138 139 #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1) 140 #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1) 141 #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0 142 #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0) 143 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0) 144 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0 145 146 #define CDC_A_MICB_2_EN (0xf144) 147 #define CDC_A_MICB_2_EN_ENABLE BIT(7) 148 #define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5) 149 #define CDC_A_MICB_2_PULL_DOWN_EN BIT(5) 150 #define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145) 151 #define CDC_A_MASTER_BIAS_CTL (0xf146) 152 #define CDC_A_MBHC_DET_CTL_1 (0xf147) 153 #define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7) 154 #define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6) 155 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5) 156 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0) 157 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5) 158 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5) 159 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4) 160 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3) 161 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3) 162 #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2) 163 #define CDC_A_MBHC_DET_CTL_2 (0xf150) 164 #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6)) 165 #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5) 166 #define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3) 167 #define CDC_A_HPHL_PLUG_TYPE_NO BIT(4) 168 #define CDC_A_GND_PLUG_TYPE_NO BIT(3) 169 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0) 170 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0) 171 #define CDC_A_MBHC_FSM_CTL (0xf151) 172 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7) 173 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7) 174 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4) 175 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4) 176 #define CDC_A_MBHC_DBNC_TIMER (0xf152) 177 #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3) 178 #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4) 179 #define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153) 180 #define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154) 181 #define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155) 182 #define CDC_A_MBHC_BTN3_CTL (0xf156) 183 #define CDC_A_MBHC_BTN4_CTL (0xf157) 184 #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2) 185 #define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2) 186 #define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5) 187 #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5) 188 #define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \ 189 CDC_A_MBHC_BTN_VREF_FINE_MASK) 190 #define CDC_A_MBHC_RESULT_1 (0xf158) 191 #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0) 192 #define CDC_A_TX_1_EN (0xf160) 193 #define CDC_A_TX_2_EN (0xf161) 194 #define CDC_A_TX_1_2_TEST_CTL_1 (0xf162) 195 #define CDC_A_TX_1_2_TEST_CTL_2 (0xf163) 196 #define CDC_A_TX_1_2_ATEST_CTL (0xf164) 197 #define CDC_A_TX_1_2_OPAMP_BIAS (0xf165) 198 #define CDC_A_TX_3_EN (0xf167) 199 #define CDC_A_NCP_EN (0xf180) 200 #define CDC_A_NCP_CLK (0xf181) 201 #define CDC_A_NCP_FBCTRL (0xf183) 202 #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5) 203 #define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5) 204 #define CDC_A_NCP_BIAS (0xf184) 205 #define CDC_A_NCP_VCTRL (0xf185) 206 #define CDC_A_NCP_TEST (0xf186) 207 #define CDC_A_NCP_CLIM_ADDR (0xf187) 208 #define CDC_A_RX_CLOCK_DIVIDER (0xf190) 209 #define CDC_A_RX_COM_OCP_CTL (0xf191) 210 #define CDC_A_RX_COM_OCP_COUNT (0xf192) 211 #define CDC_A_RX_COM_BIAS_DAC (0xf193) 212 #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7) 213 #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7) 214 #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0) 215 #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0) 216 217 #define CDC_A_RX_HPH_BIAS_PA (0xf194) 218 #define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195) 219 #define CDC_A_RX_HPH_BIAS_CNP (0xf196) 220 #define CDC_A_RX_HPH_CNP_EN (0xf197) 221 #define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B) 222 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1) 223 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1) 224 #define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D) 225 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1) 226 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1) 227 228 #define CDC_A_RX_EAR_CTL (0xf19E) 229 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0) 230 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0) 231 #define RX_EAR_CTL_PA_EAR_PA_EN_MASK BIT(6) 232 #define RX_EAR_CTL_PA_EAR_PA_EN_ENABLE BIT(6) 233 #define RX_EAR_CTL_PA_SEL_MASK BIT(7) 234 #define RX_EAR_CTL_PA_SEL BIT(7) 235 236 #define CDC_A_SPKR_DAC_CTL (0xf1B0) 237 #define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4) 238 #define SPKR_DAC_CTL_DAC_RESET_NORMAL 0 239 240 #define CDC_A_SPKR_DRV_CTL (0xf1B2) 241 #define SPKR_DRV_CTL_DEF_MASK 0xEF 242 #define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7) 243 #define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7) 244 #define SPKR_DRV_CAL_EN BIT(6) 245 #define SPKR_DRV_SETTLE_EN BIT(5) 246 #define SPKR_DRV_FW_EN BIT(3) 247 #define SPKR_DRV_BOOST_SET BIT(2) 248 #define SPKR_DRV_CMFB_SET BIT(1) 249 #define SPKR_DRV_GAIN_SET BIT(0) 250 #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \ 251 SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \ 252 SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \ 253 SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET) 254 #define CDC_A_SPKR_OCP_CTL (0xf1B4) 255 #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5) 256 #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0) 257 #define SPKR_PWRSTG_CTL_DAC_EN BIT(0) 258 #define SPKR_PWRSTG_CTL_MASK 0xE0 259 #define SPKR_PWRSTG_CTL_BBM_MASK BIT(7) 260 #define SPKR_PWRSTG_CTL_BBM_EN BIT(7) 261 #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6) 262 #define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6) 263 #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5) 264 #define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5) 265 266 #define CDC_A_SPKR_DRV_DBG (0xf1B7) 267 #define CDC_A_CURRENT_LIMIT (0xf1C0) 268 #define CDC_A_BOOST_EN_CTL (0xf1C3) 269 #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4) 270 #define CDC_A_SEC_ACCESS (0xf1D0) 271 #define CDC_A_PERPH_RESET_CTL3 (0xf1DA) 272 #define CDC_A_PERPH_RESET_CTL4 (0xf1DB) 273 274 #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 275 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) 276 #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 277 SNDRV_PCM_FMTBIT_S32_LE) 278 279 static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | 280 SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4; 281 static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET; 282 283 static const char * const supply_names[] = { 284 "vdd-cdc-io", 285 "vdd-cdc-tx-rx-cx", 286 }; 287 288 #define MBHC_MAX_BUTTONS (5) 289 290 struct pm8916_wcd_analog_priv { 291 u16 pmic_rev; 292 u16 codec_version; 293 bool mbhc_btn_enabled; 294 /* special event to detect accessory type */ 295 int mbhc_btn0_released; 296 bool detect_accessory_type; 297 struct clk *mclk; 298 struct snd_soc_component *component; 299 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; 300 struct snd_soc_jack *jack; 301 bool hphl_jack_type_normally_open; 302 bool gnd_jack_type_normally_open; 303 /* Voltage threshold when internal current source of 100uA is used */ 304 u32 vref_btn_cs[MBHC_MAX_BUTTONS]; 305 /* Voltage threshold when microphone bias is ON */ 306 u32 vref_btn_micb[MBHC_MAX_BUTTONS]; 307 unsigned int micbias1_cap_mode; 308 unsigned int micbias2_cap_mode; 309 unsigned int micbias_mv; 310 }; 311 312 static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" }; 313 static const char *const rdac2_mux_text[] = { "RX1", "RX2" }; 314 static const char *const hph_text[] = { "ZERO", "Switch", }; 315 316 static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT( 317 ARRAY_SIZE(hph_text), hph_text); 318 319 static const struct snd_kcontrol_new ear_mux = SOC_DAPM_ENUM("EAR_S", hph_enum); 320 static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum); 321 static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum); 322 323 /* ADC2 MUX */ 324 static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT( 325 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 326 327 /* RDAC2 MUX */ 328 static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE( 329 CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 2, rdac2_mux_text); 330 331 static const struct snd_kcontrol_new spkr_switch[] = { 332 SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0) 333 }; 334 335 static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM( 336 "RDAC2 MUX Mux", rdac2_mux_enum); 337 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM( 338 "ADC2 MUX Mux", adc2_enum); 339 340 /* Analog Gain control 0 dB to +24 dB in 6 dB steps */ 341 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0); 342 343 static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = { 344 SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain), 345 SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain), 346 SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain), 347 }; 348 349 static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component) 350 { 351 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 352 353 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 354 MICB_1_CTL_EXT_PRECHARG_EN_MASK | 355 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 356 MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL 357 | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE); 358 359 if (wcd->micbias_mv) { 360 snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL, 361 MICB_1_VAL_MICB_OUT_VAL_MASK, 362 MICB_VOLTAGE_REGVAL(wcd->micbias_mv)); 363 /* 364 * Special headset needs MICBIAS as 2.7V so wait for 365 * 50 msec for the MICBIAS to reach 2.7 volts. 366 */ 367 if (wcd->micbias_mv >= 2700) 368 msleep(50); 369 } 370 371 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 372 MICB_1_CTL_EXT_PRECHARG_EN_MASK | 373 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0); 374 375 } 376 377 static int pm8916_wcd_analog_enable_micbias_ext(struct snd_soc_component 378 *component, int event, 379 int reg, unsigned int cap_mode) 380 { 381 switch (event) { 382 case SND_SOC_DAPM_POST_PMU: 383 pm8916_wcd_analog_micbias_enable(component); 384 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, 385 MICB_1_EN_BYP_CAP_MASK, cap_mode); 386 break; 387 } 388 389 return 0; 390 } 391 392 static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_component 393 *component, int event, 394 int reg, u32 cap_mode) 395 { 396 397 switch (event) { 398 case SND_SOC_DAPM_PRE_PMU: 399 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS, 400 MICB_1_INT_TX2_INT_RBIAS_EN_MASK, 401 MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); 402 snd_soc_component_update_bits(component, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0); 403 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, 404 MICB_1_EN_OPA_STG2_TAIL_CURR_MASK, 405 MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA); 406 407 break; 408 case SND_SOC_DAPM_POST_PMU: 409 pm8916_wcd_analog_micbias_enable(component); 410 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, 411 MICB_1_EN_BYP_CAP_MASK, cap_mode); 412 break; 413 } 414 415 return 0; 416 } 417 418 static int pm8916_wcd_analog_enable_micbias_ext1(struct 419 snd_soc_dapm_widget 420 *w, struct snd_kcontrol 421 *kcontrol, int event) 422 { 423 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 424 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 425 426 return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg, 427 wcd->micbias1_cap_mode); 428 } 429 430 static int pm8916_wcd_analog_enable_micbias_ext2(struct 431 snd_soc_dapm_widget 432 *w, struct snd_kcontrol 433 *kcontrol, int event) 434 { 435 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 436 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 437 438 return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg, 439 wcd->micbias2_cap_mode); 440 441 } 442 443 static int pm8916_wcd_analog_enable_micbias_int1(struct 444 snd_soc_dapm_widget 445 *w, struct snd_kcontrol 446 *kcontrol, int event) 447 { 448 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 449 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 450 451 return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg, 452 wcd->micbias1_cap_mode); 453 } 454 455 static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv, 456 bool micbias2_enabled) 457 { 458 struct snd_soc_component *component = priv->component; 459 u32 coarse, fine, reg_val, reg_addr; 460 int *vrefs, i; 461 462 if (!micbias2_enabled) { /* use internal 100uA Current source */ 463 /* Enable internal 2.2k Internal Rbias Resistor */ 464 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS, 465 MICB_1_INT_TX2_INT_RBIAS_EN_MASK, 466 MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); 467 /* Remove pull down on MIC BIAS2 */ 468 snd_soc_component_update_bits(component, CDC_A_MICB_2_EN, 469 CDC_A_MICB_2_PULL_DOWN_EN_MASK, 470 0); 471 /* enable 100uA internal current source */ 472 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL, 473 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK, 474 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA); 475 } 476 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL, 477 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK, 478 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN); 479 480 if (micbias2_enabled) 481 vrefs = &priv->vref_btn_micb[0]; 482 else 483 vrefs = &priv->vref_btn_cs[0]; 484 485 /* program vref ranges for all the buttons */ 486 reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0; 487 for (i = 0; i < MBHC_MAX_BUTTONS; i++) { 488 /* split mv in to coarse parts of 100mv & fine parts of 12mv */ 489 coarse = (vrefs[i] / 100); 490 fine = ((vrefs[i] % 100) / 12); 491 reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) | 492 (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT); 493 snd_soc_component_update_bits(component, reg_addr, 494 CDC_A_MBHC_BTN_VREF_MASK, 495 reg_val); 496 reg_addr++; 497 } 498 499 return 0; 500 } 501 502 static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd) 503 { 504 struct snd_soc_component *component = wcd->component; 505 bool micbias_enabled = false; 506 u32 plug_type = 0; 507 u32 int_en_mask; 508 509 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1, 510 CDC_A_MBHC_DET_CTL_L_DET_EN | 511 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION | 512 CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO | 513 CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN); 514 515 if (wcd->hphl_jack_type_normally_open) 516 plug_type |= CDC_A_HPHL_PLUG_TYPE_NO; 517 518 if (wcd->gnd_jack_type_normally_open) 519 plug_type |= CDC_A_GND_PLUG_TYPE_NO; 520 521 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2, 522 CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 | 523 CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD | 524 plug_type | 525 CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN); 526 527 528 snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER, 529 CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS | 530 CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS); 531 532 /* enable MBHC clock */ 533 snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL, 534 DIG_CLK_CTL_D_MBHC_CLK_EN_MASK, 535 DIG_CLK_CTL_D_MBHC_CLK_EN); 536 537 if (snd_soc_component_read32(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE) 538 micbias_enabled = true; 539 540 pm8916_mbhc_configure_bias(wcd, micbias_enabled); 541 542 int_en_mask = MBHC_SWITCH_INT; 543 if (wcd->mbhc_btn_enabled) 544 int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET; 545 546 snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0); 547 snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask); 548 wcd->mbhc_btn0_released = false; 549 wcd->detect_accessory_type = true; 550 } 551 552 static int pm8916_wcd_analog_enable_micbias_int2(struct 553 snd_soc_dapm_widget 554 *w, struct snd_kcontrol 555 *kcontrol, int event) 556 { 557 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 558 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 559 560 switch (event) { 561 case SND_SOC_DAPM_POST_PMU: 562 pm8916_mbhc_configure_bias(wcd, true); 563 break; 564 case SND_SOC_DAPM_POST_PMD: 565 pm8916_mbhc_configure_bias(wcd, false); 566 break; 567 } 568 569 return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg, 570 wcd->micbias2_cap_mode); 571 } 572 573 static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w, 574 struct snd_kcontrol *kcontrol, 575 int event) 576 { 577 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 578 u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2; 579 u8 init_bit_shift; 580 581 if (w->reg == CDC_A_TX_1_EN) 582 init_bit_shift = 5; 583 else 584 init_bit_shift = 4; 585 586 switch (event) { 587 case SND_SOC_DAPM_PRE_PMU: 588 if (w->reg == CDC_A_TX_2_EN) 589 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 590 MICB_1_CTL_CFILT_REF_SEL_MASK, 591 MICB_1_CTL_CFILT_REF_SEL_HPF_REF); 592 /* 593 * Add delay of 10 ms to give sufficient time for the voltage 594 * to shoot up and settle so that the txfe init does not 595 * happen when the input voltage is changing too much. 596 */ 597 usleep_range(10000, 10010); 598 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 599 1 << init_bit_shift); 600 switch (w->reg) { 601 case CDC_A_TX_1_EN: 602 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL, 603 CONN_TX1_SERIAL_TX1_MUX, 604 CONN_TX1_SERIAL_TX1_ADC_1); 605 break; 606 case CDC_A_TX_2_EN: 607 case CDC_A_TX_3_EN: 608 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL, 609 CONN_TX2_SERIAL_TX2_MUX, 610 CONN_TX2_SERIAL_TX2_ADC_2); 611 break; 612 } 613 break; 614 case SND_SOC_DAPM_POST_PMU: 615 /* 616 * Add delay of 12 ms before deasserting the init 617 * to reduce the tx pop 618 */ 619 usleep_range(12000, 12010); 620 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00); 621 break; 622 case SND_SOC_DAPM_POST_PMD: 623 switch (w->reg) { 624 case CDC_A_TX_1_EN: 625 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL, 626 CONN_TX1_SERIAL_TX1_MUX, 627 CONN_TX1_SERIAL_TX1_ZERO); 628 break; 629 case CDC_A_TX_2_EN: 630 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 631 MICB_1_CTL_CFILT_REF_SEL_MASK, 0); 632 /* fall through */ 633 case CDC_A_TX_3_EN: 634 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL, 635 CONN_TX2_SERIAL_TX2_MUX, 636 CONN_TX2_SERIAL_TX2_ZERO); 637 break; 638 } 639 640 641 break; 642 } 643 return 0; 644 } 645 646 static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w, 647 struct snd_kcontrol *kcontrol, 648 int event) 649 { 650 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 651 652 switch (event) { 653 case SND_SOC_DAPM_PRE_PMU: 654 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL, 655 SPKR_PWRSTG_CTL_DAC_EN_MASK | 656 SPKR_PWRSTG_CTL_BBM_MASK | 657 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | 658 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 659 SPKR_PWRSTG_CTL_DAC_EN| 660 SPKR_PWRSTG_CTL_BBM_EN | 661 SPKR_PWRSTG_CTL_HBRDGE_EN | 662 SPKR_PWRSTG_CTL_CLAMP_EN); 663 664 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 665 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 666 RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE); 667 break; 668 case SND_SOC_DAPM_POST_PMU: 669 snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL, 670 SPKR_DRV_CTL_DEF_MASK, 671 SPKR_DRV_CTL_DEF_VAL); 672 snd_soc_component_update_bits(component, w->reg, 673 SPKR_DRV_CLASSD_PA_EN_MASK, 674 SPKR_DRV_CLASSD_PA_EN_ENABLE); 675 break; 676 case SND_SOC_DAPM_POST_PMD: 677 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL, 678 SPKR_PWRSTG_CTL_DAC_EN_MASK| 679 SPKR_PWRSTG_CTL_BBM_MASK | 680 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | 681 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0); 682 683 snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL, 684 SPKR_DAC_CTL_DAC_RESET_MASK, 685 SPKR_DAC_CTL_DAC_RESET_NORMAL); 686 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 687 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0); 688 break; 689 } 690 return 0; 691 } 692 693 static int pm8916_wcd_analog_enable_ear_pa(struct snd_soc_dapm_widget *w, 694 struct snd_kcontrol *kcontrol, 695 int event) 696 { 697 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 698 699 switch (event) { 700 case SND_SOC_DAPM_PRE_PMU: 701 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 702 RX_EAR_CTL_PA_SEL_MASK, RX_EAR_CTL_PA_SEL); 703 break; 704 case SND_SOC_DAPM_POST_PMU: 705 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 706 RX_EAR_CTL_PA_EAR_PA_EN_MASK, 707 RX_EAR_CTL_PA_EAR_PA_EN_ENABLE); 708 break; 709 case SND_SOC_DAPM_POST_PMD: 710 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 711 RX_EAR_CTL_PA_EAR_PA_EN_MASK, 0); 712 /* Delay to reduce ear turn off pop */ 713 usleep_range(7000, 7100); 714 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 715 RX_EAR_CTL_PA_SEL_MASK, 0); 716 break; 717 } 718 return 0; 719 } 720 721 static const struct reg_default wcd_reg_defaults_2_0[] = { 722 {CDC_A_RX_COM_OCP_CTL, 0xD1}, 723 {CDC_A_RX_COM_OCP_COUNT, 0xFF}, 724 {CDC_D_SEC_ACCESS, 0xA5}, 725 {CDC_D_PERPH_RESET_CTL3, 0x0F}, 726 {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F}, 727 {CDC_A_NCP_FBCTRL, 0x28}, 728 {CDC_A_SPKR_DRV_CTL, 0x69}, 729 {CDC_A_SPKR_DRV_DBG, 0x01}, 730 {CDC_A_BOOST_EN_CTL, 0x5F}, 731 {CDC_A_SLOPE_COMP_IP_ZERO, 0x88}, 732 {CDC_A_SEC_ACCESS, 0xA5}, 733 {CDC_A_PERPH_RESET_CTL3, 0x0F}, 734 {CDC_A_CURRENT_LIMIT, 0x82}, 735 {CDC_A_SPKR_DAC_CTL, 0x03}, 736 {CDC_A_SPKR_OCP_CTL, 0xE1}, 737 {CDC_A_MASTER_BIAS_CTL, 0x30}, 738 }; 739 740 static int pm8916_wcd_analog_probe(struct snd_soc_component *component) 741 { 742 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); 743 int err, reg; 744 745 err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 746 if (err != 0) { 747 dev_err(component->dev, "failed to enable regulators (%d)\n", err); 748 return err; 749 } 750 751 snd_soc_component_init_regmap(component, 752 dev_get_regmap(component->dev->parent, NULL)); 753 snd_soc_component_set_drvdata(component, priv); 754 priv->pmic_rev = snd_soc_component_read32(component, CDC_D_REVISION1); 755 priv->codec_version = snd_soc_component_read32(component, CDC_D_PERPH_SUBTYPE); 756 757 dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n", 758 priv->pmic_rev, priv->codec_version); 759 760 snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01); 761 snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01); 762 763 for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++) 764 snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg, 765 wcd_reg_defaults_2_0[reg].def); 766 767 priv->component = component; 768 769 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL, 770 RST_CTL_DIG_SW_RST_N_MASK, 771 RST_CTL_DIG_SW_RST_N_REMOVE_RESET); 772 773 pm8916_wcd_setup_mbhc(priv); 774 775 return 0; 776 } 777 778 static void pm8916_wcd_analog_remove(struct snd_soc_component *component) 779 { 780 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); 781 782 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL, 783 RST_CTL_DIG_SW_RST_N_MASK, 0); 784 785 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 786 priv->supplies); 787 } 788 789 static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = { 790 791 {"PDM_RX1", NULL, "PDM Playback"}, 792 {"PDM_RX2", NULL, "PDM Playback"}, 793 {"PDM_RX3", NULL, "PDM Playback"}, 794 {"PDM Capture", NULL, "PDM_TX"}, 795 796 /* ADC Connections */ 797 {"PDM_TX", NULL, "ADC2"}, 798 {"PDM_TX", NULL, "ADC3"}, 799 {"ADC2", NULL, "ADC2 MUX"}, 800 {"ADC3", NULL, "ADC2 MUX"}, 801 {"ADC2 MUX", "INP2", "ADC2_INP2"}, 802 {"ADC2 MUX", "INP3", "ADC2_INP3"}, 803 804 {"PDM_TX", NULL, "ADC1"}, 805 {"ADC1", NULL, "AMIC1"}, 806 {"ADC2_INP2", NULL, "AMIC2"}, 807 {"ADC2_INP3", NULL, "AMIC3"}, 808 809 /* RDAC Connections */ 810 {"HPHR DAC", NULL, "RDAC2 MUX"}, 811 {"RDAC2 MUX", "RX1", "PDM_RX1"}, 812 {"RDAC2 MUX", "RX2", "PDM_RX2"}, 813 {"HPHL DAC", NULL, "PDM_RX1"}, 814 {"PDM_RX1", NULL, "RXD1_CLK"}, 815 {"PDM_RX2", NULL, "RXD2_CLK"}, 816 {"PDM_RX3", NULL, "RXD3_CLK"}, 817 818 {"PDM_RX1", NULL, "RXD_PDM_CLK"}, 819 {"PDM_RX2", NULL, "RXD_PDM_CLK"}, 820 {"PDM_RX3", NULL, "RXD_PDM_CLK"}, 821 822 {"ADC1", NULL, "TXD_CLK"}, 823 {"ADC2", NULL, "TXD_CLK"}, 824 {"ADC3", NULL, "TXD_CLK"}, 825 826 {"ADC1", NULL, "TXA_CLK25"}, 827 {"ADC2", NULL, "TXA_CLK25"}, 828 {"ADC3", NULL, "TXA_CLK25"}, 829 830 {"PDM_RX1", NULL, "A_MCLK2"}, 831 {"PDM_RX2", NULL, "A_MCLK2"}, 832 {"PDM_RX3", NULL, "A_MCLK2"}, 833 834 {"PDM_TX", NULL, "A_MCLK2"}, 835 {"A_MCLK2", NULL, "A_MCLK"}, 836 837 /* Earpiece (RX MIX1) */ 838 {"EAR", NULL, "EAR_S"}, 839 {"EAR_S", "Switch", "EAR PA"}, 840 {"EAR PA", NULL, "RX_BIAS"}, 841 {"EAR PA", NULL, "HPHL DAC"}, 842 {"EAR PA", NULL, "HPHR DAC"}, 843 {"EAR PA", NULL, "EAR CP"}, 844 845 /* Headset (RX MIX1 and RX MIX2) */ 846 {"HEADPHONE", NULL, "HPHL PA"}, 847 {"HEADPHONE", NULL, "HPHR PA"}, 848 849 {"HPHL DAC", NULL, "EAR_HPHL_CLK"}, 850 {"HPHR DAC", NULL, "EAR_HPHR_CLK"}, 851 852 {"CP", NULL, "NCP_CLK"}, 853 854 {"HPHL PA", NULL, "HPHL"}, 855 {"HPHR PA", NULL, "HPHR"}, 856 {"HPHL PA", NULL, "CP"}, 857 {"HPHL PA", NULL, "RX_BIAS"}, 858 {"HPHR PA", NULL, "CP"}, 859 {"HPHR PA", NULL, "RX_BIAS"}, 860 {"HPHL", "Switch", "HPHL DAC"}, 861 {"HPHR", "Switch", "HPHR DAC"}, 862 863 {"RX_BIAS", NULL, "DAC_REF"}, 864 865 {"SPK_OUT", NULL, "SPK PA"}, 866 {"SPK PA", NULL, "RX_BIAS"}, 867 {"SPK PA", NULL, "SPKR_CLK"}, 868 {"SPK PA", NULL, "SPK DAC"}, 869 {"SPK DAC", "Switch", "PDM_RX3"}, 870 871 {"MIC BIAS Internal1", NULL, "INT_LDO_H"}, 872 {"MIC BIAS Internal2", NULL, "INT_LDO_H"}, 873 {"MIC BIAS External1", NULL, "INT_LDO_H"}, 874 {"MIC BIAS External2", NULL, "INT_LDO_H"}, 875 {"MIC BIAS Internal1", NULL, "vdd-micbias"}, 876 {"MIC BIAS Internal2", NULL, "vdd-micbias"}, 877 {"MIC BIAS External1", NULL, "vdd-micbias"}, 878 {"MIC BIAS External2", NULL, "vdd-micbias"}, 879 }; 880 881 static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = { 882 883 SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 884 SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0), 885 SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0), 886 SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0), 887 888 SND_SOC_DAPM_INPUT("AMIC1"), 889 SND_SOC_DAPM_INPUT("AMIC3"), 890 SND_SOC_DAPM_INPUT("AMIC2"), 891 SND_SOC_DAPM_OUTPUT("EAR"), 892 SND_SOC_DAPM_OUTPUT("HEADPHONE"), 893 894 /* RX stuff */ 895 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0), 896 897 SND_SOC_DAPM_PGA_E("EAR PA", SND_SOC_NOPM, 898 0, 0, NULL, 0, 899 pm8916_wcd_analog_enable_ear_pa, 900 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 901 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 902 SND_SOC_DAPM_MUX("EAR_S", SND_SOC_NOPM, 0, 0, &ear_mux), 903 SND_SOC_DAPM_SUPPLY("EAR CP", CDC_A_NCP_EN, 4, 0, NULL, 0), 904 905 SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0), 906 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux), 907 SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL, 908 0), 909 SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0), 910 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux), 911 SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL, 912 0), 913 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0, 914 spkr_switch, ARRAY_SIZE(spkr_switch)), 915 916 /* Speaker */ 917 SND_SOC_DAPM_OUTPUT("SPK_OUT"), 918 SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL, 919 6, 0, NULL, 0, 920 pm8916_wcd_analog_enable_spk_pa, 921 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 922 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 923 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0), 924 SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0), 925 926 SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0), 927 SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0), 928 929 /* TX */ 930 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_EN, 7, 0, 931 pm8916_wcd_analog_enable_micbias_int1, 932 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 933 SND_SOC_DAPM_POST_PMD), 934 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_2_EN, 7, 0, 935 pm8916_wcd_analog_enable_micbias_int2, 936 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 937 SND_SOC_DAPM_POST_PMD), 938 939 SND_SOC_DAPM_SUPPLY("MIC BIAS External1", CDC_A_MICB_1_EN, 7, 0, 940 pm8916_wcd_analog_enable_micbias_ext1, 941 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 942 SND_SOC_DAPM_SUPPLY("MIC BIAS External2", CDC_A_MICB_2_EN, 7, 0, 943 pm8916_wcd_analog_enable_micbias_ext2, 944 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 945 946 SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0, 947 pm8916_wcd_analog_enable_adc, 948 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 949 SND_SOC_DAPM_POST_PMD), 950 SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0, 951 pm8916_wcd_analog_enable_adc, 952 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 953 SND_SOC_DAPM_POST_PMD), 954 SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0, 955 pm8916_wcd_analog_enable_adc, 956 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 957 SND_SOC_DAPM_POST_PMD), 958 959 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 960 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 961 962 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 963 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux), 964 965 /* Analog path clocks */ 966 SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL, 967 0), 968 SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL, 969 0), 970 SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0), 971 SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0), 972 973 /* Digital path clocks */ 974 975 SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0), 976 SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0), 977 SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0), 978 979 SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0), 980 SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0), 981 SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL, 982 0), 983 984 /* System Clock source */ 985 SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0), 986 /* TX ADC and RX DAC Clock source. */ 987 SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0), 988 }; 989 990 static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component, 991 struct snd_soc_jack *jack, 992 void *data) 993 { 994 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 995 996 wcd->jack = jack; 997 998 return 0; 999 } 1000 1001 static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg) 1002 { 1003 struct pm8916_wcd_analog_priv *priv = arg; 1004 1005 if (priv->detect_accessory_type) { 1006 struct snd_soc_component *component = priv->component; 1007 u32 val = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1); 1008 1009 /* check if its BTN0 thats released */ 1010 if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK)) 1011 priv->mbhc_btn0_released = true; 1012 1013 } else { 1014 snd_soc_jack_report(priv->jack, 0, btn_mask); 1015 } 1016 1017 return IRQ_HANDLED; 1018 } 1019 1020 static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg) 1021 { 1022 struct pm8916_wcd_analog_priv *priv = arg; 1023 struct snd_soc_component *component = priv->component; 1024 u32 btn_result; 1025 1026 btn_result = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1) & 1027 CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK; 1028 1029 switch (btn_result) { 1030 case 0xf: 1031 snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask); 1032 break; 1033 case 0x7: 1034 snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask); 1035 break; 1036 case 0x3: 1037 snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask); 1038 break; 1039 case 0x1: 1040 snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask); 1041 break; 1042 case 0x0: 1043 /* handle BTN_0 specially for type detection */ 1044 if (!priv->detect_accessory_type) 1045 snd_soc_jack_report(priv->jack, 1046 SND_JACK_BTN_0, btn_mask); 1047 break; 1048 default: 1049 dev_err(component->dev, 1050 "Unexpected button press result (%x)", btn_result); 1051 break; 1052 } 1053 1054 return IRQ_HANDLED; 1055 } 1056 1057 static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg) 1058 { 1059 struct pm8916_wcd_analog_priv *priv = arg; 1060 struct snd_soc_component *component = priv->component; 1061 bool ins = false; 1062 1063 if (snd_soc_component_read32(component, CDC_A_MBHC_DET_CTL_1) & 1064 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK) 1065 ins = true; 1066 1067 /* Set the detection type appropriately */ 1068 snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1, 1069 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK, 1070 (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT)); 1071 1072 1073 if (ins) { /* hs insertion */ 1074 bool micbias_enabled = false; 1075 1076 if (snd_soc_component_read32(component, CDC_A_MICB_2_EN) & 1077 CDC_A_MICB_2_EN_ENABLE) 1078 micbias_enabled = true; 1079 1080 pm8916_mbhc_configure_bias(priv, micbias_enabled); 1081 1082 /* 1083 * if only a btn0 press event is receive just before 1084 * insert event then its a 3 pole headphone else if 1085 * both press and release event received then its 1086 * a headset. 1087 */ 1088 if (priv->mbhc_btn0_released) 1089 snd_soc_jack_report(priv->jack, 1090 SND_JACK_HEADSET, hs_jack_mask); 1091 else 1092 snd_soc_jack_report(priv->jack, 1093 SND_JACK_HEADPHONE, hs_jack_mask); 1094 1095 priv->detect_accessory_type = false; 1096 1097 } else { /* removal */ 1098 snd_soc_jack_report(priv->jack, 0, hs_jack_mask); 1099 priv->detect_accessory_type = true; 1100 priv->mbhc_btn0_released = false; 1101 } 1102 1103 return IRQ_HANDLED; 1104 } 1105 1106 static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = { 1107 [0] = { 1108 .name = "pm8916_wcd_analog_pdm_rx", 1109 .id = 0, 1110 .playback = { 1111 .stream_name = "PDM Playback", 1112 .rates = MSM8916_WCD_ANALOG_RATES, 1113 .formats = MSM8916_WCD_ANALOG_FORMATS, 1114 .channels_min = 1, 1115 .channels_max = 3, 1116 }, 1117 }, 1118 [1] = { 1119 .name = "pm8916_wcd_analog_pdm_tx", 1120 .id = 1, 1121 .capture = { 1122 .stream_name = "PDM Capture", 1123 .rates = MSM8916_WCD_ANALOG_RATES, 1124 .formats = MSM8916_WCD_ANALOG_FORMATS, 1125 .channels_min = 1, 1126 .channels_max = 4, 1127 }, 1128 }, 1129 }; 1130 1131 static const struct snd_soc_component_driver pm8916_wcd_analog = { 1132 .probe = pm8916_wcd_analog_probe, 1133 .remove = pm8916_wcd_analog_remove, 1134 .set_jack = pm8916_wcd_analog_set_jack, 1135 .controls = pm8916_wcd_analog_snd_controls, 1136 .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls), 1137 .dapm_widgets = pm8916_wcd_analog_dapm_widgets, 1138 .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets), 1139 .dapm_routes = pm8916_wcd_analog_audio_map, 1140 .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map), 1141 .idle_bias_on = 1, 1142 .use_pmdown_time = 1, 1143 .endianness = 1, 1144 .non_legacy_dai_naming = 1, 1145 }; 1146 1147 static int pm8916_wcd_analog_parse_dt(struct device *dev, 1148 struct pm8916_wcd_analog_priv *priv) 1149 { 1150 int rval; 1151 1152 if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap")) 1153 priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP; 1154 else 1155 priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; 1156 1157 if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap")) 1158 priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP; 1159 else 1160 priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; 1161 1162 of_property_read_u32(dev->of_node, "qcom,micbias-lvl", 1163 &priv->micbias_mv); 1164 1165 if (of_property_read_bool(dev->of_node, 1166 "qcom,hphl-jack-type-normally-open")) 1167 priv->hphl_jack_type_normally_open = true; 1168 else 1169 priv->hphl_jack_type_normally_open = false; 1170 1171 if (of_property_read_bool(dev->of_node, 1172 "qcom,gnd-jack-type-normally-open")) 1173 priv->gnd_jack_type_normally_open = true; 1174 else 1175 priv->gnd_jack_type_normally_open = false; 1176 1177 priv->mbhc_btn_enabled = true; 1178 rval = of_property_read_u32_array(dev->of_node, 1179 "qcom,mbhc-vthreshold-low", 1180 &priv->vref_btn_cs[0], 1181 MBHC_MAX_BUTTONS); 1182 if (rval < 0) { 1183 priv->mbhc_btn_enabled = false; 1184 } else { 1185 rval = of_property_read_u32_array(dev->of_node, 1186 "qcom,mbhc-vthreshold-high", 1187 &priv->vref_btn_micb[0], 1188 MBHC_MAX_BUTTONS); 1189 if (rval < 0) 1190 priv->mbhc_btn_enabled = false; 1191 } 1192 1193 if (!priv->mbhc_btn_enabled) 1194 dev_err(dev, 1195 "DT property missing, MBHC btn detection disabled\n"); 1196 1197 1198 return 0; 1199 } 1200 1201 static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev) 1202 { 1203 struct pm8916_wcd_analog_priv *priv; 1204 struct device *dev = &pdev->dev; 1205 int ret, i, irq; 1206 1207 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1208 if (!priv) 1209 return -ENOMEM; 1210 1211 ret = pm8916_wcd_analog_parse_dt(dev, priv); 1212 if (ret < 0) 1213 return ret; 1214 1215 priv->mclk = devm_clk_get(dev, "mclk"); 1216 if (IS_ERR(priv->mclk)) { 1217 dev_err(dev, "failed to get mclk\n"); 1218 return PTR_ERR(priv->mclk); 1219 } 1220 1221 for (i = 0; i < ARRAY_SIZE(supply_names); i++) 1222 priv->supplies[i].supply = supply_names[i]; 1223 1224 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies), 1225 priv->supplies); 1226 if (ret) { 1227 dev_err(dev, "Failed to get regulator supplies %d\n", ret); 1228 return ret; 1229 } 1230 1231 ret = clk_prepare_enable(priv->mclk); 1232 if (ret < 0) { 1233 dev_err(dev, "failed to enable mclk %d\n", ret); 1234 return ret; 1235 } 1236 1237 irq = platform_get_irq_byname(pdev, "mbhc_switch_int"); 1238 if (irq < 0) 1239 return irq; 1240 1241 ret = devm_request_threaded_irq(dev, irq, NULL, 1242 pm8916_mbhc_switch_irq_handler, 1243 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | 1244 IRQF_ONESHOT, 1245 "mbhc switch irq", priv); 1246 if (ret) 1247 dev_err(dev, "cannot request mbhc switch irq\n"); 1248 1249 if (priv->mbhc_btn_enabled) { 1250 irq = platform_get_irq_byname(pdev, "mbhc_but_press_det"); 1251 if (irq < 0) 1252 return irq; 1253 1254 ret = devm_request_threaded_irq(dev, irq, NULL, 1255 mbhc_btn_press_irq_handler, 1256 IRQF_TRIGGER_RISING | 1257 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1258 "mbhc btn press irq", priv); 1259 if (ret) 1260 dev_err(dev, "cannot request mbhc button press irq\n"); 1261 1262 irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det"); 1263 if (irq < 0) 1264 return irq; 1265 1266 ret = devm_request_threaded_irq(dev, irq, NULL, 1267 mbhc_btn_release_irq_handler, 1268 IRQF_TRIGGER_RISING | 1269 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1270 "mbhc btn release irq", priv); 1271 if (ret) 1272 dev_err(dev, "cannot request mbhc button release irq\n"); 1273 1274 } 1275 1276 dev_set_drvdata(dev, priv); 1277 1278 return devm_snd_soc_register_component(dev, &pm8916_wcd_analog, 1279 pm8916_wcd_analog_dai, 1280 ARRAY_SIZE(pm8916_wcd_analog_dai)); 1281 } 1282 1283 static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev) 1284 { 1285 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev); 1286 1287 clk_disable_unprepare(priv->mclk); 1288 1289 return 0; 1290 } 1291 1292 static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = { 1293 { .compatible = "qcom,pm8916-wcd-analog-codec", }, 1294 { } 1295 }; 1296 1297 MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table); 1298 1299 static struct platform_driver pm8916_wcd_analog_spmi_driver = { 1300 .driver = { 1301 .name = "qcom,pm8916-wcd-spmi-codec", 1302 .of_match_table = pm8916_wcd_analog_spmi_match_table, 1303 }, 1304 .probe = pm8916_wcd_analog_spmi_probe, 1305 .remove = pm8916_wcd_analog_spmi_remove, 1306 }; 1307 1308 module_platform_driver(pm8916_wcd_analog_spmi_driver); 1309 1310 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>"); 1311 MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver"); 1312 MODULE_LICENSE("GPL v2"); 1313