1 #include <linux/module.h> 2 #include <linux/err.h> 3 #include <linux/kernel.h> 4 #include <linux/delay.h> 5 #include <linux/regulator/consumer.h> 6 #include <linux/types.h> 7 #include <linux/clk.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 #include <sound/soc.h> 12 #include <sound/pcm.h> 13 #include <sound/pcm_params.h> 14 #include <sound/tlv.h> 15 #include <sound/jack.h> 16 17 #define CDC_D_REVISION1 (0xf000) 18 #define CDC_D_PERPH_SUBTYPE (0xf005) 19 #define CDC_D_INT_EN_SET (0x015) 20 #define CDC_D_INT_EN_CLR (0x016) 21 #define MBHC_SWITCH_INT BIT(7) 22 #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6) 23 #define MBHC_BUTTON_PRESS_DET BIT(5) 24 #define MBHC_BUTTON_RELEASE_DET BIT(4) 25 #define CDC_D_CDC_RST_CTL (0xf046) 26 #define RST_CTL_DIG_SW_RST_N_MASK BIT(7) 27 #define RST_CTL_DIG_SW_RST_N_RESET 0 28 #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7) 29 30 #define CDC_D_CDC_TOP_CLK_CTL (0xf048) 31 #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3)) 32 #define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2) 33 #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3) 34 35 #define CDC_D_CDC_ANA_CLK_CTL (0xf049) 36 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0) 37 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0) 38 #define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1) 39 #define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4) 40 #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4) 41 #define ANA_CLK_CTL_TXA_CLK25_EN BIT(5) 42 43 #define CDC_D_CDC_DIG_CLK_CTL (0xf04A) 44 #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0) 45 #define DIG_CLK_CTL_RXD2_CLK_EN BIT(1) 46 #define DIG_CLK_CTL_RXD3_CLK_EN BIT(2) 47 #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3) 48 #define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3) 49 #define DIG_CLK_CTL_TXD_CLK_EN BIT(4) 50 #define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6) 51 #define DIG_CLK_CTL_NCP_CLK_EN BIT(6) 52 #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7) 53 #define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7) 54 55 #define CDC_D_CDC_CONN_TX1_CTL (0xf050) 56 #define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0) 57 #define CONN_TX1_SERIAL_TX1_ADC_1 0x0 58 #define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1 59 #define CONN_TX1_SERIAL_TX1_ZERO 0x2 60 61 #define CDC_D_CDC_CONN_TX2_CTL (0xf051) 62 #define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0) 63 #define CONN_TX2_SERIAL_TX2_ADC_2 0x0 64 #define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1 65 #define CONN_TX2_SERIAL_TX2_ZERO 0x2 66 #define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052) 67 #define CDC_D_CDC_CONN_RX1_CTL (0xf053) 68 #define CDC_D_CDC_CONN_RX2_CTL (0xf054) 69 #define CDC_D_CDC_CONN_RX3_CTL (0xf055) 70 #define CDC_D_CDC_CONN_RX_LB_CTL (0xf056) 71 #define CDC_D_SEC_ACCESS (0xf0D0) 72 #define CDC_D_PERPH_RESET_CTL3 (0xf0DA) 73 #define CDC_D_PERPH_RESET_CTL4 (0xf0DB) 74 #define CDC_A_REVISION1 (0xf100) 75 #define CDC_A_REVISION2 (0xf101) 76 #define CDC_A_REVISION3 (0xf102) 77 #define CDC_A_REVISION4 (0xf103) 78 #define CDC_A_PERPH_TYPE (0xf104) 79 #define CDC_A_PERPH_SUBTYPE (0xf105) 80 #define CDC_A_INT_RT_STS (0xf110) 81 #define CDC_A_INT_SET_TYPE (0xf111) 82 #define CDC_A_INT_POLARITY_HIGH (0xf112) 83 #define CDC_A_INT_POLARITY_LOW (0xf113) 84 #define CDC_A_INT_LATCHED_CLR (0xf114) 85 #define CDC_A_INT_EN_SET (0xf115) 86 #define CDC_A_INT_EN_CLR (0xf116) 87 #define CDC_A_INT_LATCHED_STS (0xf118) 88 #define CDC_A_INT_PENDING_STS (0xf119) 89 #define CDC_A_INT_MID_SEL (0xf11A) 90 #define CDC_A_INT_PRIORITY (0xf11B) 91 #define CDC_A_MICB_1_EN (0xf140) 92 #define MICB_1_EN_MICB_ENABLE BIT(7) 93 #define MICB_1_EN_BYP_CAP_MASK BIT(6) 94 #define MICB_1_EN_NO_EXT_BYP_CAP BIT(6) 95 #define MICB_1_EN_EXT_BYP_CAP 0 96 #define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5) 97 #define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5) 98 #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1) 99 #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4) 100 #define MICB_1_EN_PULL_UP_EN_MASK BIT(4) 101 #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0) 102 #define MICB_1_EN_TX3_GND_SEL_TX_GND 0 103 104 #define CDC_A_MICB_1_VAL (0xf141) 105 #define MICB_MIN_VAL 1600 106 #define MICB_STEP_SIZE 50 107 #define MICB_VOLTAGE_REGVAL(v) (((v - MICB_MIN_VAL)/MICB_STEP_SIZE) << 3) 108 #define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3) 109 #define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3) 110 #define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3) 111 #define CDC_A_MICB_1_CTL (0xf142) 112 113 #define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1) 114 #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1) 115 #define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5) 116 #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5) 117 #define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6) 118 #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6) 119 120 #define CDC_A_MICB_1_INT_RBIAS (0xf143) 121 #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7) 122 #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7) 123 #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0 124 125 #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6) 126 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6) 127 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0 128 129 #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4) 130 #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4) 131 #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0 132 #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3) 133 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3) 134 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0 135 136 #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1) 137 #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1) 138 #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0 139 #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0) 140 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0) 141 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0 142 143 #define CDC_A_MICB_2_EN (0xf144) 144 #define CDC_A_MICB_2_EN_ENABLE BIT(7) 145 #define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5) 146 #define CDC_A_MICB_2_PULL_DOWN_EN BIT(5) 147 #define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145) 148 #define CDC_A_MASTER_BIAS_CTL (0xf146) 149 #define CDC_A_MBHC_DET_CTL_1 (0xf147) 150 #define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7) 151 #define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6) 152 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5) 153 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0) 154 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5) 155 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5) 156 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4) 157 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3) 158 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3) 159 #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2) 160 #define CDC_A_MBHC_DET_CTL_2 (0xf150) 161 #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6)) 162 #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5) 163 #define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3) 164 #define CDC_A_HPHL_PLUG_TYPE_NO BIT(4) 165 #define CDC_A_GND_PLUG_TYPE_NO BIT(3) 166 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0) 167 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0) 168 #define CDC_A_MBHC_FSM_CTL (0xf151) 169 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7) 170 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7) 171 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4) 172 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4) 173 #define CDC_A_MBHC_DBNC_TIMER (0xf152) 174 #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3) 175 #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4) 176 #define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153) 177 #define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154) 178 #define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155) 179 #define CDC_A_MBHC_BTN3_CTL (0xf156) 180 #define CDC_A_MBHC_BTN4_CTL (0xf157) 181 #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2) 182 #define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2) 183 #define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5) 184 #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5) 185 #define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \ 186 CDC_A_MBHC_BTN_VREF_FINE_MASK) 187 #define CDC_A_MBHC_RESULT_1 (0xf158) 188 #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0) 189 #define CDC_A_TX_1_EN (0xf160) 190 #define CDC_A_TX_2_EN (0xf161) 191 #define CDC_A_TX_1_2_TEST_CTL_1 (0xf162) 192 #define CDC_A_TX_1_2_TEST_CTL_2 (0xf163) 193 #define CDC_A_TX_1_2_ATEST_CTL (0xf164) 194 #define CDC_A_TX_1_2_OPAMP_BIAS (0xf165) 195 #define CDC_A_TX_3_EN (0xf167) 196 #define CDC_A_NCP_EN (0xf180) 197 #define CDC_A_NCP_CLK (0xf181) 198 #define CDC_A_NCP_FBCTRL (0xf183) 199 #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5) 200 #define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5) 201 #define CDC_A_NCP_BIAS (0xf184) 202 #define CDC_A_NCP_VCTRL (0xf185) 203 #define CDC_A_NCP_TEST (0xf186) 204 #define CDC_A_NCP_CLIM_ADDR (0xf187) 205 #define CDC_A_RX_CLOCK_DIVIDER (0xf190) 206 #define CDC_A_RX_COM_OCP_CTL (0xf191) 207 #define CDC_A_RX_COM_OCP_COUNT (0xf192) 208 #define CDC_A_RX_COM_BIAS_DAC (0xf193) 209 #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7) 210 #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7) 211 #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0) 212 #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0) 213 214 #define CDC_A_RX_HPH_BIAS_PA (0xf194) 215 #define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195) 216 #define CDC_A_RX_HPH_BIAS_CNP (0xf196) 217 #define CDC_A_RX_HPH_CNP_EN (0xf197) 218 #define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B) 219 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1) 220 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1) 221 #define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D) 222 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1) 223 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1) 224 225 #define CDC_A_RX_EAR_CTL (0xf19E) 226 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0) 227 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0) 228 229 #define CDC_A_SPKR_DAC_CTL (0xf1B0) 230 #define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4) 231 #define SPKR_DAC_CTL_DAC_RESET_NORMAL 0 232 233 #define CDC_A_SPKR_DRV_CTL (0xf1B2) 234 #define SPKR_DRV_CTL_DEF_MASK 0xEF 235 #define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7) 236 #define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7) 237 #define SPKR_DRV_CAL_EN BIT(6) 238 #define SPKR_DRV_SETTLE_EN BIT(5) 239 #define SPKR_DRV_FW_EN BIT(3) 240 #define SPKR_DRV_BOOST_SET BIT(2) 241 #define SPKR_DRV_CMFB_SET BIT(1) 242 #define SPKR_DRV_GAIN_SET BIT(0) 243 #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \ 244 SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \ 245 SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \ 246 SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET) 247 #define CDC_A_SPKR_OCP_CTL (0xf1B4) 248 #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5) 249 #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0) 250 #define SPKR_PWRSTG_CTL_DAC_EN BIT(0) 251 #define SPKR_PWRSTG_CTL_MASK 0xE0 252 #define SPKR_PWRSTG_CTL_BBM_MASK BIT(7) 253 #define SPKR_PWRSTG_CTL_BBM_EN BIT(7) 254 #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6) 255 #define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6) 256 #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5) 257 #define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5) 258 259 #define CDC_A_SPKR_DRV_DBG (0xf1B7) 260 #define CDC_A_CURRENT_LIMIT (0xf1C0) 261 #define CDC_A_BOOST_EN_CTL (0xf1C3) 262 #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4) 263 #define CDC_A_SEC_ACCESS (0xf1D0) 264 #define CDC_A_PERPH_RESET_CTL3 (0xf1DA) 265 #define CDC_A_PERPH_RESET_CTL4 (0xf1DB) 266 267 #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 268 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) 269 #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 270 SNDRV_PCM_FMTBIT_S32_LE) 271 272 static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | 273 SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4; 274 static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET; 275 276 static const char * const supply_names[] = { 277 "vdd-cdc-io", 278 "vdd-cdc-tx-rx-cx", 279 }; 280 281 #define MBHC_MAX_BUTTONS (5) 282 283 struct pm8916_wcd_analog_priv { 284 u16 pmic_rev; 285 u16 codec_version; 286 bool mbhc_btn_enabled; 287 /* special event to detect accessory type */ 288 int mbhc_btn0_released; 289 bool detect_accessory_type; 290 struct clk *mclk; 291 struct snd_soc_component *component; 292 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; 293 struct snd_soc_jack *jack; 294 bool hphl_jack_type_normally_open; 295 bool gnd_jack_type_normally_open; 296 /* Voltage threshold when internal current source of 100uA is used */ 297 u32 vref_btn_cs[MBHC_MAX_BUTTONS]; 298 /* Voltage threshold when microphone bias is ON */ 299 u32 vref_btn_micb[MBHC_MAX_BUTTONS]; 300 unsigned int micbias1_cap_mode; 301 unsigned int micbias2_cap_mode; 302 unsigned int micbias_mv; 303 }; 304 305 static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" }; 306 static const char *const rdac2_mux_text[] = { "ZERO", "RX2", "RX1" }; 307 static const char *const hph_text[] = { "ZERO", "Switch", }; 308 309 static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT( 310 ARRAY_SIZE(hph_text), hph_text); 311 312 static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum); 313 static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum); 314 315 /* ADC2 MUX */ 316 static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT( 317 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 318 319 /* RDAC2 MUX */ 320 static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE( 321 CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 3, rdac2_mux_text); 322 323 static const struct snd_kcontrol_new spkr_switch[] = { 324 SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0) 325 }; 326 327 static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM( 328 "RDAC2 MUX Mux", rdac2_mux_enum); 329 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM( 330 "ADC2 MUX Mux", adc2_enum); 331 332 /* Analog Gain control 0 dB to +24 dB in 6 dB steps */ 333 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0); 334 335 static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = { 336 SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain), 337 SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain), 338 SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain), 339 }; 340 341 static void pm8916_wcd_analog_micbias_enable(struct snd_soc_component *component) 342 { 343 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 344 345 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 346 MICB_1_CTL_EXT_PRECHARG_EN_MASK | 347 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 348 MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL 349 | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE); 350 351 if (wcd->micbias_mv) { 352 snd_soc_component_update_bits(component, CDC_A_MICB_1_VAL, 353 MICB_1_VAL_MICB_OUT_VAL_MASK, 354 MICB_VOLTAGE_REGVAL(wcd->micbias_mv)); 355 /* 356 * Special headset needs MICBIAS as 2.7V so wait for 357 * 50 msec for the MICBIAS to reach 2.7 volts. 358 */ 359 if (wcd->micbias_mv >= 2700) 360 msleep(50); 361 } 362 363 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 364 MICB_1_CTL_EXT_PRECHARG_EN_MASK | 365 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0); 366 367 } 368 369 static int pm8916_wcd_analog_enable_micbias_ext(struct snd_soc_component 370 *component, int event, 371 int reg, unsigned int cap_mode) 372 { 373 switch (event) { 374 case SND_SOC_DAPM_POST_PMU: 375 pm8916_wcd_analog_micbias_enable(component); 376 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, 377 MICB_1_EN_BYP_CAP_MASK, cap_mode); 378 break; 379 } 380 381 return 0; 382 } 383 384 static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_component 385 *component, int event, 386 int reg, u32 cap_mode) 387 { 388 389 switch (event) { 390 case SND_SOC_DAPM_PRE_PMU: 391 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS, 392 MICB_1_INT_TX2_INT_RBIAS_EN_MASK, 393 MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); 394 snd_soc_component_update_bits(component, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0); 395 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, 396 MICB_1_EN_OPA_STG2_TAIL_CURR_MASK, 397 MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA); 398 399 break; 400 case SND_SOC_DAPM_POST_PMU: 401 pm8916_wcd_analog_micbias_enable(component); 402 snd_soc_component_update_bits(component, CDC_A_MICB_1_EN, 403 MICB_1_EN_BYP_CAP_MASK, cap_mode); 404 break; 405 } 406 407 return 0; 408 } 409 410 static int pm8916_wcd_analog_enable_micbias_ext1(struct 411 snd_soc_dapm_widget 412 *w, struct snd_kcontrol 413 *kcontrol, int event) 414 { 415 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 416 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 417 418 return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg, 419 wcd->micbias1_cap_mode); 420 } 421 422 static int pm8916_wcd_analog_enable_micbias_ext2(struct 423 snd_soc_dapm_widget 424 *w, struct snd_kcontrol 425 *kcontrol, int event) 426 { 427 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 428 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 429 430 return pm8916_wcd_analog_enable_micbias_ext(component, event, w->reg, 431 wcd->micbias2_cap_mode); 432 433 } 434 435 static int pm8916_wcd_analog_enable_micbias_int1(struct 436 snd_soc_dapm_widget 437 *w, struct snd_kcontrol 438 *kcontrol, int event) 439 { 440 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 441 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 442 443 return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg, 444 wcd->micbias1_cap_mode); 445 } 446 447 static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv, 448 bool micbias2_enabled) 449 { 450 struct snd_soc_component *component = priv->component; 451 u32 coarse, fine, reg_val, reg_addr; 452 int *vrefs, i; 453 454 if (!micbias2_enabled) { /* use internal 100uA Current source */ 455 /* Enable internal 2.2k Internal Rbias Resistor */ 456 snd_soc_component_update_bits(component, CDC_A_MICB_1_INT_RBIAS, 457 MICB_1_INT_TX2_INT_RBIAS_EN_MASK, 458 MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); 459 /* Remove pull down on MIC BIAS2 */ 460 snd_soc_component_update_bits(component, CDC_A_MICB_2_EN, 461 CDC_A_MICB_2_PULL_DOWN_EN_MASK, 462 0); 463 /* enable 100uA internal current source */ 464 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL, 465 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK, 466 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA); 467 } 468 snd_soc_component_update_bits(component, CDC_A_MBHC_FSM_CTL, 469 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK, 470 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN); 471 472 if (micbias2_enabled) 473 vrefs = &priv->vref_btn_micb[0]; 474 else 475 vrefs = &priv->vref_btn_cs[0]; 476 477 /* program vref ranges for all the buttons */ 478 reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0; 479 for (i = 0; i < MBHC_MAX_BUTTONS; i++) { 480 /* split mv in to coarse parts of 100mv & fine parts of 12mv */ 481 coarse = (vrefs[i] / 100); 482 fine = ((vrefs[i] % 100) / 12); 483 reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) | 484 (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT); 485 snd_soc_component_update_bits(component, reg_addr, 486 CDC_A_MBHC_BTN_VREF_MASK, 487 reg_val); 488 reg_addr++; 489 } 490 491 return 0; 492 } 493 494 static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd) 495 { 496 struct snd_soc_component *component = wcd->component; 497 bool micbias_enabled = false; 498 u32 plug_type = 0; 499 u32 int_en_mask; 500 501 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_1, 502 CDC_A_MBHC_DET_CTL_L_DET_EN | 503 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION | 504 CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO | 505 CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN); 506 507 if (wcd->hphl_jack_type_normally_open) 508 plug_type |= CDC_A_HPHL_PLUG_TYPE_NO; 509 510 if (wcd->gnd_jack_type_normally_open) 511 plug_type |= CDC_A_GND_PLUG_TYPE_NO; 512 513 snd_soc_component_write(component, CDC_A_MBHC_DET_CTL_2, 514 CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 | 515 CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD | 516 plug_type | 517 CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN); 518 519 520 snd_soc_component_write(component, CDC_A_MBHC_DBNC_TIMER, 521 CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS | 522 CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS); 523 524 /* enable MBHC clock */ 525 snd_soc_component_update_bits(component, CDC_D_CDC_DIG_CLK_CTL, 526 DIG_CLK_CTL_D_MBHC_CLK_EN_MASK, 527 DIG_CLK_CTL_D_MBHC_CLK_EN); 528 529 if (snd_soc_component_read32(component, CDC_A_MICB_2_EN) & CDC_A_MICB_2_EN_ENABLE) 530 micbias_enabled = true; 531 532 pm8916_mbhc_configure_bias(wcd, micbias_enabled); 533 534 int_en_mask = MBHC_SWITCH_INT; 535 if (wcd->mbhc_btn_enabled) 536 int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET; 537 538 snd_soc_component_update_bits(component, CDC_D_INT_EN_CLR, int_en_mask, 0); 539 snd_soc_component_update_bits(component, CDC_D_INT_EN_SET, int_en_mask, int_en_mask); 540 wcd->mbhc_btn0_released = false; 541 wcd->detect_accessory_type = true; 542 } 543 544 static int pm8916_wcd_analog_enable_micbias_int2(struct 545 snd_soc_dapm_widget 546 *w, struct snd_kcontrol 547 *kcontrol, int event) 548 { 549 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 550 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 551 552 switch (event) { 553 case SND_SOC_DAPM_POST_PMU: 554 pm8916_mbhc_configure_bias(wcd, true); 555 break; 556 case SND_SOC_DAPM_POST_PMD: 557 pm8916_mbhc_configure_bias(wcd, false); 558 break; 559 } 560 561 return pm8916_wcd_analog_enable_micbias_int(component, event, w->reg, 562 wcd->micbias2_cap_mode); 563 } 564 565 static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w, 566 struct snd_kcontrol *kcontrol, 567 int event) 568 { 569 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 570 u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2; 571 u8 init_bit_shift; 572 573 if (w->reg == CDC_A_TX_1_EN) 574 init_bit_shift = 5; 575 else 576 init_bit_shift = 4; 577 578 switch (event) { 579 case SND_SOC_DAPM_PRE_PMU: 580 if (w->reg == CDC_A_TX_2_EN) 581 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 582 MICB_1_CTL_CFILT_REF_SEL_MASK, 583 MICB_1_CTL_CFILT_REF_SEL_HPF_REF); 584 /* 585 * Add delay of 10 ms to give sufficient time for the voltage 586 * to shoot up and settle so that the txfe init does not 587 * happen when the input voltage is changing too much. 588 */ 589 usleep_range(10000, 10010); 590 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 591 1 << init_bit_shift); 592 switch (w->reg) { 593 case CDC_A_TX_1_EN: 594 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL, 595 CONN_TX1_SERIAL_TX1_MUX, 596 CONN_TX1_SERIAL_TX1_ADC_1); 597 break; 598 case CDC_A_TX_2_EN: 599 case CDC_A_TX_3_EN: 600 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL, 601 CONN_TX2_SERIAL_TX2_MUX, 602 CONN_TX2_SERIAL_TX2_ADC_2); 603 break; 604 } 605 break; 606 case SND_SOC_DAPM_POST_PMU: 607 /* 608 * Add delay of 12 ms before deasserting the init 609 * to reduce the tx pop 610 */ 611 usleep_range(12000, 12010); 612 snd_soc_component_update_bits(component, adc_reg, 1 << init_bit_shift, 0x00); 613 break; 614 case SND_SOC_DAPM_POST_PMD: 615 switch (w->reg) { 616 case CDC_A_TX_1_EN: 617 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX1_CTL, 618 CONN_TX1_SERIAL_TX1_MUX, 619 CONN_TX1_SERIAL_TX1_ZERO); 620 break; 621 case CDC_A_TX_2_EN: 622 snd_soc_component_update_bits(component, CDC_A_MICB_1_CTL, 623 MICB_1_CTL_CFILT_REF_SEL_MASK, 0); 624 /* fall through */ 625 case CDC_A_TX_3_EN: 626 snd_soc_component_update_bits(component, CDC_D_CDC_CONN_TX2_CTL, 627 CONN_TX2_SERIAL_TX2_MUX, 628 CONN_TX2_SERIAL_TX2_ZERO); 629 break; 630 } 631 632 633 break; 634 } 635 return 0; 636 } 637 638 static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w, 639 struct snd_kcontrol *kcontrol, 640 int event) 641 { 642 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 643 644 switch (event) { 645 case SND_SOC_DAPM_PRE_PMU: 646 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL, 647 SPKR_PWRSTG_CTL_DAC_EN_MASK | 648 SPKR_PWRSTG_CTL_BBM_MASK | 649 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | 650 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 651 SPKR_PWRSTG_CTL_DAC_EN| 652 SPKR_PWRSTG_CTL_BBM_EN | 653 SPKR_PWRSTG_CTL_HBRDGE_EN | 654 SPKR_PWRSTG_CTL_CLAMP_EN); 655 656 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 657 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 658 RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE); 659 break; 660 case SND_SOC_DAPM_POST_PMU: 661 snd_soc_component_update_bits(component, CDC_A_SPKR_DRV_CTL, 662 SPKR_DRV_CTL_DEF_MASK, 663 SPKR_DRV_CTL_DEF_VAL); 664 snd_soc_component_update_bits(component, w->reg, 665 SPKR_DRV_CLASSD_PA_EN_MASK, 666 SPKR_DRV_CLASSD_PA_EN_ENABLE); 667 break; 668 case SND_SOC_DAPM_POST_PMD: 669 snd_soc_component_update_bits(component, CDC_A_SPKR_PWRSTG_CTL, 670 SPKR_PWRSTG_CTL_DAC_EN_MASK| 671 SPKR_PWRSTG_CTL_BBM_MASK | 672 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | 673 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0); 674 675 snd_soc_component_update_bits(component, CDC_A_SPKR_DAC_CTL, 676 SPKR_DAC_CTL_DAC_RESET_MASK, 677 SPKR_DAC_CTL_DAC_RESET_NORMAL); 678 snd_soc_component_update_bits(component, CDC_A_RX_EAR_CTL, 679 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0); 680 break; 681 } 682 return 0; 683 } 684 685 static const struct reg_default wcd_reg_defaults_2_0[] = { 686 {CDC_A_RX_COM_OCP_CTL, 0xD1}, 687 {CDC_A_RX_COM_OCP_COUNT, 0xFF}, 688 {CDC_D_SEC_ACCESS, 0xA5}, 689 {CDC_D_PERPH_RESET_CTL3, 0x0F}, 690 {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F}, 691 {CDC_A_NCP_FBCTRL, 0x28}, 692 {CDC_A_SPKR_DRV_CTL, 0x69}, 693 {CDC_A_SPKR_DRV_DBG, 0x01}, 694 {CDC_A_BOOST_EN_CTL, 0x5F}, 695 {CDC_A_SLOPE_COMP_IP_ZERO, 0x88}, 696 {CDC_A_SEC_ACCESS, 0xA5}, 697 {CDC_A_PERPH_RESET_CTL3, 0x0F}, 698 {CDC_A_CURRENT_LIMIT, 0x82}, 699 {CDC_A_SPKR_DAC_CTL, 0x03}, 700 {CDC_A_SPKR_OCP_CTL, 0xE1}, 701 {CDC_A_MASTER_BIAS_CTL, 0x30}, 702 }; 703 704 static int pm8916_wcd_analog_probe(struct snd_soc_component *component) 705 { 706 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); 707 int err, reg; 708 709 err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 710 if (err != 0) { 711 dev_err(component->dev, "failed to enable regulators (%d)\n", err); 712 return err; 713 } 714 715 snd_soc_component_init_regmap(component, 716 dev_get_regmap(component->dev->parent, NULL)); 717 snd_soc_component_set_drvdata(component, priv); 718 priv->pmic_rev = snd_soc_component_read32(component, CDC_D_REVISION1); 719 priv->codec_version = snd_soc_component_read32(component, CDC_D_PERPH_SUBTYPE); 720 721 dev_info(component->dev, "PMIC REV: %d\t CODEC Version: %d\n", 722 priv->pmic_rev, priv->codec_version); 723 724 snd_soc_component_write(component, CDC_D_PERPH_RESET_CTL4, 0x01); 725 snd_soc_component_write(component, CDC_A_PERPH_RESET_CTL4, 0x01); 726 727 for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++) 728 snd_soc_component_write(component, wcd_reg_defaults_2_0[reg].reg, 729 wcd_reg_defaults_2_0[reg].def); 730 731 priv->component = component; 732 733 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL, 734 RST_CTL_DIG_SW_RST_N_MASK, 735 RST_CTL_DIG_SW_RST_N_REMOVE_RESET); 736 737 pm8916_wcd_setup_mbhc(priv); 738 739 return 0; 740 } 741 742 static void pm8916_wcd_analog_remove(struct snd_soc_component *component) 743 { 744 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(component->dev); 745 746 snd_soc_component_update_bits(component, CDC_D_CDC_RST_CTL, 747 RST_CTL_DIG_SW_RST_N_MASK, 0); 748 749 regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 750 priv->supplies); 751 } 752 753 static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = { 754 755 {"PDM_RX1", NULL, "PDM Playback"}, 756 {"PDM_RX2", NULL, "PDM Playback"}, 757 {"PDM_RX3", NULL, "PDM Playback"}, 758 {"PDM Capture", NULL, "PDM_TX"}, 759 760 /* ADC Connections */ 761 {"PDM_TX", NULL, "ADC2"}, 762 {"PDM_TX", NULL, "ADC3"}, 763 {"ADC2", NULL, "ADC2 MUX"}, 764 {"ADC3", NULL, "ADC2 MUX"}, 765 {"ADC2 MUX", "INP2", "ADC2_INP2"}, 766 {"ADC2 MUX", "INP3", "ADC2_INP3"}, 767 768 {"PDM_TX", NULL, "ADC1"}, 769 {"ADC1", NULL, "AMIC1"}, 770 {"ADC2_INP2", NULL, "AMIC2"}, 771 {"ADC2_INP3", NULL, "AMIC3"}, 772 773 /* RDAC Connections */ 774 {"HPHR DAC", NULL, "RDAC2 MUX"}, 775 {"RDAC2 MUX", "RX1", "PDM_RX1"}, 776 {"RDAC2 MUX", "RX2", "PDM_RX2"}, 777 {"HPHL DAC", NULL, "PDM_RX1"}, 778 {"PDM_RX1", NULL, "RXD1_CLK"}, 779 {"PDM_RX2", NULL, "RXD2_CLK"}, 780 {"PDM_RX3", NULL, "RXD3_CLK"}, 781 782 {"PDM_RX1", NULL, "RXD_PDM_CLK"}, 783 {"PDM_RX2", NULL, "RXD_PDM_CLK"}, 784 {"PDM_RX3", NULL, "RXD_PDM_CLK"}, 785 786 {"ADC1", NULL, "TXD_CLK"}, 787 {"ADC2", NULL, "TXD_CLK"}, 788 {"ADC3", NULL, "TXD_CLK"}, 789 790 {"ADC1", NULL, "TXA_CLK25"}, 791 {"ADC2", NULL, "TXA_CLK25"}, 792 {"ADC3", NULL, "TXA_CLK25"}, 793 794 {"PDM_RX1", NULL, "A_MCLK2"}, 795 {"PDM_RX2", NULL, "A_MCLK2"}, 796 {"PDM_RX3", NULL, "A_MCLK2"}, 797 798 {"PDM_TX", NULL, "A_MCLK2"}, 799 {"A_MCLK2", NULL, "A_MCLK"}, 800 801 /* Headset (RX MIX1 and RX MIX2) */ 802 {"HEADPHONE", NULL, "HPHL PA"}, 803 {"HEADPHONE", NULL, "HPHR PA"}, 804 805 {"HPHL PA", NULL, "EAR_HPHL_CLK"}, 806 {"HPHR PA", NULL, "EAR_HPHR_CLK"}, 807 808 {"CP", NULL, "NCP_CLK"}, 809 810 {"HPHL PA", NULL, "HPHL"}, 811 {"HPHR PA", NULL, "HPHR"}, 812 {"HPHL PA", NULL, "CP"}, 813 {"HPHL PA", NULL, "RX_BIAS"}, 814 {"HPHR PA", NULL, "CP"}, 815 {"HPHR PA", NULL, "RX_BIAS"}, 816 {"HPHL", "Switch", "HPHL DAC"}, 817 {"HPHR", "Switch", "HPHR DAC"}, 818 819 {"RX_BIAS", NULL, "DAC_REF"}, 820 821 {"SPK_OUT", NULL, "SPK PA"}, 822 {"SPK PA", NULL, "RX_BIAS"}, 823 {"SPK PA", NULL, "SPKR_CLK"}, 824 {"SPK PA", NULL, "SPK DAC"}, 825 {"SPK DAC", "Switch", "PDM_RX3"}, 826 827 {"MIC BIAS Internal1", NULL, "INT_LDO_H"}, 828 {"MIC BIAS Internal2", NULL, "INT_LDO_H"}, 829 {"MIC BIAS External1", NULL, "INT_LDO_H"}, 830 {"MIC BIAS External2", NULL, "INT_LDO_H"}, 831 {"MIC BIAS Internal1", NULL, "vdd-micbias"}, 832 {"MIC BIAS Internal2", NULL, "vdd-micbias"}, 833 {"MIC BIAS External1", NULL, "vdd-micbias"}, 834 {"MIC BIAS External2", NULL, "vdd-micbias"}, 835 }; 836 837 static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = { 838 839 SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 840 SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0), 841 SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0), 842 SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0), 843 844 SND_SOC_DAPM_INPUT("AMIC1"), 845 SND_SOC_DAPM_INPUT("AMIC3"), 846 SND_SOC_DAPM_INPUT("AMIC2"), 847 SND_SOC_DAPM_OUTPUT("HEADPHONE"), 848 849 /* RX stuff */ 850 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0), 851 852 SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0), 853 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux), 854 SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL, 855 0), 856 SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0), 857 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux), 858 SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL, 859 0), 860 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0, 861 spkr_switch, ARRAY_SIZE(spkr_switch)), 862 863 /* Speaker */ 864 SND_SOC_DAPM_OUTPUT("SPK_OUT"), 865 SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL, 866 6, 0, NULL, 0, 867 pm8916_wcd_analog_enable_spk_pa, 868 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 869 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 870 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0), 871 SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0), 872 873 SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0), 874 SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0), 875 876 /* TX */ 877 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_EN, 7, 0, 878 pm8916_wcd_analog_enable_micbias_int1, 879 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 880 SND_SOC_DAPM_POST_PMD), 881 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_2_EN, 7, 0, 882 pm8916_wcd_analog_enable_micbias_int2, 883 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 884 SND_SOC_DAPM_POST_PMD), 885 886 SND_SOC_DAPM_SUPPLY("MIC BIAS External1", CDC_A_MICB_1_EN, 7, 0, 887 pm8916_wcd_analog_enable_micbias_ext1, 888 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 889 SND_SOC_DAPM_SUPPLY("MIC BIAS External2", CDC_A_MICB_2_EN, 7, 0, 890 pm8916_wcd_analog_enable_micbias_ext2, 891 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 892 893 SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0, 894 pm8916_wcd_analog_enable_adc, 895 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 896 SND_SOC_DAPM_POST_PMD), 897 SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0, 898 pm8916_wcd_analog_enable_adc, 899 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 900 SND_SOC_DAPM_POST_PMD), 901 SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0, 902 pm8916_wcd_analog_enable_adc, 903 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 904 SND_SOC_DAPM_POST_PMD), 905 906 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 907 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 908 909 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 910 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux), 911 912 /* Analog path clocks */ 913 SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL, 914 0), 915 SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL, 916 0), 917 SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0), 918 SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0), 919 920 /* Digital path clocks */ 921 922 SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0), 923 SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0), 924 SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0), 925 926 SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0), 927 SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0), 928 SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL, 929 0), 930 931 /* System Clock source */ 932 SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0), 933 /* TX ADC and RX DAC Clock source. */ 934 SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0), 935 }; 936 937 static int pm8916_wcd_analog_set_jack(struct snd_soc_component *component, 938 struct snd_soc_jack *jack, 939 void *data) 940 { 941 struct pm8916_wcd_analog_priv *wcd = snd_soc_component_get_drvdata(component); 942 943 wcd->jack = jack; 944 945 return 0; 946 } 947 948 static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg) 949 { 950 struct pm8916_wcd_analog_priv *priv = arg; 951 952 if (priv->detect_accessory_type) { 953 struct snd_soc_component *component = priv->component; 954 u32 val = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1); 955 956 /* check if its BTN0 thats released */ 957 if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK)) 958 priv->mbhc_btn0_released = true; 959 960 } else { 961 snd_soc_jack_report(priv->jack, 0, btn_mask); 962 } 963 964 return IRQ_HANDLED; 965 } 966 967 static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg) 968 { 969 struct pm8916_wcd_analog_priv *priv = arg; 970 struct snd_soc_component *component = priv->component; 971 u32 btn_result; 972 973 btn_result = snd_soc_component_read32(component, CDC_A_MBHC_RESULT_1) & 974 CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK; 975 976 switch (btn_result) { 977 case 0xf: 978 snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask); 979 break; 980 case 0x7: 981 snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask); 982 break; 983 case 0x3: 984 snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask); 985 break; 986 case 0x1: 987 snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask); 988 break; 989 case 0x0: 990 /* handle BTN_0 specially for type detection */ 991 if (!priv->detect_accessory_type) 992 snd_soc_jack_report(priv->jack, 993 SND_JACK_BTN_0, btn_mask); 994 break; 995 default: 996 dev_err(component->dev, 997 "Unexpected button press result (%x)", btn_result); 998 break; 999 } 1000 1001 return IRQ_HANDLED; 1002 } 1003 1004 static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg) 1005 { 1006 struct pm8916_wcd_analog_priv *priv = arg; 1007 struct snd_soc_component *component = priv->component; 1008 bool ins = false; 1009 1010 if (snd_soc_component_read32(component, CDC_A_MBHC_DET_CTL_1) & 1011 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK) 1012 ins = true; 1013 1014 /* Set the detection type appropriately */ 1015 snd_soc_component_update_bits(component, CDC_A_MBHC_DET_CTL_1, 1016 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK, 1017 (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT)); 1018 1019 1020 if (ins) { /* hs insertion */ 1021 bool micbias_enabled = false; 1022 1023 if (snd_soc_component_read32(component, CDC_A_MICB_2_EN) & 1024 CDC_A_MICB_2_EN_ENABLE) 1025 micbias_enabled = true; 1026 1027 pm8916_mbhc_configure_bias(priv, micbias_enabled); 1028 1029 /* 1030 * if only a btn0 press event is receive just before 1031 * insert event then its a 3 pole headphone else if 1032 * both press and release event received then its 1033 * a headset. 1034 */ 1035 if (priv->mbhc_btn0_released) 1036 snd_soc_jack_report(priv->jack, 1037 SND_JACK_HEADSET, hs_jack_mask); 1038 else 1039 snd_soc_jack_report(priv->jack, 1040 SND_JACK_HEADPHONE, hs_jack_mask); 1041 1042 priv->detect_accessory_type = false; 1043 1044 } else { /* removal */ 1045 snd_soc_jack_report(priv->jack, 0, hs_jack_mask); 1046 priv->detect_accessory_type = true; 1047 priv->mbhc_btn0_released = false; 1048 } 1049 1050 return IRQ_HANDLED; 1051 } 1052 1053 static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = { 1054 [0] = { 1055 .name = "pm8916_wcd_analog_pdm_rx", 1056 .id = 0, 1057 .playback = { 1058 .stream_name = "PDM Playback", 1059 .rates = MSM8916_WCD_ANALOG_RATES, 1060 .formats = MSM8916_WCD_ANALOG_FORMATS, 1061 .channels_min = 1, 1062 .channels_max = 3, 1063 }, 1064 }, 1065 [1] = { 1066 .name = "pm8916_wcd_analog_pdm_tx", 1067 .id = 1, 1068 .capture = { 1069 .stream_name = "PDM Capture", 1070 .rates = MSM8916_WCD_ANALOG_RATES, 1071 .formats = MSM8916_WCD_ANALOG_FORMATS, 1072 .channels_min = 1, 1073 .channels_max = 4, 1074 }, 1075 }, 1076 }; 1077 1078 static const struct snd_soc_component_driver pm8916_wcd_analog = { 1079 .probe = pm8916_wcd_analog_probe, 1080 .remove = pm8916_wcd_analog_remove, 1081 .set_jack = pm8916_wcd_analog_set_jack, 1082 .controls = pm8916_wcd_analog_snd_controls, 1083 .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls), 1084 .dapm_widgets = pm8916_wcd_analog_dapm_widgets, 1085 .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets), 1086 .dapm_routes = pm8916_wcd_analog_audio_map, 1087 .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map), 1088 .idle_bias_on = 1, 1089 .use_pmdown_time = 1, 1090 .endianness = 1, 1091 .non_legacy_dai_naming = 1, 1092 }; 1093 1094 static int pm8916_wcd_analog_parse_dt(struct device *dev, 1095 struct pm8916_wcd_analog_priv *priv) 1096 { 1097 int rval; 1098 1099 if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap")) 1100 priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP; 1101 else 1102 priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; 1103 1104 if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap")) 1105 priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP; 1106 else 1107 priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; 1108 1109 of_property_read_u32(dev->of_node, "qcom,micbias-lvl", 1110 &priv->micbias_mv); 1111 1112 if (of_property_read_bool(dev->of_node, 1113 "qcom,hphl-jack-type-normally-open")) 1114 priv->hphl_jack_type_normally_open = true; 1115 else 1116 priv->hphl_jack_type_normally_open = false; 1117 1118 if (of_property_read_bool(dev->of_node, 1119 "qcom,gnd-jack-type-normally-open")) 1120 priv->gnd_jack_type_normally_open = true; 1121 else 1122 priv->gnd_jack_type_normally_open = false; 1123 1124 priv->mbhc_btn_enabled = true; 1125 rval = of_property_read_u32_array(dev->of_node, 1126 "qcom,mbhc-vthreshold-low", 1127 &priv->vref_btn_cs[0], 1128 MBHC_MAX_BUTTONS); 1129 if (rval < 0) { 1130 priv->mbhc_btn_enabled = false; 1131 } else { 1132 rval = of_property_read_u32_array(dev->of_node, 1133 "qcom,mbhc-vthreshold-high", 1134 &priv->vref_btn_micb[0], 1135 MBHC_MAX_BUTTONS); 1136 if (rval < 0) 1137 priv->mbhc_btn_enabled = false; 1138 } 1139 1140 if (!priv->mbhc_btn_enabled) 1141 dev_err(dev, 1142 "DT property missing, MBHC btn detection disabled\n"); 1143 1144 1145 return 0; 1146 } 1147 1148 static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev) 1149 { 1150 struct pm8916_wcd_analog_priv *priv; 1151 struct device *dev = &pdev->dev; 1152 int ret, i, irq; 1153 1154 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1155 if (!priv) 1156 return -ENOMEM; 1157 1158 ret = pm8916_wcd_analog_parse_dt(dev, priv); 1159 if (ret < 0) 1160 return ret; 1161 1162 priv->mclk = devm_clk_get(dev, "mclk"); 1163 if (IS_ERR(priv->mclk)) { 1164 dev_err(dev, "failed to get mclk\n"); 1165 return PTR_ERR(priv->mclk); 1166 } 1167 1168 for (i = 0; i < ARRAY_SIZE(supply_names); i++) 1169 priv->supplies[i].supply = supply_names[i]; 1170 1171 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies), 1172 priv->supplies); 1173 if (ret) { 1174 dev_err(dev, "Failed to get regulator supplies %d\n", ret); 1175 return ret; 1176 } 1177 1178 ret = clk_prepare_enable(priv->mclk); 1179 if (ret < 0) { 1180 dev_err(dev, "failed to enable mclk %d\n", ret); 1181 return ret; 1182 } 1183 1184 irq = platform_get_irq_byname(pdev, "mbhc_switch_int"); 1185 if (irq < 0) { 1186 dev_err(dev, "failed to get mbhc switch irq\n"); 1187 return irq; 1188 } 1189 1190 ret = devm_request_threaded_irq(dev, irq, NULL, 1191 pm8916_mbhc_switch_irq_handler, 1192 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | 1193 IRQF_ONESHOT, 1194 "mbhc switch irq", priv); 1195 if (ret) 1196 dev_err(dev, "cannot request mbhc switch irq\n"); 1197 1198 if (priv->mbhc_btn_enabled) { 1199 irq = platform_get_irq_byname(pdev, "mbhc_but_press_det"); 1200 if (irq < 0) { 1201 dev_err(dev, "failed to get button press irq\n"); 1202 return irq; 1203 } 1204 1205 ret = devm_request_threaded_irq(dev, irq, NULL, 1206 mbhc_btn_press_irq_handler, 1207 IRQF_TRIGGER_RISING | 1208 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1209 "mbhc btn press irq", priv); 1210 if (ret) 1211 dev_err(dev, "cannot request mbhc button press irq\n"); 1212 1213 irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det"); 1214 if (irq < 0) { 1215 dev_err(dev, "failed to get button release irq\n"); 1216 return irq; 1217 } 1218 1219 ret = devm_request_threaded_irq(dev, irq, NULL, 1220 mbhc_btn_release_irq_handler, 1221 IRQF_TRIGGER_RISING | 1222 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1223 "mbhc btn release irq", priv); 1224 if (ret) 1225 dev_err(dev, "cannot request mbhc button release irq\n"); 1226 1227 } 1228 1229 dev_set_drvdata(dev, priv); 1230 1231 return devm_snd_soc_register_component(dev, &pm8916_wcd_analog, 1232 pm8916_wcd_analog_dai, 1233 ARRAY_SIZE(pm8916_wcd_analog_dai)); 1234 } 1235 1236 static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev) 1237 { 1238 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev); 1239 1240 clk_disable_unprepare(priv->mclk); 1241 1242 return 0; 1243 } 1244 1245 static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = { 1246 { .compatible = "qcom,pm8916-wcd-analog-codec", }, 1247 { } 1248 }; 1249 1250 MODULE_DEVICE_TABLE(of, pm8916_wcd_analog_spmi_match_table); 1251 1252 static struct platform_driver pm8916_wcd_analog_spmi_driver = { 1253 .driver = { 1254 .name = "qcom,pm8916-wcd-spmi-codec", 1255 .of_match_table = pm8916_wcd_analog_spmi_match_table, 1256 }, 1257 .probe = pm8916_wcd_analog_spmi_probe, 1258 .remove = pm8916_wcd_analog_spmi_remove, 1259 }; 1260 1261 module_platform_driver(pm8916_wcd_analog_spmi_driver); 1262 1263 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>"); 1264 MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver"); 1265 MODULE_LICENSE("GPL v2"); 1266