1 #include <linux/module.h> 2 #include <linux/err.h> 3 #include <linux/kernel.h> 4 #include <linux/delay.h> 5 #include <linux/regulator/consumer.h> 6 #include <linux/types.h> 7 #include <linux/clk.h> 8 #include <linux/of.h> 9 #include <linux/platform_device.h> 10 #include <linux/regmap.h> 11 #include <sound/soc.h> 12 #include <sound/pcm.h> 13 #include <sound/pcm_params.h> 14 #include <sound/tlv.h> 15 #include <sound/jack.h> 16 17 #define CDC_D_REVISION1 (0xf000) 18 #define CDC_D_PERPH_SUBTYPE (0xf005) 19 #define CDC_D_INT_EN_SET (0x015) 20 #define CDC_D_INT_EN_CLR (0x016) 21 #define MBHC_SWITCH_INT BIT(7) 22 #define MBHC_MIC_ELECTRICAL_INS_REM_DET BIT(6) 23 #define MBHC_BUTTON_PRESS_DET BIT(5) 24 #define MBHC_BUTTON_RELEASE_DET BIT(4) 25 #define CDC_D_CDC_RST_CTL (0xf046) 26 #define RST_CTL_DIG_SW_RST_N_MASK BIT(7) 27 #define RST_CTL_DIG_SW_RST_N_RESET 0 28 #define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7) 29 30 #define CDC_D_CDC_TOP_CLK_CTL (0xf048) 31 #define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3)) 32 #define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2) 33 #define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3) 34 35 #define CDC_D_CDC_ANA_CLK_CTL (0xf049) 36 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0) 37 #define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0) 38 #define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1) 39 #define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4) 40 #define ANA_CLK_CTL_SPKR_CLK_EN BIT(4) 41 #define ANA_CLK_CTL_TXA_CLK25_EN BIT(5) 42 43 #define CDC_D_CDC_DIG_CLK_CTL (0xf04A) 44 #define DIG_CLK_CTL_RXD1_CLK_EN BIT(0) 45 #define DIG_CLK_CTL_RXD2_CLK_EN BIT(1) 46 #define DIG_CLK_CTL_RXD3_CLK_EN BIT(2) 47 #define DIG_CLK_CTL_D_MBHC_CLK_EN_MASK BIT(3) 48 #define DIG_CLK_CTL_D_MBHC_CLK_EN BIT(3) 49 #define DIG_CLK_CTL_TXD_CLK_EN BIT(4) 50 #define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6) 51 #define DIG_CLK_CTL_NCP_CLK_EN BIT(6) 52 #define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7) 53 #define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7) 54 55 #define CDC_D_CDC_CONN_TX1_CTL (0xf050) 56 #define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0) 57 #define CONN_TX1_SERIAL_TX1_ADC_1 0x0 58 #define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1 59 #define CONN_TX1_SERIAL_TX1_ZERO 0x2 60 61 #define CDC_D_CDC_CONN_TX2_CTL (0xf051) 62 #define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0) 63 #define CONN_TX2_SERIAL_TX2_ADC_2 0x0 64 #define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1 65 #define CONN_TX2_SERIAL_TX2_ZERO 0x2 66 #define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052) 67 #define CDC_D_CDC_CONN_RX1_CTL (0xf053) 68 #define CDC_D_CDC_CONN_RX2_CTL (0xf054) 69 #define CDC_D_CDC_CONN_RX3_CTL (0xf055) 70 #define CDC_D_CDC_CONN_RX_LB_CTL (0xf056) 71 #define CDC_D_SEC_ACCESS (0xf0D0) 72 #define CDC_D_PERPH_RESET_CTL3 (0xf0DA) 73 #define CDC_D_PERPH_RESET_CTL4 (0xf0DB) 74 #define CDC_A_REVISION1 (0xf100) 75 #define CDC_A_REVISION2 (0xf101) 76 #define CDC_A_REVISION3 (0xf102) 77 #define CDC_A_REVISION4 (0xf103) 78 #define CDC_A_PERPH_TYPE (0xf104) 79 #define CDC_A_PERPH_SUBTYPE (0xf105) 80 #define CDC_A_INT_RT_STS (0xf110) 81 #define CDC_A_INT_SET_TYPE (0xf111) 82 #define CDC_A_INT_POLARITY_HIGH (0xf112) 83 #define CDC_A_INT_POLARITY_LOW (0xf113) 84 #define CDC_A_INT_LATCHED_CLR (0xf114) 85 #define CDC_A_INT_EN_SET (0xf115) 86 #define CDC_A_INT_EN_CLR (0xf116) 87 #define CDC_A_INT_LATCHED_STS (0xf118) 88 #define CDC_A_INT_PENDING_STS (0xf119) 89 #define CDC_A_INT_MID_SEL (0xf11A) 90 #define CDC_A_INT_PRIORITY (0xf11B) 91 #define CDC_A_MICB_1_EN (0xf140) 92 #define MICB_1_EN_MICB_ENABLE BIT(7) 93 #define MICB_1_EN_BYP_CAP_MASK BIT(6) 94 #define MICB_1_EN_NO_EXT_BYP_CAP BIT(6) 95 #define MICB_1_EN_EXT_BYP_CAP 0 96 #define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5) 97 #define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5) 98 #define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1) 99 #define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4) 100 #define MICB_1_EN_PULL_UP_EN_MASK BIT(4) 101 #define MICB_1_EN_TX3_GND_SEL_MASK BIT(0) 102 #define MICB_1_EN_TX3_GND_SEL_TX_GND 0 103 104 #define CDC_A_MICB_1_VAL (0xf141) 105 #define MICB_MIN_VAL 1600 106 #define MICB_STEP_SIZE 50 107 #define MICB_VOLTAGE_REGVAL(v) ((v - MICB_MIN_VAL)/MICB_STEP_SIZE) 108 #define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3) 109 #define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3) 110 #define MICB_1_VAL_MICB_OUT_VAL_V1P80V ((0x4) << 3) 111 #define CDC_A_MICB_1_CTL (0xf142) 112 113 #define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1) 114 #define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1) 115 #define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5) 116 #define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5) 117 #define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6) 118 #define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6) 119 120 #define CDC_A_MICB_1_INT_RBIAS (0xf143) 121 #define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7) 122 #define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7) 123 #define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0 124 125 #define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6) 126 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6) 127 #define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0 128 129 #define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4) 130 #define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4) 131 #define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0 132 #define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3) 133 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3) 134 #define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0 135 136 #define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1) 137 #define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1) 138 #define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0 139 #define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0) 140 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0) 141 #define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0 142 143 #define CDC_A_MICB_2_EN (0xf144) 144 #define CDC_A_MICB_2_EN_ENABLE BIT(7) 145 #define CDC_A_MICB_2_PULL_DOWN_EN_MASK BIT(5) 146 #define CDC_A_MICB_2_PULL_DOWN_EN BIT(5) 147 #define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145) 148 #define CDC_A_MASTER_BIAS_CTL (0xf146) 149 #define CDC_A_MBHC_DET_CTL_1 (0xf147) 150 #define CDC_A_MBHC_DET_CTL_L_DET_EN BIT(7) 151 #define CDC_A_MBHC_DET_CTL_GND_DET_EN BIT(6) 152 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION BIT(5) 153 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_REMOVAL (0) 154 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK BIT(5) 155 #define CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT (5) 156 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO BIT(4) 157 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MANUAL BIT(3) 158 #define CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_MASK GENMASK(4, 3) 159 #define CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN BIT(2) 160 #define CDC_A_MBHC_DET_CTL_2 (0xf150) 161 #define CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 (BIT(7) | BIT(6)) 162 #define CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD BIT(5) 163 #define CDC_A_PLUG_TYPE_MASK GENMASK(4, 3) 164 #define CDC_A_HPHL_PLUG_TYPE_NO BIT(4) 165 #define CDC_A_GND_PLUG_TYPE_NO BIT(3) 166 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN_MASK BIT(0) 167 #define CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN BIT(0) 168 #define CDC_A_MBHC_FSM_CTL (0xf151) 169 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN BIT(7) 170 #define CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK BIT(7) 171 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA (0x3 << 4) 172 #define CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK GENMASK(6, 4) 173 #define CDC_A_MBHC_DBNC_TIMER (0xf152) 174 #define CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS BIT(3) 175 #define CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS (0x9 << 4) 176 #define CDC_A_MBHC_BTN0_ZDET_CTL_0 (0xf153) 177 #define CDC_A_MBHC_BTN1_ZDET_CTL_1 (0xf154) 178 #define CDC_A_MBHC_BTN2_ZDET_CTL_2 (0xf155) 179 #define CDC_A_MBHC_BTN3_CTL (0xf156) 180 #define CDC_A_MBHC_BTN4_CTL (0xf157) 181 #define CDC_A_MBHC_BTN_VREF_FINE_SHIFT (2) 182 #define CDC_A_MBHC_BTN_VREF_FINE_MASK GENMASK(4, 2) 183 #define CDC_A_MBHC_BTN_VREF_COARSE_MASK GENMASK(7, 5) 184 #define CDC_A_MBHC_BTN_VREF_COARSE_SHIFT (5) 185 #define CDC_A_MBHC_BTN_VREF_MASK (CDC_A_MBHC_BTN_VREF_COARSE_MASK | \ 186 CDC_A_MBHC_BTN_VREF_FINE_MASK) 187 #define CDC_A_MBHC_RESULT_1 (0xf158) 188 #define CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK GENMASK(4, 0) 189 #define CDC_A_TX_1_EN (0xf160) 190 #define CDC_A_TX_2_EN (0xf161) 191 #define CDC_A_TX_1_2_TEST_CTL_1 (0xf162) 192 #define CDC_A_TX_1_2_TEST_CTL_2 (0xf163) 193 #define CDC_A_TX_1_2_ATEST_CTL (0xf164) 194 #define CDC_A_TX_1_2_OPAMP_BIAS (0xf165) 195 #define CDC_A_TX_3_EN (0xf167) 196 #define CDC_A_NCP_EN (0xf180) 197 #define CDC_A_NCP_CLK (0xf181) 198 #define CDC_A_NCP_FBCTRL (0xf183) 199 #define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5) 200 #define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5) 201 #define CDC_A_NCP_BIAS (0xf184) 202 #define CDC_A_NCP_VCTRL (0xf185) 203 #define CDC_A_NCP_TEST (0xf186) 204 #define CDC_A_NCP_CLIM_ADDR (0xf187) 205 #define CDC_A_RX_CLOCK_DIVIDER (0xf190) 206 #define CDC_A_RX_COM_OCP_CTL (0xf191) 207 #define CDC_A_RX_COM_OCP_COUNT (0xf192) 208 #define CDC_A_RX_COM_BIAS_DAC (0xf193) 209 #define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7) 210 #define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7) 211 #define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0) 212 #define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0) 213 214 #define CDC_A_RX_HPH_BIAS_PA (0xf194) 215 #define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195) 216 #define CDC_A_RX_HPH_BIAS_CNP (0xf196) 217 #define CDC_A_RX_HPH_CNP_EN (0xf197) 218 #define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B) 219 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1) 220 #define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1) 221 #define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D) 222 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1) 223 #define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1) 224 225 #define CDC_A_RX_EAR_CTL (0xf19E) 226 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0) 227 #define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0) 228 229 #define CDC_A_SPKR_DAC_CTL (0xf1B0) 230 #define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4) 231 #define SPKR_DAC_CTL_DAC_RESET_NORMAL 0 232 233 #define CDC_A_SPKR_DRV_CTL (0xf1B2) 234 #define SPKR_DRV_CTL_DEF_MASK 0xEF 235 #define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7) 236 #define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7) 237 #define SPKR_DRV_CAL_EN BIT(6) 238 #define SPKR_DRV_SETTLE_EN BIT(5) 239 #define SPKR_DRV_FW_EN BIT(3) 240 #define SPKR_DRV_BOOST_SET BIT(2) 241 #define SPKR_DRV_CMFB_SET BIT(1) 242 #define SPKR_DRV_GAIN_SET BIT(0) 243 #define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \ 244 SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \ 245 SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \ 246 SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET) 247 #define CDC_A_SPKR_OCP_CTL (0xf1B4) 248 #define CDC_A_SPKR_PWRSTG_CTL (0xf1B5) 249 #define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0) 250 #define SPKR_PWRSTG_CTL_DAC_EN BIT(0) 251 #define SPKR_PWRSTG_CTL_MASK 0xE0 252 #define SPKR_PWRSTG_CTL_BBM_MASK BIT(7) 253 #define SPKR_PWRSTG_CTL_BBM_EN BIT(7) 254 #define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6) 255 #define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6) 256 #define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5) 257 #define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5) 258 259 #define CDC_A_SPKR_DRV_DBG (0xf1B7) 260 #define CDC_A_CURRENT_LIMIT (0xf1C0) 261 #define CDC_A_BOOST_EN_CTL (0xf1C3) 262 #define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4) 263 #define CDC_A_SEC_ACCESS (0xf1D0) 264 #define CDC_A_PERPH_RESET_CTL3 (0xf1DA) 265 #define CDC_A_PERPH_RESET_CTL4 (0xf1DB) 266 267 #define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 268 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) 269 #define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 270 SNDRV_PCM_FMTBIT_S24_LE) 271 272 static int btn_mask = SND_JACK_BTN_0 | SND_JACK_BTN_1 | 273 SND_JACK_BTN_2 | SND_JACK_BTN_3 | SND_JACK_BTN_4; 274 static int hs_jack_mask = SND_JACK_HEADPHONE | SND_JACK_HEADSET; 275 276 static const char * const supply_names[] = { 277 "vdd-cdc-io", 278 "vdd-cdc-tx-rx-cx", 279 }; 280 281 #define MBHC_MAX_BUTTONS (5) 282 283 struct pm8916_wcd_analog_priv { 284 u16 pmic_rev; 285 u16 codec_version; 286 bool mbhc_btn_enabled; 287 /* special event to detect accessory type */ 288 bool mbhc_btn0_pressed; 289 bool detect_accessory_type; 290 struct clk *mclk; 291 struct snd_soc_codec *codec; 292 struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; 293 struct snd_soc_jack *jack; 294 bool hphl_jack_type_normally_open; 295 bool gnd_jack_type_normally_open; 296 /* Voltage threshold when internal current source of 100uA is used */ 297 u32 vref_btn_cs[MBHC_MAX_BUTTONS]; 298 /* Voltage threshold when microphone bias is ON */ 299 u32 vref_btn_micb[MBHC_MAX_BUTTONS]; 300 unsigned int micbias1_cap_mode; 301 unsigned int micbias2_cap_mode; 302 unsigned int micbias_mv; 303 }; 304 305 static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" }; 306 static const char *const rdac2_mux_text[] = { "ZERO", "RX2", "RX1" }; 307 static const char *const hph_text[] = { "ZERO", "Switch", }; 308 309 static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT( 310 ARRAY_SIZE(hph_text), hph_text); 311 312 static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum); 313 static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum); 314 315 /* ADC2 MUX */ 316 static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT( 317 ARRAY_SIZE(adc2_mux_text), adc2_mux_text); 318 319 /* RDAC2 MUX */ 320 static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE( 321 CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 3, rdac2_mux_text); 322 323 static const struct snd_kcontrol_new spkr_switch[] = { 324 SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0) 325 }; 326 327 static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM( 328 "RDAC2 MUX Mux", rdac2_mux_enum); 329 static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM( 330 "ADC2 MUX Mux", adc2_enum); 331 332 /* Analog Gain control 0 dB to +24 dB in 6 dB steps */ 333 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0); 334 335 static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = { 336 SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain), 337 SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain), 338 SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain), 339 }; 340 341 static void pm8916_wcd_analog_micbias_enable(struct snd_soc_codec *codec) 342 { 343 struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec); 344 345 snd_soc_update_bits(codec, CDC_A_MICB_1_CTL, 346 MICB_1_CTL_EXT_PRECHARG_EN_MASK | 347 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 348 MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL 349 | MICB_1_CTL_EXT_PRECHARG_EN_ENABLE); 350 351 if (wcd->micbias_mv) { 352 snd_soc_write(codec, CDC_A_MICB_1_VAL, 353 MICB_VOLTAGE_REGVAL(wcd->micbias_mv)); 354 /* 355 * Special headset needs MICBIAS as 2.7V so wait for 356 * 50 msec for the MICBIAS to reach 2.7 volts. 357 */ 358 if (wcd->micbias_mv >= 2700) 359 msleep(50); 360 } 361 362 snd_soc_update_bits(codec, CDC_A_MICB_1_CTL, 363 MICB_1_CTL_EXT_PRECHARG_EN_MASK | 364 MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0); 365 366 } 367 368 static int pm8916_wcd_analog_enable_micbias_ext(struct snd_soc_codec 369 *codec, int event, 370 int reg, unsigned int cap_mode) 371 { 372 switch (event) { 373 case SND_SOC_DAPM_POST_PMU: 374 pm8916_wcd_analog_micbias_enable(codec); 375 snd_soc_update_bits(codec, CDC_A_MICB_1_EN, 376 MICB_1_EN_BYP_CAP_MASK, cap_mode); 377 break; 378 } 379 380 return 0; 381 } 382 383 static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_codec 384 *codec, int event, 385 int reg, u32 cap_mode) 386 { 387 388 switch (event) { 389 case SND_SOC_DAPM_PRE_PMU: 390 snd_soc_update_bits(codec, CDC_A_MICB_1_INT_RBIAS, 391 MICB_1_INT_TX2_INT_RBIAS_EN_MASK, 392 MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); 393 snd_soc_update_bits(codec, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0); 394 snd_soc_update_bits(codec, CDC_A_MICB_1_EN, 395 MICB_1_EN_OPA_STG2_TAIL_CURR_MASK, 396 MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA); 397 398 break; 399 case SND_SOC_DAPM_POST_PMU: 400 pm8916_wcd_analog_micbias_enable(codec); 401 snd_soc_update_bits(codec, CDC_A_MICB_1_EN, 402 MICB_1_EN_BYP_CAP_MASK, cap_mode); 403 break; 404 } 405 406 return 0; 407 } 408 409 static int pm8916_wcd_analog_enable_micbias_ext1(struct 410 snd_soc_dapm_widget 411 *w, struct snd_kcontrol 412 *kcontrol, int event) 413 { 414 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 415 struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec); 416 417 return pm8916_wcd_analog_enable_micbias_ext(codec, event, w->reg, 418 wcd->micbias1_cap_mode); 419 } 420 421 static int pm8916_wcd_analog_enable_micbias_ext2(struct 422 snd_soc_dapm_widget 423 *w, struct snd_kcontrol 424 *kcontrol, int event) 425 { 426 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 427 struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec); 428 429 return pm8916_wcd_analog_enable_micbias_ext(codec, event, w->reg, 430 wcd->micbias2_cap_mode); 431 432 } 433 434 static int pm8916_wcd_analog_enable_micbias_int1(struct 435 snd_soc_dapm_widget 436 *w, struct snd_kcontrol 437 *kcontrol, int event) 438 { 439 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 440 struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec); 441 442 return pm8916_wcd_analog_enable_micbias_int(codec, event, w->reg, 443 wcd->micbias1_cap_mode); 444 } 445 446 static void pm8916_wcd_setup_mbhc(struct pm8916_wcd_analog_priv *wcd) 447 { 448 struct snd_soc_codec *codec = wcd->codec; 449 u32 plug_type = 0; 450 u32 int_en_mask; 451 452 snd_soc_write(codec, CDC_A_MBHC_DET_CTL_1, 453 CDC_A_MBHC_DET_CTL_L_DET_EN | 454 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_INSERTION | 455 CDC_A_MBHC_DET_CTL_MIC_CLAMP_CTL_AUTO | 456 CDC_A_MBHC_DET_CTL_MBHC_BIAS_EN); 457 458 if (wcd->hphl_jack_type_normally_open) 459 plug_type |= CDC_A_HPHL_PLUG_TYPE_NO; 460 461 if (wcd->gnd_jack_type_normally_open) 462 plug_type |= CDC_A_GND_PLUG_TYPE_NO; 463 464 snd_soc_write(codec, CDC_A_MBHC_DET_CTL_2, 465 CDC_A_MBHC_DET_CTL_HS_L_DET_PULL_UP_CTRL_I_3P0 | 466 CDC_A_MBHC_DET_CTL_HS_L_DET_COMPA_CTRL_V0P9_VDD | 467 plug_type | 468 CDC_A_MBHC_DET_CTL_HPHL_100K_TO_GND_EN); 469 470 471 snd_soc_write(codec, CDC_A_MBHC_DBNC_TIMER, 472 CDC_A_MBHC_DBNC_TIMER_INSREM_DBNC_T_256_MS | 473 CDC_A_MBHC_DBNC_TIMER_BTN_DBNC_T_16MS); 474 475 /* enable MBHC clock */ 476 snd_soc_update_bits(codec, CDC_D_CDC_DIG_CLK_CTL, 477 DIG_CLK_CTL_D_MBHC_CLK_EN_MASK, 478 DIG_CLK_CTL_D_MBHC_CLK_EN); 479 480 int_en_mask = MBHC_SWITCH_INT; 481 if (wcd->mbhc_btn_enabled) 482 int_en_mask |= MBHC_BUTTON_PRESS_DET | MBHC_BUTTON_RELEASE_DET; 483 484 snd_soc_update_bits(codec, CDC_D_INT_EN_CLR, int_en_mask, 0); 485 snd_soc_update_bits(codec, CDC_D_INT_EN_SET, int_en_mask, int_en_mask); 486 wcd->mbhc_btn0_pressed = false; 487 wcd->detect_accessory_type = true; 488 } 489 490 static int pm8916_mbhc_configure_bias(struct pm8916_wcd_analog_priv *priv, 491 bool micbias2_enabled) 492 { 493 struct snd_soc_codec *codec = priv->codec; 494 u32 coarse, fine, reg_val, reg_addr; 495 int *vrefs, i; 496 497 if (!micbias2_enabled) { /* use internal 100uA Current source */ 498 /* Enable internal 2.2k Internal Rbias Resistor */ 499 snd_soc_update_bits(codec, CDC_A_MICB_1_INT_RBIAS, 500 MICB_1_INT_TX2_INT_RBIAS_EN_MASK, 501 MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); 502 /* Remove pull down on MIC BIAS2 */ 503 snd_soc_update_bits(codec, CDC_A_MICB_2_EN, 504 CDC_A_MICB_2_PULL_DOWN_EN_MASK, 505 0); 506 /* enable 100uA internal current source */ 507 snd_soc_update_bits(codec, CDC_A_MBHC_FSM_CTL, 508 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_MASK, 509 CDC_A_MBHC_FSM_CTL_BTN_ISRC_CTRL_I_100UA); 510 } 511 snd_soc_update_bits(codec, CDC_A_MBHC_FSM_CTL, 512 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN_MASK, 513 CDC_A_MBHC_FSM_CTL_MBHC_FSM_EN); 514 515 if (micbias2_enabled) 516 vrefs = &priv->vref_btn_micb[0]; 517 else 518 vrefs = &priv->vref_btn_cs[0]; 519 520 /* program vref ranges for all the buttons */ 521 reg_addr = CDC_A_MBHC_BTN0_ZDET_CTL_0; 522 for (i = 0; i < MBHC_MAX_BUTTONS; i++) { 523 /* split mv in to coarse parts of 100mv & fine parts of 12mv */ 524 coarse = (vrefs[i] / 100); 525 fine = ((vrefs[i] % 100) / 12); 526 reg_val = (coarse << CDC_A_MBHC_BTN_VREF_COARSE_SHIFT) | 527 (fine << CDC_A_MBHC_BTN_VREF_FINE_SHIFT); 528 snd_soc_update_bits(codec, reg_addr, 529 CDC_A_MBHC_BTN_VREF_MASK, 530 reg_val); 531 reg_addr++; 532 } 533 534 return 0; 535 } 536 537 static int pm8916_wcd_analog_enable_micbias_int2(struct 538 snd_soc_dapm_widget 539 *w, struct snd_kcontrol 540 *kcontrol, int event) 541 { 542 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 543 struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec); 544 545 switch (event) { 546 case SND_SOC_DAPM_POST_PMU: 547 pm8916_mbhc_configure_bias(wcd, true); 548 break; 549 case SND_SOC_DAPM_POST_PMD: 550 pm8916_mbhc_configure_bias(wcd, false); 551 break; 552 } 553 554 return pm8916_wcd_analog_enable_micbias_int(codec, event, w->reg, 555 wcd->micbias2_cap_mode); 556 } 557 558 static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w, 559 struct snd_kcontrol *kcontrol, 560 int event) 561 { 562 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 563 u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2; 564 u8 init_bit_shift; 565 566 if (w->reg == CDC_A_TX_1_EN) 567 init_bit_shift = 5; 568 else 569 init_bit_shift = 4; 570 571 switch (event) { 572 case SND_SOC_DAPM_PRE_PMU: 573 if (w->reg == CDC_A_TX_2_EN) 574 snd_soc_update_bits(codec, CDC_A_MICB_1_CTL, 575 MICB_1_CTL_CFILT_REF_SEL_MASK, 576 MICB_1_CTL_CFILT_REF_SEL_HPF_REF); 577 /* 578 * Add delay of 10 ms to give sufficient time for the voltage 579 * to shoot up and settle so that the txfe init does not 580 * happen when the input voltage is changing too much. 581 */ 582 usleep_range(10000, 10010); 583 snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 584 1 << init_bit_shift); 585 switch (w->reg) { 586 case CDC_A_TX_1_EN: 587 snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX1_CTL, 588 CONN_TX1_SERIAL_TX1_MUX, 589 CONN_TX1_SERIAL_TX1_ADC_1); 590 break; 591 case CDC_A_TX_2_EN: 592 case CDC_A_TX_3_EN: 593 snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX2_CTL, 594 CONN_TX2_SERIAL_TX2_MUX, 595 CONN_TX2_SERIAL_TX2_ADC_2); 596 break; 597 } 598 break; 599 case SND_SOC_DAPM_POST_PMU: 600 /* 601 * Add delay of 12 ms before deasserting the init 602 * to reduce the tx pop 603 */ 604 usleep_range(12000, 12010); 605 snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00); 606 break; 607 case SND_SOC_DAPM_POST_PMD: 608 switch (w->reg) { 609 case CDC_A_TX_1_EN: 610 snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX1_CTL, 611 CONN_TX1_SERIAL_TX1_MUX, 612 CONN_TX1_SERIAL_TX1_ZERO); 613 break; 614 case CDC_A_TX_2_EN: 615 snd_soc_update_bits(codec, CDC_A_MICB_1_CTL, 616 MICB_1_CTL_CFILT_REF_SEL_MASK, 0); 617 case CDC_A_TX_3_EN: 618 snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX2_CTL, 619 CONN_TX2_SERIAL_TX2_MUX, 620 CONN_TX2_SERIAL_TX2_ZERO); 621 break; 622 } 623 624 625 break; 626 } 627 return 0; 628 } 629 630 static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w, 631 struct snd_kcontrol *kcontrol, 632 int event) 633 { 634 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 635 636 switch (event) { 637 case SND_SOC_DAPM_PRE_PMU: 638 snd_soc_update_bits(codec, CDC_A_SPKR_PWRSTG_CTL, 639 SPKR_PWRSTG_CTL_DAC_EN_MASK | 640 SPKR_PWRSTG_CTL_BBM_MASK | 641 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | 642 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 643 SPKR_PWRSTG_CTL_DAC_EN| 644 SPKR_PWRSTG_CTL_BBM_EN | 645 SPKR_PWRSTG_CTL_HBRDGE_EN | 646 SPKR_PWRSTG_CTL_CLAMP_EN); 647 648 snd_soc_update_bits(codec, CDC_A_RX_EAR_CTL, 649 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 650 RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE); 651 break; 652 case SND_SOC_DAPM_POST_PMU: 653 snd_soc_update_bits(codec, CDC_A_SPKR_DRV_CTL, 654 SPKR_DRV_CTL_DEF_MASK, 655 SPKR_DRV_CTL_DEF_VAL); 656 snd_soc_update_bits(codec, w->reg, 657 SPKR_DRV_CLASSD_PA_EN_MASK, 658 SPKR_DRV_CLASSD_PA_EN_ENABLE); 659 break; 660 case SND_SOC_DAPM_POST_PMD: 661 snd_soc_update_bits(codec, CDC_A_SPKR_PWRSTG_CTL, 662 SPKR_PWRSTG_CTL_DAC_EN_MASK| 663 SPKR_PWRSTG_CTL_BBM_MASK | 664 SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | 665 SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0); 666 667 snd_soc_update_bits(codec, CDC_A_SPKR_DAC_CTL, 668 SPKR_DAC_CTL_DAC_RESET_MASK, 669 SPKR_DAC_CTL_DAC_RESET_NORMAL); 670 snd_soc_update_bits(codec, CDC_A_RX_EAR_CTL, 671 RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0); 672 break; 673 } 674 return 0; 675 } 676 677 static const struct reg_default wcd_reg_defaults_2_0[] = { 678 {CDC_A_RX_COM_OCP_CTL, 0xD1}, 679 {CDC_A_RX_COM_OCP_COUNT, 0xFF}, 680 {CDC_D_SEC_ACCESS, 0xA5}, 681 {CDC_D_PERPH_RESET_CTL3, 0x0F}, 682 {CDC_A_TX_1_2_OPAMP_BIAS, 0x4F}, 683 {CDC_A_NCP_FBCTRL, 0x28}, 684 {CDC_A_SPKR_DRV_CTL, 0x69}, 685 {CDC_A_SPKR_DRV_DBG, 0x01}, 686 {CDC_A_BOOST_EN_CTL, 0x5F}, 687 {CDC_A_SLOPE_COMP_IP_ZERO, 0x88}, 688 {CDC_A_SEC_ACCESS, 0xA5}, 689 {CDC_A_PERPH_RESET_CTL3, 0x0F}, 690 {CDC_A_CURRENT_LIMIT, 0x82}, 691 {CDC_A_SPKR_DAC_CTL, 0x03}, 692 {CDC_A_SPKR_OCP_CTL, 0xE1}, 693 {CDC_A_MASTER_BIAS_CTL, 0x30}, 694 }; 695 696 static int pm8916_wcd_analog_probe(struct snd_soc_codec *codec) 697 { 698 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(codec->dev); 699 int err, reg; 700 701 err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 702 if (err != 0) { 703 dev_err(codec->dev, "failed to enable regulators (%d)\n", err); 704 return err; 705 } 706 707 snd_soc_codec_set_drvdata(codec, priv); 708 priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1); 709 priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE); 710 711 dev_info(codec->dev, "PMIC REV: %d\t CODEC Version: %d\n", 712 priv->pmic_rev, priv->codec_version); 713 714 snd_soc_write(codec, CDC_D_PERPH_RESET_CTL4, 0x01); 715 snd_soc_write(codec, CDC_A_PERPH_RESET_CTL4, 0x01); 716 717 for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++) 718 snd_soc_write(codec, wcd_reg_defaults_2_0[reg].reg, 719 wcd_reg_defaults_2_0[reg].def); 720 721 priv->codec = codec; 722 723 snd_soc_update_bits(codec, CDC_D_CDC_RST_CTL, 724 RST_CTL_DIG_SW_RST_N_MASK, 725 RST_CTL_DIG_SW_RST_N_REMOVE_RESET); 726 727 pm8916_wcd_setup_mbhc(priv); 728 729 return 0; 730 } 731 732 static int pm8916_wcd_analog_remove(struct snd_soc_codec *codec) 733 { 734 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(codec->dev); 735 736 snd_soc_update_bits(codec, CDC_D_CDC_RST_CTL, 737 RST_CTL_DIG_SW_RST_N_MASK, 0); 738 739 return regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 740 priv->supplies); 741 } 742 743 static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = { 744 745 {"PDM_RX1", NULL, "PDM Playback"}, 746 {"PDM_RX2", NULL, "PDM Playback"}, 747 {"PDM_RX3", NULL, "PDM Playback"}, 748 {"PDM Capture", NULL, "PDM_TX"}, 749 750 /* ADC Connections */ 751 {"PDM_TX", NULL, "ADC2"}, 752 {"PDM_TX", NULL, "ADC3"}, 753 {"ADC2", NULL, "ADC2 MUX"}, 754 {"ADC3", NULL, "ADC2 MUX"}, 755 {"ADC2 MUX", "INP2", "ADC2_INP2"}, 756 {"ADC2 MUX", "INP3", "ADC2_INP3"}, 757 758 {"PDM_TX", NULL, "ADC1"}, 759 {"ADC1", NULL, "AMIC1"}, 760 {"ADC2_INP2", NULL, "AMIC2"}, 761 {"ADC2_INP3", NULL, "AMIC3"}, 762 763 /* RDAC Connections */ 764 {"HPHR DAC", NULL, "RDAC2 MUX"}, 765 {"RDAC2 MUX", "RX1", "PDM_RX1"}, 766 {"RDAC2 MUX", "RX2", "PDM_RX2"}, 767 {"HPHL DAC", NULL, "PDM_RX1"}, 768 {"PDM_RX1", NULL, "RXD1_CLK"}, 769 {"PDM_RX2", NULL, "RXD2_CLK"}, 770 {"PDM_RX3", NULL, "RXD3_CLK"}, 771 772 {"PDM_RX1", NULL, "RXD_PDM_CLK"}, 773 {"PDM_RX2", NULL, "RXD_PDM_CLK"}, 774 {"PDM_RX3", NULL, "RXD_PDM_CLK"}, 775 776 {"ADC1", NULL, "TXD_CLK"}, 777 {"ADC2", NULL, "TXD_CLK"}, 778 {"ADC3", NULL, "TXD_CLK"}, 779 780 {"ADC1", NULL, "TXA_CLK25"}, 781 {"ADC2", NULL, "TXA_CLK25"}, 782 {"ADC3", NULL, "TXA_CLK25"}, 783 784 {"PDM_RX1", NULL, "A_MCLK2"}, 785 {"PDM_RX2", NULL, "A_MCLK2"}, 786 {"PDM_RX3", NULL, "A_MCLK2"}, 787 788 {"PDM_TX", NULL, "A_MCLK2"}, 789 {"A_MCLK2", NULL, "A_MCLK"}, 790 791 /* Headset (RX MIX1 and RX MIX2) */ 792 {"HEADPHONE", NULL, "HPHL PA"}, 793 {"HEADPHONE", NULL, "HPHR PA"}, 794 795 {"HPHL PA", NULL, "EAR_HPHL_CLK"}, 796 {"HPHR PA", NULL, "EAR_HPHR_CLK"}, 797 798 {"CP", NULL, "NCP_CLK"}, 799 800 {"HPHL PA", NULL, "HPHL"}, 801 {"HPHR PA", NULL, "HPHR"}, 802 {"HPHL PA", NULL, "CP"}, 803 {"HPHL PA", NULL, "RX_BIAS"}, 804 {"HPHR PA", NULL, "CP"}, 805 {"HPHR PA", NULL, "RX_BIAS"}, 806 {"HPHL", "Switch", "HPHL DAC"}, 807 {"HPHR", "Switch", "HPHR DAC"}, 808 809 {"RX_BIAS", NULL, "DAC_REF"}, 810 811 {"SPK_OUT", NULL, "SPK PA"}, 812 {"SPK PA", NULL, "RX_BIAS"}, 813 {"SPK PA", NULL, "SPKR_CLK"}, 814 {"SPK PA", NULL, "SPK DAC"}, 815 {"SPK DAC", "Switch", "PDM_RX3"}, 816 817 {"MIC BIAS Internal1", NULL, "INT_LDO_H"}, 818 {"MIC BIAS Internal2", NULL, "INT_LDO_H"}, 819 {"MIC BIAS External1", NULL, "INT_LDO_H"}, 820 {"MIC BIAS External2", NULL, "INT_LDO_H"}, 821 {"MIC BIAS Internal1", NULL, "vdd-micbias"}, 822 {"MIC BIAS Internal2", NULL, "vdd-micbias"}, 823 {"MIC BIAS External1", NULL, "vdd-micbias"}, 824 {"MIC BIAS External2", NULL, "vdd-micbias"}, 825 }; 826 827 static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = { 828 829 SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0), 830 SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0), 831 SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0), 832 SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0), 833 834 SND_SOC_DAPM_INPUT("AMIC1"), 835 SND_SOC_DAPM_INPUT("AMIC3"), 836 SND_SOC_DAPM_INPUT("AMIC2"), 837 SND_SOC_DAPM_OUTPUT("HEADPHONE"), 838 839 /* RX stuff */ 840 SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0), 841 842 SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0), 843 SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux), 844 SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL, 845 0), 846 SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0), 847 SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux), 848 SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL, 849 0), 850 SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0, 851 spkr_switch, ARRAY_SIZE(spkr_switch)), 852 853 /* Speaker */ 854 SND_SOC_DAPM_OUTPUT("SPK_OUT"), 855 SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL, 856 6, 0, NULL, 0, 857 pm8916_wcd_analog_enable_spk_pa, 858 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 859 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 860 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0), 861 SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0), 862 863 SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0), 864 SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0), 865 866 /* TX */ 867 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_EN, 7, 0, 868 pm8916_wcd_analog_enable_micbias_int1, 869 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 870 SND_SOC_DAPM_POST_PMD), 871 SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_2_EN, 7, 0, 872 pm8916_wcd_analog_enable_micbias_int2, 873 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 874 SND_SOC_DAPM_POST_PMD), 875 876 SND_SOC_DAPM_SUPPLY("MIC BIAS External1", CDC_A_MICB_1_EN, 7, 0, 877 pm8916_wcd_analog_enable_micbias_ext1, 878 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 879 SND_SOC_DAPM_SUPPLY("MIC BIAS External2", CDC_A_MICB_2_EN, 7, 0, 880 pm8916_wcd_analog_enable_micbias_ext2, 881 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 882 883 SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0, 884 pm8916_wcd_analog_enable_adc, 885 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 886 SND_SOC_DAPM_POST_PMD), 887 SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0, 888 pm8916_wcd_analog_enable_adc, 889 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 890 SND_SOC_DAPM_POST_PMD), 891 SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0, 892 pm8916_wcd_analog_enable_adc, 893 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 894 SND_SOC_DAPM_POST_PMD), 895 896 SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), 897 SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), 898 899 SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), 900 SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux), 901 902 /* Analog path clocks */ 903 SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL, 904 0), 905 SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL, 906 0), 907 SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0), 908 SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0), 909 910 /* Digital path clocks */ 911 912 SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0), 913 SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0), 914 SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0), 915 916 SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0), 917 SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0), 918 SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL, 919 0), 920 921 /* System Clock source */ 922 SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0), 923 /* TX ADC and RX DAC Clock source. */ 924 SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0), 925 }; 926 927 static int pm8916_wcd_analog_set_jack(struct snd_soc_codec *codec, 928 struct snd_soc_jack *jack, 929 void *data) 930 { 931 struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec); 932 933 wcd->jack = jack; 934 935 return 0; 936 } 937 938 static struct regmap *pm8916_get_regmap(struct device *dev) 939 { 940 return dev_get_regmap(dev->parent, NULL); 941 } 942 943 static irqreturn_t mbhc_btn_release_irq_handler(int irq, void *arg) 944 { 945 struct pm8916_wcd_analog_priv *priv = arg; 946 947 if (priv->detect_accessory_type) { 948 struct snd_soc_codec *codec = priv->codec; 949 u32 val = snd_soc_read(codec, CDC_A_MBHC_RESULT_1); 950 951 /* check if its BTN0 thats released */ 952 if ((val != -1) && !(val & CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK)) 953 priv->mbhc_btn0_pressed = false; 954 955 } else { 956 snd_soc_jack_report(priv->jack, 0, btn_mask); 957 } 958 959 return IRQ_HANDLED; 960 } 961 962 static irqreturn_t mbhc_btn_press_irq_handler(int irq, void *arg) 963 { 964 struct pm8916_wcd_analog_priv *priv = arg; 965 struct snd_soc_codec *codec = priv->codec; 966 u32 btn_result; 967 968 btn_result = snd_soc_read(codec, CDC_A_MBHC_RESULT_1) & 969 CDC_A_MBHC_RESULT_1_BTN_RESULT_MASK; 970 971 switch (btn_result) { 972 case 0xf: 973 snd_soc_jack_report(priv->jack, SND_JACK_BTN_4, btn_mask); 974 break; 975 case 0x7: 976 snd_soc_jack_report(priv->jack, SND_JACK_BTN_3, btn_mask); 977 break; 978 case 0x3: 979 snd_soc_jack_report(priv->jack, SND_JACK_BTN_2, btn_mask); 980 break; 981 case 0x1: 982 snd_soc_jack_report(priv->jack, SND_JACK_BTN_1, btn_mask); 983 break; 984 case 0x0: 985 /* handle BTN_0 specially for type detection */ 986 if (priv->detect_accessory_type) 987 priv->mbhc_btn0_pressed = true; 988 else 989 snd_soc_jack_report(priv->jack, 990 SND_JACK_BTN_0, btn_mask); 991 break; 992 default: 993 dev_err(codec->dev, 994 "Unexpected button press result (%x)", btn_result); 995 break; 996 } 997 998 return IRQ_HANDLED; 999 } 1000 1001 static irqreturn_t pm8916_mbhc_switch_irq_handler(int irq, void *arg) 1002 { 1003 struct pm8916_wcd_analog_priv *priv = arg; 1004 struct snd_soc_codec *codec = priv->codec; 1005 bool ins = false; 1006 1007 if (snd_soc_read(codec, CDC_A_MBHC_DET_CTL_1) & 1008 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK) 1009 ins = true; 1010 1011 /* Set the detection type appropriately */ 1012 snd_soc_update_bits(codec, CDC_A_MBHC_DET_CTL_1, 1013 CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_MASK, 1014 (!ins << CDC_A_MBHC_DET_CTL_MECH_DET_TYPE_SHIFT)); 1015 1016 1017 if (ins) { /* hs insertion */ 1018 bool micbias_enabled = false; 1019 1020 if (snd_soc_read(codec, CDC_A_MICB_2_EN) & 1021 CDC_A_MICB_2_EN_ENABLE) 1022 micbias_enabled = true; 1023 1024 pm8916_mbhc_configure_bias(priv, micbias_enabled); 1025 1026 /* 1027 * if only a btn0 press event is receive just before 1028 * insert event then its a 3 pole headphone else if 1029 * both press and release event received then its 1030 * a headset. 1031 */ 1032 if (priv->mbhc_btn0_pressed) 1033 snd_soc_jack_report(priv->jack, 1034 SND_JACK_HEADPHONE, hs_jack_mask); 1035 else 1036 snd_soc_jack_report(priv->jack, 1037 SND_JACK_HEADSET, hs_jack_mask); 1038 1039 priv->detect_accessory_type = false; 1040 1041 } else { /* removal */ 1042 snd_soc_jack_report(priv->jack, 0, hs_jack_mask); 1043 priv->detect_accessory_type = true; 1044 priv->mbhc_btn0_pressed = false; 1045 } 1046 1047 return IRQ_HANDLED; 1048 } 1049 1050 static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = { 1051 [0] = { 1052 .name = "pm8916_wcd_analog_pdm_rx", 1053 .id = 0, 1054 .playback = { 1055 .stream_name = "PDM Playback", 1056 .rates = MSM8916_WCD_ANALOG_RATES, 1057 .formats = MSM8916_WCD_ANALOG_FORMATS, 1058 .channels_min = 1, 1059 .channels_max = 3, 1060 }, 1061 }, 1062 [1] = { 1063 .name = "pm8916_wcd_analog_pdm_tx", 1064 .id = 1, 1065 .capture = { 1066 .stream_name = "PDM Capture", 1067 .rates = MSM8916_WCD_ANALOG_RATES, 1068 .formats = MSM8916_WCD_ANALOG_FORMATS, 1069 .channels_min = 1, 1070 .channels_max = 4, 1071 }, 1072 }, 1073 }; 1074 1075 static const struct snd_soc_codec_driver pm8916_wcd_analog = { 1076 .probe = pm8916_wcd_analog_probe, 1077 .remove = pm8916_wcd_analog_remove, 1078 .set_jack = pm8916_wcd_analog_set_jack, 1079 .get_regmap = pm8916_get_regmap, 1080 .component_driver = { 1081 .controls = pm8916_wcd_analog_snd_controls, 1082 .num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls), 1083 .dapm_widgets = pm8916_wcd_analog_dapm_widgets, 1084 .num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets), 1085 .dapm_routes = pm8916_wcd_analog_audio_map, 1086 .num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map), 1087 }, 1088 }; 1089 1090 static int pm8916_wcd_analog_parse_dt(struct device *dev, 1091 struct pm8916_wcd_analog_priv *priv) 1092 { 1093 int rval; 1094 1095 if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap")) 1096 priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP; 1097 else 1098 priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; 1099 1100 if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap")) 1101 priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP; 1102 else 1103 priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; 1104 1105 of_property_read_u32(dev->of_node, "qcom,micbias-lvl", 1106 &priv->micbias_mv); 1107 1108 if (of_property_read_bool(dev->of_node, 1109 "qcom,hphl-jack-type-normally-open")) 1110 priv->hphl_jack_type_normally_open = true; 1111 else 1112 priv->hphl_jack_type_normally_open = false; 1113 1114 if (of_property_read_bool(dev->of_node, 1115 "qcom,gnd-jack-type-normally-open")) 1116 priv->gnd_jack_type_normally_open = true; 1117 else 1118 priv->gnd_jack_type_normally_open = false; 1119 1120 priv->mbhc_btn_enabled = true; 1121 rval = of_property_read_u32_array(dev->of_node, 1122 "qcom,mbhc-vthreshold-low", 1123 &priv->vref_btn_cs[0], 1124 MBHC_MAX_BUTTONS); 1125 if (rval < 0) { 1126 priv->mbhc_btn_enabled = false; 1127 } else { 1128 rval = of_property_read_u32_array(dev->of_node, 1129 "qcom,mbhc-vthreshold-high", 1130 &priv->vref_btn_micb[0], 1131 MBHC_MAX_BUTTONS); 1132 if (rval < 0) 1133 priv->mbhc_btn_enabled = false; 1134 } 1135 1136 if (!priv->mbhc_btn_enabled) 1137 dev_err(dev, 1138 "DT property missing, MBHC btn detection disabled\n"); 1139 1140 1141 return 0; 1142 } 1143 1144 static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev) 1145 { 1146 struct pm8916_wcd_analog_priv *priv; 1147 struct device *dev = &pdev->dev; 1148 int ret, i, irq; 1149 1150 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1151 if (!priv) 1152 return -ENOMEM; 1153 1154 ret = pm8916_wcd_analog_parse_dt(dev, priv); 1155 if (ret < 0) 1156 return ret; 1157 1158 priv->mclk = devm_clk_get(dev, "mclk"); 1159 if (IS_ERR(priv->mclk)) { 1160 dev_err(dev, "failed to get mclk\n"); 1161 return PTR_ERR(priv->mclk); 1162 } 1163 1164 for (i = 0; i < ARRAY_SIZE(supply_names); i++) 1165 priv->supplies[i].supply = supply_names[i]; 1166 1167 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies), 1168 priv->supplies); 1169 if (ret) { 1170 dev_err(dev, "Failed to get regulator supplies %d\n", ret); 1171 return ret; 1172 } 1173 1174 ret = clk_prepare_enable(priv->mclk); 1175 if (ret < 0) { 1176 dev_err(dev, "failed to enable mclk %d\n", ret); 1177 return ret; 1178 } 1179 1180 irq = platform_get_irq_byname(pdev, "mbhc_switch_int"); 1181 if (irq < 0) { 1182 dev_err(dev, "failed to get mbhc switch irq\n"); 1183 return irq; 1184 } 1185 1186 ret = devm_request_irq(dev, irq, pm8916_mbhc_switch_irq_handler, 1187 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | 1188 IRQF_ONESHOT, 1189 "mbhc switch irq", priv); 1190 if (ret) 1191 dev_err(dev, "cannot request mbhc switch irq\n"); 1192 1193 if (priv->mbhc_btn_enabled) { 1194 irq = platform_get_irq_byname(pdev, "mbhc_but_press_det"); 1195 if (irq < 0) { 1196 dev_err(dev, "failed to get button press irq\n"); 1197 return irq; 1198 } 1199 1200 ret = devm_request_irq(dev, irq, mbhc_btn_press_irq_handler, 1201 IRQF_TRIGGER_RISING | 1202 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1203 "mbhc btn press irq", priv); 1204 if (ret) 1205 dev_err(dev, "cannot request mbhc button press irq\n"); 1206 1207 irq = platform_get_irq_byname(pdev, "mbhc_but_rel_det"); 1208 if (irq < 0) { 1209 dev_err(dev, "failed to get button release irq\n"); 1210 return irq; 1211 } 1212 1213 ret = devm_request_irq(dev, irq, mbhc_btn_release_irq_handler, 1214 IRQF_TRIGGER_RISING | 1215 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1216 "mbhc btn release irq", priv); 1217 if (ret) 1218 dev_err(dev, "cannot request mbhc button release irq\n"); 1219 1220 } 1221 1222 dev_set_drvdata(dev, priv); 1223 1224 return snd_soc_register_codec(dev, &pm8916_wcd_analog, 1225 pm8916_wcd_analog_dai, 1226 ARRAY_SIZE(pm8916_wcd_analog_dai)); 1227 } 1228 1229 static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev) 1230 { 1231 struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev); 1232 1233 snd_soc_unregister_codec(&pdev->dev); 1234 clk_disable_unprepare(priv->mclk); 1235 1236 return 0; 1237 } 1238 1239 static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = { 1240 { .compatible = "qcom,pm8916-wcd-analog-codec", }, 1241 { } 1242 }; 1243 1244 static struct platform_driver pm8916_wcd_analog_spmi_driver = { 1245 .driver = { 1246 .name = "qcom,pm8916-wcd-spmi-codec", 1247 .of_match_table = pm8916_wcd_analog_spmi_match_table, 1248 }, 1249 .probe = pm8916_wcd_analog_spmi_probe, 1250 .remove = pm8916_wcd_analog_spmi_remove, 1251 }; 1252 1253 module_platform_driver(pm8916_wcd_analog_spmi_driver); 1254 1255 MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>"); 1256 MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver"); 1257 MODULE_LICENSE("GPL v2"); 1258