1 /* 2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; version 2 of the License. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 18 #ifndef ML26124_H 19 #define ML26124_H 20 21 /* Clock Control Register */ 22 #define ML26124_SMPLING_RATE 0x00 23 #define ML26124_PLLNL 0x02 24 #define ML26124_PLLNH 0x04 25 #define ML26124_PLLML 0x06 26 #define ML26124_PLLMH 0x08 27 #define ML26124_PLLDIV 0x0a 28 #define ML26124_CLK_EN 0x0c 29 #define ML26124_CLK_CTL 0x0e 30 31 /* System Control Register */ 32 #define ML26124_SW_RST 0x10 33 #define ML26124_REC_PLYBAK_RUN 0x12 34 #define ML26124_MIC_TIM 0x14 35 36 /* Power Mnagement Register */ 37 #define ML26124_PW_REF_PW_MNG 0x20 38 #define ML26124_PW_IN_PW_MNG 0x22 39 #define ML26124_PW_DAC_PW_MNG 0x24 40 #define ML26124_PW_SPAMP_PW_MNG 0x26 41 #define ML26124_PW_LOUT_PW_MNG 0x28 42 #define ML26124_PW_VOUT_PW_MNG 0x2a 43 #define ML26124_PW_ZCCMP_PW_MNG 0x2e 44 45 /* Analog Reference Control Register */ 46 #define ML26124_PW_MICBIAS_VOL 0x30 47 48 /* Input/Output Amplifier Control Register */ 49 #define ML26124_PW_MIC_IN_VOL 0x32 50 #define ML26124_PW_MIC_BOST_VOL 0x38 51 #define ML26124_PW_SPK_AMP_VOL 0x3a 52 #define ML26124_PW_AMP_VOL_FUNC 0x48 53 #define ML26124_PW_AMP_VOL_FADE 0x4a 54 55 /* Analog Path Control Register */ 56 #define ML26124_SPK_AMP_OUT 0x54 57 #define ML26124_MIC_IF_CTL 0x5a 58 #define ML26124_MIC_SELECT 0xe8 59 60 /* Audio Interface Control Register */ 61 #define ML26124_SAI_TRANS_CTL 0x60 62 #define ML26124_SAI_RCV_CTL 0x62 63 #define ML26124_SAI_MODE_SEL 0x64 64 65 /* DSP Control Register */ 66 #define ML26124_FILTER_EN 0x66 67 #define ML26124_DVOL_CTL 0x68 68 #define ML26124_MIXER_VOL_CTL 0x6a 69 #define ML26124_RECORD_DIG_VOL 0x6c 70 #define ML26124_PLBAK_DIG_VOL 0x70 71 #define ML26124_DIGI_BOOST_VOL 0x72 72 #define ML26124_EQ_GAIN_BRAND0 0x74 73 #define ML26124_EQ_GAIN_BRAND1 0x76 74 #define ML26124_EQ_GAIN_BRAND2 0x78 75 #define ML26124_EQ_GAIN_BRAND3 0x7a 76 #define ML26124_EQ_GAIN_BRAND4 0x7c 77 #define ML26124_HPF2_CUTOFF 0x7e 78 #define ML26124_EQBRAND0_F0L 0x80 79 #define ML26124_EQBRAND0_F0H 0x82 80 #define ML26124_EQBRAND0_F1L 0x84 81 #define ML26124_EQBRAND0_F1H 0x86 82 #define ML26124_EQBRAND1_F0L 0x88 83 #define ML26124_EQBRAND1_F0H 0x8a 84 #define ML26124_EQBRAND1_F1L 0x8c 85 #define ML26124_EQBRAND1_F1H 0x8e 86 #define ML26124_EQBRAND2_F0L 0x90 87 #define ML26124_EQBRAND2_F0H 0x92 88 #define ML26124_EQBRAND2_F1L 0x94 89 #define ML26124_EQBRAND2_F1H 0x96 90 #define ML26124_EQBRAND3_F0L 0x98 91 #define ML26124_EQBRAND3_F0H 0x9a 92 #define ML26124_EQBRAND3_F1L 0x9c 93 #define ML26124_EQBRAND3_F1H 0x9e 94 #define ML26124_EQBRAND4_F0L 0xa0 95 #define ML26124_EQBRAND4_F0H 0xa2 96 #define ML26124_EQBRAND4_F1L 0xa4 97 #define ML26124_EQBRAND4_F1H 0xa6 98 99 /* ALC Control Register */ 100 #define ML26124_ALC_MODE 0xb0 101 #define ML26124_ALC_ATTACK_TIM 0xb2 102 #define ML26124_ALC_DECAY_TIM 0xb4 103 #define ML26124_ALC_HOLD_TIM 0xb6 104 #define ML26124_ALC_TARGET_LEV 0xb8 105 #define ML26124_ALC_MAXMIN_GAIN 0xba 106 #define ML26124_NOIS_GATE_THRSH 0xbc 107 #define ML26124_ALC_ZERO_TIMOUT 0xbe 108 109 /* Playback Limiter Control Register */ 110 #define ML26124_PL_ATTACKTIME 0xc0 111 #define ML26124_PL_DECAYTIME 0xc2 112 #define ML26124_PL_TARGETTIME 0xc4 113 #define ML26124_PL_MAXMIN_GAIN 0xc6 114 #define ML26124_PLYBAK_BOST_VOL 0xc8 115 #define ML26124_PL_0CROSS_TIMOUT 0xca 116 117 /* Video Amplifer Control Register */ 118 #define ML26124_VIDEO_AMP_GAIN_CTL 0xd0 119 #define ML26124_VIDEO_AMP_SETUP1 0xd2 120 #define ML26124_VIDEO_AMP_CTL2 0xd4 121 122 /* Clock select for machine driver */ 123 #define ML26124_USE_PLL 0 124 #define ML26124_USE_MCLKI_256FS 1 125 #define ML26124_USE_MCLKI_512FS 2 126 #define ML26124_USE_MCLKI_1024FS 3 127 128 /* Register Mask */ 129 #define ML26124_R0_MASK 0xf 130 #define ML26124_R2_MASK 0xff 131 #define ML26124_R4_MASK 0x1 132 #define ML26124_R6_MASK 0xf 133 #define ML26124_R8_MASK 0x3f 134 #define ML26124_Ra_MASK 0x1f 135 #define ML26124_Rc_MASK 0x1f 136 #define ML26124_Re_MASK 0x7 137 #define ML26124_R10_MASK 0x1 138 #define ML26124_R12_MASK 0x17 139 #define ML26124_R14_MASK 0x3f 140 #define ML26124_R20_MASK 0x47 141 #define ML26124_R22_MASK 0xa 142 #define ML26124_R24_MASK 0x2 143 #define ML26124_R26_MASK 0x1f 144 #define ML26124_R28_MASK 0x2 145 #define ML26124_R2a_MASK 0x2 146 #define ML26124_R2e_MASK 0x2 147 #define ML26124_R30_MASK 0x7 148 #define ML26124_R32_MASK 0x3f 149 #define ML26124_R38_MASK 0x38 150 #define ML26124_R3a_MASK 0x3f 151 #define ML26124_R48_MASK 0x3 152 #define ML26124_R4a_MASK 0x7 153 #define ML26124_R54_MASK 0x2a 154 #define ML26124_R5a_MASK 0x3 155 #define ML26124_Re8_MASK 0x3 156 #define ML26124_R60_MASK 0xff 157 #define ML26124_R62_MASK 0xff 158 #define ML26124_R64_MASK 0x1 159 #define ML26124_R66_MASK 0xff 160 #define ML26124_R68_MASK 0x3b 161 #define ML26124_R6a_MASK 0xf3 162 #define ML26124_R6c_MASK 0xff 163 #define ML26124_R70_MASK 0xff 164 165 #define ML26124_MCLKEN BIT(0) 166 #define ML26124_PLLEN BIT(1) 167 #define ML26124_PLLOE BIT(2) 168 #define ML26124_MCLKOE BIT(3) 169 170 #define ML26124_BLT_ALL_ON 0x1f 171 #define ML26124_BLT_PREAMP_ON 0x13 172 173 #define ML26124_MICBEN_ON BIT(2) 174 175 enum ml26124_regs { 176 ML26124_MCLK = 0, 177 }; 178 179 enum ml26124_clk_in { 180 ML26124_USE_PLLOUT = 0, 181 ML26124_USE_MCLKI, 182 }; 183 184 #endif 185