1 /* 2 * max98927.c -- MAX98927 ALSA Soc Audio driver 3 * 4 * Copyright (C) 2016 Maxim Integrated Products 5 * Author: Ryan Lee <ryans.lee@maximintegrated.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/acpi.h> 14 #include <linux/i2c.h> 15 #include <linux/module.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <linux/cdev.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <linux/gpio.h> 23 #include <linux/of_gpio.h> 24 #include <sound/tlv.h> 25 #include "max98927.h" 26 27 static struct reg_default max98927_reg[] = { 28 {MAX98927_R0001_INT_RAW1, 0x00}, 29 {MAX98927_R0002_INT_RAW2, 0x00}, 30 {MAX98927_R0003_INT_RAW3, 0x00}, 31 {MAX98927_R0004_INT_STATE1, 0x00}, 32 {MAX98927_R0005_INT_STATE2, 0x00}, 33 {MAX98927_R0006_INT_STATE3, 0x00}, 34 {MAX98927_R0007_INT_FLAG1, 0x00}, 35 {MAX98927_R0008_INT_FLAG2, 0x00}, 36 {MAX98927_R0009_INT_FLAG3, 0x00}, 37 {MAX98927_R000A_INT_EN1, 0x00}, 38 {MAX98927_R000B_INT_EN2, 0x00}, 39 {MAX98927_R000C_INT_EN3, 0x00}, 40 {MAX98927_R000D_INT_FLAG_CLR1, 0x00}, 41 {MAX98927_R000E_INT_FLAG_CLR2, 0x00}, 42 {MAX98927_R000F_INT_FLAG_CLR3, 0x00}, 43 {MAX98927_R0010_IRQ_CTRL, 0x00}, 44 {MAX98927_R0011_CLK_MON, 0x00}, 45 {MAX98927_R0012_WDOG_CTRL, 0x00}, 46 {MAX98927_R0013_WDOG_RST, 0x00}, 47 {MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH, 0x75}, 48 {MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH, 0x8c}, 49 {MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS, 0x08}, 50 {MAX98927_R0017_PIN_CFG, 0x55}, 51 {MAX98927_R0018_PCM_RX_EN_A, 0x00}, 52 {MAX98927_R0019_PCM_RX_EN_B, 0x00}, 53 {MAX98927_R001A_PCM_TX_EN_A, 0x00}, 54 {MAX98927_R001B_PCM_TX_EN_B, 0x00}, 55 {MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0x00}, 56 {MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0x00}, 57 {MAX98927_R001E_PCM_TX_CH_SRC_A, 0x00}, 58 {MAX98927_R001F_PCM_TX_CH_SRC_B, 0x00}, 59 {MAX98927_R0020_PCM_MODE_CFG, 0x40}, 60 {MAX98927_R0021_PCM_MASTER_MODE, 0x00}, 61 {MAX98927_R0022_PCM_CLK_SETUP, 0x22}, 62 {MAX98927_R0023_PCM_SR_SETUP1, 0x00}, 63 {MAX98927_R0024_PCM_SR_SETUP2, 0x00}, 64 {MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 0x00}, 65 {MAX98927_R0026_PCM_TO_SPK_MONOMIX_B, 0x00}, 66 {MAX98927_R0027_ICC_RX_EN_A, 0x00}, 67 {MAX98927_R0028_ICC_RX_EN_B, 0x00}, 68 {MAX98927_R002B_ICC_TX_EN_A, 0x00}, 69 {MAX98927_R002C_ICC_TX_EN_B, 0x00}, 70 {MAX98927_R002E_ICC_HIZ_MANUAL_MODE, 0x00}, 71 {MAX98927_R002F_ICC_TX_HIZ_EN_A, 0x00}, 72 {MAX98927_R0030_ICC_TX_HIZ_EN_B, 0x00}, 73 {MAX98927_R0031_ICC_LNK_EN, 0x00}, 74 {MAX98927_R0032_PDM_TX_EN, 0x00}, 75 {MAX98927_R0033_PDM_TX_HIZ_CTRL, 0x00}, 76 {MAX98927_R0034_PDM_TX_CTRL, 0x00}, 77 {MAX98927_R0035_PDM_RX_CTRL, 0x00}, 78 {MAX98927_R0036_AMP_VOL_CTRL, 0x00}, 79 {MAX98927_R0037_AMP_DSP_CFG, 0x02}, 80 {MAX98927_R0038_TONE_GEN_DC_CFG, 0x00}, 81 {MAX98927_R0039_DRE_CTRL, 0x01}, 82 {MAX98927_R003A_AMP_EN, 0x00}, 83 {MAX98927_R003B_SPK_SRC_SEL, 0x00}, 84 {MAX98927_R003C_SPK_GAIN, 0x00}, 85 {MAX98927_R003D_SSM_CFG, 0x04}, 86 {MAX98927_R003E_MEAS_EN, 0x00}, 87 {MAX98927_R003F_MEAS_DSP_CFG, 0x04}, 88 {MAX98927_R0040_BOOST_CTRL0, 0x00}, 89 {MAX98927_R0041_BOOST_CTRL3, 0x00}, 90 {MAX98927_R0042_BOOST_CTRL1, 0x00}, 91 {MAX98927_R0043_MEAS_ADC_CFG, 0x00}, 92 {MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x01}, 93 {MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x00}, 94 {MAX98927_R0046_ADC_CH0_DIVIDE, 0x00}, 95 {MAX98927_R0047_ADC_CH1_DIVIDE, 0x00}, 96 {MAX98927_R0048_ADC_CH2_DIVIDE, 0x00}, 97 {MAX98927_R0049_ADC_CH0_FILT_CFG, 0x00}, 98 {MAX98927_R004A_ADC_CH1_FILT_CFG, 0x00}, 99 {MAX98927_R004B_ADC_CH2_FILT_CFG, 0x00}, 100 {MAX98927_R004C_MEAS_ADC_CH0_READ, 0x00}, 101 {MAX98927_R004D_MEAS_ADC_CH1_READ, 0x00}, 102 {MAX98927_R004E_MEAS_ADC_CH2_READ, 0x00}, 103 {MAX98927_R0051_BROWNOUT_STATUS, 0x00}, 104 {MAX98927_R0052_BROWNOUT_EN, 0x00}, 105 {MAX98927_R0053_BROWNOUT_INFINITE_HOLD, 0x00}, 106 {MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR, 0x00}, 107 {MAX98927_R0055_BROWNOUT_LVL_HOLD, 0x00}, 108 {MAX98927_R005A_BROWNOUT_LVL1_THRESH, 0x00}, 109 {MAX98927_R005B_BROWNOUT_LVL2_THRESH, 0x00}, 110 {MAX98927_R005C_BROWNOUT_LVL3_THRESH, 0x00}, 111 {MAX98927_R005D_BROWNOUT_LVL4_THRESH, 0x00}, 112 {MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS, 0x00}, 113 {MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL, 0x00}, 114 {MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL, 0x00}, 115 {MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE, 0x00}, 116 {MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT, 0x00}, 117 {MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1, 0x00}, 118 {MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2, 0x00}, 119 {MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3, 0x00}, 120 {MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT, 0x00}, 121 {MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1, 0x00}, 122 {MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2, 0x00}, 123 {MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3, 0x00}, 124 {MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT, 0x00}, 125 {MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1, 0x00}, 126 {MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2, 0x00}, 127 {MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3, 0x00}, 128 {MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT, 0x00}, 129 {MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1, 0x00}, 130 {MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2, 0x00}, 131 {MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3, 0x00}, 132 {MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM, 0x00}, 133 {MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY, 0x00}, 134 {MAX98927_R0084_ENV_TRACK_REL_RATE, 0x00}, 135 {MAX98927_R0085_ENV_TRACK_HOLD_RATE, 0x00}, 136 {MAX98927_R0086_ENV_TRACK_CTRL, 0x00}, 137 {MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ, 0x00}, 138 {MAX98927_R00FF_GLOBAL_SHDN, 0x00}, 139 {MAX98927_R0100_SOFT_RESET, 0x00}, 140 {MAX98927_R01FF_REV_ID, 0x40}, 141 }; 142 143 static int max98927_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 144 { 145 struct snd_soc_codec *codec = codec_dai->codec; 146 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec); 147 unsigned int mode = 0; 148 unsigned int format = 0; 149 unsigned int invert = 0; 150 151 dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt); 152 153 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 154 case SND_SOC_DAIFMT_CBS_CFS: 155 mode = MAX98927_PCM_MASTER_MODE_SLAVE; 156 break; 157 case SND_SOC_DAIFMT_CBM_CFM: 158 max98927->master = true; 159 mode = MAX98927_PCM_MASTER_MODE_MASTER; 160 break; 161 default: 162 dev_err(codec->dev, "DAI clock mode unsupported\n"); 163 return -EINVAL; 164 } 165 166 regmap_update_bits(max98927->regmap, 167 MAX98927_R0021_PCM_MASTER_MODE, 168 MAX98927_PCM_MASTER_MODE_MASK, 169 mode); 170 171 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 172 case SND_SOC_DAIFMT_NB_NF: 173 break; 174 case SND_SOC_DAIFMT_IB_NF: 175 invert = MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE; 176 break; 177 default: 178 dev_err(codec->dev, "DAI invert mode unsupported\n"); 179 return -EINVAL; 180 } 181 182 regmap_update_bits(max98927->regmap, 183 MAX98927_R0020_PCM_MODE_CFG, 184 MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE, 185 invert); 186 187 /* interface format */ 188 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 189 case SND_SOC_DAIFMT_I2S: 190 max98927->iface |= SND_SOC_DAIFMT_I2S; 191 format = MAX98927_PCM_FORMAT_I2S; 192 break; 193 case SND_SOC_DAIFMT_LEFT_J: 194 max98927->iface |= SND_SOC_DAIFMT_LEFT_J; 195 format = MAX98927_PCM_FORMAT_LJ; 196 break; 197 case SND_SOC_DAIFMT_PDM: 198 max98927->iface |= SND_SOC_DAIFMT_PDM; 199 break; 200 default: 201 return -EINVAL; 202 } 203 204 /* pcm channel configuration */ 205 if (max98927->iface & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) { 206 regmap_update_bits(max98927->regmap, 207 MAX98927_R0018_PCM_RX_EN_A, 208 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN, 209 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN); 210 211 regmap_update_bits(max98927->regmap, 212 MAX98927_R0020_PCM_MODE_CFG, 213 MAX98927_PCM_MODE_CFG_FORMAT_MASK, 214 format << MAX98927_PCM_MODE_CFG_FORMAT_SHIFT); 215 216 regmap_update_bits(max98927->regmap, 217 MAX98927_R003B_SPK_SRC_SEL, 218 MAX98927_SPK_SRC_MASK, 0); 219 220 } else 221 regmap_update_bits(max98927->regmap, 222 MAX98927_R0018_PCM_RX_EN_A, 223 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN, 0); 224 225 /* pdm channel configuration */ 226 if (max98927->iface & SND_SOC_DAIFMT_PDM) { 227 regmap_update_bits(max98927->regmap, 228 MAX98927_R0035_PDM_RX_CTRL, 229 MAX98927_PDM_RX_EN_MASK, 1); 230 231 regmap_update_bits(max98927->regmap, 232 MAX98927_R003B_SPK_SRC_SEL, 233 MAX98927_SPK_SRC_MASK, 3); 234 } else 235 regmap_update_bits(max98927->regmap, 236 MAX98927_R0035_PDM_RX_CTRL, 237 MAX98927_PDM_RX_EN_MASK, 0); 238 return 0; 239 } 240 241 /* codec MCLK rate in master mode */ 242 static const int rate_table[] = { 243 5644800, 6000000, 6144000, 6500000, 244 9600000, 11289600, 12000000, 12288000, 245 13000000, 19200000, 246 }; 247 248 static int max98927_set_clock(struct max98927_priv *max98927, 249 struct snd_pcm_hw_params *params) 250 { 251 struct snd_soc_codec *codec = max98927->codec; 252 /* BCLK/LRCLK ratio calculation */ 253 int blr_clk_ratio = params_channels(params) * max98927->ch_size; 254 int value; 255 256 if (max98927->master) { 257 int i; 258 /* match rate to closest value */ 259 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 260 if (rate_table[i] >= max98927->sysclk) 261 break; 262 } 263 if (i == ARRAY_SIZE(rate_table)) { 264 dev_err(codec->dev, "failed to find proper clock rate.\n"); 265 return -EINVAL; 266 } 267 regmap_update_bits(max98927->regmap, 268 MAX98927_R0021_PCM_MASTER_MODE, 269 MAX98927_PCM_MASTER_MODE_MCLK_MASK, 270 i << MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT); 271 } 272 273 switch (blr_clk_ratio) { 274 case 32: 275 value = 2; 276 break; 277 case 48: 278 value = 3; 279 break; 280 case 64: 281 value = 4; 282 break; 283 default: 284 return -EINVAL; 285 } 286 regmap_update_bits(max98927->regmap, 287 MAX98927_R0022_PCM_CLK_SETUP, 288 MAX98927_PCM_CLK_SETUP_BSEL_MASK, 289 value); 290 return 0; 291 } 292 293 static int max98927_dai_hw_params(struct snd_pcm_substream *substream, 294 struct snd_pcm_hw_params *params, 295 struct snd_soc_dai *dai) 296 { 297 struct snd_soc_codec *codec = dai->codec; 298 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec); 299 unsigned int sampling_rate = 0; 300 unsigned int chan_sz = 0; 301 302 /* pcm mode configuration */ 303 switch (snd_pcm_format_width(params_format(params))) { 304 case 16: 305 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16; 306 break; 307 case 24: 308 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24; 309 break; 310 case 32: 311 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32; 312 break; 313 default: 314 dev_err(codec->dev, "format unsupported %d\n", 315 params_format(params)); 316 goto err; 317 } 318 319 max98927->ch_size = snd_pcm_format_width(params_format(params)); 320 321 regmap_update_bits(max98927->regmap, 322 MAX98927_R0020_PCM_MODE_CFG, 323 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 324 325 dev_dbg(codec->dev, "format supported %d", 326 params_format(params)); 327 328 /* sampling rate configuration */ 329 switch (params_rate(params)) { 330 case 8000: 331 sampling_rate = MAX98927_PCM_SR_SET1_SR_8000; 332 break; 333 case 11025: 334 sampling_rate = MAX98927_PCM_SR_SET1_SR_11025; 335 break; 336 case 12000: 337 sampling_rate = MAX98927_PCM_SR_SET1_SR_12000; 338 break; 339 case 16000: 340 sampling_rate = MAX98927_PCM_SR_SET1_SR_16000; 341 break; 342 case 22050: 343 sampling_rate = MAX98927_PCM_SR_SET1_SR_22050; 344 break; 345 case 24000: 346 sampling_rate = MAX98927_PCM_SR_SET1_SR_24000; 347 break; 348 case 32000: 349 sampling_rate = MAX98927_PCM_SR_SET1_SR_32000; 350 break; 351 case 44100: 352 sampling_rate = MAX98927_PCM_SR_SET1_SR_44100; 353 break; 354 case 48000: 355 sampling_rate = MAX98927_PCM_SR_SET1_SR_48000; 356 break; 357 default: 358 dev_err(codec->dev, "rate %d not supported\n", 359 params_rate(params)); 360 goto err; 361 } 362 /* set DAI_SR to correct LRCLK frequency */ 363 regmap_update_bits(max98927->regmap, 364 MAX98927_R0023_PCM_SR_SETUP1, 365 MAX98927_PCM_SR_SET1_SR_MASK, 366 sampling_rate); 367 regmap_update_bits(max98927->regmap, 368 MAX98927_R0024_PCM_SR_SETUP2, 369 MAX98927_PCM_SR_SET2_SR_MASK, 370 sampling_rate << MAX98927_PCM_SR_SET2_SR_SHIFT); 371 372 /* set sampling rate of IV */ 373 if (max98927->interleave_mode && 374 sampling_rate > MAX98927_PCM_SR_SET1_SR_16000) 375 regmap_update_bits(max98927->regmap, 376 MAX98927_R0024_PCM_SR_SETUP2, 377 MAX98927_PCM_SR_SET2_IVADC_SR_MASK, 378 sampling_rate - 3); 379 else 380 regmap_update_bits(max98927->regmap, 381 MAX98927_R0024_PCM_SR_SETUP2, 382 MAX98927_PCM_SR_SET2_IVADC_SR_MASK, 383 sampling_rate); 384 return max98927_set_clock(max98927, params); 385 err: 386 return -EINVAL; 387 } 388 389 #define MAX98927_RATES SNDRV_PCM_RATE_8000_48000 390 391 #define MAX98927_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 392 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 393 394 static int max98927_dai_set_sysclk(struct snd_soc_dai *dai, 395 int clk_id, unsigned int freq, int dir) 396 { 397 struct snd_soc_codec *codec = dai->codec; 398 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec); 399 400 max98927->sysclk = freq; 401 return 0; 402 } 403 404 static const struct snd_soc_dai_ops max98927_dai_ops = { 405 .set_sysclk = max98927_dai_set_sysclk, 406 .set_fmt = max98927_dai_set_fmt, 407 .hw_params = max98927_dai_hw_params, 408 }; 409 410 static int max98927_dac_event(struct snd_soc_dapm_widget *w, 411 struct snd_kcontrol *kcontrol, int event) 412 { 413 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 414 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec); 415 416 switch (event) { 417 case SND_SOC_DAPM_POST_PMU: 418 regmap_update_bits(max98927->regmap, 419 MAX98927_R003A_AMP_EN, 420 MAX98927_AMP_EN_MASK, 1); 421 regmap_update_bits(max98927->regmap, 422 MAX98927_R00FF_GLOBAL_SHDN, 423 MAX98927_GLOBAL_EN_MASK, 1); 424 break; 425 case SND_SOC_DAPM_POST_PMD: 426 regmap_update_bits(max98927->regmap, 427 MAX98927_R00FF_GLOBAL_SHDN, 428 MAX98927_GLOBAL_EN_MASK, 0); 429 regmap_update_bits(max98927->regmap, 430 MAX98927_R003A_AMP_EN, 431 MAX98927_AMP_EN_MASK, 0); 432 break; 433 default: 434 return 0; 435 } 436 return 0; 437 } 438 439 static const char * const max98927_switch_text[] = { 440 "Left", "Right", "LeftRight"}; 441 442 static const struct soc_enum dai_sel_enum = 443 SOC_ENUM_SINGLE(MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 444 MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT, 445 3, max98927_switch_text); 446 447 static const struct snd_kcontrol_new max98927_dai_controls = 448 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum); 449 450 static const struct snd_kcontrol_new max98927_vi_control = 451 SOC_DAPM_SINGLE("Switch", MAX98927_R003F_MEAS_DSP_CFG, 2, 1, 0); 452 453 static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = { 454 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_R003A_AMP_EN, 455 0, 0, max98927_dac_event, 456 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 457 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, 458 &max98927_dai_controls), 459 SND_SOC_DAPM_OUTPUT("BE_OUT"), 460 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0, 461 MAX98927_R003E_MEAS_EN, 0, 0), 462 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0, 463 MAX98927_R003E_MEAS_EN, 1, 0), 464 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0, 465 &max98927_vi_control), 466 SND_SOC_DAPM_SIGGEN("VMON"), 467 SND_SOC_DAPM_SIGGEN("IMON"), 468 }; 469 470 static DECLARE_TLV_DB_SCALE(max98927_spk_tlv, 300, 300, 0); 471 static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0); 472 473 static bool max98927_readable_register(struct device *dev, unsigned int reg) 474 { 475 switch (reg) { 476 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0028_ICC_RX_EN_B: 477 case MAX98927_R002B_ICC_TX_EN_A ... MAX98927_R002C_ICC_TX_EN_B: 478 case MAX98927_R002E_ICC_HIZ_MANUAL_MODE 479 ... MAX98927_R004E_MEAS_ADC_CH2_READ: 480 case MAX98927_R0051_BROWNOUT_STATUS 481 ... MAX98927_R0055_BROWNOUT_LVL_HOLD: 482 case MAX98927_R005A_BROWNOUT_LVL1_THRESH 483 ... MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE: 484 case MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT 485 ... MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ: 486 case MAX98927_R00FF_GLOBAL_SHDN: 487 case MAX98927_R0100_SOFT_RESET: 488 case MAX98927_R01FF_REV_ID: 489 return true; 490 default: 491 return false; 492 } 493 }; 494 495 static bool max98927_volatile_reg(struct device *dev, unsigned int reg) 496 { 497 switch (reg) { 498 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0009_INT_FLAG3: 499 case MAX98927_R004C_MEAS_ADC_CH0_READ: 500 case MAX98927_R004D_MEAS_ADC_CH1_READ: 501 case MAX98927_R004E_MEAS_ADC_CH2_READ: 502 case MAX98927_R0051_BROWNOUT_STATUS: 503 case MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ: 504 case MAX98927_R01FF_REV_ID: 505 case MAX98927_R0100_SOFT_RESET: 506 return true; 507 default: 508 return false; 509 } 510 } 511 512 static const char * const max98927_boost_voltage_text[] = { 513 "6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V", 514 "7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V", 515 "8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V", 516 "9.5V", "9.625V", "9.75V", "9.875V", "10V" 517 }; 518 519 static SOC_ENUM_SINGLE_DECL(max98927_boost_voltage, 520 MAX98927_R0040_BOOST_CTRL0, 0, 521 max98927_boost_voltage_text); 522 523 static const char * const max98927_current_limit_text[] = { 524 "1.00A", "1.10A", "1.20A", "1.30A", "1.40A", "1.50A", "1.60A", "1.70A", 525 "1.80A", "1.90A", "2.00A", "2.10A", "2.20A", "2.30A", "2.40A", "2.50A", 526 "2.60A", "2.70A", "2.80A", "2.90A", "3.00A", "3.10A", "3.20A", "3.30A", 527 "3.40A", "3.50A", "3.60A", "3.70A", "3.80A", "3.90A", "4.00A", "4.10A" 528 }; 529 530 static SOC_ENUM_SINGLE_DECL(max98927_current_limit, 531 MAX98927_R0042_BOOST_CTRL1, 1, 532 max98927_current_limit_text); 533 534 static const struct snd_kcontrol_new max98927_snd_controls[] = { 535 SOC_SINGLE_TLV("Speaker Volume", MAX98927_R003C_SPK_GAIN, 536 0, 6, 0, 537 max98927_spk_tlv), 538 SOC_SINGLE_TLV("Digital Volume", MAX98927_R0036_AMP_VOL_CTRL, 539 0, (1<<MAX98927_AMP_VOL_WIDTH)-1, 0, 540 max98927_digital_tlv), 541 SOC_SINGLE("Amp DSP Switch", MAX98927_R0052_BROWNOUT_EN, 542 MAX98927_BROWNOUT_DSP_SHIFT, 1, 0), 543 SOC_SINGLE("Ramp Switch", MAX98927_R0037_AMP_DSP_CFG, 544 MAX98927_AMP_DSP_CFG_RMP_SHIFT, 1, 0), 545 SOC_SINGLE("DRE Switch", MAX98927_R0039_DRE_CTRL, 546 MAX98927_DRE_EN_SHIFT, 1, 0), 547 SOC_SINGLE("Volume Location Switch", MAX98927_R0036_AMP_VOL_CTRL, 548 MAX98927_AMP_VOL_SEL_SHIFT, 1, 0), 549 SOC_ENUM("Boost Output Voltage", max98927_boost_voltage), 550 SOC_ENUM("Current Limit", max98927_current_limit), 551 }; 552 553 static const struct snd_soc_dapm_route max98927_audio_map[] = { 554 /* Plabyack */ 555 {"DAI Sel Mux", "Left", "Amp Enable"}, 556 {"DAI Sel Mux", "Right", "Amp Enable"}, 557 {"DAI Sel Mux", "LeftRight", "Amp Enable"}, 558 {"BE_OUT", NULL, "DAI Sel Mux"}, 559 /* Capture */ 560 { "VI Sense", "Switch", "VMON" }, 561 { "VI Sense", "Switch", "IMON" }, 562 { "Voltage Sense", NULL, "VI Sense" }, 563 { "Current Sense", NULL, "VI Sense" }, 564 }; 565 566 static struct snd_soc_dai_driver max98927_dai[] = { 567 { 568 .name = "max98927-aif1", 569 .playback = { 570 .stream_name = "HiFi Playback", 571 .channels_min = 1, 572 .channels_max = 2, 573 .rates = MAX98927_RATES, 574 .formats = MAX98927_FORMATS, 575 }, 576 .capture = { 577 .stream_name = "HiFi Capture", 578 .channels_min = 1, 579 .channels_max = 2, 580 .rates = MAX98927_RATES, 581 .formats = MAX98927_FORMATS, 582 }, 583 .ops = &max98927_dai_ops, 584 } 585 }; 586 587 static int max98927_probe(struct snd_soc_codec *codec) 588 { 589 struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec); 590 591 max98927->codec = codec; 592 codec->control_data = max98927->regmap; 593 594 /* Software Reset */ 595 regmap_write(max98927->regmap, 596 MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET); 597 598 /* IV default slot configuration */ 599 regmap_write(max98927->regmap, 600 MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 601 0xFF); 602 regmap_write(max98927->regmap, 603 MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 604 0xFF); 605 regmap_write(max98927->regmap, 606 MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 607 0x80); 608 regmap_write(max98927->regmap, 609 MAX98927_R0026_PCM_TO_SPK_MONOMIX_B, 610 0x1); 611 /* Set inital volume (+13dB) */ 612 regmap_write(max98927->regmap, 613 MAX98927_R0036_AMP_VOL_CTRL, 614 0x38); 615 regmap_write(max98927->regmap, 616 MAX98927_R003C_SPK_GAIN, 617 0x05); 618 /* Enable DC blocker */ 619 regmap_write(max98927->regmap, 620 MAX98927_R0037_AMP_DSP_CFG, 621 0x03); 622 /* Enable IMON VMON DC blocker */ 623 regmap_write(max98927->regmap, 624 MAX98927_R003F_MEAS_DSP_CFG, 625 0xF7); 626 /* Boost Output Voltage & Current limit */ 627 regmap_write(max98927->regmap, 628 MAX98927_R0040_BOOST_CTRL0, 629 0x1C); 630 regmap_write(max98927->regmap, 631 MAX98927_R0042_BOOST_CTRL1, 632 0x3E); 633 /* Measurement ADC config */ 634 regmap_write(max98927->regmap, 635 MAX98927_R0043_MEAS_ADC_CFG, 636 0x04); 637 regmap_write(max98927->regmap, 638 MAX98927_R0044_MEAS_ADC_BASE_MSB, 639 0x00); 640 regmap_write(max98927->regmap, 641 MAX98927_R0045_MEAS_ADC_BASE_LSB, 642 0x24); 643 /* Brownout Level */ 644 regmap_write(max98927->regmap, 645 MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1, 646 0x06); 647 /* Envelope Tracking configuration */ 648 regmap_write(max98927->regmap, 649 MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM, 650 0x08); 651 regmap_write(max98927->regmap, 652 MAX98927_R0086_ENV_TRACK_CTRL, 653 0x01); 654 regmap_write(max98927->regmap, 655 MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ, 656 0x10); 657 658 /* voltage, current slot configuration */ 659 regmap_write(max98927->regmap, 660 MAX98927_R001E_PCM_TX_CH_SRC_A, 661 (max98927->i_l_slot<<MAX98927_PCM_TX_CH_SRC_A_I_SHIFT| 662 max98927->v_l_slot)&0xFF); 663 664 if (max98927->v_l_slot < 8) { 665 regmap_update_bits(max98927->regmap, 666 MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 667 1 << max98927->v_l_slot, 0); 668 regmap_update_bits(max98927->regmap, 669 MAX98927_R001A_PCM_TX_EN_A, 670 1 << max98927->v_l_slot, 671 1 << max98927->v_l_slot); 672 } else { 673 regmap_update_bits(max98927->regmap, 674 MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 675 1 << (max98927->v_l_slot - 8), 0); 676 regmap_update_bits(max98927->regmap, 677 MAX98927_R001B_PCM_TX_EN_B, 678 1 << (max98927->v_l_slot - 8), 679 1 << (max98927->v_l_slot - 8)); 680 } 681 682 if (max98927->i_l_slot < 8) { 683 regmap_update_bits(max98927->regmap, 684 MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 685 1 << max98927->i_l_slot, 0); 686 regmap_update_bits(max98927->regmap, 687 MAX98927_R001A_PCM_TX_EN_A, 688 1 << max98927->i_l_slot, 689 1 << max98927->i_l_slot); 690 } else { 691 regmap_update_bits(max98927->regmap, 692 MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 693 1 << (max98927->i_l_slot - 8), 0); 694 regmap_update_bits(max98927->regmap, 695 MAX98927_R001B_PCM_TX_EN_B, 696 1 << (max98927->i_l_slot - 8), 697 1 << (max98927->i_l_slot - 8)); 698 } 699 700 /* Set interleave mode */ 701 if (max98927->interleave_mode) 702 regmap_update_bits(max98927->regmap, 703 MAX98927_R001F_PCM_TX_CH_SRC_B, 704 MAX98927_PCM_TX_CH_INTERLEAVE_MASK, 705 MAX98927_PCM_TX_CH_INTERLEAVE_MASK); 706 return 0; 707 } 708 709 #ifdef CONFIG_PM_SLEEP 710 static int max98927_suspend(struct device *dev) 711 { 712 struct max98927_priv *max98927 = dev_get_drvdata(dev); 713 714 regcache_cache_only(max98927->regmap, true); 715 regcache_mark_dirty(max98927->regmap); 716 return 0; 717 } 718 static int max98927_resume(struct device *dev) 719 { 720 struct max98927_priv *max98927 = dev_get_drvdata(dev); 721 722 regmap_write(max98927->regmap, 723 MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET); 724 regcache_cache_only(max98927->regmap, false); 725 regcache_sync(max98927->regmap); 726 return 0; 727 } 728 #endif 729 730 static const struct dev_pm_ops max98927_pm = { 731 SET_SYSTEM_SLEEP_PM_OPS(max98927_suspend, max98927_resume) 732 }; 733 734 static const struct snd_soc_codec_driver soc_codec_dev_max98927 = { 735 .probe = max98927_probe, 736 .component_driver = { 737 .controls = max98927_snd_controls, 738 .num_controls = ARRAY_SIZE(max98927_snd_controls), 739 .dapm_widgets = max98927_dapm_widgets, 740 .num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets), 741 .dapm_routes = max98927_audio_map, 742 .num_dapm_routes = ARRAY_SIZE(max98927_audio_map), 743 }, 744 }; 745 746 static const struct regmap_config max98927_regmap = { 747 .reg_bits = 16, 748 .val_bits = 8, 749 .max_register = MAX98927_R01FF_REV_ID, 750 .reg_defaults = max98927_reg, 751 .num_reg_defaults = ARRAY_SIZE(max98927_reg), 752 .readable_reg = max98927_readable_register, 753 .volatile_reg = max98927_volatile_reg, 754 .cache_type = REGCACHE_RBTREE, 755 }; 756 757 static void max98927_slot_config(struct i2c_client *i2c, 758 struct max98927_priv *max98927) 759 { 760 int value; 761 struct device *dev = &i2c->dev; 762 763 if (!device_property_read_u32(dev, "vmon-slot-no", &value)) 764 max98927->v_l_slot = value & 0xF; 765 else 766 max98927->v_l_slot = 0; 767 768 if (!device_property_read_u32(dev, "imon-slot-no", &value)) 769 max98927->i_l_slot = value & 0xF; 770 else 771 max98927->i_l_slot = 1; 772 } 773 774 static int max98927_i2c_probe(struct i2c_client *i2c, 775 const struct i2c_device_id *id) 776 { 777 778 int ret = 0, value; 779 int reg = 0; 780 struct max98927_priv *max98927 = NULL; 781 782 max98927 = devm_kzalloc(&i2c->dev, 783 sizeof(*max98927), GFP_KERNEL); 784 785 if (!max98927) { 786 ret = -ENOMEM; 787 return ret; 788 } 789 i2c_set_clientdata(i2c, max98927); 790 791 /* update interleave mode info */ 792 if (!of_property_read_u32(i2c->dev.of_node, 793 "interleave_mode", &value)) { 794 if (value > 0) 795 max98927->interleave_mode = 1; 796 else 797 max98927->interleave_mode = 0; 798 } else 799 max98927->interleave_mode = 0; 800 801 /* regmap initialization */ 802 max98927->regmap 803 = devm_regmap_init_i2c(i2c, &max98927_regmap); 804 if (IS_ERR(max98927->regmap)) { 805 ret = PTR_ERR(max98927->regmap); 806 dev_err(&i2c->dev, 807 "Failed to allocate regmap: %d\n", ret); 808 return ret; 809 } 810 811 /* Check Revision ID */ 812 ret = regmap_read(max98927->regmap, 813 MAX98927_R01FF_REV_ID, ®); 814 if (ret < 0) { 815 dev_err(&i2c->dev, 816 "Failed to read: 0x%02X\n", MAX98927_R01FF_REV_ID); 817 return ret; 818 } 819 dev_info(&i2c->dev, "MAX98927 revisionID: 0x%02X\n", reg); 820 821 /* voltage/current slot configuration */ 822 max98927_slot_config(i2c, max98927); 823 824 /* codec registeration */ 825 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98927, 826 max98927_dai, ARRAY_SIZE(max98927_dai)); 827 if (ret < 0) 828 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 829 830 return ret; 831 } 832 833 static int max98927_i2c_remove(struct i2c_client *client) 834 { 835 snd_soc_unregister_codec(&client->dev); 836 return 0; 837 } 838 839 static const struct i2c_device_id max98927_i2c_id[] = { 840 { "max98927", 0}, 841 { }, 842 }; 843 844 MODULE_DEVICE_TABLE(i2c, max98927_i2c_id); 845 846 #if defined(CONFIG_OF) 847 static const struct of_device_id max98927_of_match[] = { 848 { .compatible = "maxim,max98927", }, 849 { } 850 }; 851 MODULE_DEVICE_TABLE(of, max98927_of_match); 852 #endif 853 854 #ifdef CONFIG_ACPI 855 static const struct acpi_device_id max98927_acpi_match[] = { 856 { "MX98927", 0 }, 857 {}, 858 }; 859 MODULE_DEVICE_TABLE(acpi, max98927_acpi_match); 860 #endif 861 862 static struct i2c_driver max98927_i2c_driver = { 863 .driver = { 864 .name = "max98927", 865 .of_match_table = of_match_ptr(max98927_of_match), 866 .acpi_match_table = ACPI_PTR(max98927_acpi_match), 867 .pm = &max98927_pm, 868 }, 869 .probe = max98927_i2c_probe, 870 .remove = max98927_i2c_remove, 871 .id_table = max98927_i2c_id, 872 }; 873 874 module_i2c_driver(max98927_i2c_driver) 875 876 MODULE_DESCRIPTION("ALSA SoC MAX98927 driver"); 877 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>"); 878 MODULE_LICENSE("GPL"); 879