1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 21ff27651SAnish Kumar /* 31ff27651SAnish Kumar * max98925.h -- MAX98925 ALSA SoC Audio driver 41ff27651SAnish Kumar * 51ff27651SAnish Kumar * Copyright 2013-2015 Maxim Integrated Products 61ff27651SAnish Kumar */ 71ff27651SAnish Kumar 81ff27651SAnish Kumar #ifndef _MAX98925_H 91ff27651SAnish Kumar #define _MAX98925_H 101ff27651SAnish Kumar 111ff27651SAnish Kumar #define MAX98925_VERSION 0x51 121ff27651SAnish Kumar #define MAX98925_VERSION1 0x80 131ff27651SAnish Kumar #define MAX98925_VBAT_DATA 0x00 141ff27651SAnish Kumar #define MAX98925_VBST_DATA 0x01 151ff27651SAnish Kumar #define MAX98925_LIVE_STATUS0 0x02 161ff27651SAnish Kumar #define MAX98925_LIVE_STATUS1 0x03 171ff27651SAnish Kumar #define MAX98925_LIVE_STATUS2 0x04 181ff27651SAnish Kumar #define MAX98925_STATE0 0x05 191ff27651SAnish Kumar #define MAX98925_STATE1 0x06 201ff27651SAnish Kumar #define MAX98925_STATE2 0x07 211ff27651SAnish Kumar #define MAX98925_FLAG0 0x08 221ff27651SAnish Kumar #define MAX98925_FLAG1 0x09 231ff27651SAnish Kumar #define MAX98925_FLAG2 0x0A 241ff27651SAnish Kumar #define MAX98925_IRQ_ENABLE0 0x0B 251ff27651SAnish Kumar #define MAX98925_IRQ_ENABLE1 0x0C 261ff27651SAnish Kumar #define MAX98925_IRQ_ENABLE2 0x0D 271ff27651SAnish Kumar #define MAX98925_IRQ_CLEAR0 0x0E 281ff27651SAnish Kumar #define MAX98925_IRQ_CLEAR1 0x0F 291ff27651SAnish Kumar #define MAX98925_IRQ_CLEAR2 0x10 301ff27651SAnish Kumar #define MAX98925_MAP0 0x11 311ff27651SAnish Kumar #define MAX98925_MAP1 0x12 321ff27651SAnish Kumar #define MAX98925_MAP2 0x13 331ff27651SAnish Kumar #define MAX98925_MAP3 0x14 341ff27651SAnish Kumar #define MAX98925_MAP4 0x15 351ff27651SAnish Kumar #define MAX98925_MAP5 0x16 361ff27651SAnish Kumar #define MAX98925_MAP6 0x17 371ff27651SAnish Kumar #define MAX98925_MAP7 0x18 381ff27651SAnish Kumar #define MAX98925_MAP8 0x19 391ff27651SAnish Kumar #define MAX98925_DAI_CLK_MODE1 0x1A 401ff27651SAnish Kumar #define MAX98925_DAI_CLK_MODE2 0x1B 411ff27651SAnish Kumar #define MAX98925_DAI_CLK_DIV_M_MSBS 0x1C 421ff27651SAnish Kumar #define MAX98925_DAI_CLK_DIV_M_LSBS 0x1D 431ff27651SAnish Kumar #define MAX98925_DAI_CLK_DIV_N_MSBS 0x1E 441ff27651SAnish Kumar #define MAX98925_DAI_CLK_DIV_N_LSBS 0x1F 451ff27651SAnish Kumar #define MAX98925_FORMAT 0x20 461ff27651SAnish Kumar #define MAX98925_TDM_SLOT_SELECT 0x21 471ff27651SAnish Kumar #define MAX98925_DOUT_CFG_VMON 0x22 481ff27651SAnish Kumar #define MAX98925_DOUT_CFG_IMON 0x23 491ff27651SAnish Kumar #define MAX98925_DOUT_CFG_VBAT 0x24 501ff27651SAnish Kumar #define MAX98925_DOUT_CFG_VBST 0x25 511ff27651SAnish Kumar #define MAX98925_DOUT_CFG_FLAG 0x26 521ff27651SAnish Kumar #define MAX98925_DOUT_HIZ_CFG1 0x27 531ff27651SAnish Kumar #define MAX98925_DOUT_HIZ_CFG2 0x28 541ff27651SAnish Kumar #define MAX98925_DOUT_HIZ_CFG3 0x29 551ff27651SAnish Kumar #define MAX98925_DOUT_HIZ_CFG4 0x2A 561ff27651SAnish Kumar #define MAX98925_DOUT_DRV_STRENGTH 0x2B 571ff27651SAnish Kumar #define MAX98925_FILTERS 0x2C 581ff27651SAnish Kumar #define MAX98925_GAIN 0x2D 591ff27651SAnish Kumar #define MAX98925_GAIN_RAMPING 0x2E 601ff27651SAnish Kumar #define MAX98925_SPK_AMP 0x2F 611ff27651SAnish Kumar #define MAX98925_THRESHOLD 0x30 621ff27651SAnish Kumar #define MAX98925_ALC_ATTACK 0x31 631ff27651SAnish Kumar #define MAX98925_ALC_ATTEN_RLS 0x32 641ff27651SAnish Kumar #define MAX98925_ALC_HOLD_RLS 0x33 651ff27651SAnish Kumar #define MAX98925_ALC_CONFIGURATION 0x34 661ff27651SAnish Kumar #define MAX98925_BOOST_CONVERTER 0x35 671ff27651SAnish Kumar #define MAX98925_BLOCK_ENABLE 0x36 681ff27651SAnish Kumar #define MAX98925_CONFIGURATION 0x37 691ff27651SAnish Kumar #define MAX98925_GLOBAL_ENABLE 0x38 701ff27651SAnish Kumar #define MAX98925_BOOST_LIMITER 0x3A 711ff27651SAnish Kumar #define MAX98925_REV_VERSION 0xFF 721ff27651SAnish Kumar 731ff27651SAnish Kumar #define MAX98925_REG_CNT (MAX98925_R03A_BOOST_LIMITER+1) 741ff27651SAnish Kumar 751ff27651SAnish Kumar /* MAX98925 Register Bit Fields */ 761ff27651SAnish Kumar 771ff27651SAnish Kumar /* MAX98925_R002_LIVE_STATUS0 */ 781ff27651SAnish Kumar #define M98925_THERMWARN_STATUS_MASK (1<<3) 791ff27651SAnish Kumar #define M98925_THERMWARN_STATUS_SHIFT 3 801ff27651SAnish Kumar #define M98925_THERMWARN_STATUS_WIDTH 1 811ff27651SAnish Kumar #define M98925_THERMSHDN_STATUS_MASK (1<<1) 821ff27651SAnish Kumar #define M98925_THERMSHDN_STATUS_SHIFT 1 831ff27651SAnish Kumar #define M98925_THERMSHDN_STATUS_WIDTH 1 841ff27651SAnish Kumar 851ff27651SAnish Kumar /* MAX98925_R003_LIVE_STATUS1 */ 861ff27651SAnish Kumar #define M98925_SPKCURNT_STATUS_MASK (1<<5) 871ff27651SAnish Kumar #define M98925_SPKCURNT_STATUS_SHIFT 5 881ff27651SAnish Kumar #define M98925_SPKCURNT_STATUS_WIDTH 1 891ff27651SAnish Kumar #define M98925_WATCHFAIL_STATUS_MASK (1<<4) 901ff27651SAnish Kumar #define M98925_WATCHFAIL_STATUS_SHIFT 4 911ff27651SAnish Kumar #define M98925_WATCHFAIL_STATUS_WIDTH 1 921ff27651SAnish Kumar #define M98925_ALCINFH_STATUS_MASK (1<<3) 931ff27651SAnish Kumar #define M98925_ALCINFH_STATUS_SHIFT 3 941ff27651SAnish Kumar #define M98925_ALCINFH_STATUS_WIDTH 1 951ff27651SAnish Kumar #define M98925_ALCACT_STATUS_MASK (1<<2) 961ff27651SAnish Kumar #define M98925_ALCACT_STATUS_SHIFT 2 971ff27651SAnish Kumar #define M98925_ALCACT_STATUS_WIDTH 1 981ff27651SAnish Kumar #define M98925_ALCMUT_STATUS_MASK (1<<1) 991ff27651SAnish Kumar #define M98925_ALCMUT_STATUS_SHIFT 1 1001ff27651SAnish Kumar #define M98925_ALCMUT_STATUS_WIDTH 1 1011ff27651SAnish Kumar #define M98925_ACLP_STATUS_MASK (1<<0) 1021ff27651SAnish Kumar #define M98925_ACLP_STATUS_SHIFT 0 1031ff27651SAnish Kumar #define M98925_ACLP_STATUS_WIDTH 1 1041ff27651SAnish Kumar 1051ff27651SAnish Kumar /* MAX98925_R004_LIVE_STATUS2 */ 1061ff27651SAnish Kumar #define M98925_SLOTOVRN_STATUS_MASK (1<<6) 1071ff27651SAnish Kumar #define M98925_SLOTOVRN_STATUS_SHIFT 6 1081ff27651SAnish Kumar #define M98925_SLOTOVRN_STATUS_WIDTH 1 1091ff27651SAnish Kumar #define M98925_INVALSLOT_STATUS_MASK (1<<5) 1101ff27651SAnish Kumar #define M98925_INVALSLOT_STATUS_SHIFT 5 1111ff27651SAnish Kumar #define M98925_INVALSLOT_STATUS_WIDTH 1 1121ff27651SAnish Kumar #define M98925_SLOTCNFLT_STATUS_MASK (1<<4) 1131ff27651SAnish Kumar #define M98925_SLOTCNFLT_STATUS_SHIFT 4 1141ff27651SAnish Kumar #define M98925_SLOTCNFLT_STATUS_WIDTH 1 1151ff27651SAnish Kumar #define M98925_VBSTOVFL_STATUS_MASK (1<<3) 1161ff27651SAnish Kumar #define M98925_VBSTOVFL_STATUS_SHIFT 3 1171ff27651SAnish Kumar #define M98925_VBSTOVFL_STATUS_WIDTH 1 1181ff27651SAnish Kumar #define M98925_VBATOVFL_STATUS_MASK (1<<2) 1191ff27651SAnish Kumar #define M98925_VBATOVFL_STATUS_SHIFT 2 1201ff27651SAnish Kumar #define M98925_VBATOVFL_STATUS_WIDTH 1 1211ff27651SAnish Kumar #define M98925_IMONOVFL_STATUS_MASK (1<<1) 1221ff27651SAnish Kumar #define M98925_IMONOVFL_STATUS_SHIFT 1 1231ff27651SAnish Kumar #define M98925_IMONOVFL_STATUS_WIDTH 1 1241ff27651SAnish Kumar #define M98925_VMONOVFL_STATUS_MASK (1<<0) 1251ff27651SAnish Kumar #define M98925_VMONOVFL_STATUS_SHIFT 0 1261ff27651SAnish Kumar #define M98925_VMONOVFL_STATUS_WIDTH 1 1271ff27651SAnish Kumar 1281ff27651SAnish Kumar /* MAX98925_R005_STATE0 */ 1291ff27651SAnish Kumar #define M98925_THERMWARN_END_STATE_MASK (1<<3) 1301ff27651SAnish Kumar #define M98925_THERMWARN_END_STATE_SHIFT 3 1311ff27651SAnish Kumar #define M98925_THERMWARN_END_STATE_WIDTH 1 1321ff27651SAnish Kumar #define M98925_THERMWARN_BGN_STATE_MASK (1<<2) 1331ff27651SAnish Kumar #define M98925_THERMWARN_BGN_STATE_SHIFT 1 1341ff27651SAnish Kumar #define M98925_THERMWARN_BGN_STATE_WIDTH 1 1351ff27651SAnish Kumar #define M98925_THERMSHDN_END_STATE_MASK (1<<1) 1361ff27651SAnish Kumar #define M98925_THERMSHDN_END_STATE_SHIFT 1 1371ff27651SAnish Kumar #define M98925_THERMSHDN_END_STATE_WIDTH 1 1381ff27651SAnish Kumar #define M98925_THERMSHDN_BGN_STATE_MASK (1<<0) 1391ff27651SAnish Kumar #define M98925_THERMSHDN_BGN_STATE_SHIFT 0 1401ff27651SAnish Kumar #define M98925_THERMSHDN_BGN_STATE_WIDTH 1 1411ff27651SAnish Kumar 1421ff27651SAnish Kumar /* MAX98925_R006_STATE1 */ 1431ff27651SAnish Kumar #define M98925_SPRCURNT_STATE_MASK (1<<5) 1441ff27651SAnish Kumar #define M98925_SPRCURNT_STATE_SHIFT 5 1451ff27651SAnish Kumar #define M98925_SPRCURNT_STATE_WIDTH 1 1461ff27651SAnish Kumar #define M98925_WATCHFAIL_STATE_MASK (1<<4) 1471ff27651SAnish Kumar #define M98925_WATCHFAIL_STATE_SHIFT 4 1481ff27651SAnish Kumar #define M98925_WATCHFAIL_STATE_WIDTH 1 1491ff27651SAnish Kumar #define M98925_ALCINFH_STATE_MASK (1<<3) 1501ff27651SAnish Kumar #define M98925_ALCINFH_STATE_SHIFT 3 1511ff27651SAnish Kumar #define M98925_ALCINFH_STATE_WIDTH 1 1521ff27651SAnish Kumar #define M98925_ALCACT_STATE_MASK (1<<2) 1531ff27651SAnish Kumar #define M98925_ALCACT_STATE_SHIFT 2 1541ff27651SAnish Kumar #define M98925_ALCACT_STATE_WIDTH 1 1551ff27651SAnish Kumar #define M98925_ALCMUT_STATE_MASK (1<<1) 1561ff27651SAnish Kumar #define M98925_ALCMUT_STATE_SHIFT 1 1571ff27651SAnish Kumar #define M98925_ALCMUT_STATE_WIDTH 1 1581ff27651SAnish Kumar #define M98925_ALCP_STATE_MASK (1<<0) 1591ff27651SAnish Kumar #define M98925_ALCP_STATE_SHIFT 0 1601ff27651SAnish Kumar #define M98925_ALCP_STATE_WIDTH 1 1611ff27651SAnish Kumar 1621ff27651SAnish Kumar /* MAX98925_R007_STATE2 */ 1631ff27651SAnish Kumar #define M98925_SLOTOVRN_STATE_MASK (1<<6) 1641ff27651SAnish Kumar #define M98925_SLOTOVRN_STATE_SHIFT 6 1651ff27651SAnish Kumar #define M98925_SLOTOVRN_STATE_WIDTH 1 1661ff27651SAnish Kumar #define M98925_INVALSLOT_STATE_MASK (1<<5) 1671ff27651SAnish Kumar #define M98925_INVALSLOT_STATE_SHIFT 5 1681ff27651SAnish Kumar #define M98925_INVALSLOT_STATE_WIDTH 1 1691ff27651SAnish Kumar #define M98925_SLOTCNFLT_STATE_MASK (1<<4) 1701ff27651SAnish Kumar #define M98925_SLOTCNFLT_STATE_SHIFT 4 1711ff27651SAnish Kumar #define M98925_SLOTCNFLT_STATE_WIDTH 1 1721ff27651SAnish Kumar #define M98925_VBSTOVFL_STATE_MASK (1<<3) 1731ff27651SAnish Kumar #define M98925_VBSTOVFL_STATE_SHIFT 3 1741ff27651SAnish Kumar #define M98925_VBSTOVFL_STATE_WIDTH 1 1751ff27651SAnish Kumar #define M98925_VBATOVFL_STATE_MASK (1<<2) 1761ff27651SAnish Kumar #define M98925_VBATOVFL_STATE_SHIFT 2 1771ff27651SAnish Kumar #define M98925_VBATOVFL_STATE_WIDTH 1 1781ff27651SAnish Kumar #define M98925_IMONOVFL_STATE_MASK (1<<1) 1791ff27651SAnish Kumar #define M98925_IMONOVFL_STATE_SHIFT 1 1801ff27651SAnish Kumar #define M98925_IMONOVFL_STATE_WIDTH 1 1811ff27651SAnish Kumar #define M98925_VMONOVFL_STATE_MASK (1<<0) 1821ff27651SAnish Kumar #define M98925_VMONOVFL_STATE_SHIFT 0 1831ff27651SAnish Kumar #define M98925_VMONOVFL_STATE_WIDTH 1 1841ff27651SAnish Kumar 1851ff27651SAnish Kumar /* MAX98925_R008_FLAG0 */ 1861ff27651SAnish Kumar #define M98925_THERMWARN_END_FLAG_MASK (1<<3) 1871ff27651SAnish Kumar #define M98925_THERMWARN_END_FLAG_SHIFT 3 1881ff27651SAnish Kumar #define M98925_THERMWARN_END_FLAG_WIDTH 1 1891ff27651SAnish Kumar #define M98925_THERMWARN_BGN_FLAG_MASK (1<<2) 1901ff27651SAnish Kumar #define M98925_THERMWARN_BGN_FLAG_SHIFT 2 1911ff27651SAnish Kumar #define M98925_THERMWARN_BGN_FLAG_WIDTH 1 1921ff27651SAnish Kumar #define M98925_THERMSHDN_END_FLAG_MASK (1<<1) 1931ff27651SAnish Kumar #define M98925_THERMSHDN_END_FLAG_SHIFT 1 1941ff27651SAnish Kumar #define M98925_THERMSHDN_END_FLAG_WIDTH 1 1951ff27651SAnish Kumar #define M98925_THERMSHDN_BGN_FLAG_MASK (1<<0) 1961ff27651SAnish Kumar #define M98925_THERMSHDN_BGN_FLAG_SHIFT 0 1971ff27651SAnish Kumar #define M98925_THERMSHDN_BGN_FLAG_WIDTH 1 1981ff27651SAnish Kumar 1991ff27651SAnish Kumar /* MAX98925_R009_FLAG1 */ 2001ff27651SAnish Kumar #define M98925_SPKCURNT_FLAG_MASK (1<<5) 2011ff27651SAnish Kumar #define M98925_SPKCURNT_FLAG_SHIFT 5 2021ff27651SAnish Kumar #define M98925_SPKCURNT_FLAG_WIDTH 1 2031ff27651SAnish Kumar #define M98925_WATCHFAIL_FLAG_MASK (1<<4) 2041ff27651SAnish Kumar #define M98925_WATCHFAIL_FLAG_SHIFT 4 2051ff27651SAnish Kumar #define M98925_WATCHFAIL_FLAG_WIDTH 1 2061ff27651SAnish Kumar #define M98925_ALCINFH_FLAG_MASK (1<<3) 2071ff27651SAnish Kumar #define M98925_ALCINFH_FLAG_SHIFT 3 2081ff27651SAnish Kumar #define M98925_ALCINFH_FLAG_WIDTH 1 2091ff27651SAnish Kumar #define M98925_ALCACT_FLAG_MASK (1<<2) 2101ff27651SAnish Kumar #define M98925_ALCACT_FLAG_SHIFT 2 2111ff27651SAnish Kumar #define M98925_ALCACT_FLAG_WIDTH 1 2121ff27651SAnish Kumar #define M98925_ALCMUT_FLAG_MASK (1<<1) 2131ff27651SAnish Kumar #define M98925_ALCMUT_FLAG_SHIFT 1 2141ff27651SAnish Kumar #define M98925_ALCMUT_FLAG_WIDTH 1 2151ff27651SAnish Kumar #define M98925_ALCP_FLAG_MASK (1<<0) 2161ff27651SAnish Kumar #define M98925_ALCP_FLAG_SHIFT 0 2171ff27651SAnish Kumar #define M98925_ALCP_FLAG_WIDTH 1 2181ff27651SAnish Kumar 2191ff27651SAnish Kumar /* MAX98925_R00A_FLAG2 */ 2201ff27651SAnish Kumar #define M98925_SLOTOVRN_FLAG_MASK (1<<6) 2211ff27651SAnish Kumar #define M98925_SLOTOVRN_FLAG_SHIFT 6 2221ff27651SAnish Kumar #define M98925_SLOTOVRN_FLAG_WIDTH 1 2231ff27651SAnish Kumar #define M98925_INVALSLOT_FLAG_MASK (1<<5) 2241ff27651SAnish Kumar #define M98925_INVALSLOT_FLAG_SHIFT 5 2251ff27651SAnish Kumar #define M98925_INVALSLOT_FLAG_WIDTH 1 2261ff27651SAnish Kumar #define M98925_SLOTCNFLT_FLAG_MASK (1<<4) 2271ff27651SAnish Kumar #define M98925_SLOTCNFLT_FLAG_SHIFT 4 2281ff27651SAnish Kumar #define M98925_SLOTCNFLT_FLAG_WIDTH 1 2291ff27651SAnish Kumar #define M98925_VBSTOVFL_FLAG_MASK (1<<3) 2301ff27651SAnish Kumar #define M98925_VBSTOVFL_FLAG_SHIFT 3 2311ff27651SAnish Kumar #define M98925_VBSTOVFL_FLAG_WIDTH 1 2321ff27651SAnish Kumar #define M98925_VBATOVFL_FLAG_MASK (1<<2) 2331ff27651SAnish Kumar #define M98925_VBATOVFL_FLAG_SHIFT 2 2341ff27651SAnish Kumar #define M98925_VBATOVFL_FLAG_WIDTH 1 2351ff27651SAnish Kumar #define M98925_IMONOVFL_FLAG_MASK (1<<1) 2361ff27651SAnish Kumar #define M98925_IMONOVFL_FLAG_SHIFT 1 2371ff27651SAnish Kumar #define M98925_IMONOVFL_FLAG_WIDTH 1 2381ff27651SAnish Kumar #define M98925_VMONOVFL_FLAG_MASK (1<<0) 2391ff27651SAnish Kumar #define M98925_VMONOVFL_FLAG_SHIFT 0 2401ff27651SAnish Kumar #define M98925_VMONOVFL_FLAG_WIDTH 1 2411ff27651SAnish Kumar 2421ff27651SAnish Kumar /* MAX98925_R00B_IRQ_ENABLE0 */ 2431ff27651SAnish Kumar #define M98925_THERMWARN_END_EN_MASK (1<<3) 2441ff27651SAnish Kumar #define M98925_THERMWARN_END_EN_SHIFT 3 2451ff27651SAnish Kumar #define M98925_THERMWARN_END_EN_WIDTH 1 2461ff27651SAnish Kumar #define M98925_THERMWARN_BGN_EN_MASK (1<<2) 2471ff27651SAnish Kumar #define M98925_THERMWARN_BGN_EN_SHIFT 2 2481ff27651SAnish Kumar #define M98925_THERMWARN_BGN_EN_WIDTH 1 2491ff27651SAnish Kumar #define M98925_THERMSHDN_END_EN_MASK (1<<1) 2501ff27651SAnish Kumar #define M98925_THERMSHDN_END_EN_SHIFT 1 2511ff27651SAnish Kumar #define M98925_THERMSHDN_END_EN_WIDTH 1 2521ff27651SAnish Kumar #define M98925_THERMSHDN_BGN_EN_MASK (1<<0) 2531ff27651SAnish Kumar #define M98925_THERMSHDN_BGN_EN_SHIFT 0 2541ff27651SAnish Kumar #define M98925_THERMSHDN_BGN_EN_WIDTH 1 2551ff27651SAnish Kumar 2561ff27651SAnish Kumar /* MAX98925_R00C_IRQ_ENABLE1 */ 2571ff27651SAnish Kumar #define M98925_SPKCURNT_EN_MASK (1<<5) 2581ff27651SAnish Kumar #define M98925_SPKCURNT_EN_SHIFT 5 2591ff27651SAnish Kumar #define M98925_SPKCURNT_EN_WIDTH 1 2601ff27651SAnish Kumar #define M98925_WATCHFAIL_EN_MASK (1<<4) 2611ff27651SAnish Kumar #define M98925_WATCHFAIL_EN_SHIFT 4 2621ff27651SAnish Kumar #define M98925_WATCHFAIL_EN_WIDTH 1 2631ff27651SAnish Kumar #define M98925_ALCINFH_EN_MASK (1<<3) 2641ff27651SAnish Kumar #define M98925_ALCINFH_EN_SHIFT 3 2651ff27651SAnish Kumar #define M98925_ALCINFH_EN_WIDTH 1 2661ff27651SAnish Kumar #define M98925_ALCACT_EN_MASK (1<<2) 2671ff27651SAnish Kumar #define M98925_ALCACT_EN_SHIFT 2 2681ff27651SAnish Kumar #define M98925_ALCACT_EN_WIDTH 1 2691ff27651SAnish Kumar #define M98925_ALCMUT_EN_MASK (1<<1) 2701ff27651SAnish Kumar #define M98925_ALCMUT_EN_SHIFT 1 2711ff27651SAnish Kumar #define M98925_ALCMUT_EN_WIDTH 1 2721ff27651SAnish Kumar #define M98925_ALCP_EN_MASK (1<<0) 2731ff27651SAnish Kumar #define M98925_ALCP_EN_SHIFT 0 2741ff27651SAnish Kumar #define M98925_ALCP_EN_WIDTH 1 2751ff27651SAnish Kumar 2761ff27651SAnish Kumar /* MAX98925_R00D_IRQ_ENABLE2 */ 2771ff27651SAnish Kumar #define M98925_SLOTOVRN_EN_MASK (1<<6) 2781ff27651SAnish Kumar #define M98925_SLOTOVRN_EN_SHIFT 6 2791ff27651SAnish Kumar #define M98925_SLOTOVRN_EN_WIDTH 1 2801ff27651SAnish Kumar #define M98925_INVALSLOT_EN_MASK (1<<5) 2811ff27651SAnish Kumar #define M98925_INVALSLOT_EN_SHIFT 5 2821ff27651SAnish Kumar #define M98925_INVALSLOT_EN_WIDTH 1 2831ff27651SAnish Kumar #define M98925_SLOTCNFLT_EN_MASK (1<<4) 2841ff27651SAnish Kumar #define M98925_SLOTCNFLT_EN_SHIFT 4 2851ff27651SAnish Kumar #define M98925_SLOTCNFLT_EN_WIDTH 1 2861ff27651SAnish Kumar #define M98925_VBSTOVFL_EN_MASK (1<<3) 2871ff27651SAnish Kumar #define M98925_VBSTOVFL_EN_SHIFT 3 2881ff27651SAnish Kumar #define M98925_VBSTOVFL_EN_WIDTH 1 2891ff27651SAnish Kumar #define M98925_VBATOVFL_EN_MASK (1<<2) 2901ff27651SAnish Kumar #define M98925_VBATOVFL_EN_SHIFT 2 2911ff27651SAnish Kumar #define M98925_VBATOVFL_EN_WIDTH 1 2921ff27651SAnish Kumar #define M98925_IMONOVFL_EN_MASK (1<<1) 2931ff27651SAnish Kumar #define M98925_IMONOVFL_EN_SHIFT 1 2941ff27651SAnish Kumar #define M98925_IMONOVFL_EN_WIDTH 1 2951ff27651SAnish Kumar #define M98925_VMONOVFL_EN_MASK (1<<0) 2961ff27651SAnish Kumar #define M98925_VMONOVFL_EN_SHIFT 0 2971ff27651SAnish Kumar #define M98925_VMONOVFL_EN_WIDTH 1 2981ff27651SAnish Kumar 2991ff27651SAnish Kumar /* MAX98925_R00E_IRQ_CLEAR0 */ 3001ff27651SAnish Kumar #define M98925_THERMWARN_END_CLR_MASK (1<<3) 3011ff27651SAnish Kumar #define M98925_THERMWARN_END_CLR_SHIFT 3 3021ff27651SAnish Kumar #define M98925_THERMWARN_END_CLR_WIDTH 1 3031ff27651SAnish Kumar #define M98925_THERMWARN_BGN_CLR_MASK (1<<2) 3041ff27651SAnish Kumar #define M98925_THERMWARN_BGN_CLR_SHIFT 2 3051ff27651SAnish Kumar #define M98925_THERMWARN_BGN_CLR_WIDTH 1 3061ff27651SAnish Kumar #define M98925_THERMSHDN_END_CLR_MASK (1<<1) 3071ff27651SAnish Kumar #define M98925_THERMSHDN_END_CLR_SHIFT 1 3081ff27651SAnish Kumar #define M98925_THERMSHDN_END_CLR_WIDTH 1 3091ff27651SAnish Kumar #define M98925_THERMSHDN_BGN_CLR_MASK (1<<0) 3101ff27651SAnish Kumar #define M98925_THERMSHDN_BGN_CLR_SHIFT 0 3111ff27651SAnish Kumar #define M98925_THERMSHDN_BGN_CLR_WIDTH 1 3121ff27651SAnish Kumar 3131ff27651SAnish Kumar /* MAX98925_R00F_IRQ_CLEAR1 */ 3141ff27651SAnish Kumar #define M98925_SPKCURNT_CLR_MASK (1<<5) 3151ff27651SAnish Kumar #define M98925_SPKCURNT_CLR_SHIFT 5 3161ff27651SAnish Kumar #define M98925_SPKCURNT_CLR_WIDTH 1 3171ff27651SAnish Kumar #define M98925_WATCHFAIL_CLR_MASK (1<<4) 3181ff27651SAnish Kumar #define M98925_WATCHFAIL_CLR_SHIFT 4 3191ff27651SAnish Kumar #define M98925_WATCHFAIL_CLR_WIDTH 1 3201ff27651SAnish Kumar #define M98925_ALCINFH_CLR_MASK (1<<3) 3211ff27651SAnish Kumar #define M98925_ALCINFH_CLR_SHIFT 3 3221ff27651SAnish Kumar #define M98925_ALCINFH_CLR_WIDTH 1 3231ff27651SAnish Kumar #define M98925_ALCACT_CLR_MASK (1<<2) 3241ff27651SAnish Kumar #define M98925_ALCACT_CLR_SHIFT 2 3251ff27651SAnish Kumar #define M98925_ALCACT_CLR_WIDTH 1 3261ff27651SAnish Kumar #define M98925_ALCMUT_CLR_MASK (1<<1) 3271ff27651SAnish Kumar #define M98925_ALCMUT_CLR_SHIFT 1 3281ff27651SAnish Kumar #define M98925_ALCMUT_CLR_WIDTH 1 3291ff27651SAnish Kumar #define M98925_ALCP_CLR_MASK (1<<0) 3301ff27651SAnish Kumar #define M98925_ALCP_CLR_SHIFT 0 3311ff27651SAnish Kumar #define M98925_ALCP_CLR_WIDTH 1 3321ff27651SAnish Kumar 3331ff27651SAnish Kumar /* MAX98925_R010_IRQ_CLEAR2 */ 3341ff27651SAnish Kumar #define M98925_SLOTOVRN_CLR_MASK (1<<6) 3351ff27651SAnish Kumar #define M98925_SLOTOVRN_CLR_SHIFT 6 3361ff27651SAnish Kumar #define M98925_SLOTOVRN_CLR_WIDTH 1 3371ff27651SAnish Kumar #define M98925_INVALSLOT_CLR_MASK (1<<5) 3381ff27651SAnish Kumar #define M98925_INVALSLOT_CLR_SHIFT 5 3391ff27651SAnish Kumar #define M98925_INVALSLOT_CLR_WIDTH 1 3401ff27651SAnish Kumar #define M98925_SLOTCNFLT_CLR_MASK (1<<4) 3411ff27651SAnish Kumar #define M98925_SLOTCNFLT_CLR_SHIFT 4 3421ff27651SAnish Kumar #define M98925_SLOTCNFLT_CLR_WIDTH 1 3431ff27651SAnish Kumar #define M98925_VBSTOVFL_CLR_MASK (1<<3) 3441ff27651SAnish Kumar #define M98925_VBSTOVFL_CLR_SHIFT 3 3451ff27651SAnish Kumar #define M98925_VBSTOVFL_CLR_WIDTH 1 3461ff27651SAnish Kumar #define M98925_VBATOVFL_CLR_MASK (1<<2) 3471ff27651SAnish Kumar #define M98925_VBATOVFL_CLR_SHIFT 2 3481ff27651SAnish Kumar #define M98925_VBATOVFL_CLR_WIDTH 1 3491ff27651SAnish Kumar #define M98925_IMONOVFL_CLR_MASK (1<<1) 3501ff27651SAnish Kumar #define M98925_IMONOVFL_CLR_SHIFT 1 3511ff27651SAnish Kumar #define M98925_IMONOVFL_CLR_WIDTH 1 3521ff27651SAnish Kumar #define M98925_VMONOVFL_CLR_MASK (1<<0) 3531ff27651SAnish Kumar #define M98925_VMONOVFL_CLR_SHIFT 0 3541ff27651SAnish Kumar #define M98925_VMONOVFL_CLR_WIDTH 1 3551ff27651SAnish Kumar 3561ff27651SAnish Kumar /* MAX98925_R011_MAP0 */ 3571ff27651SAnish Kumar #define M98925_ER_THERMWARN_EN_MASK (1<<7) 3581ff27651SAnish Kumar #define M98925_ER_THERMWARN_EN_SHIFT 7 3591ff27651SAnish Kumar #define M98925_ER_THERMWARN_EN_WIDTH 1 3601ff27651SAnish Kumar #define M98925_ER_THERMWARN_MAP_MASK (0x07<<4) 3611ff27651SAnish Kumar #define M98925_ER_THERMWARN_MAP_SHIFT 4 3621ff27651SAnish Kumar #define M98925_ER_THERMWARN_MAP_WIDTH 3 3631ff27651SAnish Kumar 3641ff27651SAnish Kumar /* MAX98925_R012_MAP1 */ 3651ff27651SAnish Kumar #define M98925_ER_ALCMUT_EN_MASK (1<<7) 3661ff27651SAnish Kumar #define M98925_ER_ALCMUT_EN_SHIFT 7 3671ff27651SAnish Kumar #define M98925_ER_ALCMUT_EN_WIDTH 1 3681ff27651SAnish Kumar #define M98925_ER_ALCMUT_MAP_MASK (0x07<<4) 3691ff27651SAnish Kumar #define M98925_ER_ALCMUT_MAP_SHIFT 4 3701ff27651SAnish Kumar #define M98925_ER_ALCMUT_MAP_WIDTH 3 3711ff27651SAnish Kumar #define M98925_ER_ALCP_EN_MASK (1<<3) 3721ff27651SAnish Kumar #define M98925_ER_ALCP_EN_SHIFT 3 3731ff27651SAnish Kumar #define M98925_ER_ALCP_EN_WIDTH 1 3741ff27651SAnish Kumar #define M98925_ER_ALCP_MAP_MASK (0x07<<0) 3751ff27651SAnish Kumar #define M98925_ER_ALCP_MAP_SHIFT 0 3761ff27651SAnish Kumar #define M98925_ER_ALCP_MAP_WIDTH 3 3771ff27651SAnish Kumar 3781ff27651SAnish Kumar /* MAX98925_R013_MAP2 */ 3791ff27651SAnish Kumar #define M98925_ER_ALCINFH_EN_MASK (1<<7) 3801ff27651SAnish Kumar #define M98925_ER_ALCINFH_EN_SHIFT 7 3811ff27651SAnish Kumar #define M98925_ER_ALCINFH_EN_WIDTH 1 3821ff27651SAnish Kumar #define M98925_ER_ALCINFH_MAP_MASK (0x07<<4) 3831ff27651SAnish Kumar #define M98925_ER_ALCINFH_MAP_SHIFT 4 3841ff27651SAnish Kumar #define M98925_ER_ALCINFH_MAP_WIDTH 3 3851ff27651SAnish Kumar #define M98925_ER_ALCACT_EN_MASK (1<<3) 3861ff27651SAnish Kumar #define M98925_ER_ALCACT_EN_SHIFT 3 3871ff27651SAnish Kumar #define M98925_ER_ALCACT_EN_WIDTH 1 3881ff27651SAnish Kumar #define M98925_ER_ALCACT_MAP_MASK (0x07<<0) 3891ff27651SAnish Kumar #define M98925_ER_ALCACT_MAP_SHIFT 0 3901ff27651SAnish Kumar #define M98925_ER_ALCACT_MAP_WIDTH 3 3911ff27651SAnish Kumar 3921ff27651SAnish Kumar /* MAX98925_R014_MAP3 */ 3931ff27651SAnish Kumar #define M98925_ER_SPKCURNT_EN_MASK (1<<7) 3941ff27651SAnish Kumar #define M98925_ER_SPKCURNT_EN_SHIFT 7 3951ff27651SAnish Kumar #define M98925_ER_SPKCURNT_EN_WIDTH 1 3961ff27651SAnish Kumar #define M98925_ER_SPKCURNT_MAP_MASK (0x07<<4) 3971ff27651SAnish Kumar #define M98925_ER_SPKCURNT_MAP_SHIFT 4 3981ff27651SAnish Kumar #define M98925_ER_SPKCURNT_MAP_WIDTH 3 3991ff27651SAnish Kumar 4001ff27651SAnish Kumar /* MAX98925_R015_MAP4 */ 4011ff27651SAnish Kumar /* RESERVED */ 4021ff27651SAnish Kumar 4031ff27651SAnish Kumar /* MAX98925_R016_MAP5 */ 4041ff27651SAnish Kumar #define M98925_ER_IMONOVFL_EN_MASK (1<<7) 4051ff27651SAnish Kumar #define M98925_ER_IMONOVFL_EN_SHIFT 7 4061ff27651SAnish Kumar #define M98925_ER_IMONOVFL_EN_WIDTH 1 4071ff27651SAnish Kumar #define M98925_ER_IMONOVFL_MAP_MASK (0x07<<4) 4081ff27651SAnish Kumar #define M98925_ER_IMONOVFL_MAP_SHIFT 4 4091ff27651SAnish Kumar #define M98925_ER_IMONOVFL_MAP_WIDTH 3 4101ff27651SAnish Kumar #define M98925_ER_VMONOVFL_EN_MASK (1<<3) 4111ff27651SAnish Kumar #define M98925_ER_VMONOVFL_EN_SHIFT 3 4121ff27651SAnish Kumar #define M98925_ER_VMONOVFL_EN_WIDTH 1 4131ff27651SAnish Kumar #define M98925_ER_VMONOVFL_MAP_MASK (0x07<<0) 4141ff27651SAnish Kumar #define M98925_ER_VMONOVFL_MAP_SHIFT 0 4151ff27651SAnish Kumar #define M98925_ER_VMONOVFL_MAP_WIDTH 3 4161ff27651SAnish Kumar 4171ff27651SAnish Kumar /* MAX98925_R017_MAP6 */ 4181ff27651SAnish Kumar #define M98925_ER_VBSTOVFL_EN_MASK (1<<7) 4191ff27651SAnish Kumar #define M98925_ER_VBSTOVFL_EN_SHIFT 7 4201ff27651SAnish Kumar #define M98925_ER_VBSTOVFL_EN_WIDTH 1 4211ff27651SAnish Kumar #define M98925_ER_VBSTOVFL_MAP_MASK (0x07<<4) 4221ff27651SAnish Kumar #define M98925_ER_VBSTOVFL_MAP_SHIFT 4 4231ff27651SAnish Kumar #define M98925_ER_VBSTOVFL_MAP_WIDTH 3 4241ff27651SAnish Kumar #define M98925_ER_VBATOVFL_EN_MASK (1<<3) 4251ff27651SAnish Kumar #define M98925_ER_VBATOVFL_EN_SHIFT 3 4261ff27651SAnish Kumar #define M98925_ER_VBATOVFL_EN_WIDTH 1 4271ff27651SAnish Kumar #define M98925_ER_VBATOVFL_MAP_MASK (0x07<<0) 4281ff27651SAnish Kumar #define M98925_ER_VBATOVFL_MAP_SHIFT 0 4291ff27651SAnish Kumar #define M98925_ER_VBATOVFL_MAP_WIDTH 3 4301ff27651SAnish Kumar 4311ff27651SAnish Kumar /* MAX98925_R018_MAP7 */ 4321ff27651SAnish Kumar #define M98925_ER_INVALSLOT_EN_MASK (1<<7) 4331ff27651SAnish Kumar #define M98925_ER_INVALSLOT_EN_SHIFT 7 4341ff27651SAnish Kumar #define M98925_ER_INVALSLOT_EN_WIDTH 1 4351ff27651SAnish Kumar #define M98925_ER_INVALSLOT_MAP_MASK (0x07<<4) 4361ff27651SAnish Kumar #define M98925_ER_INVALSLOT_MAP_SHIFT 4 4371ff27651SAnish Kumar #define M98925_ER_INVALSLOT_MAP_WIDTH 3 4381ff27651SAnish Kumar #define M98925_ER_SLOTCNFLT_EN_MASK (1<<3) 4391ff27651SAnish Kumar #define M98925_ER_SLOTCNFLT_EN_SHIFT 3 4401ff27651SAnish Kumar #define M98925_ER_SLOTCNFLT_EN_WIDTH 1 4411ff27651SAnish Kumar #define M98925_ER_SLOTCNFLT_MAP_MASK (0x07<<0) 4421ff27651SAnish Kumar #define M98925_ER_SLOTCNFLT_MAP_SHIFT 0 4431ff27651SAnish Kumar #define M98925_ER_SLOTCNFLT_MAP_WIDTH 3 4441ff27651SAnish Kumar 4451ff27651SAnish Kumar /* MAX98925_R019_MAP8 */ 4461ff27651SAnish Kumar #define M98925_ER_SLOTOVRN_EN_MASK (1<<3) 4471ff27651SAnish Kumar #define M98925_ER_SLOTOVRN_EN_SHIFT 3 4481ff27651SAnish Kumar #define M98925_ER_SLOTOVRN_EN_WIDTH 1 4491ff27651SAnish Kumar #define M98925_ER_SLOTOVRN_MAP_MASK (0x07<<0) 4501ff27651SAnish Kumar #define M98925_ER_SLOTOVRN_MAP_SHIFT 0 4511ff27651SAnish Kumar #define M98925_ER_SLOTOVRN_MAP_WIDTH 3 4521ff27651SAnish Kumar 4531ff27651SAnish Kumar /* MAX98925_R01A_DAI_CLK_MODE1 */ 4541ff27651SAnish Kumar #define M98925_DAI_CLK_SOURCE_MASK (1<<6) 4551ff27651SAnish Kumar #define M98925_DAI_CLK_SOURCE_SHIFT 6 4561ff27651SAnish Kumar #define M98925_DAI_CLK_SOURCE_WIDTH 1 4571ff27651SAnish Kumar #define M98925_MDLL_MULT_MASK (0x0F<<0) 4581ff27651SAnish Kumar #define M98925_MDLL_MULT_SHIFT 0 4591ff27651SAnish Kumar #define M98925_MDLL_MULT_WIDTH 4 4601ff27651SAnish Kumar 4611ff27651SAnish Kumar #define M98925_MDLL_MULT_MCLKx8 6 4621ff27651SAnish Kumar #define M98925_MDLL_MULT_MCLKx16 8 4631ff27651SAnish Kumar 4641ff27651SAnish Kumar /* MAX98925_R01B_DAI_CLK_MODE2 */ 4651ff27651SAnish Kumar #define M98925_DAI_SR_MASK (0x0F<<4) 4661ff27651SAnish Kumar #define M98925_DAI_SR_SHIFT 4 4671ff27651SAnish Kumar #define M98925_DAI_SR_WIDTH 4 4681ff27651SAnish Kumar #define M98925_DAI_MAS_MASK (1<<3) 4691ff27651SAnish Kumar #define M98925_DAI_MAS_SHIFT 3 4701ff27651SAnish Kumar #define M98925_DAI_MAS_WIDTH 1 4711ff27651SAnish Kumar #define M98925_DAI_BSEL_MASK (0x07<<0) 4721ff27651SAnish Kumar #define M98925_DAI_BSEL_SHIFT 0 4731ff27651SAnish Kumar #define M98925_DAI_BSEL_WIDTH 3 4741ff27651SAnish Kumar 4751ff27651SAnish Kumar #define M98925_DAI_BSEL_32 (0 << M98925_DAI_BSEL_SHIFT) 4761ff27651SAnish Kumar #define M98925_DAI_BSEL_48 (1 << M98925_DAI_BSEL_SHIFT) 4771ff27651SAnish Kumar #define M98925_DAI_BSEL_64 (2 << M98925_DAI_BSEL_SHIFT) 4781ff27651SAnish Kumar #define M98925_DAI_BSEL_256 (6 << M98925_DAI_BSEL_SHIFT) 4791ff27651SAnish Kumar 4801ff27651SAnish Kumar /* MAX98925_R01C_DAI_CLK_DIV_M_MSBS */ 4811ff27651SAnish Kumar #define M98925_DAI_M_MSBS_MASK (0xFF<<0) 4821ff27651SAnish Kumar #define M98925_DAI_M_MSBS_SHIFT 0 4831ff27651SAnish Kumar #define M98925_DAI_M_MSBS_WIDTH 8 4841ff27651SAnish Kumar 4851ff27651SAnish Kumar /* MAX98925_R01D_DAI_CLK_DIV_M_LSBS */ 4861ff27651SAnish Kumar #define M98925_DAI_M_LSBS_MASK (0xFF<<0) 4871ff27651SAnish Kumar #define M98925_DAI_M_LSBS_SHIFT 0 4881ff27651SAnish Kumar #define M98925_DAI_M_LSBS_WIDTH 8 4891ff27651SAnish Kumar 4901ff27651SAnish Kumar /* MAX98925_R01E_DAI_CLK_DIV_N_MSBS */ 4911ff27651SAnish Kumar #define M98925_DAI_N_MSBS_MASK (0x7F<<0) 4921ff27651SAnish Kumar #define M98925_DAI_N_MSBS_SHIFT 0 4931ff27651SAnish Kumar #define M98925_DAI_N_MSBS_WIDTH 7 4941ff27651SAnish Kumar 4951ff27651SAnish Kumar /* MAX98925_R01F_DAI_CLK_DIV_N_LSBS */ 4961ff27651SAnish Kumar #define M98925_DAI_N_LSBS_MASK (0xFF<<0) 4971ff27651SAnish Kumar #define M98925_DAI_N_LSBS_SHIFT 0 4981ff27651SAnish Kumar #define M98925_DAI_N_LSBS_WIDTH 8 4991ff27651SAnish Kumar 5001ff27651SAnish Kumar /* MAX98925_R020_FORMAT */ 5011ff27651SAnish Kumar #define M98925_DAI_CHANSZ_MASK (0x03<<6) 5021ff27651SAnish Kumar #define M98925_DAI_CHANSZ_SHIFT 6 5031ff27651SAnish Kumar #define M98925_DAI_CHANSZ_WIDTH 2 5041ff27651SAnish Kumar #define M98925_DAI_EXTBCLK_HIZ_MASK (1<<4) 5051ff27651SAnish Kumar #define M98925_DAI_EXTBCLK_HIZ_SHIFT 4 5061ff27651SAnish Kumar #define M98925_DAI_EXTBCLK_HIZ_WIDTH 1 5071ff27651SAnish Kumar #define M98925_DAI_WCI_MASK (1<<3) 5081ff27651SAnish Kumar #define M98925_DAI_WCI_SHIFT 3 5091ff27651SAnish Kumar #define M98925_DAI_WCI_WIDTH 1 5101ff27651SAnish Kumar #define M98925_DAI_BCI_MASK (1<<2) 5111ff27651SAnish Kumar #define M98925_DAI_BCI_SHIFT 2 5121ff27651SAnish Kumar #define M98925_DAI_BCI_WIDTH 1 5131ff27651SAnish Kumar #define M98925_DAI_DLY_MASK (1<<1) 5141ff27651SAnish Kumar #define M98925_DAI_DLY_SHIFT 1 5151ff27651SAnish Kumar #define M98925_DAI_DLY_WIDTH 1 5161ff27651SAnish Kumar #define M98925_DAI_TDM_MASK (1<<0) 5171ff27651SAnish Kumar #define M98925_DAI_TDM_SHIFT 0 5181ff27651SAnish Kumar #define M98925_DAI_TDM_WIDTH 1 5191ff27651SAnish Kumar 5201ff27651SAnish Kumar #define M98925_DAI_CHANSZ_16 (1 << M98925_DAI_CHANSZ_SHIFT) 5211ff27651SAnish Kumar #define M98925_DAI_CHANSZ_24 (2 << M98925_DAI_CHANSZ_SHIFT) 5221ff27651SAnish Kumar #define M98925_DAI_CHANSZ_32 (3 << M98925_DAI_CHANSZ_SHIFT) 5231ff27651SAnish Kumar 5241ff27651SAnish Kumar /* MAX98925_R021_TDM_SLOT_SELECT */ 5251ff27651SAnish Kumar #define M98925_DAI_DO_EN_MASK (1<<7) 5261ff27651SAnish Kumar #define M98925_DAI_DO_EN_SHIFT 7 5271ff27651SAnish Kumar #define M98925_DAI_DO_EN_WIDTH 1 5281ff27651SAnish Kumar #define M98925_DAI_DIN_EN_MASK (1<<6) 5291ff27651SAnish Kumar #define M98925_DAI_DIN_EN_SHIFT 6 5301ff27651SAnish Kumar #define M98925_DAI_DIN_EN_WIDTH 1 5311ff27651SAnish Kumar #define M98925_DAI_INR_SOURCE_MASK (0x07<<3) 5321ff27651SAnish Kumar #define M98925_DAI_INR_SOURCE_SHIFT 3 5331ff27651SAnish Kumar #define M98925_DAI_INR_SOURCE_WIDTH 3 5341ff27651SAnish Kumar #define M98925_DAI_INL_SOURCE_MASK (0x07<<0) 5351ff27651SAnish Kumar #define M98925_DAI_INL_SOURCE_SHIFT 0 5361ff27651SAnish Kumar #define M98925_DAI_INL_SOURCE_WIDTH 3 5371ff27651SAnish Kumar 5381ff27651SAnish Kumar /* MAX98925_R022_DOUT_CFG_VMON */ 5391ff27651SAnish Kumar #define M98925_DAI_VMON_EN_MASK (1<<5) 5401ff27651SAnish Kumar #define M98925_DAI_VMON_EN_SHIFT 5 5411ff27651SAnish Kumar #define M98925_DAI_VMON_EN_WIDTH 1 5421ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_MASK (0x1F<<0) 5431ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_SHIFT 0 5441ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_WIDTH 5 5451ff27651SAnish Kumar 5461ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_00_01 (0 << M98925_DAI_VMON_SLOT_SHIFT) 5471ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_01_02 (1 << M98925_DAI_VMON_SLOT_SHIFT) 5481ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_02_03 (2 << M98925_DAI_VMON_SLOT_SHIFT) 5491ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_03_04 (3 << M98925_DAI_VMON_SLOT_SHIFT) 5501ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_04_05 (4 << M98925_DAI_VMON_SLOT_SHIFT) 5511ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_05_06 (5 << M98925_DAI_VMON_SLOT_SHIFT) 5521ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_06_07 (6 << M98925_DAI_VMON_SLOT_SHIFT) 5531ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_07_08 (7 << M98925_DAI_VMON_SLOT_SHIFT) 5541ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_08_09 (8 << M98925_DAI_VMON_SLOT_SHIFT) 5551ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_09_0A (9 << M98925_DAI_VMON_SLOT_SHIFT) 5561ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_0A_0B (10 << M98925_DAI_VMON_SLOT_SHIFT) 5571ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_0B_0C (11 << M98925_DAI_VMON_SLOT_SHIFT) 5581ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_0C_0D (12 << M98925_DAI_VMON_SLOT_SHIFT) 5591ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_0D_0E (13 << M98925_DAI_VMON_SLOT_SHIFT) 5601ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_0E_0F (14 << M98925_DAI_VMON_SLOT_SHIFT) 5611ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_0F_10 (15 << M98925_DAI_VMON_SLOT_SHIFT) 5621ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_10_11 (16 << M98925_DAI_VMON_SLOT_SHIFT) 5631ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_11_12 (17 << M98925_DAI_VMON_SLOT_SHIFT) 5641ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_12_13 (18 << M98925_DAI_VMON_SLOT_SHIFT) 5651ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_13_14 (19 << M98925_DAI_VMON_SLOT_SHIFT) 5661ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_14_15 (20 << M98925_DAI_VMON_SLOT_SHIFT) 5671ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_15_16 (21 << M98925_DAI_VMON_SLOT_SHIFT) 5681ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_16_17 (22 << M98925_DAI_VMON_SLOT_SHIFT) 5691ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_17_18 (23 << M98925_DAI_VMON_SLOT_SHIFT) 5701ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_18_19 (24 << M98925_DAI_VMON_SLOT_SHIFT) 5711ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_19_1A (25 << M98925_DAI_VMON_SLOT_SHIFT) 5721ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_1A_1B (26 << M98925_DAI_VMON_SLOT_SHIFT) 5731ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_1B_1C (27 << M98925_DAI_VMON_SLOT_SHIFT) 5741ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_1C_1D (28 << M98925_DAI_VMON_SLOT_SHIFT) 5751ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_1D_1E (29 << M98925_DAI_VMON_SLOT_SHIFT) 5761ff27651SAnish Kumar #define M98925_DAI_VMON_SLOT_1E_1F (30 << M98925_DAI_VMON_SLOT_SHIFT) 5771ff27651SAnish Kumar 5781ff27651SAnish Kumar /* MAX98925_R023_DOUT_CFG_IMON */ 5791ff27651SAnish Kumar #define M98925_DAI_IMON_EN_MASK (1<<5) 5801ff27651SAnish Kumar #define M98925_DAI_IMON_EN_SHIFT 5 5811ff27651SAnish Kumar #define M98925_DAI_IMON_EN_WIDTH 1 5821ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_MASK (0x1F<<0) 5831ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_SHIFT 0 5841ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_WIDTH 5 5851ff27651SAnish Kumar 5861ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_00_01 (0 << M98925_DAI_IMON_SLOT_SHIFT) 5871ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_01_02 (1 << M98925_DAI_IMON_SLOT_SHIFT) 5881ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_02_03 (2 << M98925_DAI_IMON_SLOT_SHIFT) 5891ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_03_04 (3 << M98925_DAI_IMON_SLOT_SHIFT) 5901ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_04_05 (4 << M98925_DAI_IMON_SLOT_SHIFT) 5911ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_05_06 (5 << M98925_DAI_IMON_SLOT_SHIFT) 5921ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_06_07 (6 << M98925_DAI_IMON_SLOT_SHIFT) 5931ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_07_08 (7 << M98925_DAI_IMON_SLOT_SHIFT) 5941ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_08_09 (8 << M98925_DAI_IMON_SLOT_SHIFT) 5951ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_09_0A (9 << M98925_DAI_IMON_SLOT_SHIFT) 5961ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_0A_0B (10 << M98925_DAI_IMON_SLOT_SHIFT) 5971ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_0B_0C (11 << M98925_DAI_IMON_SLOT_SHIFT) 5981ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_0C_0D (12 << M98925_DAI_IMON_SLOT_SHIFT) 5991ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_0D_0E (13 << M98925_DAI_IMON_SLOT_SHIFT) 6001ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_0E_0F (14 << M98925_DAI_IMON_SLOT_SHIFT) 6011ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_0F_10 (15 << M98925_DAI_IMON_SLOT_SHIFT) 6021ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_10_11 (16 << M98925_DAI_IMON_SLOT_SHIFT) 6031ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_11_12 (17 << M98925_DAI_IMON_SLOT_SHIFT) 6041ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_12_13 (18 << M98925_DAI_IMON_SLOT_SHIFT) 6051ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_13_14 (19 << M98925_DAI_IMON_SLOT_SHIFT) 6061ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_14_15 (20 << M98925_DAI_IMON_SLOT_SHIFT) 6071ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_15_16 (21 << M98925_DAI_IMON_SLOT_SHIFT) 6081ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_16_17 (22 << M98925_DAI_IMON_SLOT_SHIFT) 6091ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_17_18 (23 << M98925_DAI_IMON_SLOT_SHIFT) 6101ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_18_19 (24 << M98925_DAI_IMON_SLOT_SHIFT) 6111ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_19_1A (25 << M98925_DAI_IMON_SLOT_SHIFT) 6121ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_1A_1B (26 << M98925_DAI_IMON_SLOT_SHIFT) 6131ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_1B_1C (27 << M98925_DAI_IMON_SLOT_SHIFT) 6141ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_1C_1D (28 << M98925_DAI_IMON_SLOT_SHIFT) 6151ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_1D_1E (29 << M98925_DAI_IMON_SLOT_SHIFT) 6161ff27651SAnish Kumar #define M98925_DAI_IMON_SLOT_1E_1F (30 << M98925_DAI_IMON_SLOT_SHIFT) 6171ff27651SAnish Kumar 6181ff27651SAnish Kumar /* MAX98925_R024_DOUT_CFG_VBAT */ 6191ff27651SAnish Kumar #define M98925_DAI_VBAT_EN_MASK (1<<5) 6201ff27651SAnish Kumar #define M98925_DAI_VBAT_EN_SHIFT 5 6211ff27651SAnish Kumar #define M98925_DAI_VBAT_EN_WIDTH 1 6221ff27651SAnish Kumar #define M98925_DAI_VBAT_SLOT_MASK (0x1F<<0) 6231ff27651SAnish Kumar #define M98925_DAI_VBAT_SLOT_SHIFT 0 6241ff27651SAnish Kumar #define M98925_DAI_VBAT_SLOT_WIDTH 5 6251ff27651SAnish Kumar 6261ff27651SAnish Kumar /* MAX98925_R025_DOUT_CFG_VBST */ 6271ff27651SAnish Kumar #define M98925_DAI_VBST_EN_MASK (1<<5) 6281ff27651SAnish Kumar #define M98925_DAI_VBST_EN_SHIFT 5 6291ff27651SAnish Kumar #define M98925_DAI_VBST_EN_WIDTH 1 6301ff27651SAnish Kumar #define M98925_DAI_VBST_SLOT_MASK (0x1F<<0) 6311ff27651SAnish Kumar #define M98925_DAI_VBST_SLOT_SHIFT 0 6321ff27651SAnish Kumar #define M98925_DAI_VBST_SLOT_WIDTH 5 6331ff27651SAnish Kumar 6341ff27651SAnish Kumar /* MAX98925_R026_DOUT_CFG_FLAG */ 6351ff27651SAnish Kumar #define M98925_DAI_FLAG_EN_MASK (1<<5) 6361ff27651SAnish Kumar #define M98925_DAI_FLAG_EN_SHIFT 5 6371ff27651SAnish Kumar #define M98925_DAI_FLAG_EN_WIDTH 1 6381ff27651SAnish Kumar #define M98925_DAI_FLAG_SLOT_MASK (0x1F<<0) 6391ff27651SAnish Kumar #define M98925_DAI_FLAG_SLOT_SHIFT 0 6401ff27651SAnish Kumar #define M98925_DAI_FLAG_SLOT_WIDTH 5 6411ff27651SAnish Kumar 6421ff27651SAnish Kumar /* MAX98925_R027_DOUT_HIZ_CFG1 */ 6431ff27651SAnish Kumar #define M98925_DAI_SLOT_HIZ_CFG1_MASK (0xFF<<0) 6441ff27651SAnish Kumar #define M98925_DAI_SLOT_HIZ_CFG1_SHIFT 0 6451ff27651SAnish Kumar #define M98925_DAI_SLOT_HIZ_CFG1_WIDTH 8 6461ff27651SAnish Kumar 6471ff27651SAnish Kumar /* MAX98925_R028_DOUT_HIZ_CFG2 */ 6481ff27651SAnish Kumar #define M98925_DAI_SLOT_HIZ_CFG2_MASK (0xFF<<0) 6491ff27651SAnish Kumar #define M98925_DAI_SLOT_HIZ_CFG2_SHIFT 0 6501ff27651SAnish Kumar #define M98925_DAI_SLOT_HIZ_CFG2_WIDTH 8 6511ff27651SAnish Kumar 6521ff27651SAnish Kumar /* MAX98925_R029_DOUT_HIZ_CFG3 */ 6531ff27651SAnish Kumar #define M98925_DAI_SLOT_HIZ_CFG3_MASK (0xFF<<0) 6541ff27651SAnish Kumar #define M98925_DAI_SLOT_HIZ_CFG3_SHIFT 0 6551ff27651SAnish Kumar #define M98925_DAI_SLOT_HIZ_CFG3_WIDTH 8 6561ff27651SAnish Kumar 6571ff27651SAnish Kumar /* MAX98925_R02A_DOUT_HIZ_CFG4 */ 6581ff27651SAnish Kumar #define M98925_DAI_SLOT_HIZ_CFG4_MASK (0xFF<<0) 6591ff27651SAnish Kumar #define M98925_DAI_SLOT_HIZ_CFG4_SHIFT 0 6601ff27651SAnish Kumar #define M98925_DAI_SLOT_HIZ_CFG4_WIDTH 8 6611ff27651SAnish Kumar 6621ff27651SAnish Kumar /* MAX98925_R02B_DOUT_DRV_STRENGTH */ 6631ff27651SAnish Kumar #define M98925_DAI_OUT_DRIVE_MASK (0x03<<0) 6641ff27651SAnish Kumar #define M98925_DAI_OUT_DRIVE_SHIFT 0 6651ff27651SAnish Kumar #define M98925_DAI_OUT_DRIVE_WIDTH 2 6661ff27651SAnish Kumar 6671ff27651SAnish Kumar /* MAX98925_R02C_FILTERS */ 6681ff27651SAnish Kumar #define M98925_ADC_DITHER_EN_MASK (1<<7) 6691ff27651SAnish Kumar #define M98925_ADC_DITHER_EN_SHIFT 7 6701ff27651SAnish Kumar #define M98925_ADC_DITHER_EN_WIDTH 1 6711ff27651SAnish Kumar #define M98925_IV_DCB_EN_MASK (1<<6) 6721ff27651SAnish Kumar #define M98925_IV_DCB_EN_SHIFT 6 6731ff27651SAnish Kumar #define M98925_IV_DCB_EN_WIDTH 1 6741ff27651SAnish Kumar #define M98925_DAC_DITHER_EN_MASK (1<<4) 6751ff27651SAnish Kumar #define M98925_DAC_DITHER_EN_SHIFT 4 6761ff27651SAnish Kumar #define M98925_DAC_DITHER_EN_WIDTH 1 6771ff27651SAnish Kumar #define M98925_DAC_FILTER_MODE_MASK (1<<3) 6781ff27651SAnish Kumar #define M98925_DAC_FILTER_MODE_SHIFT 3 6791ff27651SAnish Kumar #define M98925_DAC_FILTER_MODE_WIDTH 1 6801ff27651SAnish Kumar #define M98925_DAC_HPF_MASK (0x07<<0) 6811ff27651SAnish Kumar #define M98925_DAC_HPF_SHIFT 0 6821ff27651SAnish Kumar #define M98925_DAC_HPF_WIDTH 3 6831ff27651SAnish Kumar #define M98925_DAC_HPF_DISABLE (0 << M98925_DAC_HPF_SHIFT) 6841ff27651SAnish Kumar #define M98925_DAC_HPF_DC_BLOCK (1 << M98925_DAC_HPF_SHIFT) 6851ff27651SAnish Kumar #define M98925_DAC_HPF_EN_100 (2 << M98925_DAC_HPF_SHIFT) 6861ff27651SAnish Kumar #define M98925_DAC_HPF_EN_200 (3 << M98925_DAC_HPF_SHIFT) 6871ff27651SAnish Kumar #define M98925_DAC_HPF_EN_400 (4 << M98925_DAC_HPF_SHIFT) 6881ff27651SAnish Kumar #define M98925_DAC_HPF_EN_800 (5 << M98925_DAC_HPF_SHIFT) 6891ff27651SAnish Kumar 6901ff27651SAnish Kumar /* MAX98925_R02D_GAIN */ 6911ff27651SAnish Kumar #define M98925_DAC_IN_SEL_MASK (0x03<<5) 6921ff27651SAnish Kumar #define M98925_DAC_IN_SEL_SHIFT 5 6931ff27651SAnish Kumar #define M98925_DAC_IN_SEL_WIDTH 2 6941ff27651SAnish Kumar #define M98925_SPK_GAIN_MASK (0x1F<<0) 6951ff27651SAnish Kumar #define M98925_SPK_GAIN_SHIFT 0 6961ff27651SAnish Kumar #define M98925_SPK_GAIN_WIDTH 5 6971ff27651SAnish Kumar 6981ff27651SAnish Kumar #define M98925_DAC_IN_SEL_LEFT_DAI (0 << M98925_DAC_IN_SEL_SHIFT) 6991ff27651SAnish Kumar #define M98925_DAC_IN_SEL_RIGHT_DAI (1 << M98925_DAC_IN_SEL_SHIFT) 7001ff27651SAnish Kumar #define M98925_DAC_IN_SEL_SUMMED_DAI (2 << M98925_DAC_IN_SEL_SHIFT) 7011ff27651SAnish Kumar #define M98925_DAC_IN_SEL_DIV2_SUMMED_DAI (3 << M98925_DAC_IN_SEL_SHIFT) 7021ff27651SAnish Kumar 7031ff27651SAnish Kumar /* MAX98925_R02E_GAIN_RAMPING */ 7041ff27651SAnish Kumar #define M98925_SPK_RMP_EN_MASK (1<<1) 7051ff27651SAnish Kumar #define M98925_SPK_RMP_EN_SHIFT 1 7061ff27651SAnish Kumar #define M98925_SPK_RMP_EN_WIDTH 1 7071ff27651SAnish Kumar #define M98925_SPK_ZCD_EN_MASK (1<<0) 7081ff27651SAnish Kumar #define M98925_SPK_ZCD_EN_SHIFT 0 7091ff27651SAnish Kumar #define M98925_SPK_ZCD_EN_WIDTH 1 7101ff27651SAnish Kumar 7111ff27651SAnish Kumar /* MAX98925_R02F_SPK_AMP */ 7121ff27651SAnish Kumar #define M98925_SPK_MODE_MASK (1<<0) 7131ff27651SAnish Kumar #define M98925_SPK_MODE_SHIFT 0 7141ff27651SAnish Kumar #define M98925_SPK_MODE_WIDTH 1 7151ff27651SAnish Kumar 7161ff27651SAnish Kumar /* MAX98925_R030_THRESHOLD */ 7171ff27651SAnish Kumar #define M98925_ALC_EN_MASK (1<<5) 7181ff27651SAnish Kumar #define M98925_ALC_EN_SHIFT 5 7191ff27651SAnish Kumar #define M98925_ALC_EN_WIDTH 1 7201ff27651SAnish Kumar #define M98925_ALC_TH_MASK (0x1F<<0) 7211ff27651SAnish Kumar #define M98925_ALC_TH_SHIFT 0 7221ff27651SAnish Kumar #define M98925_ALC_TH_WIDTH 5 7231ff27651SAnish Kumar 7241ff27651SAnish Kumar /* MAX98925_R031_ALC_ATTACK */ 7251ff27651SAnish Kumar #define M98925_ALC_ATK_STEP_MASK (0x0F<<4) 7261ff27651SAnish Kumar #define M98925_ALC_ATK_STEP_SHIFT 4 7271ff27651SAnish Kumar #define M98925_ALC_ATK_STEP_WIDTH 4 7281ff27651SAnish Kumar #define M98925_ALC_ATK_RATE_MASK (0x7<<0) 7291ff27651SAnish Kumar #define M98925_ALC_ATK_RATE_SHIFT 0 7301ff27651SAnish Kumar #define M98925_ALC_ATK_RATE_WIDTH 3 7311ff27651SAnish Kumar 7321ff27651SAnish Kumar /* MAX98925_R032_ALC_ATTEN_RLS */ 7331ff27651SAnish Kumar #define M98925_ALC_MAX_ATTEN_MASK (0x0F<<4) 7341ff27651SAnish Kumar #define M98925_ALC_MAX_ATTEN_SHIFT 4 7351ff27651SAnish Kumar #define M98925_ALC_MAX_ATTEN_WIDTH 4 7361ff27651SAnish Kumar #define M98925_ALC_RLS_RATE_MASK (0x7<<0) 7371ff27651SAnish Kumar #define M98925_ALC_RLS_RATE_SHIFT 0 7381ff27651SAnish Kumar #define M98925_ALC_RLS_RATE_WIDTH 3 7391ff27651SAnish Kumar 7401ff27651SAnish Kumar /* MAX98925_R033_ALC_HOLD_RLS */ 7411ff27651SAnish Kumar #define M98925_ALC_RLS_TGR_MASK (1<<0) 7421ff27651SAnish Kumar #define M98925_ALC_RLS_TGR_SHIFT 0 7431ff27651SAnish Kumar #define M98925_ALC_RLS_TGR_WIDTH 1 7441ff27651SAnish Kumar 7451ff27651SAnish Kumar /* MAX98925_R034_ALC_CONFIGURATION */ 7461ff27651SAnish Kumar #define M98925_ALC_MUTE_EN_MASK (1<<7) 7471ff27651SAnish Kumar #define M98925_ALC_MUTE_EN_SHIFT 7 7481ff27651SAnish Kumar #define M98925_ALC_MUTE_EN_WIDTH 1 7491ff27651SAnish Kumar #define M98925_ALC_MUTE_DLY_MASK (0x07<<4) 7501ff27651SAnish Kumar #define M98925_ALC_MUTE_DLY_SHIFT 4 7511ff27651SAnish Kumar #define M98925_ALC_MUTE_DLY_WIDTH 3 7521ff27651SAnish Kumar #define M98925_ALC_RLS_DBT_MASK (0x07<<0) 7531ff27651SAnish Kumar #define M98925_ALC_RLS_DBT_SHIFT 0 7541ff27651SAnish Kumar #define M98925_ALC_RLS_DBT_WIDTH 3 7551ff27651SAnish Kumar 7561ff27651SAnish Kumar /* MAX98925_R035_BOOST_CONVERTER */ 7571ff27651SAnish Kumar #define M98925_BST_SYNC_MASK (1<<7) 7581ff27651SAnish Kumar #define M98925_BST_SYNC_SHIFT 7 7591ff27651SAnish Kumar #define M98925_BST_SYNC_WIDTH 1 7601ff27651SAnish Kumar #define M98925_BST_PHASE_MASK (0x03<<4) 7611ff27651SAnish Kumar #define M98925_BST_PHASE_SHIFT 4 7621ff27651SAnish Kumar #define M98925_BST_PHASE_WIDTH 2 7631ff27651SAnish Kumar #define M98925_BST_SKIP_MODE_MASK (0x03<<0) 7641ff27651SAnish Kumar #define M98925_BST_SKIP_MODE_SHIFT 0 7651ff27651SAnish Kumar #define M98925_BST_SKIP_MODE_WIDTH 2 7661ff27651SAnish Kumar 7671ff27651SAnish Kumar /* MAX98925_R036_BLOCK_ENABLE */ 7681ff27651SAnish Kumar #define M98925_BST_EN_MASK (1<<7) 7691ff27651SAnish Kumar #define M98925_BST_EN_SHIFT 7 7701ff27651SAnish Kumar #define M98925_BST_EN_WIDTH 1 7711ff27651SAnish Kumar #define M98925_WATCH_EN_MASK (1<<6) 7721ff27651SAnish Kumar #define M98925_WATCH_EN_SHIFT 6 7731ff27651SAnish Kumar #define M98925_WATCH_EN_WIDTH 1 7741ff27651SAnish Kumar #define M98925_CLKMON_EN_MASK (1<<5) 7751ff27651SAnish Kumar #define M98925_CLKMON_EN_SHIFT 5 7761ff27651SAnish Kumar #define M98925_CLKMON_EN_WIDTH 1 7771ff27651SAnish Kumar #define M98925_SPK_EN_MASK (1<<4) 7781ff27651SAnish Kumar #define M98925_SPK_EN_SHIFT 4 7791ff27651SAnish Kumar #define M98925_SPK_EN_WIDTH 1 7801ff27651SAnish Kumar #define M98925_ADC_VBST_EN_MASK (1<<3) 7811ff27651SAnish Kumar #define M98925_ADC_VBST_EN_SHIFT 3 7821ff27651SAnish Kumar #define M98925_ADC_VBST_EN_WIDTH 1 7831ff27651SAnish Kumar #define M98925_ADC_VBAT_EN_MASK (1<<2) 7841ff27651SAnish Kumar #define M98925_ADC_VBAT_EN_SHIFT 2 7851ff27651SAnish Kumar #define M98925_ADC_VBAT_EN_WIDTH 1 7861ff27651SAnish Kumar #define M98925_ADC_IMON_EN_MASK (1<<1) 7871ff27651SAnish Kumar #define M98925_ADC_IMON_EN_SHIFT 1 7881ff27651SAnish Kumar #define M98925_ADC_IMON_EN_WIDTH 1 7891ff27651SAnish Kumar #define M98925_ADC_VMON_EN_MASK (1<<0) 7901ff27651SAnish Kumar #define M98925_ADC_VMON_EN_SHIFT 0 7911ff27651SAnish Kumar #define M98925_ADC_VMON_EN_WIDTH 1 7921ff27651SAnish Kumar 7931ff27651SAnish Kumar /* MAX98925_R037_CONFIGURATION */ 7941ff27651SAnish Kumar #define M98925_BST_VOUT_MASK (0x0F<<4) 7951ff27651SAnish Kumar #define M98925_BST_VOUT_SHIFT 4 7961ff27651SAnish Kumar #define M98925_BST_VOUT_WIDTH 4 7971ff27651SAnish Kumar #define M98925_THERMWARN_LEVEL_MASK (0x03<<2) 7981ff27651SAnish Kumar #define M98925_THERMWARN_LEVEL_SHIFT 2 7991ff27651SAnish Kumar #define M98925_THERMWARN_LEVEL_WIDTH 2 8001ff27651SAnish Kumar #define M98925_WATCH_TIME_MASK (0x03<<0) 8011ff27651SAnish Kumar #define M98925_WATCH_TIME_SHIFT 0 8021ff27651SAnish Kumar #define M98925_WATCH_TIME_WIDTH 2 8031ff27651SAnish Kumar 8041ff27651SAnish Kumar /* MAX98925_R038_GLOBAL_ENABLE */ 8051ff27651SAnish Kumar #define M98925_EN_MASK (1<<7) 8061ff27651SAnish Kumar #define M98925_EN_SHIFT 7 8071ff27651SAnish Kumar #define M98925_EN_WIDTH 1 8081ff27651SAnish Kumar 8091ff27651SAnish Kumar /* MAX98925_R03A_BOOST_LIMITER */ 8101ff27651SAnish Kumar #define M98925_BST_ILIM_MASK (0x1F<<3) 8111ff27651SAnish Kumar #define M98925_BST_ILIM_SHIFT 3 8121ff27651SAnish Kumar #define M98925_BST_ILIM_WIDTH 5 8131ff27651SAnish Kumar 8141ff27651SAnish Kumar /* MAX98925_R0FF_VERSION */ 8151ff27651SAnish Kumar #define M98925_REV_ID_MASK (0xFF<<0) 8161ff27651SAnish Kumar #define M98925_REV_ID_SHIFT 0 8171ff27651SAnish Kumar #define M98925_REV_ID_WIDTH 8 8181ff27651SAnish Kumar 8191ff27651SAnish Kumar struct max98925_priv { 8201ff27651SAnish Kumar struct regmap *regmap; 821cf9cb34eSKuninori Morimoto struct snd_soc_component *component; 8221ff27651SAnish Kumar struct max98925_pdata *pdata; 8231ff27651SAnish Kumar unsigned int sysclk; 8241ff27651SAnish Kumar unsigned int v_slot; 8251ff27651SAnish Kumar unsigned int i_slot; 8261ff27651SAnish Kumar unsigned int spk_gain; 8271ff27651SAnish Kumar unsigned int ch_size; 8281ff27651SAnish Kumar }; 8291ff27651SAnish Kumar #endif 830