1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2022, Analog Devices Inc. 3 4 #include <linux/gpio/consumer.h> 5 #include <linux/i2c.h> 6 #include <linux/module.h> 7 #include <sound/pcm_params.h> 8 #include <sound/soc.h> 9 #include <linux/gpio.h> 10 #include <sound/tlv.h> 11 #include "max98396.h" 12 13 static struct reg_default max98396_reg[] = { 14 {MAX98396_R2000_SW_RESET, 0x00}, 15 {MAX98396_R2001_INT_RAW1, 0x00}, 16 {MAX98396_R2002_INT_RAW2, 0x00}, 17 {MAX98396_R2003_INT_RAW3, 0x00}, 18 {MAX98396_R2004_INT_RAW4, 0x00}, 19 {MAX98396_R2006_INT_STATE1, 0x00}, 20 {MAX98396_R2007_INT_STATE2, 0x00}, 21 {MAX98396_R2008_INT_STATE3, 0x00}, 22 {MAX98396_R2009_INT_STATE4, 0x00}, 23 {MAX98396_R200B_INT_FLAG1, 0x00}, 24 {MAX98396_R200C_INT_FLAG2, 0x00}, 25 {MAX98396_R200D_INT_FLAG3, 0x00}, 26 {MAX98396_R200E_INT_FLAG4, 0x00}, 27 {MAX98396_R2010_INT_EN1, 0x02}, 28 {MAX98396_R2011_INT_EN2, 0x00}, 29 {MAX98396_R2012_INT_EN3, 0x00}, 30 {MAX98396_R2013_INT_EN4, 0x00}, 31 {MAX98396_R2015_INT_FLAG_CLR1, 0x00}, 32 {MAX98396_R2016_INT_FLAG_CLR2, 0x00}, 33 {MAX98396_R2017_INT_FLAG_CLR3, 0x00}, 34 {MAX98396_R2018_INT_FLAG_CLR4, 0x00}, 35 {MAX98396_R201F_IRQ_CTRL, 0x00}, 36 {MAX98396_R2020_THERM_WARN_THRESH, 0x46}, 37 {MAX98396_R2021_THERM_WARN_THRESH2, 0x46}, 38 {MAX98396_R2022_THERM_SHDN_THRESH, 0x64}, 39 {MAX98396_R2023_THERM_HYSTERESIS, 0x02}, 40 {MAX98396_R2024_THERM_FOLDBACK_SET, 0xC5}, 41 {MAX98396_R2027_THERM_FOLDBACK_EN, 0x01}, 42 {MAX98396_R2030_NOISEGATE_MODE_CTRL, 0x32}, 43 {MAX98396_R2033_NOISEGATE_MODE_EN, 0x00}, 44 {MAX98396_R2038_CLK_MON_CTRL, 0x00}, 45 {MAX98396_R2039_DATA_MON_CTRL, 0x00}, 46 {MAX98396_R203F_ENABLE_CTRLS, 0x0F}, 47 {MAX98396_R2040_PIN_CFG, 0x55}, 48 {MAX98396_R2041_PCM_MODE_CFG, 0xC0}, 49 {MAX98396_R2042_PCM_CLK_SETUP, 0x04}, 50 {MAX98396_R2043_PCM_SR_SETUP, 0x88}, 51 {MAX98396_R2044_PCM_TX_CTRL_1, 0x00}, 52 {MAX98396_R2045_PCM_TX_CTRL_2, 0x00}, 53 {MAX98396_R2046_PCM_TX_CTRL_3, 0x00}, 54 {MAX98396_R2047_PCM_TX_CTRL_4, 0x00}, 55 {MAX98396_R2048_PCM_TX_CTRL_5, 0x00}, 56 {MAX98396_R2049_PCM_TX_CTRL_6, 0x00}, 57 {MAX98396_R204A_PCM_TX_CTRL_7, 0x00}, 58 {MAX98396_R204B_PCM_TX_CTRL_8, 0x00}, 59 {MAX98396_R204C_PCM_TX_HIZ_CTRL_1, 0xFF}, 60 {MAX98396_R204D_PCM_TX_HIZ_CTRL_2, 0xFF}, 61 {MAX98396_R204E_PCM_TX_HIZ_CTRL_3, 0xFF}, 62 {MAX98396_R204F_PCM_TX_HIZ_CTRL_4, 0xFF}, 63 {MAX98396_R2050_PCM_TX_HIZ_CTRL_5, 0xFF}, 64 {MAX98396_R2051_PCM_TX_HIZ_CTRL_6, 0xFF}, 65 {MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 0xFF}, 66 {MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 0xFF}, 67 {MAX98396_R2055_PCM_RX_SRC1, 0x00}, 68 {MAX98396_R2056_PCM_RX_SRC2, 0x00}, 69 {MAX98396_R2058_PCM_BYPASS_SRC, 0x00}, 70 {MAX98396_R205D_PCM_TX_SRC_EN, 0x00}, 71 {MAX98396_R205E_PCM_RX_EN, 0x00}, 72 {MAX98396_R205F_PCM_TX_EN, 0x00}, 73 {MAX98396_R2070_ICC_RX_EN_A, 0x00}, 74 {MAX98396_R2071_ICC_RX_EN_B, 0x00}, 75 {MAX98396_R2072_ICC_TX_CTRL, 0x00}, 76 {MAX98396_R207F_ICC_EN, 0x00}, 77 {MAX98396_R2083_TONE_GEN_DC_CFG, 0x04}, 78 {MAX98396_R2084_TONE_GEN_DC_LVL1, 0x00}, 79 {MAX98396_R2085_TONE_GEN_DC_LVL2, 0x00}, 80 {MAX98396_R2086_TONE_GEN_DC_LVL3, 0x00}, 81 {MAX98396_R208F_TONE_GEN_EN, 0x00}, 82 {MAX98396_R2090_AMP_VOL_CTRL, 0x00}, 83 {MAX98396_R2091_AMP_PATH_GAIN, 0x0B}, 84 {MAX98396_R2092_AMP_DSP_CFG, 0x23}, 85 {MAX98396_R2093_SSM_CFG, 0x0D}, 86 {MAX98396_R2094_SPK_CLS_DG_THRESH, 0x12}, 87 {MAX98396_R2095_SPK_CLS_DG_HDR, 0x17}, 88 {MAX98396_R2096_SPK_CLS_DG_HOLD_TIME, 0x17}, 89 {MAX98396_R2097_SPK_CLS_DG_DELAY, 0x00}, 90 {MAX98396_R2098_SPK_CLS_DG_MODE, 0x00}, 91 {MAX98396_R2099_SPK_CLS_DG_VBAT_LVL, 0x03}, 92 {MAX98396_R209A_SPK_EDGE_CTRL, 0x00}, 93 {MAX98396_R209C_SPK_EDGE_CTRL1, 0x0A}, 94 {MAX98396_R209D_SPK_EDGE_CTRL2, 0xAA}, 95 {MAX98396_R209E_AMP_CLIP_GAIN, 0x00}, 96 {MAX98396_R209F_BYPASS_PATH_CFG, 0x00}, 97 {MAX98396_R20A0_AMP_SUPPLY_CTL, 0x00}, 98 {MAX98396_R20AF_AMP_EN, 0x00}, 99 {MAX98396_R20B0_ADC_SR, 0x30}, 100 {MAX98396_R20B1_ADC_PVDD_CFG, 0x00}, 101 {MAX98396_R20B2_ADC_VBAT_CFG, 0x00}, 102 {MAX98396_R20B3_ADC_THERMAL_CFG, 0x00}, 103 {MAX98396_R20B4_ADC_READBACK_CTRL1, 0x00}, 104 {MAX98396_R20B5_ADC_READBACK_CTRL2, 0x00}, 105 {MAX98396_R20B6_ADC_PVDD_READBACK_MSB, 0x00}, 106 {MAX98396_R20B7_ADC_PVDD_READBACK_LSB, 0x00}, 107 {MAX98396_R20B8_ADC_VBAT_READBACK_MSB, 0x00}, 108 {MAX98396_R20B9_ADC_VBAT_READBACK_LSB, 0x00}, 109 {MAX98396_R20BA_ADC_TEMP_READBACK_MSB, 0x00}, 110 {MAX98396_R20BB_ADC_TEMP_READBACK_LSB, 0x00}, 111 {MAX98396_R20BC_ADC_LO_PVDD_READBACK_MSB, 0x00}, 112 {MAX98396_R20BD_ADC_LO_PVDD_READBACK_LSB, 0x00}, 113 {MAX98396_R20BE_ADC_LO_VBAT_READBACK_MSB, 0x00}, 114 {MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB, 0x00}, 115 {MAX98396_R20C7_ADC_CFG, 0x00}, 116 {MAX98396_R20D0_DHT_CFG1, 0x00}, 117 {MAX98396_R20D1_LIMITER_CFG1, 0x08}, 118 {MAX98396_R20D2_LIMITER_CFG2, 0x00}, 119 {MAX98396_R20D3_DHT_CFG2, 0x14}, 120 {MAX98396_R20D4_DHT_CFG3, 0x02}, 121 {MAX98396_R20D5_DHT_CFG4, 0x04}, 122 {MAX98396_R20D6_DHT_HYSTERESIS_CFG, 0x07}, 123 {MAX98396_R20DF_DHT_EN, 0x00}, 124 {MAX98396_R20E0_IV_SENSE_PATH_CFG, 0x04}, 125 {MAX98396_R20E4_IV_SENSE_PATH_EN, 0x00}, 126 {MAX98396_R20E5_BPE_STATE, 0x00}, 127 {MAX98396_R20E6_BPE_L3_THRESH_MSB, 0x00}, 128 {MAX98396_R20E7_BPE_L3_THRESH_LSB, 0x00}, 129 {MAX98396_R20E8_BPE_L2_THRESH_MSB, 0x00}, 130 {MAX98396_R20E9_BPE_L2_THRESH_LSB, 0x00}, 131 {MAX98396_R20EA_BPE_L1_THRESH_MSB, 0x00}, 132 {MAX98396_R20EB_BPE_L1_THRESH_LSB, 0x00}, 133 {MAX98396_R20EC_BPE_L0_THRESH_MSB, 0x00}, 134 {MAX98396_R20ED_BPE_L0_THRESH_LSB, 0x00}, 135 {MAX98396_R20EE_BPE_L3_DWELL_HOLD_TIME, 0x00}, 136 {MAX98396_R20EF_BPE_L2_DWELL_HOLD_TIME, 0x00}, 137 {MAX98396_R20F0_BPE_L1_DWELL_HOLD_TIME, 0x00}, 138 {MAX98396_R20F1_BPE_L0_HOLD_TIME, 0x00}, 139 {MAX98396_R20F2_BPE_L3_ATTACK_REL_STEP, 0x00}, 140 {MAX98396_R20F3_BPE_L2_ATTACK_REL_STEP, 0x00}, 141 {MAX98396_R20F4_BPE_L1_ATTACK_REL_STEP, 0x00}, 142 {MAX98396_R20F5_BPE_L0_ATTACK_REL_STEP, 0x00}, 143 {MAX98396_R20F6_BPE_L3_MAX_GAIN_ATTN, 0x00}, 144 {MAX98396_R20F7_BPE_L2_MAX_GAIN_ATTN, 0x00}, 145 {MAX98396_R20F8_BPE_L1_MAX_GAIN_ATTN, 0x00}, 146 {MAX98396_R20F9_BPE_L0_MAX_GAIN_ATTN, 0x00}, 147 {MAX98396_R20FA_BPE_L3_ATT_REL_RATE, 0x00}, 148 {MAX98396_R20FB_BPE_L2_ATT_REL_RATE, 0x00}, 149 {MAX98396_R20FC_BPE_L1_ATT_REL_RATE, 0x00}, 150 {MAX98396_R20FD_BPE_L0_ATT_REL_RATE, 0x00}, 151 {MAX98396_R20FE_BPE_L3_LIMITER_CFG, 0x00}, 152 {MAX98396_R20FF_BPE_L2_LIMITER_CFG, 0x00}, 153 {MAX98396_R2100_BPE_L1_LIMITER_CFG, 0x00}, 154 {MAX98396_R2101_BPE_L0_LIMITER_CFG, 0x00}, 155 {MAX98396_R2102_BPE_L3_LIM_ATT_REL_RATE, 0x00}, 156 {MAX98396_R2103_BPE_L2_LIM_ATT_REL_RATE, 0x00}, 157 {MAX98396_R2104_BPE_L1_LIM_ATT_REL_RATE, 0x00}, 158 {MAX98396_R2105_BPE_L0_LIM_ATT_REL_RATE, 0x00}, 159 {MAX98396_R2106_BPE_THRESH_HYSTERESIS, 0x00}, 160 {MAX98396_R2107_BPE_INFINITE_HOLD_CLR, 0x00}, 161 {MAX98396_R2108_BPE_SUPPLY_SRC, 0x00}, 162 {MAX98396_R2109_BPE_LOW_STATE, 0x00}, 163 {MAX98396_R210A_BPE_LOW_GAIN, 0x00}, 164 {MAX98396_R210B_BPE_LOW_LIMITER, 0x00}, 165 {MAX98396_R210D_BPE_EN, 0x00}, 166 {MAX98396_R210E_AUTO_RESTART, 0x00}, 167 {MAX98396_R210F_GLOBAL_EN, 0x00}, 168 {MAX98396_R21FF_REVISION_ID, 0x00}, 169 }; 170 171 static struct reg_default max98397_reg[] = { 172 {MAX98396_R2000_SW_RESET, 0x00}, 173 {MAX98396_R2001_INT_RAW1, 0x00}, 174 {MAX98396_R2002_INT_RAW2, 0x00}, 175 {MAX98396_R2003_INT_RAW3, 0x00}, 176 {MAX98396_R2004_INT_RAW4, 0x00}, 177 {MAX98396_R2006_INT_STATE1, 0x00}, 178 {MAX98396_R2007_INT_STATE2, 0x00}, 179 {MAX98396_R2008_INT_STATE3, 0x00}, 180 {MAX98396_R2009_INT_STATE4, 0x00}, 181 {MAX98396_R200B_INT_FLAG1, 0x00}, 182 {MAX98396_R200C_INT_FLAG2, 0x00}, 183 {MAX98396_R200D_INT_FLAG3, 0x00}, 184 {MAX98396_R200E_INT_FLAG4, 0x00}, 185 {MAX98396_R2010_INT_EN1, 0x02}, 186 {MAX98396_R2011_INT_EN2, 0x00}, 187 {MAX98396_R2012_INT_EN3, 0x00}, 188 {MAX98396_R2013_INT_EN4, 0x00}, 189 {MAX98396_R2015_INT_FLAG_CLR1, 0x00}, 190 {MAX98396_R2016_INT_FLAG_CLR2, 0x00}, 191 {MAX98396_R2017_INT_FLAG_CLR3, 0x00}, 192 {MAX98396_R2018_INT_FLAG_CLR4, 0x00}, 193 {MAX98396_R201F_IRQ_CTRL, 0x00}, 194 {MAX98396_R2020_THERM_WARN_THRESH, 0x46}, 195 {MAX98396_R2021_THERM_WARN_THRESH2, 0x46}, 196 {MAX98396_R2022_THERM_SHDN_THRESH, 0x64}, 197 {MAX98396_R2023_THERM_HYSTERESIS, 0x02}, 198 {MAX98396_R2024_THERM_FOLDBACK_SET, 0xC5}, 199 {MAX98396_R2027_THERM_FOLDBACK_EN, 0x01}, 200 {MAX98396_R2030_NOISEGATE_MODE_CTRL, 0x32}, 201 {MAX98396_R2033_NOISEGATE_MODE_EN, 0x00}, 202 {MAX98396_R2038_CLK_MON_CTRL, 0x00}, 203 {MAX98396_R2039_DATA_MON_CTRL, 0x00}, 204 {MAX98397_R203A_SPK_MON_THRESH, 0x03}, 205 {MAX98396_R203F_ENABLE_CTRLS, 0x0F}, 206 {MAX98396_R2040_PIN_CFG, 0x55}, 207 {MAX98396_R2041_PCM_MODE_CFG, 0xC0}, 208 {MAX98396_R2042_PCM_CLK_SETUP, 0x04}, 209 {MAX98396_R2043_PCM_SR_SETUP, 0x88}, 210 {MAX98396_R2044_PCM_TX_CTRL_1, 0x00}, 211 {MAX98396_R2045_PCM_TX_CTRL_2, 0x00}, 212 {MAX98396_R2046_PCM_TX_CTRL_3, 0x00}, 213 {MAX98396_R2047_PCM_TX_CTRL_4, 0x00}, 214 {MAX98396_R2048_PCM_TX_CTRL_5, 0x00}, 215 {MAX98396_R2049_PCM_TX_CTRL_6, 0x00}, 216 {MAX98396_R204A_PCM_TX_CTRL_7, 0x00}, 217 {MAX98396_R204B_PCM_TX_CTRL_8, 0x00}, 218 {MAX98397_R204C_PCM_TX_CTRL_9, 0x00}, 219 {MAX98397_R204D_PCM_TX_HIZ_CTRL_1, 0xFF}, 220 {MAX98397_R204E_PCM_TX_HIZ_CTRL_2, 0xFF}, 221 {MAX98397_R204F_PCM_TX_HIZ_CTRL_3, 0xFF}, 222 {MAX98397_R2050_PCM_TX_HIZ_CTRL_4, 0xFF}, 223 {MAX98397_R2051_PCM_TX_HIZ_CTRL_5, 0xFF}, 224 {MAX98397_R2052_PCM_TX_HIZ_CTRL_6, 0xFF}, 225 {MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 0xFF}, 226 {MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 0xFF}, 227 {MAX98397_R2056_PCM_RX_SRC1, 0x00}, 228 {MAX98397_R2057_PCM_RX_SRC2, 0x00}, 229 {MAX98396_R2058_PCM_BYPASS_SRC, 0x00}, 230 {MAX98396_R205D_PCM_TX_SRC_EN, 0x00}, 231 {MAX98396_R205E_PCM_RX_EN, 0x00}, 232 {MAX98396_R205F_PCM_TX_EN, 0x00}, 233 {MAX98397_R2060_PCM_TX_SUPPLY_SEL, 0x00}, 234 {MAX98396_R2070_ICC_RX_EN_A, 0x00}, 235 {MAX98396_R2071_ICC_RX_EN_B, 0x00}, 236 {MAX98396_R2072_ICC_TX_CTRL, 0x00}, 237 {MAX98396_R207F_ICC_EN, 0x00}, 238 {MAX98396_R2083_TONE_GEN_DC_CFG, 0x04}, 239 {MAX98396_R2084_TONE_GEN_DC_LVL1, 0x00}, 240 {MAX98396_R2085_TONE_GEN_DC_LVL2, 0x00}, 241 {MAX98396_R2086_TONE_GEN_DC_LVL3, 0x00}, 242 {MAX98396_R208F_TONE_GEN_EN, 0x00}, 243 {MAX98396_R2090_AMP_VOL_CTRL, 0x00}, 244 {MAX98396_R2091_AMP_PATH_GAIN, 0x12}, 245 {MAX98396_R2092_AMP_DSP_CFG, 0x22}, 246 {MAX98396_R2093_SSM_CFG, 0x08}, 247 {MAX98396_R2094_SPK_CLS_DG_THRESH, 0x12}, 248 {MAX98396_R2095_SPK_CLS_DG_HDR, 0x17}, 249 {MAX98396_R2096_SPK_CLS_DG_HOLD_TIME, 0x17}, 250 {MAX98396_R2097_SPK_CLS_DG_DELAY, 0x00}, 251 {MAX98396_R2098_SPK_CLS_DG_MODE, 0x00}, 252 {MAX98396_R2099_SPK_CLS_DG_VBAT_LVL, 0x03}, 253 {MAX98396_R209A_SPK_EDGE_CTRL, 0x00}, 254 {MAX98397_R209B_SPK_PATH_WB_ONLY, 0x00}, 255 {MAX98396_R209C_SPK_EDGE_CTRL1, 0x03}, 256 {MAX98396_R209D_SPK_EDGE_CTRL2, 0xFC}, 257 {MAX98396_R209E_AMP_CLIP_GAIN, 0x00}, 258 {MAX98396_R209F_BYPASS_PATH_CFG, 0x00}, 259 {MAX98396_R20AF_AMP_EN, 0x00}, 260 {MAX98396_R20B0_ADC_SR, 0x30}, 261 {MAX98396_R20B1_ADC_PVDD_CFG, 0x00}, 262 {MAX98396_R20B2_ADC_VBAT_CFG, 0x00}, 263 {MAX98396_R20B3_ADC_THERMAL_CFG, 0x00}, 264 {MAX98397_R20B4_ADC_VDDH_CFG, 0x00}, 265 {MAX98397_R20B5_ADC_READBACK_CTRL1, 0x00}, 266 {MAX98397_R20B6_ADC_READBACK_CTRL2, 0x00}, 267 {MAX98397_R20B7_ADC_PVDD_READBACK_MSB, 0x00}, 268 {MAX98397_R20B8_ADC_PVDD_READBACK_LSB, 0x00}, 269 {MAX98397_R20B9_ADC_VBAT_READBACK_MSB, 0x00}, 270 {MAX98397_R20BA_ADC_VBAT_READBACK_LSB, 0x00}, 271 {MAX98397_R20BB_ADC_TEMP_READBACK_MSB, 0x00}, 272 {MAX98397_R20BC_ADC_TEMP_READBACK_LSB, 0x00}, 273 {MAX98397_R20BD_ADC_VDDH__READBACK_MSB, 0x00}, 274 {MAX98397_R20BE_ADC_VDDH_READBACK_LSB, 0x00}, 275 {MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB, 0x00}, 276 {MAX98397_R20C3_ADC_LO_VDDH_READBACK_MSB, 0x00}, 277 {MAX98397_R20C4_ADC_LO_VDDH_READBACK_LSB, 0x00}, 278 {MAX98397_R20C5_MEAS_ADC_OPTIMAL_MODE, 0x04}, 279 {MAX98396_R20C7_ADC_CFG, 0x00}, 280 {MAX98396_R20D0_DHT_CFG1, 0x00}, 281 {MAX98396_R20D1_LIMITER_CFG1, 0x08}, 282 {MAX98396_R20D2_LIMITER_CFG2, 0x00}, 283 {MAX98396_R20D3_DHT_CFG2, 0x14}, 284 {MAX98396_R20D4_DHT_CFG3, 0x02}, 285 {MAX98396_R20D5_DHT_CFG4, 0x04}, 286 {MAX98396_R20D6_DHT_HYSTERESIS_CFG, 0x07}, 287 {MAX98396_R20DF_DHT_EN, 0x00}, 288 {MAX98396_R20E0_IV_SENSE_PATH_CFG, 0x04}, 289 {MAX98396_R20E4_IV_SENSE_PATH_EN, 0x00}, 290 {MAX98396_R20E5_BPE_STATE, 0x00}, 291 {MAX98396_R20E6_BPE_L3_THRESH_MSB, 0x00}, 292 {MAX98396_R20E7_BPE_L3_THRESH_LSB, 0x00}, 293 {MAX98396_R20E8_BPE_L2_THRESH_MSB, 0x00}, 294 {MAX98396_R20E9_BPE_L2_THRESH_LSB, 0x00}, 295 {MAX98396_R20EA_BPE_L1_THRESH_MSB, 0x00}, 296 {MAX98396_R20EB_BPE_L1_THRESH_LSB, 0x00}, 297 {MAX98396_R20EC_BPE_L0_THRESH_MSB, 0x00}, 298 {MAX98396_R20ED_BPE_L0_THRESH_LSB, 0x00}, 299 {MAX98396_R20EE_BPE_L3_DWELL_HOLD_TIME, 0x00}, 300 {MAX98396_R20EF_BPE_L2_DWELL_HOLD_TIME, 0x00}, 301 {MAX98396_R20F0_BPE_L1_DWELL_HOLD_TIME, 0x00}, 302 {MAX98396_R20F1_BPE_L0_HOLD_TIME, 0x00}, 303 {MAX98396_R20F2_BPE_L3_ATTACK_REL_STEP, 0x00}, 304 {MAX98396_R20F3_BPE_L2_ATTACK_REL_STEP, 0x00}, 305 {MAX98396_R20F4_BPE_L1_ATTACK_REL_STEP, 0x00}, 306 {MAX98396_R20F5_BPE_L0_ATTACK_REL_STEP, 0x00}, 307 {MAX98396_R20F6_BPE_L3_MAX_GAIN_ATTN, 0x00}, 308 {MAX98396_R20F7_BPE_L2_MAX_GAIN_ATTN, 0x00}, 309 {MAX98396_R20F8_BPE_L1_MAX_GAIN_ATTN, 0x00}, 310 {MAX98396_R20F9_BPE_L0_MAX_GAIN_ATTN, 0x00}, 311 {MAX98396_R20FA_BPE_L3_ATT_REL_RATE, 0x00}, 312 {MAX98396_R20FB_BPE_L2_ATT_REL_RATE, 0x00}, 313 {MAX98396_R20FC_BPE_L1_ATT_REL_RATE, 0x00}, 314 {MAX98396_R20FD_BPE_L0_ATT_REL_RATE, 0x00}, 315 {MAX98396_R20FE_BPE_L3_LIMITER_CFG, 0x00}, 316 {MAX98396_R20FF_BPE_L2_LIMITER_CFG, 0x00}, 317 {MAX98396_R2100_BPE_L1_LIMITER_CFG, 0x00}, 318 {MAX98396_R2101_BPE_L0_LIMITER_CFG, 0x00}, 319 {MAX98396_R2102_BPE_L3_LIM_ATT_REL_RATE, 0x00}, 320 {MAX98396_R2103_BPE_L2_LIM_ATT_REL_RATE, 0x00}, 321 {MAX98396_R2104_BPE_L1_LIM_ATT_REL_RATE, 0x00}, 322 {MAX98396_R2105_BPE_L0_LIM_ATT_REL_RATE, 0x00}, 323 {MAX98396_R2106_BPE_THRESH_HYSTERESIS, 0x00}, 324 {MAX98396_R2107_BPE_INFINITE_HOLD_CLR, 0x00}, 325 {MAX98396_R2108_BPE_SUPPLY_SRC, 0x00}, 326 {MAX98396_R2109_BPE_LOW_STATE, 0x00}, 327 {MAX98396_R210A_BPE_LOW_GAIN, 0x00}, 328 {MAX98396_R210B_BPE_LOW_LIMITER, 0x00}, 329 {MAX98396_R210D_BPE_EN, 0x00}, 330 {MAX98396_R210E_AUTO_RESTART, 0x00}, 331 {MAX98396_R210F_GLOBAL_EN, 0x00}, 332 {MAX98397_R22FF_REVISION_ID, 0x00}, 333 }; 334 335 static void max98396_global_enable_onoff(struct regmap *regmap, bool onoff) 336 { 337 regmap_write(regmap, MAX98396_R210F_GLOBAL_EN, onoff ? 1 : 0); 338 usleep_range(11000, 12000); 339 } 340 341 static int max98396_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 342 { 343 struct snd_soc_component *component = codec_dai->component; 344 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 345 unsigned int format_mask, format = 0; 346 unsigned int bclk_pol = 0; 347 int ret, status; 348 int reg; 349 bool update = false; 350 351 format_mask = MAX98396_PCM_MODE_CFG_FORMAT_MASK | 352 MAX98396_PCM_MODE_CFG_LRCLKEDGE; 353 354 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt); 355 356 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 357 case SND_SOC_DAIFMT_NB_NF: 358 break; 359 case SND_SOC_DAIFMT_NB_IF: 360 format = MAX98396_PCM_MODE_CFG_LRCLKEDGE; 361 break; 362 case SND_SOC_DAIFMT_IB_NF: 363 bclk_pol = MAX98396_PCM_MODE_CFG_BCLKEDGE; 364 break; 365 case SND_SOC_DAIFMT_IB_IF: 366 bclk_pol = MAX98396_PCM_MODE_CFG_BCLKEDGE; 367 format = MAX98396_PCM_MODE_CFG_LRCLKEDGE; 368 break; 369 370 default: 371 dev_err(component->dev, "DAI invert mode unsupported\n"); 372 return -EINVAL; 373 } 374 375 /* interface format */ 376 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 377 case SND_SOC_DAIFMT_I2S: 378 format |= MAX98396_PCM_FORMAT_I2S; 379 break; 380 case SND_SOC_DAIFMT_LEFT_J: 381 format |= MAX98396_PCM_FORMAT_LJ; 382 break; 383 case SND_SOC_DAIFMT_DSP_A: 384 format |= MAX98396_PCM_FORMAT_TDM_MODE1; 385 break; 386 case SND_SOC_DAIFMT_DSP_B: 387 format |= MAX98396_PCM_FORMAT_TDM_MODE0; 388 break; 389 default: 390 return -EINVAL; 391 } 392 393 ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status); 394 if (ret < 0) 395 return -EINVAL; 396 397 if (status) { 398 ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, ®); 399 if (ret < 0) 400 return -EINVAL; 401 if (format != (reg & format_mask)) { 402 update = true; 403 } else { 404 ret = regmap_read(max98396->regmap, 405 MAX98396_R2042_PCM_CLK_SETUP, ®); 406 if (ret < 0) 407 return -EINVAL; 408 if (bclk_pol != (reg & MAX98396_PCM_MODE_CFG_BCLKEDGE)) 409 update = true; 410 } 411 /* GLOBAL_EN OFF prior to pcm mode, clock configuration change */ 412 if (update) 413 max98396_global_enable_onoff(max98396->regmap, false); 414 } 415 416 regmap_update_bits(max98396->regmap, 417 MAX98396_R2041_PCM_MODE_CFG, 418 format_mask, format); 419 420 regmap_update_bits(max98396->regmap, 421 MAX98396_R2042_PCM_CLK_SETUP, 422 MAX98396_PCM_MODE_CFG_BCLKEDGE, 423 bclk_pol); 424 425 if (status && update) 426 max98396_global_enable_onoff(max98396->regmap, true); 427 428 return 0; 429 } 430 431 /* BCLKs per LRCLK */ 432 static const int bclk_sel_table[] = { 433 32, 48, 64, 96, 128, 192, 256, 384, 512, 320, 434 }; 435 436 static int max98396_get_bclk_sel(int bclk) 437 { 438 int i; 439 /* match BCLKs per LRCLK */ 440 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) { 441 if (bclk_sel_table[i] == bclk) 442 return i + 2; 443 } 444 return 0; 445 } 446 447 static int max98396_set_clock(struct snd_soc_component *component, 448 struct snd_pcm_hw_params *params) 449 { 450 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 451 /* BCLK/LRCLK ratio calculation */ 452 int blr_clk_ratio = params_channels(params) * max98396->ch_size; 453 int value; 454 455 if (!max98396->tdm_mode) { 456 /* BCLK configuration */ 457 value = max98396_get_bclk_sel(blr_clk_ratio); 458 if (!value) { 459 dev_err(component->dev, "format unsupported %d\n", 460 params_format(params)); 461 return -EINVAL; 462 } 463 464 regmap_update_bits(max98396->regmap, 465 MAX98396_R2042_PCM_CLK_SETUP, 466 MAX98396_PCM_CLK_SETUP_BSEL_MASK, 467 value); 468 } 469 470 return 0; 471 } 472 473 static int max98396_dai_hw_params(struct snd_pcm_substream *substream, 474 struct snd_pcm_hw_params *params, 475 struct snd_soc_dai *dai) 476 { 477 struct snd_soc_component *component = dai->component; 478 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 479 unsigned int sampling_rate = 0; 480 unsigned int chan_sz = 0; 481 int ret, reg; 482 int status; 483 bool update = false; 484 485 /* pcm mode configuration */ 486 switch (snd_pcm_format_width(params_format(params))) { 487 case 16: 488 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_16; 489 break; 490 case 24: 491 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_24; 492 break; 493 case 32: 494 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_32; 495 break; 496 default: 497 dev_err(component->dev, "format unsupported %d\n", 498 params_format(params)); 499 goto err; 500 } 501 502 max98396->ch_size = snd_pcm_format_width(params_format(params)); 503 504 dev_dbg(component->dev, "format supported %d", 505 params_format(params)); 506 507 /* sampling rate configuration */ 508 switch (params_rate(params)) { 509 case 8000: 510 sampling_rate = MAX98396_PCM_SR_8000; 511 break; 512 case 11025: 513 sampling_rate = MAX98396_PCM_SR_11025; 514 break; 515 case 12000: 516 sampling_rate = MAX98396_PCM_SR_12000; 517 break; 518 case 16000: 519 sampling_rate = MAX98396_PCM_SR_16000; 520 break; 521 case 22050: 522 sampling_rate = MAX98396_PCM_SR_22050; 523 break; 524 case 24000: 525 sampling_rate = MAX98396_PCM_SR_24000; 526 break; 527 case 32000: 528 sampling_rate = MAX98396_PCM_SR_32000; 529 break; 530 case 44100: 531 sampling_rate = MAX98396_PCM_SR_44100; 532 break; 533 case 48000: 534 sampling_rate = MAX98396_PCM_SR_48000; 535 break; 536 case 88200: 537 sampling_rate = MAX98396_PCM_SR_88200; 538 break; 539 case 96000: 540 sampling_rate = MAX98396_PCM_SR_96000; 541 break; 542 case 192000: 543 sampling_rate = MAX98396_PCM_SR_192000; 544 break; 545 default: 546 dev_err(component->dev, "rate %d not supported\n", 547 params_rate(params)); 548 goto err; 549 } 550 551 ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status); 552 if (ret < 0) 553 goto err; 554 555 if (status) { 556 ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, ®); 557 if (ret < 0) 558 goto err; 559 if (chan_sz != (reg & MAX98396_PCM_MODE_CFG_CHANSZ_MASK)) { 560 update = true; 561 } else { 562 ret = regmap_read(max98396->regmap, MAX98396_R2043_PCM_SR_SETUP, ®); 563 if (ret < 0) 564 goto err; 565 if (sampling_rate != (reg & MAX98396_PCM_SR_MASK)) 566 update = true; 567 } 568 569 /* GLOBAL_EN OFF prior to channel size and sampling rate change */ 570 if (update) 571 max98396_global_enable_onoff(max98396->regmap, false); 572 } 573 574 /* set channel size */ 575 regmap_update_bits(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, 576 MAX98396_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 577 578 /* set DAI_SR to correct LRCLK frequency */ 579 regmap_update_bits(max98396->regmap, MAX98396_R2043_PCM_SR_SETUP, 580 MAX98396_PCM_SR_MASK, sampling_rate); 581 582 /* set sampling rate of IV */ 583 if (max98396->interleave_mode && 584 sampling_rate > MAX98396_PCM_SR_16000) 585 regmap_update_bits(max98396->regmap, 586 MAX98396_R2043_PCM_SR_SETUP, 587 MAX98396_IVADC_SR_MASK, 588 (sampling_rate - 3) 589 << MAX98396_IVADC_SR_SHIFT); 590 else 591 regmap_update_bits(max98396->regmap, 592 MAX98396_R2043_PCM_SR_SETUP, 593 MAX98396_IVADC_SR_MASK, 594 sampling_rate << MAX98396_IVADC_SR_SHIFT); 595 596 ret = max98396_set_clock(component, params); 597 598 if (status && update) 599 max98396_global_enable_onoff(max98396->regmap, true); 600 601 return ret; 602 603 err: 604 return -EINVAL; 605 } 606 607 static int max98396_dai_tdm_slot(struct snd_soc_dai *dai, 608 unsigned int tx_mask, unsigned int rx_mask, 609 int slots, int slot_width) 610 { 611 struct snd_soc_component *component = dai->component; 612 struct max98396_priv *max98396 = 613 snd_soc_component_get_drvdata(component); 614 int bsel; 615 unsigned int chan_sz = 0; 616 int ret, status; 617 int reg; 618 bool update = false; 619 620 if (!tx_mask && !rx_mask && !slots && !slot_width) 621 max98396->tdm_mode = false; 622 else 623 max98396->tdm_mode = true; 624 625 /* BCLK configuration */ 626 bsel = max98396_get_bclk_sel(slots * slot_width); 627 if (bsel == 0) { 628 dev_err(component->dev, "BCLK %d not supported\n", 629 slots * slot_width); 630 return -EINVAL; 631 } 632 633 /* Channel size configuration */ 634 switch (slot_width) { 635 case 16: 636 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_16; 637 break; 638 case 24: 639 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_24; 640 break; 641 case 32: 642 chan_sz = MAX98396_PCM_MODE_CFG_CHANSZ_32; 643 break; 644 default: 645 dev_err(component->dev, "format unsupported %d\n", 646 slot_width); 647 return -EINVAL; 648 } 649 650 ret = regmap_read(max98396->regmap, MAX98396_R210F_GLOBAL_EN, &status); 651 if (ret < 0) 652 return -EINVAL; 653 654 if (status) { 655 ret = regmap_read(max98396->regmap, MAX98396_R2042_PCM_CLK_SETUP, ®); 656 if (ret < 0) 657 return -EINVAL; 658 if (bsel != (reg & MAX98396_PCM_CLK_SETUP_BSEL_MASK)) { 659 update = true; 660 } else { 661 ret = regmap_read(max98396->regmap, MAX98396_R2041_PCM_MODE_CFG, ®); 662 if (ret < 0) 663 return -EINVAL; 664 if (chan_sz != (reg & MAX98396_PCM_MODE_CFG_CHANSZ_MASK)) 665 update = true; 666 } 667 668 /* GLOBAL_EN OFF prior to channel size and BCLK per LRCLK change */ 669 if (update) 670 max98396_global_enable_onoff(max98396->regmap, false); 671 } 672 673 regmap_update_bits(max98396->regmap, 674 MAX98396_R2042_PCM_CLK_SETUP, 675 MAX98396_PCM_CLK_SETUP_BSEL_MASK, 676 bsel); 677 678 regmap_update_bits(max98396->regmap, 679 MAX98396_R2041_PCM_MODE_CFG, 680 MAX98396_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 681 682 /* Rx slot configuration */ 683 if (max98396->device_id == CODEC_TYPE_MAX98396) { 684 regmap_update_bits(max98396->regmap, 685 MAX98396_R2056_PCM_RX_SRC2, 686 MAX98396_PCM_DMIX_CH0_SRC_MASK, 687 rx_mask); 688 regmap_update_bits(max98396->regmap, 689 MAX98396_R2056_PCM_RX_SRC2, 690 MAX98396_PCM_DMIX_CH1_SRC_MASK, 691 rx_mask << MAX98396_PCM_DMIX_CH1_SHIFT); 692 } else { 693 regmap_update_bits(max98396->regmap, 694 MAX98397_R2057_PCM_RX_SRC2, 695 MAX98396_PCM_DMIX_CH0_SRC_MASK, 696 rx_mask); 697 regmap_update_bits(max98396->regmap, 698 MAX98397_R2057_PCM_RX_SRC2, 699 MAX98396_PCM_DMIX_CH1_SRC_MASK, 700 rx_mask << MAX98396_PCM_DMIX_CH1_SHIFT); 701 } 702 703 /* Tx slot Hi-Z configuration */ 704 if (max98396->device_id == CODEC_TYPE_MAX98396) { 705 regmap_write(max98396->regmap, 706 MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 707 ~tx_mask & 0xFF); 708 regmap_write(max98396->regmap, 709 MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 710 (~tx_mask & 0xFF00) >> 8); 711 } else { 712 regmap_write(max98396->regmap, 713 MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 714 ~tx_mask & 0xFF); 715 regmap_write(max98396->regmap, 716 MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 717 (~tx_mask & 0xFF00) >> 8); 718 } 719 720 if (status && update) 721 max98396_global_enable_onoff(max98396->regmap, true); 722 723 return 0; 724 } 725 726 #define MAX98396_RATES SNDRV_PCM_RATE_8000_192000 727 728 #define MAX98396_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 729 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 730 731 static const struct snd_soc_dai_ops max98396_dai_ops = { 732 .set_fmt = max98396_dai_set_fmt, 733 .hw_params = max98396_dai_hw_params, 734 .set_tdm_slot = max98396_dai_tdm_slot, 735 }; 736 737 static int max98396_dac_event(struct snd_soc_dapm_widget *w, 738 struct snd_kcontrol *kcontrol, int event) 739 { 740 struct snd_soc_component *component = 741 snd_soc_dapm_to_component(w->dapm); 742 struct max98396_priv *max98396 = 743 snd_soc_component_get_drvdata(component); 744 745 switch (event) { 746 case SND_SOC_DAPM_POST_PMU: 747 max98396_global_enable_onoff(max98396->regmap, true); 748 break; 749 case SND_SOC_DAPM_PRE_PMD: 750 max98396_global_enable_onoff(max98396->regmap, false); 751 752 max98396->tdm_mode = false; 753 break; 754 default: 755 return 0; 756 } 757 return 0; 758 } 759 760 static bool max98396_readable_register(struct device *dev, unsigned int reg) 761 { 762 switch (reg) { 763 case MAX98396_R2001_INT_RAW1 ... MAX98396_R2004_INT_RAW4: 764 case MAX98396_R2006_INT_STATE1 ... MAX98396_R2009_INT_STATE4: 765 case MAX98396_R200B_INT_FLAG1 ... MAX98396_R200E_INT_FLAG4: 766 case MAX98396_R2010_INT_EN1 ... MAX98396_R2013_INT_EN4: 767 case MAX98396_R2015_INT_FLAG_CLR1 ... MAX98396_R2018_INT_FLAG_CLR4: 768 case MAX98396_R201F_IRQ_CTRL ... MAX98396_R2024_THERM_FOLDBACK_SET: 769 case MAX98396_R2027_THERM_FOLDBACK_EN: 770 case MAX98396_R2030_NOISEGATE_MODE_CTRL: 771 case MAX98396_R2033_NOISEGATE_MODE_EN: 772 case MAX98396_R2038_CLK_MON_CTRL ... MAX98396_R2039_DATA_MON_CTRL: 773 case MAX98396_R203F_ENABLE_CTRLS ... MAX98396_R2053_PCM_TX_HIZ_CTRL_8: 774 case MAX98396_R2055_PCM_RX_SRC1 ... MAX98396_R2056_PCM_RX_SRC2: 775 case MAX98396_R2058_PCM_BYPASS_SRC: 776 case MAX98396_R205D_PCM_TX_SRC_EN ... MAX98396_R205F_PCM_TX_EN: 777 case MAX98396_R2070_ICC_RX_EN_A... MAX98396_R2072_ICC_TX_CTRL: 778 case MAX98396_R207F_ICC_EN: 779 case MAX98396_R2083_TONE_GEN_DC_CFG ... MAX98396_R2086_TONE_GEN_DC_LVL3: 780 case MAX98396_R208F_TONE_GEN_EN ... MAX98396_R209A_SPK_EDGE_CTRL: 781 case MAX98396_R209C_SPK_EDGE_CTRL1 ... MAX98396_R20A0_AMP_SUPPLY_CTL: 782 case MAX98396_R20AF_AMP_EN ... MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB: 783 case MAX98396_R20C7_ADC_CFG: 784 case MAX98396_R20D0_DHT_CFG1 ... MAX98396_R20D6_DHT_HYSTERESIS_CFG: 785 case MAX98396_R20DF_DHT_EN: 786 case MAX98396_R20E0_IV_SENSE_PATH_CFG: 787 case MAX98396_R20E4_IV_SENSE_PATH_EN 788 ... MAX98396_R2106_BPE_THRESH_HYSTERESIS: 789 case MAX98396_R2108_BPE_SUPPLY_SRC ... MAX98396_R210B_BPE_LOW_LIMITER: 790 case MAX98396_R210D_BPE_EN ... MAX98396_R210F_GLOBAL_EN: 791 case MAX98396_R21FF_REVISION_ID: 792 return true; 793 default: 794 return false; 795 } 796 }; 797 798 static bool max98396_volatile_reg(struct device *dev, unsigned int reg) 799 { 800 switch (reg) { 801 case MAX98396_R2000_SW_RESET: 802 case MAX98396_R2001_INT_RAW1 ... MAX98396_R200E_INT_FLAG4: 803 case MAX98396_R2041_PCM_MODE_CFG: 804 case MAX98396_R20B6_ADC_PVDD_READBACK_MSB 805 ... MAX98396_R20BF_ADC_LO_VBAT_READBACK_LSB: 806 case MAX98396_R20E5_BPE_STATE: 807 case MAX98396_R2109_BPE_LOW_STATE 808 ... MAX98396_R210B_BPE_LOW_LIMITER: 809 case MAX98396_R210F_GLOBAL_EN: 810 case MAX98396_R21FF_REVISION_ID: 811 return true; 812 default: 813 return false; 814 } 815 } 816 817 static bool max98397_readable_register(struct device *dev, unsigned int reg) 818 { 819 switch (reg) { 820 case MAX98396_R2001_INT_RAW1 ... MAX98396_R2004_INT_RAW4: 821 case MAX98396_R2006_INT_STATE1 ... MAX98396_R2009_INT_STATE4: 822 case MAX98396_R200B_INT_FLAG1 ... MAX98396_R200E_INT_FLAG4: 823 case MAX98396_R2010_INT_EN1 ... MAX98396_R2013_INT_EN4: 824 case MAX98396_R2015_INT_FLAG_CLR1 ... MAX98396_R2018_INT_FLAG_CLR4: 825 case MAX98396_R201F_IRQ_CTRL ... MAX98396_R2024_THERM_FOLDBACK_SET: 826 case MAX98396_R2027_THERM_FOLDBACK_EN: 827 case MAX98396_R2030_NOISEGATE_MODE_CTRL: 828 case MAX98396_R2033_NOISEGATE_MODE_EN: 829 case MAX98396_R2038_CLK_MON_CTRL ... MAX98397_R203A_SPK_MON_THRESH: 830 case MAX98396_R203F_ENABLE_CTRLS ... MAX98397_R2054_PCM_TX_HIZ_CTRL_8: 831 case MAX98397_R2056_PCM_RX_SRC1... MAX98396_R2058_PCM_BYPASS_SRC: 832 case MAX98396_R205D_PCM_TX_SRC_EN ... MAX98397_R2060_PCM_TX_SUPPLY_SEL: 833 case MAX98396_R2070_ICC_RX_EN_A... MAX98396_R2072_ICC_TX_CTRL: 834 case MAX98396_R207F_ICC_EN: 835 case MAX98396_R2083_TONE_GEN_DC_CFG ... MAX98396_R2086_TONE_GEN_DC_LVL3: 836 case MAX98396_R208F_TONE_GEN_EN ... MAX98396_R209F_BYPASS_PATH_CFG: 837 case MAX98396_R20AF_AMP_EN ... MAX98397_R20C5_MEAS_ADC_OPTIMAL_MODE: 838 case MAX98396_R20C7_ADC_CFG: 839 case MAX98396_R20D0_DHT_CFG1 ... MAX98396_R20D6_DHT_HYSTERESIS_CFG: 840 case MAX98396_R20DF_DHT_EN: 841 case MAX98396_R20E0_IV_SENSE_PATH_CFG: 842 case MAX98396_R20E4_IV_SENSE_PATH_EN 843 ... MAX98396_R2106_BPE_THRESH_HYSTERESIS: 844 case MAX98396_R2108_BPE_SUPPLY_SRC ... MAX98396_R210B_BPE_LOW_LIMITER: 845 case MAX98396_R210D_BPE_EN ... MAX98396_R210F_GLOBAL_EN: 846 case MAX98397_R22FF_REVISION_ID: 847 return true; 848 default: 849 return false; 850 } 851 }; 852 853 static bool max98397_volatile_reg(struct device *dev, unsigned int reg) 854 { 855 switch (reg) { 856 case MAX98396_R2001_INT_RAW1 ... MAX98396_R200E_INT_FLAG4: 857 case MAX98396_R2041_PCM_MODE_CFG: 858 case MAX98397_R20B7_ADC_PVDD_READBACK_MSB 859 ... MAX98397_R20C4_ADC_LO_VDDH_READBACK_LSB: 860 case MAX98396_R20E5_BPE_STATE: 861 case MAX98396_R2109_BPE_LOW_STATE 862 ... MAX98396_R210B_BPE_LOW_LIMITER: 863 case MAX98396_R210F_GLOBAL_EN: 864 case MAX98397_R22FF_REVISION_ID: 865 return true; 866 default: 867 return false; 868 } 869 } 870 871 static const char * const max98396_op_mod_text[] = { 872 "DG", "PVDD", "VBAT", 873 }; 874 875 static SOC_ENUM_SINGLE_DECL(max98396_op_mod_enum, 876 MAX98396_R2098_SPK_CLS_DG_MODE, 877 0, max98396_op_mod_text); 878 879 static DECLARE_TLV_DB_SCALE(max98396_digital_tlv, -6350, 50, 1); 880 static const DECLARE_TLV_DB_RANGE(max98396_spk_tlv, 881 0, 0x11, TLV_DB_SCALE_ITEM(400, 100, 0), 882 ); 883 static DECLARE_TLV_DB_RANGE(max98397_digital_tlv, 884 0, 0x4A, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 885 0x4B, 0xFF, TLV_DB_SCALE_ITEM(-9000, 50, 0), 886 ); 887 static const DECLARE_TLV_DB_RANGE(max98397_spk_tlv, 888 0, 0x15, TLV_DB_SCALE_ITEM(600, 100, 0), 889 ); 890 891 static int max98396_mux_get(struct snd_kcontrol *kcontrol, 892 struct snd_ctl_elem_value *ucontrol) 893 { 894 struct snd_soc_component *component = 895 snd_soc_dapm_kcontrol_component(kcontrol); 896 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 897 int reg, val; 898 899 if (max98396->device_id == CODEC_TYPE_MAX98396) 900 reg = MAX98396_R2055_PCM_RX_SRC1; 901 else 902 reg = MAX98397_R2056_PCM_RX_SRC1; 903 904 regmap_read(max98396->regmap, reg, &val); 905 906 ucontrol->value.enumerated.item[0] = val; 907 908 return 0; 909 } 910 911 static int max98396_mux_put(struct snd_kcontrol *kcontrol, 912 struct snd_ctl_elem_value *ucontrol) 913 { 914 struct snd_soc_component *component = 915 snd_soc_dapm_kcontrol_component(kcontrol); 916 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol); 917 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 918 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 919 unsigned int *item = ucontrol->value.enumerated.item; 920 int reg, val; 921 int change; 922 923 if (item[0] >= e->items) 924 return -EINVAL; 925 926 val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l; 927 928 if (max98396->device_id == CODEC_TYPE_MAX98396) 929 reg = MAX98396_R2055_PCM_RX_SRC1; 930 else 931 reg = MAX98397_R2056_PCM_RX_SRC1; 932 933 change = snd_soc_component_test_bits(component, reg, 934 MAX98396_PCM_RX_MASK, val); 935 936 if (change) 937 regmap_update_bits(max98396->regmap, reg, 938 MAX98396_PCM_RX_MASK, val); 939 940 snd_soc_dapm_mux_update_power(dapm, kcontrol, item[0], e, NULL); 941 942 return change; 943 } 944 945 static const char * const max98396_switch_text[] = { 946 "Left", "Right", "LeftRight"}; 947 948 static SOC_ENUM_SINGLE_DECL(dai_sel_enum, SND_SOC_NOPM, 0, 949 max98396_switch_text); 950 951 static const struct snd_kcontrol_new max98396_dai_mux = 952 SOC_DAPM_ENUM_EXT("DAI Sel Mux", dai_sel_enum, 953 max98396_mux_get, max98396_mux_put); 954 955 static const struct snd_kcontrol_new max98396_vi_control = 956 SOC_DAPM_SINGLE("Switch", MAX98396_R205F_PCM_TX_EN, 0, 1, 0); 957 958 static const struct snd_soc_dapm_widget max98396_dapm_widgets[] = { 959 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", 960 MAX98396_R20AF_AMP_EN, 0, 0, max98396_dac_event, 961 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD), 962 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, 963 &max98396_dai_mux), 964 SND_SOC_DAPM_OUTPUT("BE_OUT"), 965 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0, 966 MAX98396_R20E4_IV_SENSE_PATH_EN, 0, 0), 967 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0, 968 MAX98396_R20E4_IV_SENSE_PATH_EN, 1, 0), 969 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0, 970 &max98396_vi_control), 971 SND_SOC_DAPM_SIGGEN("VMON"), 972 SND_SOC_DAPM_SIGGEN("IMON"), 973 SND_SOC_DAPM_SIGGEN("FBMON"), 974 }; 975 976 static const char * const max98396_thermal_thresh_text[] = { 977 "50C", "51C", "52C", "53C", "54C", "55C", "56C", "57C", 978 "58C", "59C", "60C", "61C", "62C", "63C", "64C", "65C", 979 "66C", "67C", "68C", "69C", "70C", "71C", "72C", "73C", 980 "74C", "75C", "76C", "77C", "78C", "79C", "80C", "81C", 981 "82C", "83C", "84C", "85C", "86C", "87C", "88C", "89C", 982 "90C", "91C", "92C", "93C", "94C", "95C", "96C", "97C", 983 "98C", "99C", "100C", "101C", "102C", "103C", "104C", "105C", 984 "106C", "107C", "108C", "109C", "110C", "111C", "112C", "113C", 985 "114C", "115C", "116C", "117C", "118C", "119C", "120C", "121C", 986 "122C", "123C", "124C", "125C", "126C", "127C", "128C", "129C", 987 "130C", "131C", "132C", "133C", "134C", "135C", "136C", "137C", 988 "138C", "139C", "140C", "141C", "142C", "143C", "144C", "145C", 989 "146C", "147C", "148C", "149C", "150C" 990 }; 991 992 static SOC_ENUM_SINGLE_DECL(max98396_thermal_warn_thresh1_enum, 993 MAX98396_R2020_THERM_WARN_THRESH, 0, 994 max98396_thermal_thresh_text); 995 996 static SOC_ENUM_SINGLE_DECL(max98396_thermal_warn_thresh2_enum, 997 MAX98396_R2021_THERM_WARN_THRESH2, 0, 998 max98396_thermal_thresh_text); 999 1000 static SOC_ENUM_SINGLE_DECL(max98396_thermal_shdn_thresh_enum, 1001 MAX98396_R2022_THERM_SHDN_THRESH, 0, 1002 max98396_thermal_thresh_text); 1003 1004 static const char * const max98396_thermal_hyteresis_text[] = { 1005 "2C", "5C", "7C", "10C" 1006 }; 1007 1008 static SOC_ENUM_SINGLE_DECL(max98396_thermal_hysteresis_enum, 1009 MAX98396_R2023_THERM_HYSTERESIS, 0, 1010 max98396_thermal_hyteresis_text); 1011 1012 static const char * const max98396_foldback_slope_text[] = { 1013 "0.25", "0.5", "1.0", "2.0" 1014 }; 1015 1016 static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_slope1_enum, 1017 MAX98396_R2024_THERM_FOLDBACK_SET, 1018 MAX98396_THERM_FB_SLOPE1_SHIFT, 1019 max98396_foldback_slope_text); 1020 1021 static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_slope2_enum, 1022 MAX98396_R2024_THERM_FOLDBACK_SET, 1023 MAX98396_THERM_FB_SLOPE2_SHIFT, 1024 max98396_foldback_slope_text); 1025 1026 static const char * const max98396_foldback_reltime_text[] = { 1027 "3ms", "10ms", "100ms", "300ms" 1028 }; 1029 1030 static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_reltime_enum, 1031 MAX98396_R2024_THERM_FOLDBACK_SET, 1032 MAX98396_THERM_FB_REL_SHIFT, 1033 max98396_foldback_reltime_text); 1034 1035 static const char * const max98396_foldback_holdtime_text[] = { 1036 "0ms", "20ms", "40ms", "80ms" 1037 }; 1038 1039 static SOC_ENUM_SINGLE_DECL(max98396_thermal_fb_holdtime_enum, 1040 MAX98396_R2024_THERM_FOLDBACK_SET, 1041 MAX98396_THERM_FB_HOLD_SHIFT, 1042 max98396_foldback_holdtime_text); 1043 1044 static int max98396_adc_value_get(struct snd_kcontrol *kcontrol, 1045 struct snd_ctl_elem_value *ucontrol) 1046 { 1047 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1048 struct soc_mixer_control *mc = 1049 (struct soc_mixer_control *)kcontrol->private_value; 1050 struct max98396_priv *max98396 = snd_soc_component_get_drvdata(component); 1051 int ret; 1052 u8 val[2]; 1053 int reg = mc->reg; 1054 1055 /* ADC value is not available if the device is powered down */ 1056 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 1057 goto exit; 1058 1059 if (max98396->device_id == CODEC_TYPE_MAX98397) { 1060 switch (mc->reg) { 1061 case MAX98396_R20B6_ADC_PVDD_READBACK_MSB: 1062 reg = MAX98397_R20B7_ADC_PVDD_READBACK_MSB; 1063 break; 1064 case MAX98396_R20B8_ADC_VBAT_READBACK_MSB: 1065 reg = MAX98397_R20B9_ADC_VBAT_READBACK_MSB; 1066 break; 1067 case MAX98396_R20BA_ADC_TEMP_READBACK_MSB: 1068 reg = MAX98397_R20BB_ADC_TEMP_READBACK_MSB; 1069 break; 1070 default: 1071 goto exit; 1072 } 1073 } 1074 1075 ret = regmap_raw_read(max98396->regmap, reg, &val, 2); 1076 if (ret) 1077 goto exit; 1078 1079 /* ADC readback bits[8:0] rearrangement */ 1080 ucontrol->value.integer.value[0] = (val[0] << 1) | (val[1] & 1); 1081 return 0; 1082 1083 exit: 1084 ucontrol->value.integer.value[0] = 0; 1085 return 0; 1086 } 1087 1088 static const struct snd_kcontrol_new max98396_snd_controls[] = { 1089 /* Volume */ 1090 SOC_SINGLE_TLV("Digital Volume", MAX98396_R2090_AMP_VOL_CTRL, 1091 0, 0x7F, 1, max98396_digital_tlv), 1092 SOC_SINGLE_TLV("Speaker Volume", MAX98396_R2091_AMP_PATH_GAIN, 1093 0, 0x11, 0, max98396_spk_tlv), 1094 /* Volume Ramp Up/Down Enable*/ 1095 SOC_SINGLE("Ramp Up Switch", MAX98396_R2092_AMP_DSP_CFG, 1096 MAX98396_DSP_SPK_VOL_RMPUP_SHIFT, 1, 0), 1097 SOC_SINGLE("Ramp Down Switch", MAX98396_R2092_AMP_DSP_CFG, 1098 MAX98396_DSP_SPK_VOL_RMPDN_SHIFT, 1, 0), 1099 /* Clock Monitor Enable */ 1100 SOC_SINGLE("CLK Monitor Switch", MAX98396_R203F_ENABLE_CTRLS, 1101 MAX98396_CTRL_CMON_EN_SHIFT, 1, 0), 1102 /* Dither Enable */ 1103 SOC_SINGLE("Dither Switch", MAX98396_R2092_AMP_DSP_CFG, 1104 MAX98396_DSP_SPK_DITH_EN_SHIFT, 1, 0), 1105 SOC_SINGLE("IV Dither Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1106 MAX98396_IV_SENSE_DITH_EN_SHIFT, 1, 0), 1107 /* DC Blocker Enable */ 1108 SOC_SINGLE("DC Blocker Switch", MAX98396_R2092_AMP_DSP_CFG, 1109 MAX98396_DSP_SPK_DCBLK_EN_SHIFT, 1, 0), 1110 SOC_SINGLE("IV DC Blocker Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1111 MAX98396_IV_SENSE_DCBLK_EN_SHIFT, 3, 0), 1112 /* Speaker Safe Mode Enable */ 1113 SOC_SINGLE("Safe Mode Switch", MAX98396_R2092_AMP_DSP_CFG, 1114 MAX98396_DSP_SPK_SAFE_EN_SHIFT, 1, 0), 1115 /* Wideband Filter Enable */ 1116 SOC_SINGLE("WB Filter Switch", MAX98396_R2092_AMP_DSP_CFG, 1117 MAX98396_DSP_SPK_WB_FLT_EN_SHIFT, 1, 0), 1118 SOC_SINGLE("IV WB Filter Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1119 MAX98396_IV_SENSE_WB_FLT_EN_SHIFT, 1, 0), 1120 /* Dynamic Headroom Tracking */ 1121 SOC_SINGLE("DHT Switch", MAX98396_R20DF_DHT_EN, 0, 1, 0), 1122 /* Brownout Protection Engine */ 1123 SOC_SINGLE("BPE Switch", MAX98396_R210D_BPE_EN, 0, 1, 0), 1124 SOC_SINGLE("BPE Limiter Switch", MAX98396_R210D_BPE_EN, 1, 1, 0), 1125 /* Bypass Path Enable */ 1126 SOC_SINGLE("Bypass Path Switch", 1127 MAX98396_R205E_PCM_RX_EN, 1, 1, 0), 1128 /* Speaker Operation Mode */ 1129 SOC_ENUM("OP Mode", max98396_op_mod_enum), 1130 /* Auto Restart functions */ 1131 SOC_SINGLE("CMON Auto Restart Switch", MAX98396_R2038_CLK_MON_CTRL, 1132 MAX98396_CLK_MON_AUTO_RESTART_SHIFT, 1, 0), 1133 SOC_SINGLE("PVDD Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1134 MAX98396_PVDD_UVLO_RESTART_SHFT, 1, 0), 1135 SOC_SINGLE("VBAT Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1136 MAX98396_VBAT_UVLO_RESTART_SHFT, 1, 0), 1137 SOC_SINGLE("THERM Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1138 MAX98396_THEM_SHDN_RESTART_SHFT, 1, 0), 1139 SOC_SINGLE("OVC Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1140 MAX98396_OVC_RESTART_SHFT, 1, 0), 1141 /* Thermal Threshold */ 1142 SOC_ENUM("THERM Thresh1", max98396_thermal_warn_thresh1_enum), 1143 SOC_ENUM("THERM Thresh2", max98396_thermal_warn_thresh2_enum), 1144 SOC_ENUM("THERM SHDN Thresh", max98396_thermal_shdn_thresh_enum), 1145 SOC_ENUM("THERM Hysteresis", max98396_thermal_hysteresis_enum), 1146 SOC_SINGLE("THERM Foldback Switch", 1147 MAX98396_R2027_THERM_FOLDBACK_EN, 0, 1, 0), 1148 SOC_ENUM("THERM Slope1", max98396_thermal_fb_slope1_enum), 1149 SOC_ENUM("THERM Slope2", max98396_thermal_fb_slope2_enum), 1150 SOC_ENUM("THERM Release", max98396_thermal_fb_reltime_enum), 1151 SOC_ENUM("THERM Hold", max98396_thermal_fb_holdtime_enum), 1152 /* ADC */ 1153 SOC_SINGLE_EXT("ADC PVDD", MAX98396_R20B6_ADC_PVDD_READBACK_MSB, 0, 0x1FF, 0, 1154 max98396_adc_value_get, NULL), 1155 SOC_SINGLE_EXT("ADC VBAT", MAX98396_R20B8_ADC_VBAT_READBACK_MSB, 0, 0x1FF, 0, 1156 max98396_adc_value_get, NULL), 1157 SOC_SINGLE_EXT("ADC TEMP", MAX98396_R20BA_ADC_TEMP_READBACK_MSB, 0, 0x1FF, 0, 1158 max98396_adc_value_get, NULL), 1159 }; 1160 1161 static const struct snd_kcontrol_new max98397_snd_controls[] = { 1162 /* Volume */ 1163 SOC_SINGLE_TLV("Digital Volume", MAX98396_R2090_AMP_VOL_CTRL, 1164 0, 0xFF, 1, max98397_digital_tlv), 1165 SOC_SINGLE_TLV("Speaker Volume", MAX98396_R2091_AMP_PATH_GAIN, 1166 0, 0x15, 0, max98397_spk_tlv), 1167 /* Volume Ramp Up/Down Enable*/ 1168 SOC_SINGLE("Ramp Up Switch", MAX98396_R2092_AMP_DSP_CFG, 1169 MAX98396_DSP_SPK_VOL_RMPUP_SHIFT, 1, 0), 1170 SOC_SINGLE("Ramp Down Switch", MAX98396_R2092_AMP_DSP_CFG, 1171 MAX98396_DSP_SPK_VOL_RMPDN_SHIFT, 1, 0), 1172 /* Clock Monitor Enable */ 1173 SOC_SINGLE("CLK Monitor Switch", MAX98396_R203F_ENABLE_CTRLS, 1174 MAX98396_CTRL_CMON_EN_SHIFT, 1, 0), 1175 /* Dither Enable */ 1176 SOC_SINGLE("Dither Switch", MAX98396_R2092_AMP_DSP_CFG, 1177 MAX98396_DSP_SPK_DITH_EN_SHIFT, 1, 0), 1178 SOC_SINGLE("IV Dither Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1179 MAX98396_IV_SENSE_DITH_EN_SHIFT, 1, 0), 1180 /* DC Blocker Enable */ 1181 SOC_SINGLE("DC Blocker Switch", MAX98396_R2092_AMP_DSP_CFG, 1182 MAX98396_DSP_SPK_DCBLK_EN_SHIFT, 1, 0), 1183 SOC_SINGLE("IV DC Blocker Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1184 MAX98396_IV_SENSE_DCBLK_EN_SHIFT, 3, 0), 1185 /* Speaker Safe Mode Enable */ 1186 SOC_SINGLE("Safe Mode Switch", MAX98396_R2092_AMP_DSP_CFG, 1187 MAX98396_DSP_SPK_SAFE_EN_SHIFT, 1, 0), 1188 /* Wideband Filter Enable */ 1189 SOC_SINGLE("WB Filter Switch", MAX98396_R2092_AMP_DSP_CFG, 1190 MAX98396_DSP_SPK_WB_FLT_EN_SHIFT, 1, 0), 1191 SOC_SINGLE("IV WB Filter Switch", MAX98396_R20E0_IV_SENSE_PATH_CFG, 1192 MAX98396_IV_SENSE_WB_FLT_EN_SHIFT, 1, 0), 1193 /* Dynamic Headroom Tracking */ 1194 SOC_SINGLE("DHT Switch", MAX98396_R20DF_DHT_EN, 0, 1, 0), 1195 /* Brownout Protection Engine */ 1196 SOC_SINGLE("BPE Switch", MAX98396_R210D_BPE_EN, 0, 1, 0), 1197 SOC_SINGLE("BPE Limiter Switch", MAX98396_R210D_BPE_EN, 1, 1, 0), 1198 /* Bypass Path Enable */ 1199 SOC_SINGLE("Bypass Path Switch", 1200 MAX98396_R205E_PCM_RX_EN, 1, 1, 0), 1201 /* Speaker Operation Mode */ 1202 SOC_ENUM("OP Mode", max98396_op_mod_enum), 1203 /* Auto Restart functions */ 1204 SOC_SINGLE("CMON Auto Restart Switch", MAX98396_R2038_CLK_MON_CTRL, 1205 MAX98396_CLK_MON_AUTO_RESTART_SHIFT, 1, 0), 1206 SOC_SINGLE("PVDD Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1207 MAX98396_PVDD_UVLO_RESTART_SHFT, 1, 0), 1208 SOC_SINGLE("VBAT Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1209 MAX98396_VBAT_UVLO_RESTART_SHFT, 1, 0), 1210 SOC_SINGLE("THERM Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1211 MAX98396_THEM_SHDN_RESTART_SHFT, 1, 0), 1212 SOC_SINGLE("OVC Auto Restart Switch", MAX98396_R210E_AUTO_RESTART, 1213 MAX98396_OVC_RESTART_SHFT, 1, 0), 1214 /* Thermal Threshold */ 1215 SOC_ENUM("THERM Thresh1", max98396_thermal_warn_thresh1_enum), 1216 SOC_ENUM("THERM Thresh2", max98396_thermal_warn_thresh2_enum), 1217 SOC_ENUM("THERM SHDN Thresh", max98396_thermal_shdn_thresh_enum), 1218 SOC_ENUM("THERM Hysteresis", max98396_thermal_hysteresis_enum), 1219 SOC_SINGLE("THERM Foldback Switch", 1220 MAX98396_R2027_THERM_FOLDBACK_EN, 0, 1, 0), 1221 SOC_ENUM("THERM Slope1", max98396_thermal_fb_slope1_enum), 1222 SOC_ENUM("THERM Slope2", max98396_thermal_fb_slope2_enum), 1223 SOC_ENUM("THERM Release", max98396_thermal_fb_reltime_enum), 1224 SOC_ENUM("THERM Hold", max98396_thermal_fb_holdtime_enum), 1225 /* ADC */ 1226 SOC_SINGLE_EXT("ADC PVDD", MAX98396_R20B6_ADC_PVDD_READBACK_MSB, 0, 0x1FF, 0, 1227 max98396_adc_value_get, NULL), 1228 SOC_SINGLE_EXT("ADC VBAT", MAX98396_R20B8_ADC_VBAT_READBACK_MSB, 0, 0x1FF, 0, 1229 max98396_adc_value_get, NULL), 1230 SOC_SINGLE_EXT("ADC TEMP", MAX98396_R20BA_ADC_TEMP_READBACK_MSB, 0, 0x1FF, 0, 1231 max98396_adc_value_get, NULL), 1232 }; 1233 1234 static const struct snd_soc_dapm_route max98396_audio_map[] = { 1235 /* Plabyack */ 1236 {"DAI Sel Mux", "Left", "Amp Enable"}, 1237 {"DAI Sel Mux", "Right", "Amp Enable"}, 1238 {"DAI Sel Mux", "LeftRight", "Amp Enable"}, 1239 {"BE_OUT", NULL, "DAI Sel Mux"}, 1240 /* Capture */ 1241 { "VI Sense", "Switch", "VMON" }, 1242 { "VI Sense", "Switch", "IMON" }, 1243 { "Voltage Sense", NULL, "VI Sense" }, 1244 { "Current Sense", NULL, "VI Sense" }, 1245 }; 1246 1247 static struct snd_soc_dai_driver max98396_dai[] = { 1248 { 1249 .name = "max98396-aif1", 1250 .playback = { 1251 .stream_name = "HiFi Playback", 1252 .channels_min = 1, 1253 .channels_max = 2, 1254 .rates = MAX98396_RATES, 1255 .formats = MAX98396_FORMATS, 1256 }, 1257 .capture = { 1258 .stream_name = "HiFi Capture", 1259 .channels_min = 1, 1260 .channels_max = 2, 1261 .rates = MAX98396_RATES, 1262 .formats = MAX98396_FORMATS, 1263 }, 1264 .ops = &max98396_dai_ops, 1265 } 1266 }; 1267 1268 static struct snd_soc_dai_driver max98397_dai[] = { 1269 { 1270 .name = "max98397-aif1", 1271 .playback = { 1272 .stream_name = "HiFi Playback", 1273 .channels_min = 1, 1274 .channels_max = 2, 1275 .rates = MAX98396_RATES, 1276 .formats = MAX98396_FORMATS, 1277 }, 1278 .capture = { 1279 .stream_name = "HiFi Capture", 1280 .channels_min = 1, 1281 .channels_max = 2, 1282 .rates = MAX98396_RATES, 1283 .formats = MAX98396_FORMATS, 1284 }, 1285 .ops = &max98396_dai_ops, 1286 } 1287 }; 1288 1289 static void max98396_reset(struct max98396_priv *max98396, struct device *dev) 1290 { 1291 int ret, reg, count; 1292 1293 /* Software Reset */ 1294 ret = regmap_write(max98396->regmap, 1295 MAX98396_R2000_SW_RESET, 1); 1296 if (ret) 1297 dev_err(dev, "Reset command failed. (ret:%d)\n", ret); 1298 1299 count = 0; 1300 while (count < 3) { 1301 usleep_range(5000, 6000); 1302 /* Software Reset Verification */ 1303 ret = regmap_read(max98396->regmap, 1304 GET_REG_ADDR_REV_ID(max98396->device_id), ®); 1305 if (!ret) { 1306 dev_info(dev, "Reset completed (retry:%d)\n", count); 1307 return; 1308 } 1309 count++; 1310 } 1311 dev_err(dev, "Reset failed. (ret:%d)\n", ret); 1312 } 1313 1314 static int max98396_probe(struct snd_soc_component *component) 1315 { 1316 struct max98396_priv *max98396 = 1317 snd_soc_component_get_drvdata(component); 1318 1319 /* Software Reset */ 1320 max98396_reset(max98396, component->dev); 1321 1322 /* L/R mix configuration */ 1323 if (max98396->device_id == CODEC_TYPE_MAX98396) { 1324 regmap_write(max98396->regmap, 1325 MAX98396_R2055_PCM_RX_SRC1, 0x02); 1326 regmap_write(max98396->regmap, 1327 MAX98396_R2056_PCM_RX_SRC2, 0x10); 1328 } else { 1329 regmap_write(max98396->regmap, 1330 MAX98397_R2056_PCM_RX_SRC1, 0x02); 1331 regmap_write(max98396->regmap, 1332 MAX98397_R2057_PCM_RX_SRC2, 0x10); 1333 } 1334 /* Enable DC blocker */ 1335 regmap_update_bits(max98396->regmap, 1336 MAX98396_R2092_AMP_DSP_CFG, 1, 1); 1337 /* Enable IV Monitor DC blocker */ 1338 regmap_update_bits(max98396->regmap, 1339 MAX98396_R20E0_IV_SENSE_PATH_CFG, 1340 MAX98396_IV_SENSE_DCBLK_EN_MASK, 1341 MAX98396_IV_SENSE_DCBLK_EN_MASK); 1342 /* Configure default data output sources */ 1343 regmap_write(max98396->regmap, 1344 MAX98396_R205D_PCM_TX_SRC_EN, 3); 1345 /* Enable Wideband Filter */ 1346 regmap_update_bits(max98396->regmap, 1347 MAX98396_R2092_AMP_DSP_CFG, 0x40, 0x40); 1348 /* Enable IV Wideband Filter */ 1349 regmap_update_bits(max98396->regmap, 1350 MAX98396_R20E0_IV_SENSE_PATH_CFG, 8, 8); 1351 1352 /* Enable Bypass Source */ 1353 regmap_write(max98396->regmap, 1354 MAX98396_R2058_PCM_BYPASS_SRC, 1355 max98396->bypass_slot); 1356 /* Voltage, current slot configuration */ 1357 regmap_write(max98396->regmap, 1358 MAX98396_R2044_PCM_TX_CTRL_1, 1359 max98396->v_slot); 1360 regmap_write(max98396->regmap, 1361 MAX98396_R2045_PCM_TX_CTRL_2, 1362 max98396->i_slot); 1363 1364 if (max98396->v_slot < 8) 1365 if (max98396->device_id == CODEC_TYPE_MAX98396) 1366 regmap_update_bits(max98396->regmap, 1367 MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 1368 1 << max98396->v_slot, 0); 1369 else 1370 regmap_update_bits(max98396->regmap, 1371 MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 1372 1 << max98396->v_slot, 0); 1373 else 1374 if (max98396->device_id == CODEC_TYPE_MAX98396) 1375 regmap_update_bits(max98396->regmap, 1376 MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 1377 1 << (max98396->v_slot - 8), 0); 1378 else 1379 regmap_update_bits(max98396->regmap, 1380 MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 1381 1 << (max98396->v_slot - 8), 0); 1382 1383 if (max98396->i_slot < 8) 1384 if (max98396->device_id == CODEC_TYPE_MAX98396) 1385 regmap_update_bits(max98396->regmap, 1386 MAX98396_R2053_PCM_TX_HIZ_CTRL_8, 1387 1 << max98396->i_slot, 0); 1388 else 1389 regmap_update_bits(max98396->regmap, 1390 MAX98397_R2054_PCM_TX_HIZ_CTRL_8, 1391 1 << max98396->i_slot, 0); 1392 else 1393 if (max98396->device_id == CODEC_TYPE_MAX98396) 1394 regmap_update_bits(max98396->regmap, 1395 MAX98396_R2052_PCM_TX_HIZ_CTRL_7, 1396 1 << (max98396->i_slot - 8), 0); 1397 else 1398 regmap_update_bits(max98396->regmap, 1399 MAX98397_R2053_PCM_TX_HIZ_CTRL_7, 1400 1 << (max98396->i_slot - 8), 0); 1401 1402 /* Set interleave mode */ 1403 if (max98396->interleave_mode) 1404 regmap_update_bits(max98396->regmap, 1405 MAX98396_R2041_PCM_MODE_CFG, 1406 MAX98396_PCM_TX_CH_INTERLEAVE_MASK, 1407 MAX98396_PCM_TX_CH_INTERLEAVE_MASK); 1408 1409 regmap_update_bits(max98396->regmap, 1410 MAX98396_R2038_CLK_MON_CTRL, 1411 MAX98396_CLK_MON_AUTO_RESTART_MASK, 1412 MAX98396_CLK_MON_AUTO_RESTART_MASK); 1413 1414 /* Speaker Amplifier PCM RX Enable by default */ 1415 regmap_update_bits(max98396->regmap, 1416 MAX98396_R205E_PCM_RX_EN, 1417 MAX98396_PCM_RX_EN_MASK, 1); 1418 1419 return 0; 1420 } 1421 1422 #ifdef CONFIG_PM_SLEEP 1423 static int max98396_suspend(struct device *dev) 1424 { 1425 struct max98396_priv *max98396 = dev_get_drvdata(dev); 1426 1427 regcache_cache_only(max98396->regmap, true); 1428 regcache_mark_dirty(max98396->regmap); 1429 return 0; 1430 } 1431 1432 static int max98396_resume(struct device *dev) 1433 { 1434 struct max98396_priv *max98396 = dev_get_drvdata(dev); 1435 1436 regcache_cache_only(max98396->regmap, false); 1437 max98396_reset(max98396, dev); 1438 regcache_sync(max98396->regmap); 1439 return 0; 1440 } 1441 #endif 1442 1443 static const struct dev_pm_ops max98396_pm = { 1444 SET_SYSTEM_SLEEP_PM_OPS(max98396_suspend, max98396_resume) 1445 }; 1446 1447 static const struct snd_soc_component_driver soc_codec_dev_max98396 = { 1448 .probe = max98396_probe, 1449 .controls = max98396_snd_controls, 1450 .num_controls = ARRAY_SIZE(max98396_snd_controls), 1451 .dapm_widgets = max98396_dapm_widgets, 1452 .num_dapm_widgets = ARRAY_SIZE(max98396_dapm_widgets), 1453 .dapm_routes = max98396_audio_map, 1454 .num_dapm_routes = ARRAY_SIZE(max98396_audio_map), 1455 .idle_bias_on = 1, 1456 .use_pmdown_time = 1, 1457 .endianness = 1, 1458 .non_legacy_dai_naming = 1, 1459 }; 1460 1461 static const struct snd_soc_component_driver soc_codec_dev_max98397 = { 1462 .probe = max98396_probe, 1463 .controls = max98397_snd_controls, 1464 .num_controls = ARRAY_SIZE(max98397_snd_controls), 1465 .dapm_widgets = max98396_dapm_widgets, 1466 .num_dapm_widgets = ARRAY_SIZE(max98396_dapm_widgets), 1467 .dapm_routes = max98396_audio_map, 1468 .num_dapm_routes = ARRAY_SIZE(max98396_audio_map), 1469 .idle_bias_on = 1, 1470 .use_pmdown_time = 1, 1471 .endianness = 1, 1472 .non_legacy_dai_naming = 1, 1473 }; 1474 1475 static const struct regmap_config max98396_regmap = { 1476 .reg_bits = 16, 1477 .val_bits = 8, 1478 .max_register = MAX98396_R21FF_REVISION_ID, 1479 .reg_defaults = max98396_reg, 1480 .num_reg_defaults = ARRAY_SIZE(max98396_reg), 1481 .readable_reg = max98396_readable_register, 1482 .volatile_reg = max98396_volatile_reg, 1483 .cache_type = REGCACHE_RBTREE, 1484 }; 1485 1486 static const struct regmap_config max98397_regmap = { 1487 .reg_bits = 16, 1488 .val_bits = 8, 1489 .max_register = MAX98397_R22FF_REVISION_ID, 1490 .reg_defaults = max98397_reg, 1491 .num_reg_defaults = ARRAY_SIZE(max98397_reg), 1492 .readable_reg = max98397_readable_register, 1493 .volatile_reg = max98397_volatile_reg, 1494 .cache_type = REGCACHE_RBTREE, 1495 }; 1496 1497 static void max98396_read_device_property(struct device *dev, 1498 struct max98396_priv *max98396) 1499 { 1500 int value; 1501 1502 if (!device_property_read_u32(dev, "adi,vmon-slot-no", &value)) 1503 max98396->v_slot = value & 0xF; 1504 else 1505 max98396->v_slot = 0; 1506 1507 if (!device_property_read_u32(dev, "adi,imon-slot-no", &value)) 1508 max98396->i_slot = value & 0xF; 1509 else 1510 max98396->i_slot = 1; 1511 1512 if (!device_property_read_u32(dev, "adi,bypass-slot-no", &value)) 1513 max98396->bypass_slot = value & 0xF; 1514 else 1515 max98396->bypass_slot = 0; 1516 } 1517 1518 static int max98396_i2c_probe(struct i2c_client *i2c, 1519 const struct i2c_device_id *id) 1520 { 1521 struct max98396_priv *max98396 = NULL; 1522 int ret, reg; 1523 1524 max98396 = devm_kzalloc(&i2c->dev, sizeof(*max98396), GFP_KERNEL); 1525 1526 if (!max98396) { 1527 ret = -ENOMEM; 1528 return ret; 1529 } 1530 i2c_set_clientdata(i2c, max98396); 1531 1532 max98396->device_id = id->driver_data; 1533 1534 /* regmap initialization */ 1535 if (max98396->device_id == CODEC_TYPE_MAX98396) 1536 max98396->regmap = devm_regmap_init_i2c(i2c, &max98396_regmap); 1537 1538 else 1539 max98396->regmap = devm_regmap_init_i2c(i2c, &max98397_regmap); 1540 1541 if (IS_ERR(max98396->regmap)) { 1542 ret = PTR_ERR(max98396->regmap); 1543 dev_err(&i2c->dev, 1544 "Failed to allocate regmap: %d\n", ret); 1545 return ret; 1546 } 1547 1548 /* update interleave mode info */ 1549 if (device_property_read_bool(&i2c->dev, "adi,interleave_mode")) 1550 max98396->interleave_mode = true; 1551 else 1552 max98396->interleave_mode = false; 1553 1554 /* voltage/current slot & gpio configuration */ 1555 max98396_read_device_property(&i2c->dev, max98396); 1556 1557 /* Reset the Device */ 1558 max98396->reset_gpio = devm_gpiod_get_optional(&i2c->dev, 1559 "reset", GPIOD_OUT_HIGH); 1560 if (IS_ERR(max98396->reset_gpio)) { 1561 ret = PTR_ERR(max98396->reset_gpio); 1562 dev_err(&i2c->dev, "Unable to request GPIO pin: %d.\n", ret); 1563 return ret; 1564 } 1565 1566 if (max98396->reset_gpio) { 1567 usleep_range(5000, 6000); 1568 gpiod_set_value_cansleep(max98396->reset_gpio, 0); 1569 /* Wait for the hw reset done */ 1570 usleep_range(5000, 6000); 1571 } 1572 1573 ret = regmap_read(max98396->regmap, 1574 GET_REG_ADDR_REV_ID(max98396->device_id), ®); 1575 if (ret < 0) { 1576 dev_err(&i2c->dev, "%s: failed to read revision of the device.\n", id->name); 1577 return ret; 1578 } 1579 dev_info(&i2c->dev, "%s revision ID: 0x%02X\n", id->name, reg); 1580 1581 /* codec registration */ 1582 if (max98396->device_id == CODEC_TYPE_MAX98396) 1583 ret = devm_snd_soc_register_component(&i2c->dev, 1584 &soc_codec_dev_max98396, 1585 max98396_dai, 1586 ARRAY_SIZE(max98396_dai)); 1587 else 1588 ret = devm_snd_soc_register_component(&i2c->dev, 1589 &soc_codec_dev_max98397, 1590 max98397_dai, 1591 ARRAY_SIZE(max98397_dai)); 1592 if (ret < 0) 1593 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 1594 1595 return ret; 1596 } 1597 1598 static const struct i2c_device_id max98396_i2c_id[] = { 1599 { "max98396", CODEC_TYPE_MAX98396}, 1600 { "max98397", CODEC_TYPE_MAX98397}, 1601 { }, 1602 }; 1603 1604 MODULE_DEVICE_TABLE(i2c, max98396_i2c_id); 1605 1606 #if defined(CONFIG_OF) 1607 static const struct of_device_id max98396_of_match[] = { 1608 { .compatible = "adi,max98396", }, 1609 { .compatible = "adi,max98397", }, 1610 { } 1611 }; 1612 MODULE_DEVICE_TABLE(of, max98396_of_match); 1613 #endif 1614 1615 #ifdef CONFIG_ACPI 1616 static const struct acpi_device_id max98396_acpi_match[] = { 1617 { "ADS8396", 0 }, 1618 { "ADS8397", 0 }, 1619 {}, 1620 }; 1621 MODULE_DEVICE_TABLE(acpi, max98396_acpi_match); 1622 #endif 1623 1624 static struct i2c_driver max98396_i2c_driver = { 1625 .driver = { 1626 .name = "max98396", 1627 .of_match_table = of_match_ptr(max98396_of_match), 1628 .acpi_match_table = ACPI_PTR(max98396_acpi_match), 1629 .pm = &max98396_pm, 1630 }, 1631 .probe = max98396_i2c_probe, 1632 .id_table = max98396_i2c_id, 1633 }; 1634 1635 module_i2c_driver(max98396_i2c_driver) 1636 1637 MODULE_DESCRIPTION("ALSA SoC MAX98396 driver"); 1638 MODULE_AUTHOR("Ryan Lee <ryans.lee@analog.com>"); 1639 MODULE_LICENSE("GPL"); 1640