1*6a8e1d46SRyan Lee /* SPDX-License-Identifier: GPL-2.0 */ 2*6a8e1d46SRyan Lee /* 3*6a8e1d46SRyan Lee * max98388.h -- MAX98388 ALSA SoC audio driver header 4*6a8e1d46SRyan Lee * 5*6a8e1d46SRyan Lee * Copyright(c) 2022, Analog Devices Inc. 6*6a8e1d46SRyan Lee */ 7*6a8e1d46SRyan Lee 8*6a8e1d46SRyan Lee #ifndef _MAX98388_H 9*6a8e1d46SRyan Lee #define _MAX98388_H 10*6a8e1d46SRyan Lee 11*6a8e1d46SRyan Lee /* Device Status Registers */ 12*6a8e1d46SRyan Lee #define MAX98388_R2000_SW_RESET 0x2000 13*6a8e1d46SRyan Lee #define MAX98388_R2001_INT_RAW1 0x2001 14*6a8e1d46SRyan Lee #define MAX98388_R2002_INT_RAW2 0x2002 15*6a8e1d46SRyan Lee #define MAX98388_R2004_INT_STATE1 0x2004 16*6a8e1d46SRyan Lee #define MAX98388_R2005_INT_STATE2 0x2005 17*6a8e1d46SRyan Lee /* Thermal Protection Registers */ 18*6a8e1d46SRyan Lee #define MAX98388_R2020_THERM_WARN_THRESH 0x2020 19*6a8e1d46SRyan Lee /* Error Monitor */ 20*6a8e1d46SRyan Lee #define MAX98388_R2031_SPK_MON_THRESH 0x2031 21*6a8e1d46SRyan Lee #define MAX98388_R2032_SPK_MON_LD_SEL 0x2032 22*6a8e1d46SRyan Lee #define MAX98388_R2033_SPK_MON_DURATION 0x2033 23*6a8e1d46SRyan Lee #define MAX98388_R2037_ERR_MON_CTRL 0x2037 24*6a8e1d46SRyan Lee /* PCM Registers */ 25*6a8e1d46SRyan Lee #define MAX98388_R2040_PCM_MODE_CFG 0x2040 26*6a8e1d46SRyan Lee #define MAX98388_R2041_PCM_CLK_SETUP 0x2041 27*6a8e1d46SRyan Lee #define MAX98388_R2042_PCM_SR_SETUP 0x2042 28*6a8e1d46SRyan Lee #define MAX98388_R2044_PCM_TX_CTRL1 0x2044 29*6a8e1d46SRyan Lee #define MAX98388_R2045_PCM_TX_CTRL2 0x2045 30*6a8e1d46SRyan Lee #define MAX98388_R2050_PCM_TX_HIZ_CTRL1 0x2050 31*6a8e1d46SRyan Lee #define MAX98388_R2051_PCM_TX_HIZ_CTRL2 0x2051 32*6a8e1d46SRyan Lee #define MAX98388_R2052_PCM_TX_HIZ_CTRL3 0x2052 33*6a8e1d46SRyan Lee #define MAX98388_R2053_PCM_TX_HIZ_CTRL4 0x2053 34*6a8e1d46SRyan Lee #define MAX98388_R2054_PCM_TX_HIZ_CTRL5 0x2054 35*6a8e1d46SRyan Lee #define MAX98388_R2055_PCM_TX_HIZ_CTRL6 0x2055 36*6a8e1d46SRyan Lee #define MAX98388_R2056_PCM_TX_HIZ_CTRL7 0x2056 37*6a8e1d46SRyan Lee #define MAX98388_R2057_PCM_TX_HIZ_CTRL8 0x2057 38*6a8e1d46SRyan Lee #define MAX98388_R2058_PCM_RX_SRC1 0x2058 39*6a8e1d46SRyan Lee #define MAX98388_R2059_PCM_RX_SRC2 0x2059 40*6a8e1d46SRyan Lee #define MAX98388_R205C_PCM_TX_DRIVE_STRENGTH 0x205C 41*6a8e1d46SRyan Lee #define MAX98388_R205D_PCM_TX_SRC_EN 0x205D 42*6a8e1d46SRyan Lee #define MAX98388_R205E_PCM_RX_EN 0x205E 43*6a8e1d46SRyan Lee #define MAX98388_R205F_PCM_TX_EN 0x205F 44*6a8e1d46SRyan Lee /* Speaker Channel Control */ 45*6a8e1d46SRyan Lee #define MAX98388_R2090_SPK_CH_VOL_CTRL 0x2090 46*6a8e1d46SRyan Lee #define MAX98388_R2091_SPK_CH_CFG 0x2091 47*6a8e1d46SRyan Lee #define MAX98388_R2092_SPK_AMP_OUT_CFG 0x2092 48*6a8e1d46SRyan Lee #define MAX98388_R2093_SPK_AMP_SSM_CFG 0x2093 49*6a8e1d46SRyan Lee #define MAX98388_R2094_SPK_AMP_ER_CTRL 0x2094 50*6a8e1d46SRyan Lee #define MAX98388_R209E_SPK_CH_PINK_NOISE_EN 0x209E 51*6a8e1d46SRyan Lee #define MAX98388_R209F_SPK_CH_AMP_EN 0x209F 52*6a8e1d46SRyan Lee #define MAX98388_R20A0_IV_DATA_DSP_CTRL 0x20A0 53*6a8e1d46SRyan Lee #define MAX98388_R20A7_IV_DATA_EN 0x20A7 54*6a8e1d46SRyan Lee #define MAX98388_R20E0_BP_ALC_THRESH 0x20E0 55*6a8e1d46SRyan Lee #define MAX98388_R20E1_BP_ALC_RATES 0x20E1 56*6a8e1d46SRyan Lee #define MAX98388_R20E2_BP_ALC_ATTEN 0x20E2 57*6a8e1d46SRyan Lee #define MAX98388_R20E3_BP_ALC_REL 0x20E3 58*6a8e1d46SRyan Lee #define MAX98388_R20E4_BP_ALC_MUTE 0x20E4 59*6a8e1d46SRyan Lee #define MAX98388_R20EE_BP_INF_HOLD_REL 0x20EE 60*6a8e1d46SRyan Lee #define MAX98388_R20EF_BP_ALC_EN 0x20EF 61*6a8e1d46SRyan Lee #define MAX98388_R210E_AUTO_RESTART 0x210E 62*6a8e1d46SRyan Lee #define MAX98388_R210F_GLOBAL_EN 0x210F 63*6a8e1d46SRyan Lee #define MAX98388_R22FF_REV_ID 0x22FF 64*6a8e1d46SRyan Lee 65*6a8e1d46SRyan Lee /* MAX98388_R2000_SW_RESET */ 66*6a8e1d46SRyan Lee #define MAX98388_SOFT_RESET (0x1 << 0) 67*6a8e1d46SRyan Lee 68*6a8e1d46SRyan Lee /* MAX98388_R2020_THERM_WARN_THRESH */ 69*6a8e1d46SRyan Lee #define MAX98388_THERM_SHDN_THRESH_SHIFT (0) 70*6a8e1d46SRyan Lee #define MAX98388_THERM_WARN_THRESH_SHIFT (2) 71*6a8e1d46SRyan Lee 72*6a8e1d46SRyan Lee /* MAX98388_R2022_PCM_TX_SRC_1 */ 73*6a8e1d46SRyan Lee #define MAX98388_PCM_TX_CH_SRC_A_V_SHIFT (0) 74*6a8e1d46SRyan Lee #define MAX98388_PCM_TX_CH_SRC_A_I_SHIFT (4) 75*6a8e1d46SRyan Lee 76*6a8e1d46SRyan Lee /* MAX98388_R2024_PCM_DATA_FMT_CFG */ 77*6a8e1d46SRyan Lee #define MAX98388_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3) 78*6a8e1d46SRyan Lee #define MAX98388_PCM_MODE_CFG_FORMAT_SHIFT (3) 79*6a8e1d46SRyan Lee #define MAX98388_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 2) 80*6a8e1d46SRyan Lee #define MAX98388_PCM_FORMAT_I2S (0x0 << 0) 81*6a8e1d46SRyan Lee #define MAX98388_PCM_FORMAT_LJ (0x1 << 0) 82*6a8e1d46SRyan Lee #define MAX98388_PCM_FORMAT_TDM_MODE0 (0x3 << 0) 83*6a8e1d46SRyan Lee #define MAX98388_PCM_FORMAT_TDM_MODE1 (0x4 << 0) 84*6a8e1d46SRyan Lee #define MAX98388_PCM_FORMAT_TDM_MODE2 (0x5 << 0) 85*6a8e1d46SRyan Lee #define MAX98388_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6) 86*6a8e1d46SRyan Lee #define MAX98388_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6) 87*6a8e1d46SRyan Lee #define MAX98388_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6) 88*6a8e1d46SRyan Lee #define MAX98388_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6) 89*6a8e1d46SRyan Lee 90*6a8e1d46SRyan Lee /* MAX98388_R2031_SPK_MON_THRESH */ 91*6a8e1d46SRyan Lee #define MAX98388_SPKMON_THRESH_SHIFT (0) 92*6a8e1d46SRyan Lee 93*6a8e1d46SRyan Lee /* MAX98388_R2032_SPK_MON_LD_SEL */ 94*6a8e1d46SRyan Lee #define MAX98388_SPKMON_LOAD_SHIFT (0) 95*6a8e1d46SRyan Lee 96*6a8e1d46SRyan Lee /* MAX98388_R2033_SPK_MON_DURATION */ 97*6a8e1d46SRyan Lee #define MAX98388_SPKMON_DURATION_SHIFT (0) 98*6a8e1d46SRyan Lee 99*6a8e1d46SRyan Lee /* MAX98388_R2037_ERR_MON_CTRL */ 100*6a8e1d46SRyan Lee #define MAX98388_CLOCK_MON_SHIFT (0) 101*6a8e1d46SRyan Lee #define MAX98388_SPK_MON_SHIFT (1) 102*6a8e1d46SRyan Lee 103*6a8e1d46SRyan Lee /* MAX98388_R203E_AMP_PATH_GAIN */ 104*6a8e1d46SRyan Lee #define MAX98388_SPK_DIGI_GAIN_MASK (0xF << 4) 105*6a8e1d46SRyan Lee #define MAX98388_SPK_DIGI_GAIN_SHIFT (4) 106*6a8e1d46SRyan Lee #define MAX98388_FS_GAIN_MAX_MASK (0xF << 0) 107*6a8e1d46SRyan Lee #define MAX98388_FS_GAIN_MAX_SHIFT (0) 108*6a8e1d46SRyan Lee 109*6a8e1d46SRyan Lee /* MAX98388_R2041_PCM_CLK_SETUP */ 110*6a8e1d46SRyan Lee #define MAX98388_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 4) 111*6a8e1d46SRyan Lee #define MAX98388_PCM_CLK_SETUP_BSEL_MASK (0xF << 0) 112*6a8e1d46SRyan Lee 113*6a8e1d46SRyan Lee /* MAX98388_R2042_PCM_SR_SETUP */ 114*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_MASK (0xF << 0) 115*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_IV_MASK (0xF << 4) 116*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_IV_SHIFT (4) 117*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_8000 (0x0 << 0) 118*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_11025 (0x1 << 0) 119*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_12000 (0x2 << 0) 120*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_16000 (0x3 << 0) 121*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_22050 (0x4 << 0) 122*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_24000 (0x5 << 0) 123*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_32000 (0x6 << 0) 124*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_44100 (0x7 << 0) 125*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_48000 (0x8 << 0) 126*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_88200 (0x9 << 0) 127*6a8e1d46SRyan Lee #define MAX98388_PCM_SR_96000 (0xA << 0) 128*6a8e1d46SRyan Lee 129*6a8e1d46SRyan Lee /* MAX98388_R2043_AMP_EN */ 130*6a8e1d46SRyan Lee #define MAX98388_SPK_EN_MASK (0x1 << 0) 131*6a8e1d46SRyan Lee #define MAX98388_SPKFB_EN_MASK (0x1 << 1) 132*6a8e1d46SRyan Lee #define MAX98388_SPKFB_EN_SHIFT (1) 133*6a8e1d46SRyan Lee 134*6a8e1d46SRyan Lee /* MAX98388_R2052_MEAS_ADC_PVDD_FLT_CFG */ 135*6a8e1d46SRyan Lee #define MAX98388_FLT_EN_SHIFT (4) 136*6a8e1d46SRyan Lee 137*6a8e1d46SRyan Lee /* MAX98388_R2058_PCM_RX_SRC1 */ 138*6a8e1d46SRyan Lee #define MAX98388_PCM_TO_SPK_MONOMIX_CFG_SHIFT (0) 139*6a8e1d46SRyan Lee 140*6a8e1d46SRyan Lee /* MAX98388_R2059_PCM_RX_SRC2 */ 141*6a8e1d46SRyan Lee #define MAX98388_RX_SRC_CH0_SHIFT (0) 142*6a8e1d46SRyan Lee #define MAX98388_RX_SRC_CH1_SHIFT (4) 143*6a8e1d46SRyan Lee 144*6a8e1d46SRyan Lee /* MAX98388_R2091_SPK_CH_CFG */ 145*6a8e1d46SRyan Lee #define MAX98388_SPK_CFG_DCBLK_SHIFT (0) 146*6a8e1d46SRyan Lee #define MAX98388_SPK_CFG_DITH_EN_SHIFT (1) 147*6a8e1d46SRyan Lee #define MAX98388_SPK_CFG_INV_SHIFT (2) 148*6a8e1d46SRyan Lee #define MAX98388_SPK_CFG_VOL_RMPUP_SHIFT (3) 149*6a8e1d46SRyan Lee #define MAX98388_SPK_CFG_VOL_RMPDN_SHIFT (4) 150*6a8e1d46SRyan Lee 151*6a8e1d46SRyan Lee /* MAX98388_R2092_SPK_AMP_OUT_CFG */ 152*6a8e1d46SRyan Lee #define MAX98388_SPK_AMP_OUT_GAIN_SHIFT (0) 153*6a8e1d46SRyan Lee #define MAX98388_SPK_AMP_OUT_MODE_SHIFT (3) 154*6a8e1d46SRyan Lee 155*6a8e1d46SRyan Lee /* MAX98388_R2093_SPK_AMP_SSM_CFG */ 156*6a8e1d46SRyan Lee #define MAX98388_SPK_AMP_SSM_EN_SHIFT (0) 157*6a8e1d46SRyan Lee #define MAX98388_SPK_AMP_SSM_MOD_SHIFT (1) 158*6a8e1d46SRyan Lee 159*6a8e1d46SRyan Lee /* MAX98388_R2094_SPK_AMP_ER_CTRL */ 160*6a8e1d46SRyan Lee #define MAX98388_EDGE_RATE_RISE_SHIFT (0) 161*6a8e1d46SRyan Lee #define MAX98388_EDGE_RATE_FALL_SHIFT (2) 162*6a8e1d46SRyan Lee 163*6a8e1d46SRyan Lee /* MAX98388_R209E_SPK_CH_PINK_NOISE_EN */ 164*6a8e1d46SRyan Lee #define MAX98388_PINK_NOISE_GEN_SHIFT (0) 165*6a8e1d46SRyan Lee 166*6a8e1d46SRyan Lee /* MAX98388_R20A0_IV_DATA_DSP_CTRL */ 167*6a8e1d46SRyan Lee #define MAX98388_AMP_DSP_CTRL_VOL_DCBLK_SHIFT (0) 168*6a8e1d46SRyan Lee #define MAX98388_AMP_DSP_CTRL_CUR_DCBLK_SHIFT (1) 169*6a8e1d46SRyan Lee #define MAX98388_AMP_DSP_CTRL_VOL_INV_SHIFT (2) 170*6a8e1d46SRyan Lee #define MAX98388_AMP_DSP_CTRL_CUR_INV_SHIFT (3) 171*6a8e1d46SRyan Lee #define MAX98388_AMP_DSP_CTRL_DITH_SHIFT (4) 172*6a8e1d46SRyan Lee 173*6a8e1d46SRyan Lee /* MAX98388_R20B2_BDE_L4_CFG_2 */ 174*6a8e1d46SRyan Lee #define MAX98388_LVL4_HOLD_EN_SHIFT (6) 175*6a8e1d46SRyan Lee #define MAX98388_LVL4_MUTE_EN_SHIFT (7) 176*6a8e1d46SRyan Lee 177*6a8e1d46SRyan Lee /* MAX98388_R20B5_BDE_EN */ 178*6a8e1d46SRyan Lee #define MAX98388_BDE_EN_SHIFT (0) 179*6a8e1d46SRyan Lee 180*6a8e1d46SRyan Lee /* MAX98388_R20D1_DHT_CFG */ 181*6a8e1d46SRyan Lee #define MAX98388_DHT_ROT_PNT_SHIFT (0) 182*6a8e1d46SRyan Lee #define MAX98388_DHT_SPK_GAIN_MIN_SHIFT (4) 183*6a8e1d46SRyan Lee 184*6a8e1d46SRyan Lee /* MAX98388_R20D2_DHT_ATTACK_CFG */ 185*6a8e1d46SRyan Lee #define MAX98388_DHT_ATTACK_RATE_SHIFT (0) 186*6a8e1d46SRyan Lee #define MAX98388_DHT_ATTACK_STEP_SHIFT (3) 187*6a8e1d46SRyan Lee 188*6a8e1d46SRyan Lee /* MAX98388_R20D3_DHT_RELEASE_CFG */ 189*6a8e1d46SRyan Lee #define MAX98388_DHT_RELEASE_RATE_SHIFT (0) 190*6a8e1d46SRyan Lee #define MAX98388_DHT_RELEASE_STEP_SHIFT (3) 191*6a8e1d46SRyan Lee 192*6a8e1d46SRyan Lee /* MAX98388_R20D4_DHT_EN */ 193*6a8e1d46SRyan Lee #define MAX98388_DHT_EN_SHIFT (0) 194*6a8e1d46SRyan Lee 195*6a8e1d46SRyan Lee /* MAX98388_R20E0_BP_ALC_THRESH */ 196*6a8e1d46SRyan Lee #define MAX98388_ALC_THRESH_SHIFT (0) 197*6a8e1d46SRyan Lee 198*6a8e1d46SRyan Lee /* MAX98388_R20E1_BP_ALC_RATES */ 199*6a8e1d46SRyan Lee #define MAX98388_ALC_RELEASE_RATE_SHIFT (0) 200*6a8e1d46SRyan Lee #define MAX98388_ALC_ATTACK_RATE_SHIFT (4) 201*6a8e1d46SRyan Lee 202*6a8e1d46SRyan Lee /* MAX98388_R20E2_BP_ALC_ATTEN */ 203*6a8e1d46SRyan Lee #define MAX98388_ALC_MAX_ATTEN_SHIFT (0) 204*6a8e1d46SRyan Lee 205*6a8e1d46SRyan Lee /* MAX98388_R20E3_BP_ALC_REL */ 206*6a8e1d46SRyan Lee #define MAX98388_ALC_DEBOUNCE_TIME_SHIFT (0) 207*6a8e1d46SRyan Lee 208*6a8e1d46SRyan Lee /* MAX98388_R20E4_BP_ALC_MUTE */ 209*6a8e1d46SRyan Lee #define MAX98388_ALC_MUTE_EN_SHIFT (0) 210*6a8e1d46SRyan Lee #define MAX98388_ALC_MUTE_DELAY_SHIFT (1) 211*6a8e1d46SRyan Lee #define MAX98388_ALC_MUTE_RAMP_EN_SHIFT (4) 212*6a8e1d46SRyan Lee #define MAX98388_ALC_UNMUTE_RAMP_EN_SHIFT (5) 213*6a8e1d46SRyan Lee 214*6a8e1d46SRyan Lee /* MAX98388_R210E_AUTO_RESTART */ 215*6a8e1d46SRyan Lee #define MAX98388_PVDD_UVLO_AUTORESTART_SHIFT (0) 216*6a8e1d46SRyan Lee #define MAX98388_THERM_AUTORESTART_SHIFT (1) 217*6a8e1d46SRyan Lee #define MAX98388_OVC_AUTORESTART_SHIFT (2) 218*6a8e1d46SRyan Lee #define MAX98388_CMON_AUTORESTART_SHIFT (3) 219*6a8e1d46SRyan Lee 220*6a8e1d46SRyan Lee /* MAX98388_R210F_GLOBAL_EN */ 221*6a8e1d46SRyan Lee #define MAX98388_GLOBAL_EN_MASK (0x1 << 0) 222*6a8e1d46SRyan Lee 223*6a8e1d46SRyan Lee struct max98388_priv { 224*6a8e1d46SRyan Lee struct regmap *regmap; 225*6a8e1d46SRyan Lee struct gpio_desc *reset_gpio; 226*6a8e1d46SRyan Lee unsigned int v_slot; 227*6a8e1d46SRyan Lee unsigned int i_slot; 228*6a8e1d46SRyan Lee unsigned int spkfb_slot; 229*6a8e1d46SRyan Lee bool interleave_mode; 230*6a8e1d46SRyan Lee unsigned int ch_size; 231*6a8e1d46SRyan Lee bool tdm_mode; 232*6a8e1d46SRyan Lee }; 233*6a8e1d46SRyan Lee 234*6a8e1d46SRyan Lee #endif 235