1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2017, Maxim Integrated */ 3 4 #include <linux/acpi.h> 5 #include <linux/i2c.h> 6 #include <linux/module.h> 7 #include <linux/regmap.h> 8 #include <linux/slab.h> 9 #include <linux/cdev.h> 10 #include <sound/pcm.h> 11 #include <sound/pcm_params.h> 12 #include <sound/soc.h> 13 #include <linux/gpio.h> 14 #include <linux/of_gpio.h> 15 #include <sound/tlv.h> 16 #include "max98373.h" 17 18 static struct reg_default max98373_reg[] = { 19 {MAX98373_R2000_SW_RESET, 0x00}, 20 {MAX98373_R2001_INT_RAW1, 0x00}, 21 {MAX98373_R2002_INT_RAW2, 0x00}, 22 {MAX98373_R2003_INT_RAW3, 0x00}, 23 {MAX98373_R2004_INT_STATE1, 0x00}, 24 {MAX98373_R2005_INT_STATE2, 0x00}, 25 {MAX98373_R2006_INT_STATE3, 0x00}, 26 {MAX98373_R2007_INT_FLAG1, 0x00}, 27 {MAX98373_R2008_INT_FLAG2, 0x00}, 28 {MAX98373_R2009_INT_FLAG3, 0x00}, 29 {MAX98373_R200A_INT_EN1, 0x00}, 30 {MAX98373_R200B_INT_EN2, 0x00}, 31 {MAX98373_R200C_INT_EN3, 0x00}, 32 {MAX98373_R200D_INT_FLAG_CLR1, 0x00}, 33 {MAX98373_R200E_INT_FLAG_CLR2, 0x00}, 34 {MAX98373_R200F_INT_FLAG_CLR3, 0x00}, 35 {MAX98373_R2010_IRQ_CTRL, 0x00}, 36 {MAX98373_R2014_THERM_WARN_THRESH, 0x10}, 37 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27}, 38 {MAX98373_R2016_THERM_HYSTERESIS, 0x01}, 39 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0}, 40 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00}, 41 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55}, 42 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE}, 43 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF}, 44 {MAX98373_R2022_PCM_TX_SRC_1, 0x00}, 45 {MAX98373_R2023_PCM_TX_SRC_2, 0x00}, 46 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0}, 47 {MAX98373_R2025_AUDIO_IF_MODE, 0x00}, 48 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04}, 49 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08}, 50 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88}, 51 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00}, 52 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00}, 53 {MAX98373_R202B_PCM_RX_EN, 0x00}, 54 {MAX98373_R202C_PCM_TX_EN, 0x00}, 55 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00}, 56 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00}, 57 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF}, 58 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF}, 59 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30}, 60 {MAX98373_R2034_ICC_TX_CNTL, 0x00}, 61 {MAX98373_R2035_ICC_TX_EN, 0x00}, 62 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05}, 63 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00}, 64 {MAX98373_R203E_AMP_PATH_GAIN, 0x08}, 65 {MAX98373_R203F_AMP_DSP_CFG, 0x02}, 66 {MAX98373_R2040_TONE_GEN_CFG, 0x00}, 67 {MAX98373_R2041_AMP_CFG, 0x03}, 68 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00}, 69 {MAX98373_R2043_AMP_EN, 0x00}, 70 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04}, 71 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00}, 72 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00}, 73 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00}, 74 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00}, 75 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00}, 76 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00}, 77 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00}, 78 {MAX98373_R2090_BDE_LVL_HOLD, 0x00}, 79 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00}, 80 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00}, 81 {MAX98373_R2097_BDE_L1_THRESH, 0x00}, 82 {MAX98373_R2098_BDE_L2_THRESH, 0x00}, 83 {MAX98373_R2099_BDE_L3_THRESH, 0x00}, 84 {MAX98373_R209A_BDE_L4_THRESH, 0x00}, 85 {MAX98373_R209B_BDE_THRESH_HYST, 0x00}, 86 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00}, 87 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00}, 88 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00}, 89 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00}, 90 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00}, 91 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00}, 92 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00}, 93 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00}, 94 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00}, 95 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00}, 96 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00}, 97 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00}, 98 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00}, 99 {MAX98373_R20B5_BDE_EN, 0x00}, 100 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00}, 101 {MAX98373_R20D1_DHT_CFG, 0x01}, 102 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02}, 103 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03}, 104 {MAX98373_R20D4_DHT_EN, 0x00}, 105 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00}, 106 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00}, 107 {MAX98373_R20E2_LIMITER_EN, 0x00}, 108 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00}, 109 {MAX98373_R20FF_GLOBAL_SHDN, 0x00}, 110 {MAX98373_R21FF_REV_ID, 0x42}, 111 }; 112 113 static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 114 { 115 struct snd_soc_codec *codec = codec_dai->codec; 116 struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec); 117 unsigned int format = 0; 118 unsigned int invert = 0; 119 120 dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt); 121 122 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 123 case SND_SOC_DAIFMT_NB_NF: 124 break; 125 case SND_SOC_DAIFMT_IB_NF: 126 invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE; 127 break; 128 default: 129 dev_err(codec->dev, "DAI invert mode unsupported\n"); 130 return -EINVAL; 131 } 132 133 regmap_update_bits(max98373->regmap, 134 MAX98373_R2026_PCM_CLOCK_RATIO, 135 MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE, 136 invert); 137 138 /* interface format */ 139 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 140 case SND_SOC_DAIFMT_I2S: 141 format = MAX98373_PCM_FORMAT_I2S; 142 break; 143 case SND_SOC_DAIFMT_LEFT_J: 144 format = MAX98373_PCM_FORMAT_LJ; 145 break; 146 case SND_SOC_DAIFMT_DSP_A: 147 format = MAX98373_PCM_FORMAT_TDM_MODE1; 148 break; 149 case SND_SOC_DAIFMT_DSP_B: 150 format = MAX98373_PCM_FORMAT_TDM_MODE0; 151 break; 152 default: 153 return -EINVAL; 154 } 155 156 regmap_update_bits(max98373->regmap, 157 MAX98373_R2024_PCM_DATA_FMT_CFG, 158 MAX98373_PCM_MODE_CFG_FORMAT_MASK, 159 format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT); 160 161 return 0; 162 } 163 164 /* BCLKs per LRCLK */ 165 static const int bclk_sel_table[] = { 166 32, 48, 64, 96, 128, 192, 256, 384, 512, 320, 167 }; 168 169 static int max98373_get_bclk_sel(int bclk) 170 { 171 int i; 172 /* match BCLKs per LRCLK */ 173 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) { 174 if (bclk_sel_table[i] == bclk) 175 return i + 2; 176 } 177 return 0; 178 } 179 180 static int max98373_set_clock(struct snd_soc_codec *codec, 181 struct snd_pcm_hw_params *params) 182 { 183 struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec); 184 /* BCLK/LRCLK ratio calculation */ 185 int blr_clk_ratio = params_channels(params) * max98373->ch_size; 186 int value; 187 188 if (!max98373->tdm_mode) { 189 /* BCLK configuration */ 190 value = max98373_get_bclk_sel(blr_clk_ratio); 191 if (!value) { 192 dev_err(codec->dev, "format unsupported %d\n", 193 params_format(params)); 194 return -EINVAL; 195 } 196 197 regmap_update_bits(max98373->regmap, 198 MAX98373_R2026_PCM_CLOCK_RATIO, 199 MAX98373_PCM_CLK_SETUP_BSEL_MASK, 200 value); 201 } 202 return 0; 203 } 204 205 static int max98373_dai_hw_params(struct snd_pcm_substream *substream, 206 struct snd_pcm_hw_params *params, 207 struct snd_soc_dai *dai) 208 { 209 struct snd_soc_codec *codec = dai->codec; 210 struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec); 211 unsigned int sampling_rate = 0; 212 unsigned int chan_sz = 0; 213 214 /* pcm mode configuration */ 215 switch (snd_pcm_format_width(params_format(params))) { 216 case 16: 217 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 218 break; 219 case 24: 220 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 221 break; 222 case 32: 223 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 224 break; 225 default: 226 dev_err(codec->dev, "format unsupported %d\n", 227 params_format(params)); 228 goto err; 229 } 230 231 max98373->ch_size = snd_pcm_format_width(params_format(params)); 232 233 regmap_update_bits(max98373->regmap, 234 MAX98373_R2024_PCM_DATA_FMT_CFG, 235 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 236 237 dev_dbg(codec->dev, "format supported %d", 238 params_format(params)); 239 240 /* sampling rate configuration */ 241 switch (params_rate(params)) { 242 case 8000: 243 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000; 244 break; 245 case 11025: 246 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025; 247 break; 248 case 12000: 249 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000; 250 break; 251 case 16000: 252 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000; 253 break; 254 case 22050: 255 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050; 256 break; 257 case 24000: 258 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000; 259 break; 260 case 32000: 261 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000; 262 break; 263 case 44100: 264 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100; 265 break; 266 case 48000: 267 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000; 268 break; 269 default: 270 dev_err(codec->dev, "rate %d not supported\n", 271 params_rate(params)); 272 goto err; 273 } 274 275 /* set DAI_SR to correct LRCLK frequency */ 276 regmap_update_bits(max98373->regmap, 277 MAX98373_R2027_PCM_SR_SETUP_1, 278 MAX98373_PCM_SR_SET1_SR_MASK, 279 sampling_rate); 280 regmap_update_bits(max98373->regmap, 281 MAX98373_R2028_PCM_SR_SETUP_2, 282 MAX98373_PCM_SR_SET2_SR_MASK, 283 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT); 284 285 /* set sampling rate of IV */ 286 if (max98373->interleave_mode && 287 sampling_rate > MAX98373_PCM_SR_SET1_SR_16000) 288 regmap_update_bits(max98373->regmap, 289 MAX98373_R2028_PCM_SR_SETUP_2, 290 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 291 sampling_rate - 3); 292 else 293 regmap_update_bits(max98373->regmap, 294 MAX98373_R2028_PCM_SR_SETUP_2, 295 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 296 sampling_rate); 297 298 return max98373_set_clock(codec, params); 299 err: 300 return -EINVAL; 301 } 302 303 static int max98373_dai_tdm_slot(struct snd_soc_dai *dai, 304 unsigned int tx_mask, unsigned int rx_mask, 305 int slots, int slot_width) 306 { 307 struct snd_soc_codec *codec = dai->codec; 308 struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec); 309 int bsel = 0; 310 unsigned int chan_sz = 0; 311 unsigned int mask; 312 int x, slot_found; 313 314 max98373->tdm_mode = true; 315 316 /* BCLK configuration */ 317 bsel = max98373_get_bclk_sel(slots * slot_width); 318 if (bsel == 0) { 319 dev_err(codec->dev, "BCLK %d not supported\n", 320 slots * slot_width); 321 return -EINVAL; 322 } 323 324 regmap_update_bits(max98373->regmap, 325 MAX98373_R2026_PCM_CLOCK_RATIO, 326 MAX98373_PCM_CLK_SETUP_BSEL_MASK, 327 bsel); 328 329 /* Channel size configuration */ 330 switch (slot_width) { 331 case 16: 332 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 333 break; 334 case 24: 335 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 336 break; 337 case 32: 338 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 339 break; 340 default: 341 dev_err(codec->dev, "format unsupported %d\n", 342 slot_width); 343 return -EINVAL; 344 } 345 346 regmap_update_bits(max98373->regmap, 347 MAX98373_R2024_PCM_DATA_FMT_CFG, 348 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 349 350 /* Rx slot configuration */ 351 slot_found = 0; 352 mask = rx_mask; 353 for (x = 0 ; x < 16 ; x++, mask >>= 1) { 354 if (mask & 0x1) { 355 if (slot_found == 0) 356 regmap_update_bits(max98373->regmap, 357 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 358 MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x); 359 else 360 regmap_write(max98373->regmap, 361 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 362 x); 363 slot_found++; 364 if (slot_found > 1) 365 break; 366 } 367 } 368 369 /* Tx slot Hi-Z configuration */ 370 regmap_write(max98373->regmap, 371 MAX98373_R2020_PCM_TX_HIZ_EN_1, 372 ~tx_mask & 0xFF); 373 regmap_write(max98373->regmap, 374 MAX98373_R2021_PCM_TX_HIZ_EN_2, 375 (~tx_mask & 0xFF00) >> 8); 376 377 return 0; 378 } 379 380 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000 381 382 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 383 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 384 385 static const struct snd_soc_dai_ops max98373_dai_ops = { 386 .set_fmt = max98373_dai_set_fmt, 387 .hw_params = max98373_dai_hw_params, 388 .set_tdm_slot = max98373_dai_tdm_slot, 389 }; 390 391 static int max98373_dac_event(struct snd_soc_dapm_widget *w, 392 struct snd_kcontrol *kcontrol, int event) 393 { 394 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 395 struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec); 396 397 switch (event) { 398 case SND_SOC_DAPM_POST_PMU: 399 regmap_update_bits(max98373->regmap, 400 MAX98373_R20FF_GLOBAL_SHDN, 401 MAX98373_GLOBAL_EN_MASK, 1); 402 break; 403 case SND_SOC_DAPM_POST_PMD: 404 regmap_update_bits(max98373->regmap, 405 MAX98373_R20FF_GLOBAL_SHDN, 406 MAX98373_GLOBAL_EN_MASK, 0); 407 max98373->tdm_mode = 0; 408 break; 409 default: 410 return 0; 411 } 412 return 0; 413 } 414 415 static const char * const max98373_switch_text[] = { 416 "Left", "Right", "LeftRight"}; 417 418 static const struct soc_enum dai_sel_enum = 419 SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 420 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT, 421 3, max98373_switch_text); 422 423 static const struct snd_kcontrol_new max98373_dai_controls = 424 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum); 425 426 static const struct snd_kcontrol_new max98373_vi_control = 427 SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0); 428 429 static const struct snd_kcontrol_new max98373_spkfb_control = 430 SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0); 431 432 static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = { 433 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", 434 MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event, 435 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 436 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, 437 &max98373_dai_controls), 438 SND_SOC_DAPM_OUTPUT("BE_OUT"), 439 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0, 440 MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0), 441 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0, 442 MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0), 443 SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0, 444 SND_SOC_NOPM, 0, 0), 445 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0, 446 &max98373_vi_control), 447 SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0, 448 &max98373_spkfb_control), 449 SND_SOC_DAPM_SIGGEN("VMON"), 450 SND_SOC_DAPM_SIGGEN("IMON"), 451 SND_SOC_DAPM_SIGGEN("FBMON"), 452 }; 453 454 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, 0, -50, 0); 455 static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv, 456 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0), 457 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0), 458 ); 459 static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv, 460 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 461 ); 462 static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv, 463 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0), 464 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0), 465 ); 466 static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv, 467 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 468 ); 469 static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv, 470 0, 1, TLV_DB_SCALE_ITEM(-50, -50, 0), 471 2, 7, TLV_DB_SCALE_ITEM(-200, -100, 0), 472 8, 9, TLV_DB_SCALE_ITEM(-1000, -200, 0), 473 10, 11, TLV_DB_SCALE_ITEM(-1500, -300, 0), 474 12, 13, TLV_DB_SCALE_ITEM(-2000, -200, 0), 475 14, 15, TLV_DB_SCALE_ITEM(-2500, -500, 0), 476 ); 477 static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv, 478 0, 15, TLV_DB_SCALE_ITEM(0, -100, 0), 479 ); 480 481 static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv, 482 0, 60, TLV_DB_SCALE_ITEM(0, -25, 0), 483 ); 484 485 static bool max98373_readable_register(struct device *dev, unsigned int reg) 486 { 487 switch (reg) { 488 case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3: 489 case MAX98373_R2010_IRQ_CTRL: 490 case MAX98373_R2014_THERM_WARN_THRESH 491 ... MAX98373_R2018_THERM_FOLDBACK_EN: 492 case MAX98373_R201E_PIN_DRIVE_STRENGTH 493 ... MAX98373_R2036_SOUNDWIRE_CTRL: 494 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN: 495 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 496 ... MAX98373_R2047_IV_SENSE_ADC_EN: 497 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 498 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN: 499 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE: 500 case MAX98373_R2097_BDE_L1_THRESH 501 ... MAX98373_R209B_BDE_THRESH_HYST: 502 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3: 503 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK: 504 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN: 505 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN: 506 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 507 ... MAX98373_R20FF_GLOBAL_SHDN: 508 case MAX98373_R21FF_REV_ID: 509 return true; 510 default: 511 return false; 512 } 513 }; 514 515 static bool max98373_volatile_reg(struct device *dev, unsigned int reg) 516 { 517 switch (reg) { 518 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3: 519 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK: 520 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK: 521 case MAX98373_R20B6_BDE_CUR_STATE_READBACK: 522 case MAX98373_R21FF_REV_ID: 523 return true; 524 default: 525 return false; 526 } 527 } 528 529 static const char * const max98373_output_voltage_lvl_text[] = { 530 "5.43V", "6.09V", "6.83V", "7.67V", "8.60V", 531 "9.65V", "10.83V", "12.15V", "13.63V", "15.29V" 532 }; 533 534 static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum, 535 MAX98373_R203E_AMP_PATH_GAIN, 0, 536 max98373_output_voltage_lvl_text); 537 538 static const char * const max98373_dht_attack_rate_text[] = { 539 "17.5us", "35us", "70us", "140us", 540 "280us", "560us", "1120us", "2240us" 541 }; 542 543 static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum, 544 MAX98373_R20D2_DHT_ATTACK_CFG, 0, 545 max98373_dht_attack_rate_text); 546 547 static const char * const max98373_dht_release_rate_text[] = { 548 "45ms", "225ms", "450ms", "1150ms", 549 "2250ms", "3100ms", "4500ms", "6750ms" 550 }; 551 552 static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum, 553 MAX98373_R20D3_DHT_RELEASE_CFG, 0, 554 max98373_dht_release_rate_text); 555 556 static const char * const max98373_limiter_attack_rate_text[] = { 557 "10us", "20us", "40us", "80us", 558 "160us", "320us", "640us", "1.28ms", 559 "2.56ms", "5.12ms", "10.24ms", "20.48ms", 560 "40.96ms", "81.92ms", "16.384ms", "32.768ms" 561 }; 562 563 static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum, 564 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4, 565 max98373_limiter_attack_rate_text); 566 567 static const char * const max98373_limiter_release_rate_text[] = { 568 "40us", "80us", "160us", "320us", 569 "640us", "1.28ms", "2.56ms", "5.120ms", 570 "10.24ms", "20.48ms", "40.96ms", "81.92ms", 571 "163.84ms", "327.68ms", "655.36ms", "1310.72ms" 572 }; 573 574 static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum, 575 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0, 576 max98373_limiter_release_rate_text); 577 578 static const char * const max98373_ADC_samplerate_text[] = { 579 "333kHz", "192kHz", "64kHz", "48kHz" 580 }; 581 582 static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum, 583 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0, 584 max98373_ADC_samplerate_text); 585 586 static const struct snd_kcontrol_new max98373_snd_controls[] = { 587 SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG, 588 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 589 SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG, 590 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 591 SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG, 592 MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0), 593 SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG, 594 MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0), 595 SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 596 MAX98373_CLOCK_MON_SHIFT, 1, 0), 597 SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG, 598 MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0), 599 SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG, 600 MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0), 601 SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL, 602 0, 0x7F, 0, max98373_digital_tlv), 603 SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN, 604 MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv), 605 SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN, 606 MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv), 607 SOC_ENUM("Output Voltage", max98373_out_volt_enum), 608 /* Dynamic Headroom Tracking */ 609 SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN, 610 MAX98373_DHT_EN_SHIFT, 1, 0), 611 SOC_SINGLE_TLV("DHT Gain Min", MAX98373_R20D1_DHT_CFG, 612 MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv), 613 SOC_SINGLE_TLV("DHT Rot Pnt", MAX98373_R20D1_DHT_CFG, 614 MAX98373_DHT_ROT_PNT_SHIFT, 15, 0, max98373_dht_rotation_point_tlv), 615 SOC_SINGLE_TLV("DHT Attack Step", MAX98373_R20D2_DHT_ATTACK_CFG, 616 MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 617 SOC_SINGLE_TLV("DHT Release Step", MAX98373_R20D3_DHT_RELEASE_CFG, 618 MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 619 SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum), 620 SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum), 621 /* ADC configuration */ 622 SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0), 623 SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 624 MAX98373_FLT_EN_SHIFT, 1, 0), 625 SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 626 MAX98373_FLT_EN_SHIFT, 1, 0), 627 SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0), 628 SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0), 629 SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 630 0, 0x3, 0), 631 SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 632 0, 0x3, 0), 633 SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum), 634 /* Brownout Detection Engine */ 635 SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0), 636 SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2, 637 MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0), 638 SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2, 639 MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0), 640 SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0), 641 SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0), 642 SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0), 643 SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0), 644 SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0), 645 SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0), 646 SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0), 647 SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0), 648 SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0), 649 SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0), 650 SOC_SINGLE_TLV("BDE LVL1 Clip Thresh", MAX98373_R20A9_BDE_L1_CFG_2, 651 0, 0x3C, 0, max98373_bde_gain_tlv), 652 SOC_SINGLE_TLV("BDE LVL2 Clip Thresh", MAX98373_R20AC_BDE_L2_CFG_2, 653 0, 0x3C, 0, max98373_bde_gain_tlv), 654 SOC_SINGLE_TLV("BDE LVL3 Clip Thresh", MAX98373_R20AF_BDE_L3_CFG_2, 655 0, 0x3C, 0, max98373_bde_gain_tlv), 656 SOC_SINGLE_TLV("BDE LVL4 Clip Thresh", MAX98373_R20B2_BDE_L4_CFG_2, 657 0, 0x3C, 0, max98373_bde_gain_tlv), 658 SOC_SINGLE_TLV("BDE LVL1 Clip Gain Reduct", MAX98373_R20AA_BDE_L1_CFG_3, 659 0, 0x3C, 0, max98373_bde_gain_tlv), 660 SOC_SINGLE_TLV("BDE LVL2 Clip Gain Reduct", MAX98373_R20AD_BDE_L2_CFG_3, 661 0, 0x3C, 0, max98373_bde_gain_tlv), 662 SOC_SINGLE_TLV("BDE LVL3 Clip Gain Reduct", MAX98373_R20B0_BDE_L3_CFG_3, 663 0, 0x3C, 0, max98373_bde_gain_tlv), 664 SOC_SINGLE_TLV("BDE LVL4 Clip Gain Reduct", MAX98373_R20B3_BDE_L4_CFG_3, 665 0, 0x3C, 0, max98373_bde_gain_tlv), 666 SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh", MAX98373_R20A8_BDE_L1_CFG_1, 667 0, 0xF, 0, max98373_limiter_thresh_tlv), 668 SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh", MAX98373_R20AB_BDE_L2_CFG_1, 669 0, 0xF, 0, max98373_limiter_thresh_tlv), 670 SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh", MAX98373_R20AE_BDE_L3_CFG_1, 671 0, 0xF, 0, max98373_limiter_thresh_tlv), 672 SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh", MAX98373_R20B1_BDE_L4_CFG_1, 673 0, 0xF, 0, max98373_limiter_thresh_tlv), 674 /* Limiter */ 675 SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN, 676 MAX98373_LIMITER_EN_SHIFT, 1, 0), 677 SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG, 678 MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0), 679 SOC_SINGLE_TLV("Limiter Thresh", MAX98373_R20E0_LIMITER_THRESH_CFG, 680 MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv), 681 SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum), 682 SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum), 683 }; 684 685 static const struct snd_soc_dapm_route max98373_audio_map[] = { 686 /* Plabyack */ 687 {"DAI Sel Mux", "Left", "Amp Enable"}, 688 {"DAI Sel Mux", "Right", "Amp Enable"}, 689 {"DAI Sel Mux", "LeftRight", "Amp Enable"}, 690 {"BE_OUT", NULL, "DAI Sel Mux"}, 691 /* Capture */ 692 { "VI Sense", "Switch", "VMON" }, 693 { "VI Sense", "Switch", "IMON" }, 694 { "SpkFB Sense", "Switch", "FBMON" }, 695 { "Voltage Sense", NULL, "VI Sense" }, 696 { "Current Sense", NULL, "VI Sense" }, 697 { "Speaker FB Sense", NULL, "SpkFB Sense" }, 698 }; 699 700 static struct snd_soc_dai_driver max98373_dai[] = { 701 { 702 .name = "max98373-aif1", 703 .playback = { 704 .stream_name = "HiFi Playback", 705 .channels_min = 1, 706 .channels_max = 2, 707 .rates = MAX98373_RATES, 708 .formats = MAX98373_FORMATS, 709 }, 710 .capture = { 711 .stream_name = "HiFi Capture", 712 .channels_min = 1, 713 .channels_max = 2, 714 .rates = MAX98373_RATES, 715 .formats = MAX98373_FORMATS, 716 }, 717 .ops = &max98373_dai_ops, 718 } 719 }; 720 721 static int max98373_probe(struct snd_soc_codec *codec) 722 { 723 struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec); 724 725 codec->control_data = max98373->regmap; 726 727 /* Software Reset */ 728 regmap_write(max98373->regmap, 729 MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET); 730 731 /* IV default slot configuration */ 732 regmap_write(max98373->regmap, 733 MAX98373_R2020_PCM_TX_HIZ_EN_1, 734 0xFF); 735 regmap_write(max98373->regmap, 736 MAX98373_R2021_PCM_TX_HIZ_EN_2, 737 0xFF); 738 /* L/R mix configuration */ 739 regmap_write(max98373->regmap, 740 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 741 0x80); 742 regmap_write(max98373->regmap, 743 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 744 0x1); 745 /* Set inital volume (0dB) */ 746 regmap_write(max98373->regmap, 747 MAX98373_R203D_AMP_DIG_VOL_CTRL, 748 0x00); 749 regmap_write(max98373->regmap, 750 MAX98373_R203E_AMP_PATH_GAIN, 751 0x00); 752 /* Enable DC blocker */ 753 regmap_write(max98373->regmap, 754 MAX98373_R203F_AMP_DSP_CFG, 755 0x3); 756 /* Enable IMON VMON DC blocker */ 757 regmap_write(max98373->regmap, 758 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 759 0x7); 760 /* voltage, current slot configuration */ 761 regmap_write(max98373->regmap, 762 MAX98373_R2022_PCM_TX_SRC_1, 763 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT | 764 max98373->v_slot) & 0xFF); 765 if (max98373->v_slot < 8) 766 regmap_update_bits(max98373->regmap, 767 MAX98373_R2020_PCM_TX_HIZ_EN_1, 768 1 << max98373->v_slot, 0); 769 else 770 regmap_update_bits(max98373->regmap, 771 MAX98373_R2021_PCM_TX_HIZ_EN_2, 772 1 << (max98373->v_slot - 8), 0); 773 774 if (max98373->i_slot < 8) 775 regmap_update_bits(max98373->regmap, 776 MAX98373_R2020_PCM_TX_HIZ_EN_1, 777 1 << max98373->i_slot, 0); 778 else 779 regmap_update_bits(max98373->regmap, 780 MAX98373_R2021_PCM_TX_HIZ_EN_2, 781 1 << (max98373->i_slot - 8), 0); 782 783 /* speaker feedback slot configuration */ 784 regmap_write(max98373->regmap, 785 MAX98373_R2023_PCM_TX_SRC_2, 786 max98373->spkfb_slot & 0xFF); 787 788 /* Set interleave mode */ 789 if (max98373->interleave_mode) 790 regmap_update_bits(max98373->regmap, 791 MAX98373_R2024_PCM_DATA_FMT_CFG, 792 MAX98373_PCM_TX_CH_INTERLEAVE_MASK, 793 MAX98373_PCM_TX_CH_INTERLEAVE_MASK); 794 795 /* Speaker enable */ 796 regmap_update_bits(max98373->regmap, 797 MAX98373_R2043_AMP_EN, 798 MAX98373_SPK_EN_MASK, 1); 799 800 return 0; 801 } 802 803 #ifdef CONFIG_PM_SLEEP 804 static int max98373_suspend(struct device *dev) 805 { 806 struct max98373_priv *max98373 = dev_get_drvdata(dev); 807 808 regcache_cache_only(max98373->regmap, true); 809 regcache_mark_dirty(max98373->regmap); 810 return 0; 811 } 812 static int max98373_resume(struct device *dev) 813 { 814 struct max98373_priv *max98373 = dev_get_drvdata(dev); 815 816 regmap_write(max98373->regmap, 817 MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET); 818 regcache_cache_only(max98373->regmap, false); 819 regcache_sync(max98373->regmap); 820 return 0; 821 } 822 #endif 823 824 static const struct dev_pm_ops max98373_pm = { 825 SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume) 826 }; 827 828 static const struct snd_soc_codec_driver soc_codec_dev_max98373 = { 829 .probe = max98373_probe, 830 .component_driver = { 831 .controls = max98373_snd_controls, 832 .num_controls = ARRAY_SIZE(max98373_snd_controls), 833 .dapm_widgets = max98373_dapm_widgets, 834 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets), 835 .dapm_routes = max98373_audio_map, 836 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map), 837 }, 838 }; 839 840 static const struct regmap_config max98373_regmap = { 841 .reg_bits = 16, 842 .val_bits = 8, 843 .max_register = MAX98373_R21FF_REV_ID, 844 .reg_defaults = max98373_reg, 845 .num_reg_defaults = ARRAY_SIZE(max98373_reg), 846 .readable_reg = max98373_readable_register, 847 .volatile_reg = max98373_volatile_reg, 848 .cache_type = REGCACHE_RBTREE, 849 }; 850 851 static void max98373_slot_config(struct i2c_client *i2c, 852 struct max98373_priv *max98373) 853 { 854 int value; 855 struct device *dev = &i2c->dev; 856 857 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value)) 858 max98373->v_slot = value & 0xF; 859 else 860 max98373->v_slot = 0; 861 862 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value)) 863 max98373->i_slot = value & 0xF; 864 else 865 max98373->i_slot = 1; 866 867 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value)) 868 max98373->spkfb_slot = value & 0xF; 869 else 870 max98373->spkfb_slot = 2; 871 } 872 873 static int max98373_i2c_probe(struct i2c_client *i2c, 874 const struct i2c_device_id *id) 875 { 876 877 int ret = 0; 878 int reg = 0; 879 struct max98373_priv *max98373 = NULL; 880 881 max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL); 882 883 if (!max98373) { 884 ret = -ENOMEM; 885 return ret; 886 } 887 i2c_set_clientdata(i2c, max98373); 888 889 /* update interleave mode info */ 890 if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode")) 891 max98373->interleave_mode = 1; 892 else 893 max98373->interleave_mode = 0; 894 895 896 /* regmap initialization */ 897 max98373->regmap 898 = devm_regmap_init_i2c(i2c, &max98373_regmap); 899 if (IS_ERR(max98373->regmap)) { 900 ret = PTR_ERR(max98373->regmap); 901 dev_err(&i2c->dev, 902 "Failed to allocate regmap: %d\n", ret); 903 return ret; 904 } 905 906 /* Check Revision ID */ 907 ret = regmap_read(max98373->regmap, 908 MAX98373_R21FF_REV_ID, ®); 909 if (ret < 0) { 910 dev_err(&i2c->dev, 911 "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID); 912 return ret; 913 } 914 dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg); 915 916 /* voltage/current slot configuration */ 917 max98373_slot_config(i2c, max98373); 918 919 /* codec registeration */ 920 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98373, 921 max98373_dai, ARRAY_SIZE(max98373_dai)); 922 if (ret < 0) 923 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 924 925 return ret; 926 } 927 928 static int max98373_i2c_remove(struct i2c_client *client) 929 { 930 snd_soc_unregister_codec(&client->dev); 931 return 0; 932 } 933 934 static const struct i2c_device_id max98373_i2c_id[] = { 935 { "max98373", 0}, 936 { }, 937 }; 938 939 MODULE_DEVICE_TABLE(i2c, max98373_i2c_id); 940 941 #if defined(CONFIG_OF) 942 static const struct of_device_id max98373_of_match[] = { 943 { .compatible = "maxim,max98373", }, 944 { } 945 }; 946 MODULE_DEVICE_TABLE(of, max98373_of_match); 947 #endif 948 949 #ifdef CONFIG_ACPI 950 static const struct acpi_device_id max98373_acpi_match[] = { 951 { "MX98373", 0 }, 952 {}, 953 }; 954 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match); 955 #endif 956 957 static struct i2c_driver max98373_i2c_driver = { 958 .driver = { 959 .name = "max98373", 960 .of_match_table = of_match_ptr(max98373_of_match), 961 .acpi_match_table = ACPI_PTR(max98373_acpi_match), 962 .pm = &max98373_pm, 963 }, 964 .probe = max98373_i2c_probe, 965 .remove = max98373_i2c_remove, 966 .id_table = max98373_i2c_id, 967 }; 968 969 module_i2c_driver(max98373_i2c_driver) 970 971 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver"); 972 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>"); 973 MODULE_LICENSE("GPL"); 974