1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017, Maxim Integrated 3 4 #include <linux/acpi.h> 5 #include <linux/delay.h> 6 #include <linux/i2c.h> 7 #include <linux/module.h> 8 #include <linux/regmap.h> 9 #include <linux/slab.h> 10 #include <linux/cdev.h> 11 #include <sound/pcm.h> 12 #include <sound/pcm_params.h> 13 #include <sound/soc.h> 14 #include <linux/gpio.h> 15 #include <linux/of.h> 16 #include <linux/of_gpio.h> 17 #include <sound/tlv.h> 18 #include "max98373.h" 19 20 static int max98373_dac_event(struct snd_soc_dapm_widget *w, 21 struct snd_kcontrol *kcontrol, int event) 22 { 23 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 24 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 25 26 switch (event) { 27 case SND_SOC_DAPM_POST_PMU: 28 regmap_update_bits(max98373->regmap, 29 MAX98373_R20FF_GLOBAL_SHDN, 30 MAX98373_GLOBAL_EN_MASK, 1); 31 break; 32 case SND_SOC_DAPM_POST_PMD: 33 regmap_update_bits(max98373->regmap, 34 MAX98373_R20FF_GLOBAL_SHDN, 35 MAX98373_GLOBAL_EN_MASK, 0); 36 max98373->tdm_mode = false; 37 break; 38 default: 39 return 0; 40 } 41 return 0; 42 } 43 44 static const char * const max98373_switch_text[] = { 45 "Left", "Right", "LeftRight"}; 46 47 static const struct soc_enum dai_sel_enum = 48 SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 49 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT, 50 3, max98373_switch_text); 51 52 static const struct snd_kcontrol_new max98373_dai_controls = 53 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum); 54 55 static const struct snd_kcontrol_new max98373_vi_control = 56 SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0); 57 58 static const struct snd_kcontrol_new max98373_spkfb_control = 59 SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0); 60 61 static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = { 62 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", 63 MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event, 64 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 65 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, 66 &max98373_dai_controls), 67 SND_SOC_DAPM_OUTPUT("BE_OUT"), 68 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0, 69 MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0), 70 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0, 71 MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0), 72 SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0, 73 SND_SOC_NOPM, 0, 0), 74 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0, 75 &max98373_vi_control), 76 SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0, 77 &max98373_spkfb_control), 78 SND_SOC_DAPM_SIGGEN("VMON"), 79 SND_SOC_DAPM_SIGGEN("IMON"), 80 SND_SOC_DAPM_SIGGEN("FBMON"), 81 }; 82 83 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1); 84 static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv, 85 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0), 86 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0), 87 ); 88 static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv, 89 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 90 ); 91 static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv, 92 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0), 93 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0), 94 ); 95 static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv, 96 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 97 ); 98 static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv, 99 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0), 100 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0), 101 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0), 102 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0), 103 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0), 104 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0), 105 ); 106 static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv, 107 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0), 108 ); 109 110 static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv, 111 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0), 112 ); 113 114 static const char * const max98373_output_voltage_lvl_text[] = { 115 "5.43V", "6.09V", "6.83V", "7.67V", "8.60V", 116 "9.65V", "10.83V", "12.15V", "13.63V", "15.29V" 117 }; 118 119 static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum, 120 MAX98373_R203E_AMP_PATH_GAIN, 0, 121 max98373_output_voltage_lvl_text); 122 123 static const char * const max98373_dht_attack_rate_text[] = { 124 "17.5us", "35us", "70us", "140us", 125 "280us", "560us", "1120us", "2240us" 126 }; 127 128 static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum, 129 MAX98373_R20D2_DHT_ATTACK_CFG, 0, 130 max98373_dht_attack_rate_text); 131 132 static const char * const max98373_dht_release_rate_text[] = { 133 "45ms", "225ms", "450ms", "1150ms", 134 "2250ms", "3100ms", "4500ms", "6750ms" 135 }; 136 137 static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum, 138 MAX98373_R20D3_DHT_RELEASE_CFG, 0, 139 max98373_dht_release_rate_text); 140 141 static const char * const max98373_limiter_attack_rate_text[] = { 142 "10us", "20us", "40us", "80us", 143 "160us", "320us", "640us", "1.28ms", 144 "2.56ms", "5.12ms", "10.24ms", "20.48ms", 145 "40.96ms", "81.92ms", "16.384ms", "32.768ms" 146 }; 147 148 static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum, 149 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4, 150 max98373_limiter_attack_rate_text); 151 152 static const char * const max98373_limiter_release_rate_text[] = { 153 "40us", "80us", "160us", "320us", 154 "640us", "1.28ms", "2.56ms", "5.120ms", 155 "10.24ms", "20.48ms", "40.96ms", "81.92ms", 156 "163.84ms", "327.68ms", "655.36ms", "1310.72ms" 157 }; 158 159 static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum, 160 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0, 161 max98373_limiter_release_rate_text); 162 163 static const char * const max98373_ADC_samplerate_text[] = { 164 "333kHz", "192kHz", "64kHz", "48kHz" 165 }; 166 167 static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum, 168 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0, 169 max98373_ADC_samplerate_text); 170 171 static const struct snd_kcontrol_new max98373_snd_controls[] = { 172 SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG, 173 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 174 SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG, 175 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 176 SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG, 177 MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0), 178 SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG, 179 MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0), 180 SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 181 MAX98373_CLOCK_MON_SHIFT, 1, 0), 182 SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG, 183 MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0), 184 SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG, 185 MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0), 186 SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL, 187 0, 0x7F, 1, max98373_digital_tlv), 188 SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN, 189 MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv), 190 SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN, 191 MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv), 192 SOC_ENUM("Output Voltage", max98373_out_volt_enum), 193 /* Dynamic Headroom Tracking */ 194 SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN, 195 MAX98373_DHT_EN_SHIFT, 1, 0), 196 SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG, 197 MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv), 198 SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG, 199 MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv), 200 SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG, 201 MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 202 SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG, 203 MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 204 SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum), 205 SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum), 206 /* ADC configuration */ 207 SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0), 208 SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 209 MAX98373_FLT_EN_SHIFT, 1, 0), 210 SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 211 MAX98373_FLT_EN_SHIFT, 1, 0), 212 SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0), 213 SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0), 214 SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 215 0, 0x3, 0), 216 SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 217 0, 0x3, 0), 218 SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum), 219 /* Brownout Detection Engine */ 220 SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0), 221 SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2, 222 MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0), 223 SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2, 224 MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0), 225 SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0), 226 SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0), 227 SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0), 228 SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0), 229 SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0), 230 SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0), 231 SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0), 232 SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0), 233 SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0), 234 SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0), 235 SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2, 236 0, 0x3C, 1, max98373_bde_gain_tlv), 237 SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2, 238 0, 0x3C, 1, max98373_bde_gain_tlv), 239 SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2, 240 0, 0x3C, 1, max98373_bde_gain_tlv), 241 SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2, 242 0, 0x3C, 1, max98373_bde_gain_tlv), 243 SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3, 244 0, 0x3C, 1, max98373_bde_gain_tlv), 245 SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3, 246 0, 0x3C, 1, max98373_bde_gain_tlv), 247 SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3, 248 0, 0x3C, 1, max98373_bde_gain_tlv), 249 SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3, 250 0, 0x3C, 1, max98373_bde_gain_tlv), 251 SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1, 252 0, 0xF, 1, max98373_limiter_thresh_tlv), 253 SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1, 254 0, 0xF, 1, max98373_limiter_thresh_tlv), 255 SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1, 256 0, 0xF, 1, max98373_limiter_thresh_tlv), 257 SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1, 258 0, 0xF, 1, max98373_limiter_thresh_tlv), 259 /* Limiter */ 260 SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN, 261 MAX98373_LIMITER_EN_SHIFT, 1, 0), 262 SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG, 263 MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0), 264 SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG, 265 MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv), 266 SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum), 267 SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum), 268 }; 269 270 static const struct snd_soc_dapm_route max98373_audio_map[] = { 271 /* Plabyack */ 272 {"DAI Sel Mux", "Left", "Amp Enable"}, 273 {"DAI Sel Mux", "Right", "Amp Enable"}, 274 {"DAI Sel Mux", "LeftRight", "Amp Enable"}, 275 {"BE_OUT", NULL, "DAI Sel Mux"}, 276 /* Capture */ 277 { "VI Sense", "Switch", "VMON" }, 278 { "VI Sense", "Switch", "IMON" }, 279 { "SpkFB Sense", "Switch", "FBMON" }, 280 { "Voltage Sense", NULL, "VI Sense" }, 281 { "Current Sense", NULL, "VI Sense" }, 282 { "Speaker FB Sense", NULL, "SpkFB Sense" }, 283 }; 284 285 void max98373_reset(struct max98373_priv *max98373, struct device *dev) 286 { 287 int ret, reg, count; 288 289 /* Software Reset */ 290 ret = regmap_update_bits(max98373->regmap, 291 MAX98373_R2000_SW_RESET, 292 MAX98373_SOFT_RESET, 293 MAX98373_SOFT_RESET); 294 if (ret) 295 dev_err(dev, "Reset command failed. (ret:%d)\n", ret); 296 297 count = 0; 298 while (count < 3) { 299 usleep_range(10000, 11000); 300 /* Software Reset Verification */ 301 ret = regmap_read(max98373->regmap, 302 MAX98373_R21FF_REV_ID, ®); 303 if (!ret) { 304 dev_info(dev, "Reset completed (retry:%d)\n", count); 305 return; 306 } 307 count++; 308 } 309 dev_err(dev, "Reset failed. (ret:%d)\n", ret); 310 } 311 EXPORT_SYMBOL_GPL(max98373_reset); 312 313 static int max98373_probe(struct snd_soc_component *component) 314 { 315 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 316 317 /* Software Reset */ 318 max98373_reset(max98373, component->dev); 319 320 /* IV default slot configuration */ 321 regmap_write(max98373->regmap, 322 MAX98373_R2020_PCM_TX_HIZ_EN_1, 323 0xFF); 324 regmap_write(max98373->regmap, 325 MAX98373_R2021_PCM_TX_HIZ_EN_2, 326 0xFF); 327 /* L/R mix configuration */ 328 regmap_write(max98373->regmap, 329 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 330 0x80); 331 regmap_write(max98373->regmap, 332 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 333 0x1); 334 /* Set inital volume (0dB) */ 335 regmap_write(max98373->regmap, 336 MAX98373_R203D_AMP_DIG_VOL_CTRL, 337 0x00); 338 regmap_write(max98373->regmap, 339 MAX98373_R203E_AMP_PATH_GAIN, 340 0x00); 341 /* Enable DC blocker */ 342 regmap_write(max98373->regmap, 343 MAX98373_R203F_AMP_DSP_CFG, 344 0x3); 345 /* Enable IMON VMON DC blocker */ 346 regmap_write(max98373->regmap, 347 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 348 0x7); 349 /* voltage, current slot configuration */ 350 regmap_write(max98373->regmap, 351 MAX98373_R2022_PCM_TX_SRC_1, 352 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT | 353 max98373->v_slot) & 0xFF); 354 if (max98373->v_slot < 8) 355 regmap_update_bits(max98373->regmap, 356 MAX98373_R2020_PCM_TX_HIZ_EN_1, 357 1 << max98373->v_slot, 0); 358 else 359 regmap_update_bits(max98373->regmap, 360 MAX98373_R2021_PCM_TX_HIZ_EN_2, 361 1 << (max98373->v_slot - 8), 0); 362 363 if (max98373->i_slot < 8) 364 regmap_update_bits(max98373->regmap, 365 MAX98373_R2020_PCM_TX_HIZ_EN_1, 366 1 << max98373->i_slot, 0); 367 else 368 regmap_update_bits(max98373->regmap, 369 MAX98373_R2021_PCM_TX_HIZ_EN_2, 370 1 << (max98373->i_slot - 8), 0); 371 372 /* speaker feedback slot configuration */ 373 regmap_write(max98373->regmap, 374 MAX98373_R2023_PCM_TX_SRC_2, 375 max98373->spkfb_slot & 0xFF); 376 377 /* Set interleave mode */ 378 if (max98373->interleave_mode) 379 regmap_update_bits(max98373->regmap, 380 MAX98373_R2024_PCM_DATA_FMT_CFG, 381 MAX98373_PCM_TX_CH_INTERLEAVE_MASK, 382 MAX98373_PCM_TX_CH_INTERLEAVE_MASK); 383 384 /* Speaker enable */ 385 regmap_update_bits(max98373->regmap, 386 MAX98373_R2043_AMP_EN, 387 MAX98373_SPK_EN_MASK, 1); 388 389 return 0; 390 } 391 392 const struct snd_soc_component_driver soc_codec_dev_max98373 = { 393 .probe = max98373_probe, 394 .controls = max98373_snd_controls, 395 .num_controls = ARRAY_SIZE(max98373_snd_controls), 396 .dapm_widgets = max98373_dapm_widgets, 397 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets), 398 .dapm_routes = max98373_audio_map, 399 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map), 400 .idle_bias_on = 1, 401 .use_pmdown_time = 1, 402 .endianness = 1, 403 .non_legacy_dai_naming = 1, 404 }; 405 EXPORT_SYMBOL_GPL(soc_codec_dev_max98373); 406 407 void max98373_slot_config(struct device *dev, 408 struct max98373_priv *max98373) 409 { 410 int value; 411 412 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value)) 413 max98373->v_slot = value & 0xF; 414 else 415 max98373->v_slot = 0; 416 417 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value)) 418 max98373->i_slot = value & 0xF; 419 else 420 max98373->i_slot = 1; 421 if (dev->of_node) { 422 max98373->reset_gpio = of_get_named_gpio(dev->of_node, 423 "maxim,reset-gpio", 0); 424 if (!gpio_is_valid(max98373->reset_gpio)) { 425 dev_err(dev, "Looking up %s property in node %s failed %d\n", 426 "maxim,reset-gpio", dev->of_node->full_name, 427 max98373->reset_gpio); 428 } else { 429 dev_dbg(dev, "maxim,reset-gpio=%d", 430 max98373->reset_gpio); 431 } 432 } else { 433 /* this makes reset_gpio as invalid */ 434 max98373->reset_gpio = -1; 435 } 436 437 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value)) 438 max98373->spkfb_slot = value & 0xF; 439 else 440 max98373->spkfb_slot = 2; 441 } 442 EXPORT_SYMBOL_GPL(max98373_slot_config); 443 444 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver"); 445 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>"); 446 MODULE_LICENSE("GPL"); 447