1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017, Maxim Integrated 3 4 #include <linux/acpi.h> 5 #include <linux/delay.h> 6 #include <linux/i2c.h> 7 #include <linux/module.h> 8 #include <linux/regmap.h> 9 #include <linux/slab.h> 10 #include <linux/cdev.h> 11 #include <sound/pcm.h> 12 #include <sound/pcm_params.h> 13 #include <sound/soc.h> 14 #include <linux/gpio.h> 15 #include <linux/of.h> 16 #include <linux/of_gpio.h> 17 #include <sound/tlv.h> 18 #include "max98373.h" 19 20 static struct reg_default max98373_reg[] = { 21 {MAX98373_R2000_SW_RESET, 0x00}, 22 {MAX98373_R2001_INT_RAW1, 0x00}, 23 {MAX98373_R2002_INT_RAW2, 0x00}, 24 {MAX98373_R2003_INT_RAW3, 0x00}, 25 {MAX98373_R2004_INT_STATE1, 0x00}, 26 {MAX98373_R2005_INT_STATE2, 0x00}, 27 {MAX98373_R2006_INT_STATE3, 0x00}, 28 {MAX98373_R2007_INT_FLAG1, 0x00}, 29 {MAX98373_R2008_INT_FLAG2, 0x00}, 30 {MAX98373_R2009_INT_FLAG3, 0x00}, 31 {MAX98373_R200A_INT_EN1, 0x00}, 32 {MAX98373_R200B_INT_EN2, 0x00}, 33 {MAX98373_R200C_INT_EN3, 0x00}, 34 {MAX98373_R200D_INT_FLAG_CLR1, 0x00}, 35 {MAX98373_R200E_INT_FLAG_CLR2, 0x00}, 36 {MAX98373_R200F_INT_FLAG_CLR3, 0x00}, 37 {MAX98373_R2010_IRQ_CTRL, 0x00}, 38 {MAX98373_R2014_THERM_WARN_THRESH, 0x10}, 39 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27}, 40 {MAX98373_R2016_THERM_HYSTERESIS, 0x01}, 41 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0}, 42 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00}, 43 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55}, 44 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE}, 45 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF}, 46 {MAX98373_R2022_PCM_TX_SRC_1, 0x00}, 47 {MAX98373_R2023_PCM_TX_SRC_2, 0x00}, 48 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0}, 49 {MAX98373_R2025_AUDIO_IF_MODE, 0x00}, 50 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04}, 51 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08}, 52 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88}, 53 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00}, 54 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00}, 55 {MAX98373_R202B_PCM_RX_EN, 0x00}, 56 {MAX98373_R202C_PCM_TX_EN, 0x00}, 57 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00}, 58 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00}, 59 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF}, 60 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF}, 61 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30}, 62 {MAX98373_R2034_ICC_TX_CNTL, 0x00}, 63 {MAX98373_R2035_ICC_TX_EN, 0x00}, 64 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05}, 65 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00}, 66 {MAX98373_R203E_AMP_PATH_GAIN, 0x08}, 67 {MAX98373_R203F_AMP_DSP_CFG, 0x02}, 68 {MAX98373_R2040_TONE_GEN_CFG, 0x00}, 69 {MAX98373_R2041_AMP_CFG, 0x03}, 70 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00}, 71 {MAX98373_R2043_AMP_EN, 0x00}, 72 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04}, 73 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00}, 74 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00}, 75 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00}, 76 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00}, 77 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00}, 78 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00}, 79 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00}, 80 {MAX98373_R2090_BDE_LVL_HOLD, 0x00}, 81 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00}, 82 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00}, 83 {MAX98373_R2097_BDE_L1_THRESH, 0x00}, 84 {MAX98373_R2098_BDE_L2_THRESH, 0x00}, 85 {MAX98373_R2099_BDE_L3_THRESH, 0x00}, 86 {MAX98373_R209A_BDE_L4_THRESH, 0x00}, 87 {MAX98373_R209B_BDE_THRESH_HYST, 0x00}, 88 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00}, 89 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00}, 90 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00}, 91 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00}, 92 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00}, 93 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00}, 94 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00}, 95 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00}, 96 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00}, 97 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00}, 98 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00}, 99 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00}, 100 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00}, 101 {MAX98373_R20B5_BDE_EN, 0x00}, 102 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00}, 103 {MAX98373_R20D1_DHT_CFG, 0x01}, 104 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02}, 105 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03}, 106 {MAX98373_R20D4_DHT_EN, 0x00}, 107 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00}, 108 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00}, 109 {MAX98373_R20E2_LIMITER_EN, 0x00}, 110 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00}, 111 {MAX98373_R20FF_GLOBAL_SHDN, 0x00}, 112 {MAX98373_R21FF_REV_ID, 0x42}, 113 }; 114 115 static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 116 { 117 struct snd_soc_component *component = codec_dai->component; 118 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 119 unsigned int format = 0; 120 unsigned int invert = 0; 121 122 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt); 123 124 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 125 case SND_SOC_DAIFMT_NB_NF: 126 break; 127 case SND_SOC_DAIFMT_IB_NF: 128 invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE; 129 break; 130 default: 131 dev_err(component->dev, "DAI invert mode unsupported\n"); 132 return -EINVAL; 133 } 134 135 regmap_update_bits(max98373->regmap, 136 MAX98373_R2026_PCM_CLOCK_RATIO, 137 MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE, 138 invert); 139 140 /* interface format */ 141 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 142 case SND_SOC_DAIFMT_I2S: 143 format = MAX98373_PCM_FORMAT_I2S; 144 break; 145 case SND_SOC_DAIFMT_LEFT_J: 146 format = MAX98373_PCM_FORMAT_LJ; 147 break; 148 case SND_SOC_DAIFMT_DSP_A: 149 format = MAX98373_PCM_FORMAT_TDM_MODE1; 150 break; 151 case SND_SOC_DAIFMT_DSP_B: 152 format = MAX98373_PCM_FORMAT_TDM_MODE0; 153 break; 154 default: 155 return -EINVAL; 156 } 157 158 regmap_update_bits(max98373->regmap, 159 MAX98373_R2024_PCM_DATA_FMT_CFG, 160 MAX98373_PCM_MODE_CFG_FORMAT_MASK, 161 format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT); 162 163 return 0; 164 } 165 166 /* BCLKs per LRCLK */ 167 static const int bclk_sel_table[] = { 168 32, 48, 64, 96, 128, 192, 256, 384, 512, 320, 169 }; 170 171 static int max98373_get_bclk_sel(int bclk) 172 { 173 int i; 174 /* match BCLKs per LRCLK */ 175 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) { 176 if (bclk_sel_table[i] == bclk) 177 return i + 2; 178 } 179 return 0; 180 } 181 182 static int max98373_set_clock(struct snd_soc_component *component, 183 struct snd_pcm_hw_params *params) 184 { 185 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 186 /* BCLK/LRCLK ratio calculation */ 187 int blr_clk_ratio = params_channels(params) * max98373->ch_size; 188 int value; 189 190 if (!max98373->tdm_mode) { 191 /* BCLK configuration */ 192 value = max98373_get_bclk_sel(blr_clk_ratio); 193 if (!value) { 194 dev_err(component->dev, "format unsupported %d\n", 195 params_format(params)); 196 return -EINVAL; 197 } 198 199 regmap_update_bits(max98373->regmap, 200 MAX98373_R2026_PCM_CLOCK_RATIO, 201 MAX98373_PCM_CLK_SETUP_BSEL_MASK, 202 value); 203 } 204 return 0; 205 } 206 207 static int max98373_dai_hw_params(struct snd_pcm_substream *substream, 208 struct snd_pcm_hw_params *params, 209 struct snd_soc_dai *dai) 210 { 211 struct snd_soc_component *component = dai->component; 212 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 213 unsigned int sampling_rate = 0; 214 unsigned int chan_sz = 0; 215 216 /* pcm mode configuration */ 217 switch (snd_pcm_format_width(params_format(params))) { 218 case 16: 219 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 220 break; 221 case 24: 222 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 223 break; 224 case 32: 225 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 226 break; 227 default: 228 dev_err(component->dev, "format unsupported %d\n", 229 params_format(params)); 230 goto err; 231 } 232 233 max98373->ch_size = snd_pcm_format_width(params_format(params)); 234 235 regmap_update_bits(max98373->regmap, 236 MAX98373_R2024_PCM_DATA_FMT_CFG, 237 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 238 239 dev_dbg(component->dev, "format supported %d", 240 params_format(params)); 241 242 /* sampling rate configuration */ 243 switch (params_rate(params)) { 244 case 8000: 245 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000; 246 break; 247 case 11025: 248 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025; 249 break; 250 case 12000: 251 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000; 252 break; 253 case 16000: 254 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000; 255 break; 256 case 22050: 257 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050; 258 break; 259 case 24000: 260 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000; 261 break; 262 case 32000: 263 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000; 264 break; 265 case 44100: 266 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100; 267 break; 268 case 48000: 269 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000; 270 break; 271 default: 272 dev_err(component->dev, "rate %d not supported\n", 273 params_rate(params)); 274 goto err; 275 } 276 277 /* set DAI_SR to correct LRCLK frequency */ 278 regmap_update_bits(max98373->regmap, 279 MAX98373_R2027_PCM_SR_SETUP_1, 280 MAX98373_PCM_SR_SET1_SR_MASK, 281 sampling_rate); 282 regmap_update_bits(max98373->regmap, 283 MAX98373_R2028_PCM_SR_SETUP_2, 284 MAX98373_PCM_SR_SET2_SR_MASK, 285 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT); 286 287 /* set sampling rate of IV */ 288 if (max98373->interleave_mode && 289 sampling_rate > MAX98373_PCM_SR_SET1_SR_16000) 290 regmap_update_bits(max98373->regmap, 291 MAX98373_R2028_PCM_SR_SETUP_2, 292 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 293 sampling_rate - 3); 294 else 295 regmap_update_bits(max98373->regmap, 296 MAX98373_R2028_PCM_SR_SETUP_2, 297 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 298 sampling_rate); 299 300 return max98373_set_clock(component, params); 301 err: 302 return -EINVAL; 303 } 304 305 static int max98373_dai_tdm_slot(struct snd_soc_dai *dai, 306 unsigned int tx_mask, unsigned int rx_mask, 307 int slots, int slot_width) 308 { 309 struct snd_soc_component *component = dai->component; 310 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 311 int bsel = 0; 312 unsigned int chan_sz = 0; 313 unsigned int mask; 314 int x, slot_found; 315 316 if (!tx_mask && !rx_mask && !slots && !slot_width) 317 max98373->tdm_mode = false; 318 else 319 max98373->tdm_mode = true; 320 321 /* BCLK configuration */ 322 bsel = max98373_get_bclk_sel(slots * slot_width); 323 if (bsel == 0) { 324 dev_err(component->dev, "BCLK %d not supported\n", 325 slots * slot_width); 326 return -EINVAL; 327 } 328 329 regmap_update_bits(max98373->regmap, 330 MAX98373_R2026_PCM_CLOCK_RATIO, 331 MAX98373_PCM_CLK_SETUP_BSEL_MASK, 332 bsel); 333 334 /* Channel size configuration */ 335 switch (slot_width) { 336 case 16: 337 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 338 break; 339 case 24: 340 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 341 break; 342 case 32: 343 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 344 break; 345 default: 346 dev_err(component->dev, "format unsupported %d\n", 347 slot_width); 348 return -EINVAL; 349 } 350 351 regmap_update_bits(max98373->regmap, 352 MAX98373_R2024_PCM_DATA_FMT_CFG, 353 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 354 355 /* Rx slot configuration */ 356 slot_found = 0; 357 mask = rx_mask; 358 for (x = 0 ; x < 16 ; x++, mask >>= 1) { 359 if (mask & 0x1) { 360 if (slot_found == 0) 361 regmap_update_bits(max98373->regmap, 362 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 363 MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x); 364 else 365 regmap_write(max98373->regmap, 366 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 367 x); 368 slot_found++; 369 if (slot_found > 1) 370 break; 371 } 372 } 373 374 /* Tx slot Hi-Z configuration */ 375 regmap_write(max98373->regmap, 376 MAX98373_R2020_PCM_TX_HIZ_EN_1, 377 ~tx_mask & 0xFF); 378 regmap_write(max98373->regmap, 379 MAX98373_R2021_PCM_TX_HIZ_EN_2, 380 (~tx_mask & 0xFF00) >> 8); 381 382 return 0; 383 } 384 385 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000 386 387 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 388 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 389 390 static const struct snd_soc_dai_ops max98373_dai_ops = { 391 .set_fmt = max98373_dai_set_fmt, 392 .hw_params = max98373_dai_hw_params, 393 .set_tdm_slot = max98373_dai_tdm_slot, 394 }; 395 396 static int max98373_dac_event(struct snd_soc_dapm_widget *w, 397 struct snd_kcontrol *kcontrol, int event) 398 { 399 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 400 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 401 402 switch (event) { 403 case SND_SOC_DAPM_POST_PMU: 404 regmap_update_bits(max98373->regmap, 405 MAX98373_R20FF_GLOBAL_SHDN, 406 MAX98373_GLOBAL_EN_MASK, 1); 407 break; 408 case SND_SOC_DAPM_POST_PMD: 409 regmap_update_bits(max98373->regmap, 410 MAX98373_R20FF_GLOBAL_SHDN, 411 MAX98373_GLOBAL_EN_MASK, 0); 412 max98373->tdm_mode = false; 413 break; 414 default: 415 return 0; 416 } 417 return 0; 418 } 419 420 static const char * const max98373_switch_text[] = { 421 "Left", "Right", "LeftRight"}; 422 423 static const struct soc_enum dai_sel_enum = 424 SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 425 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT, 426 3, max98373_switch_text); 427 428 static const struct snd_kcontrol_new max98373_dai_controls = 429 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum); 430 431 static const struct snd_kcontrol_new max98373_vi_control = 432 SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0); 433 434 static const struct snd_kcontrol_new max98373_spkfb_control = 435 SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0); 436 437 static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = { 438 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", 439 MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event, 440 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 441 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, 442 &max98373_dai_controls), 443 SND_SOC_DAPM_OUTPUT("BE_OUT"), 444 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0, 445 MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0), 446 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0, 447 MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0), 448 SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0, 449 SND_SOC_NOPM, 0, 0), 450 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0, 451 &max98373_vi_control), 452 SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0, 453 &max98373_spkfb_control), 454 SND_SOC_DAPM_SIGGEN("VMON"), 455 SND_SOC_DAPM_SIGGEN("IMON"), 456 SND_SOC_DAPM_SIGGEN("FBMON"), 457 }; 458 459 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1); 460 static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv, 461 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0), 462 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0), 463 ); 464 static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv, 465 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 466 ); 467 static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv, 468 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0), 469 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0), 470 ); 471 static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv, 472 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 473 ); 474 static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv, 475 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0), 476 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0), 477 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0), 478 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0), 479 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0), 480 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0), 481 ); 482 static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv, 483 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0), 484 ); 485 486 static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv, 487 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0), 488 ); 489 490 static bool max98373_readable_register(struct device *dev, unsigned int reg) 491 { 492 switch (reg) { 493 case MAX98373_R2000_SW_RESET: 494 case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3: 495 case MAX98373_R2010_IRQ_CTRL: 496 case MAX98373_R2014_THERM_WARN_THRESH 497 ... MAX98373_R2018_THERM_FOLDBACK_EN: 498 case MAX98373_R201E_PIN_DRIVE_STRENGTH 499 ... MAX98373_R2036_SOUNDWIRE_CTRL: 500 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN: 501 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 502 ... MAX98373_R2047_IV_SENSE_ADC_EN: 503 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 504 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN: 505 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE: 506 case MAX98373_R2097_BDE_L1_THRESH 507 ... MAX98373_R209B_BDE_THRESH_HYST: 508 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3: 509 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK: 510 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN: 511 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN: 512 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 513 ... MAX98373_R20FF_GLOBAL_SHDN: 514 case MAX98373_R21FF_REV_ID: 515 return true; 516 default: 517 return false; 518 } 519 }; 520 521 static bool max98373_volatile_reg(struct device *dev, unsigned int reg) 522 { 523 switch (reg) { 524 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3: 525 case MAX98373_R203E_AMP_PATH_GAIN: 526 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK: 527 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK: 528 case MAX98373_R20B6_BDE_CUR_STATE_READBACK: 529 case MAX98373_R21FF_REV_ID: 530 return true; 531 default: 532 return false; 533 } 534 } 535 536 static const char * const max98373_output_voltage_lvl_text[] = { 537 "5.43V", "6.09V", "6.83V", "7.67V", "8.60V", 538 "9.65V", "10.83V", "12.15V", "13.63V", "15.29V" 539 }; 540 541 static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum, 542 MAX98373_R203E_AMP_PATH_GAIN, 0, 543 max98373_output_voltage_lvl_text); 544 545 static const char * const max98373_dht_attack_rate_text[] = { 546 "17.5us", "35us", "70us", "140us", 547 "280us", "560us", "1120us", "2240us" 548 }; 549 550 static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum, 551 MAX98373_R20D2_DHT_ATTACK_CFG, 0, 552 max98373_dht_attack_rate_text); 553 554 static const char * const max98373_dht_release_rate_text[] = { 555 "45ms", "225ms", "450ms", "1150ms", 556 "2250ms", "3100ms", "4500ms", "6750ms" 557 }; 558 559 static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum, 560 MAX98373_R20D3_DHT_RELEASE_CFG, 0, 561 max98373_dht_release_rate_text); 562 563 static const char * const max98373_limiter_attack_rate_text[] = { 564 "10us", "20us", "40us", "80us", 565 "160us", "320us", "640us", "1.28ms", 566 "2.56ms", "5.12ms", "10.24ms", "20.48ms", 567 "40.96ms", "81.92ms", "16.384ms", "32.768ms" 568 }; 569 570 static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum, 571 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4, 572 max98373_limiter_attack_rate_text); 573 574 static const char * const max98373_limiter_release_rate_text[] = { 575 "40us", "80us", "160us", "320us", 576 "640us", "1.28ms", "2.56ms", "5.120ms", 577 "10.24ms", "20.48ms", "40.96ms", "81.92ms", 578 "163.84ms", "327.68ms", "655.36ms", "1310.72ms" 579 }; 580 581 static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum, 582 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0, 583 max98373_limiter_release_rate_text); 584 585 static const char * const max98373_ADC_samplerate_text[] = { 586 "333kHz", "192kHz", "64kHz", "48kHz" 587 }; 588 589 static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum, 590 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0, 591 max98373_ADC_samplerate_text); 592 593 static const struct snd_kcontrol_new max98373_snd_controls[] = { 594 SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG, 595 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 596 SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG, 597 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 598 SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG, 599 MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0), 600 SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG, 601 MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0), 602 SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 603 MAX98373_CLOCK_MON_SHIFT, 1, 0), 604 SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG, 605 MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0), 606 SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG, 607 MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0), 608 SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL, 609 0, 0x7F, 1, max98373_digital_tlv), 610 SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN, 611 MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv), 612 SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN, 613 MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv), 614 SOC_ENUM("Output Voltage", max98373_out_volt_enum), 615 /* Dynamic Headroom Tracking */ 616 SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN, 617 MAX98373_DHT_EN_SHIFT, 1, 0), 618 SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG, 619 MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv), 620 SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG, 621 MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv), 622 SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG, 623 MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 624 SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG, 625 MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 626 SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum), 627 SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum), 628 /* ADC configuration */ 629 SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0), 630 SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 631 MAX98373_FLT_EN_SHIFT, 1, 0), 632 SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 633 MAX98373_FLT_EN_SHIFT, 1, 0), 634 SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0), 635 SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0), 636 SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 637 0, 0x3, 0), 638 SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 639 0, 0x3, 0), 640 SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum), 641 /* Brownout Detection Engine */ 642 SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0), 643 SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2, 644 MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0), 645 SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2, 646 MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0), 647 SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0), 648 SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0), 649 SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0), 650 SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0), 651 SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0), 652 SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0), 653 SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0), 654 SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0), 655 SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0), 656 SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0), 657 SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2, 658 0, 0x3C, 1, max98373_bde_gain_tlv), 659 SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2, 660 0, 0x3C, 1, max98373_bde_gain_tlv), 661 SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2, 662 0, 0x3C, 1, max98373_bde_gain_tlv), 663 SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2, 664 0, 0x3C, 1, max98373_bde_gain_tlv), 665 SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3, 666 0, 0x3C, 1, max98373_bde_gain_tlv), 667 SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3, 668 0, 0x3C, 1, max98373_bde_gain_tlv), 669 SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3, 670 0, 0x3C, 1, max98373_bde_gain_tlv), 671 SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3, 672 0, 0x3C, 1, max98373_bde_gain_tlv), 673 SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1, 674 0, 0xF, 1, max98373_limiter_thresh_tlv), 675 SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1, 676 0, 0xF, 1, max98373_limiter_thresh_tlv), 677 SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1, 678 0, 0xF, 1, max98373_limiter_thresh_tlv), 679 SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1, 680 0, 0xF, 1, max98373_limiter_thresh_tlv), 681 /* Limiter */ 682 SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN, 683 MAX98373_LIMITER_EN_SHIFT, 1, 0), 684 SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG, 685 MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0), 686 SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG, 687 MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv), 688 SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum), 689 SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum), 690 }; 691 692 static const struct snd_soc_dapm_route max98373_audio_map[] = { 693 /* Plabyack */ 694 {"DAI Sel Mux", "Left", "Amp Enable"}, 695 {"DAI Sel Mux", "Right", "Amp Enable"}, 696 {"DAI Sel Mux", "LeftRight", "Amp Enable"}, 697 {"BE_OUT", NULL, "DAI Sel Mux"}, 698 /* Capture */ 699 { "VI Sense", "Switch", "VMON" }, 700 { "VI Sense", "Switch", "IMON" }, 701 { "SpkFB Sense", "Switch", "FBMON" }, 702 { "Voltage Sense", NULL, "VI Sense" }, 703 { "Current Sense", NULL, "VI Sense" }, 704 { "Speaker FB Sense", NULL, "SpkFB Sense" }, 705 }; 706 707 static struct snd_soc_dai_driver max98373_dai[] = { 708 { 709 .name = "max98373-aif1", 710 .playback = { 711 .stream_name = "HiFi Playback", 712 .channels_min = 1, 713 .channels_max = 2, 714 .rates = MAX98373_RATES, 715 .formats = MAX98373_FORMATS, 716 }, 717 .capture = { 718 .stream_name = "HiFi Capture", 719 .channels_min = 1, 720 .channels_max = 2, 721 .rates = MAX98373_RATES, 722 .formats = MAX98373_FORMATS, 723 }, 724 .ops = &max98373_dai_ops, 725 } 726 }; 727 728 static void max98373_reset(struct max98373_priv *max98373, struct device *dev) 729 { 730 int ret, reg, count; 731 732 /* Software Reset */ 733 ret = regmap_update_bits(max98373->regmap, 734 MAX98373_R2000_SW_RESET, 735 MAX98373_SOFT_RESET, 736 MAX98373_SOFT_RESET); 737 if (ret) 738 dev_err(dev, "Reset command failed. (ret:%d)\n", ret); 739 740 count = 0; 741 while (count < 3) { 742 usleep_range(10000, 11000); 743 /* Software Reset Verification */ 744 ret = regmap_read(max98373->regmap, 745 MAX98373_R21FF_REV_ID, ®); 746 if (!ret) { 747 dev_info(dev, "Reset completed (retry:%d)\n", count); 748 return; 749 } 750 count++; 751 } 752 dev_err(dev, "Reset failed. (ret:%d)\n", ret); 753 } 754 755 static int max98373_probe(struct snd_soc_component *component) 756 { 757 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 758 759 /* Software Reset */ 760 max98373_reset(max98373, component->dev); 761 762 /* IV default slot configuration */ 763 regmap_write(max98373->regmap, 764 MAX98373_R2020_PCM_TX_HIZ_EN_1, 765 0xFF); 766 regmap_write(max98373->regmap, 767 MAX98373_R2021_PCM_TX_HIZ_EN_2, 768 0xFF); 769 /* L/R mix configuration */ 770 regmap_write(max98373->regmap, 771 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 772 0x80); 773 regmap_write(max98373->regmap, 774 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 775 0x1); 776 /* Set inital volume (0dB) */ 777 regmap_write(max98373->regmap, 778 MAX98373_R203D_AMP_DIG_VOL_CTRL, 779 0x00); 780 regmap_write(max98373->regmap, 781 MAX98373_R203E_AMP_PATH_GAIN, 782 0x00); 783 /* Enable DC blocker */ 784 regmap_write(max98373->regmap, 785 MAX98373_R203F_AMP_DSP_CFG, 786 0x3); 787 /* Enable IMON VMON DC blocker */ 788 regmap_write(max98373->regmap, 789 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 790 0x7); 791 /* voltage, current slot configuration */ 792 regmap_write(max98373->regmap, 793 MAX98373_R2022_PCM_TX_SRC_1, 794 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT | 795 max98373->v_slot) & 0xFF); 796 if (max98373->v_slot < 8) 797 regmap_update_bits(max98373->regmap, 798 MAX98373_R2020_PCM_TX_HIZ_EN_1, 799 1 << max98373->v_slot, 0); 800 else 801 regmap_update_bits(max98373->regmap, 802 MAX98373_R2021_PCM_TX_HIZ_EN_2, 803 1 << (max98373->v_slot - 8), 0); 804 805 if (max98373->i_slot < 8) 806 regmap_update_bits(max98373->regmap, 807 MAX98373_R2020_PCM_TX_HIZ_EN_1, 808 1 << max98373->i_slot, 0); 809 else 810 regmap_update_bits(max98373->regmap, 811 MAX98373_R2021_PCM_TX_HIZ_EN_2, 812 1 << (max98373->i_slot - 8), 0); 813 814 /* speaker feedback slot configuration */ 815 regmap_write(max98373->regmap, 816 MAX98373_R2023_PCM_TX_SRC_2, 817 max98373->spkfb_slot & 0xFF); 818 819 /* Set interleave mode */ 820 if (max98373->interleave_mode) 821 regmap_update_bits(max98373->regmap, 822 MAX98373_R2024_PCM_DATA_FMT_CFG, 823 MAX98373_PCM_TX_CH_INTERLEAVE_MASK, 824 MAX98373_PCM_TX_CH_INTERLEAVE_MASK); 825 826 /* Speaker enable */ 827 regmap_update_bits(max98373->regmap, 828 MAX98373_R2043_AMP_EN, 829 MAX98373_SPK_EN_MASK, 1); 830 831 return 0; 832 } 833 834 #ifdef CONFIG_PM_SLEEP 835 static int max98373_suspend(struct device *dev) 836 { 837 struct max98373_priv *max98373 = dev_get_drvdata(dev); 838 839 regcache_cache_only(max98373->regmap, true); 840 regcache_mark_dirty(max98373->regmap); 841 return 0; 842 } 843 static int max98373_resume(struct device *dev) 844 { 845 struct max98373_priv *max98373 = dev_get_drvdata(dev); 846 847 max98373_reset(max98373, dev); 848 regcache_cache_only(max98373->regmap, false); 849 regcache_sync(max98373->regmap); 850 return 0; 851 } 852 #endif 853 854 static const struct dev_pm_ops max98373_pm = { 855 SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume) 856 }; 857 858 static const struct snd_soc_component_driver soc_codec_dev_max98373 = { 859 .probe = max98373_probe, 860 .controls = max98373_snd_controls, 861 .num_controls = ARRAY_SIZE(max98373_snd_controls), 862 .dapm_widgets = max98373_dapm_widgets, 863 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets), 864 .dapm_routes = max98373_audio_map, 865 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map), 866 .idle_bias_on = 1, 867 .use_pmdown_time = 1, 868 .endianness = 1, 869 .non_legacy_dai_naming = 1, 870 }; 871 872 static const struct regmap_config max98373_regmap = { 873 .reg_bits = 16, 874 .val_bits = 8, 875 .max_register = MAX98373_R21FF_REV_ID, 876 .reg_defaults = max98373_reg, 877 .num_reg_defaults = ARRAY_SIZE(max98373_reg), 878 .readable_reg = max98373_readable_register, 879 .volatile_reg = max98373_volatile_reg, 880 .cache_type = REGCACHE_RBTREE, 881 }; 882 883 static void max98373_slot_config(struct i2c_client *i2c, 884 struct max98373_priv *max98373) 885 { 886 int value; 887 struct device *dev = &i2c->dev; 888 889 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value)) 890 max98373->v_slot = value & 0xF; 891 else 892 max98373->v_slot = 0; 893 894 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value)) 895 max98373->i_slot = value & 0xF; 896 else 897 max98373->i_slot = 1; 898 899 max98373->reset_gpio = of_get_named_gpio(dev->of_node, 900 "maxim,reset-gpio", 0); 901 if (!gpio_is_valid(max98373->reset_gpio)) { 902 dev_err(dev, "Looking up %s property in node %s failed %d\n", 903 "maxim,reset-gpio", dev->of_node->full_name, 904 max98373->reset_gpio); 905 } else { 906 dev_dbg(dev, "maxim,reset-gpio=%d", 907 max98373->reset_gpio); 908 } 909 910 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value)) 911 max98373->spkfb_slot = value & 0xF; 912 else 913 max98373->spkfb_slot = 2; 914 } 915 916 static int max98373_i2c_probe(struct i2c_client *i2c, 917 const struct i2c_device_id *id) 918 { 919 920 int ret = 0; 921 int reg = 0; 922 struct max98373_priv *max98373 = NULL; 923 924 max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL); 925 926 if (!max98373) { 927 ret = -ENOMEM; 928 return ret; 929 } 930 i2c_set_clientdata(i2c, max98373); 931 932 /* update interleave mode info */ 933 if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode")) 934 max98373->interleave_mode = true; 935 else 936 max98373->interleave_mode = false; 937 938 /* regmap initialization */ 939 max98373->regmap 940 = devm_regmap_init_i2c(i2c, &max98373_regmap); 941 if (IS_ERR(max98373->regmap)) { 942 ret = PTR_ERR(max98373->regmap); 943 dev_err(&i2c->dev, 944 "Failed to allocate regmap: %d\n", ret); 945 return ret; 946 } 947 948 /* voltage/current slot & gpio configuration */ 949 max98373_slot_config(i2c, max98373); 950 951 /* Power on device */ 952 if (gpio_is_valid(max98373->reset_gpio)) { 953 ret = gpio_request(max98373->reset_gpio, "MAX98373_RESET"); 954 if (ret) { 955 dev_err(&i2c->dev, "%s: Failed to request gpio %d\n", 956 __func__, max98373->reset_gpio); 957 gpio_free(max98373->reset_gpio); 958 return -EINVAL; 959 } 960 gpio_direction_output(max98373->reset_gpio, 0); 961 msleep(50); 962 gpio_direction_output(max98373->reset_gpio, 1); 963 msleep(20); 964 } 965 966 /* Check Revision ID */ 967 ret = regmap_read(max98373->regmap, 968 MAX98373_R21FF_REV_ID, ®); 969 if (ret < 0) { 970 dev_err(&i2c->dev, 971 "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID); 972 return ret; 973 } 974 dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg); 975 976 /* codec registeration */ 977 ret = devm_snd_soc_register_component(&i2c->dev, &soc_codec_dev_max98373, 978 max98373_dai, ARRAY_SIZE(max98373_dai)); 979 if (ret < 0) 980 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 981 982 return ret; 983 } 984 985 static const struct i2c_device_id max98373_i2c_id[] = { 986 { "max98373", 0}, 987 { }, 988 }; 989 990 MODULE_DEVICE_TABLE(i2c, max98373_i2c_id); 991 992 #if defined(CONFIG_OF) 993 static const struct of_device_id max98373_of_match[] = { 994 { .compatible = "maxim,max98373", }, 995 { } 996 }; 997 MODULE_DEVICE_TABLE(of, max98373_of_match); 998 #endif 999 1000 #ifdef CONFIG_ACPI 1001 static const struct acpi_device_id max98373_acpi_match[] = { 1002 { "MX98373", 0 }, 1003 {}, 1004 }; 1005 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match); 1006 #endif 1007 1008 static struct i2c_driver max98373_i2c_driver = { 1009 .driver = { 1010 .name = "max98373", 1011 .of_match_table = of_match_ptr(max98373_of_match), 1012 .acpi_match_table = ACPI_PTR(max98373_acpi_match), 1013 .pm = &max98373_pm, 1014 }, 1015 .probe = max98373_i2c_probe, 1016 .id_table = max98373_i2c_id, 1017 }; 1018 1019 module_i2c_driver(max98373_i2c_driver) 1020 1021 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver"); 1022 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>"); 1023 MODULE_LICENSE("GPL"); 1024