1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017, Maxim Integrated 3 4 #include <linux/acpi.h> 5 #include <linux/delay.h> 6 #include <linux/i2c.h> 7 #include <linux/module.h> 8 #include <linux/regmap.h> 9 #include <linux/slab.h> 10 #include <linux/cdev.h> 11 #include <sound/pcm.h> 12 #include <sound/pcm_params.h> 13 #include <sound/soc.h> 14 #include <linux/gpio.h> 15 #include <linux/of_gpio.h> 16 #include <sound/tlv.h> 17 #include "max98373.h" 18 19 static struct reg_default max98373_reg[] = { 20 {MAX98373_R2000_SW_RESET, 0x00}, 21 {MAX98373_R2001_INT_RAW1, 0x00}, 22 {MAX98373_R2002_INT_RAW2, 0x00}, 23 {MAX98373_R2003_INT_RAW3, 0x00}, 24 {MAX98373_R2004_INT_STATE1, 0x00}, 25 {MAX98373_R2005_INT_STATE2, 0x00}, 26 {MAX98373_R2006_INT_STATE3, 0x00}, 27 {MAX98373_R2007_INT_FLAG1, 0x00}, 28 {MAX98373_R2008_INT_FLAG2, 0x00}, 29 {MAX98373_R2009_INT_FLAG3, 0x00}, 30 {MAX98373_R200A_INT_EN1, 0x00}, 31 {MAX98373_R200B_INT_EN2, 0x00}, 32 {MAX98373_R200C_INT_EN3, 0x00}, 33 {MAX98373_R200D_INT_FLAG_CLR1, 0x00}, 34 {MAX98373_R200E_INT_FLAG_CLR2, 0x00}, 35 {MAX98373_R200F_INT_FLAG_CLR3, 0x00}, 36 {MAX98373_R2010_IRQ_CTRL, 0x00}, 37 {MAX98373_R2014_THERM_WARN_THRESH, 0x10}, 38 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27}, 39 {MAX98373_R2016_THERM_HYSTERESIS, 0x01}, 40 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0}, 41 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00}, 42 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55}, 43 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE}, 44 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF}, 45 {MAX98373_R2022_PCM_TX_SRC_1, 0x00}, 46 {MAX98373_R2023_PCM_TX_SRC_2, 0x00}, 47 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0}, 48 {MAX98373_R2025_AUDIO_IF_MODE, 0x00}, 49 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04}, 50 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08}, 51 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88}, 52 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00}, 53 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00}, 54 {MAX98373_R202B_PCM_RX_EN, 0x00}, 55 {MAX98373_R202C_PCM_TX_EN, 0x00}, 56 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00}, 57 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00}, 58 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF}, 59 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF}, 60 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30}, 61 {MAX98373_R2034_ICC_TX_CNTL, 0x00}, 62 {MAX98373_R2035_ICC_TX_EN, 0x00}, 63 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05}, 64 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00}, 65 {MAX98373_R203E_AMP_PATH_GAIN, 0x08}, 66 {MAX98373_R203F_AMP_DSP_CFG, 0x02}, 67 {MAX98373_R2040_TONE_GEN_CFG, 0x00}, 68 {MAX98373_R2041_AMP_CFG, 0x03}, 69 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00}, 70 {MAX98373_R2043_AMP_EN, 0x00}, 71 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04}, 72 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00}, 73 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00}, 74 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00}, 75 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00}, 76 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00}, 77 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00}, 78 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00}, 79 {MAX98373_R2090_BDE_LVL_HOLD, 0x00}, 80 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00}, 81 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00}, 82 {MAX98373_R2097_BDE_L1_THRESH, 0x00}, 83 {MAX98373_R2098_BDE_L2_THRESH, 0x00}, 84 {MAX98373_R2099_BDE_L3_THRESH, 0x00}, 85 {MAX98373_R209A_BDE_L4_THRESH, 0x00}, 86 {MAX98373_R209B_BDE_THRESH_HYST, 0x00}, 87 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00}, 88 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00}, 89 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00}, 90 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00}, 91 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00}, 92 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00}, 93 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00}, 94 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00}, 95 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00}, 96 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00}, 97 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00}, 98 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00}, 99 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00}, 100 {MAX98373_R20B5_BDE_EN, 0x00}, 101 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00}, 102 {MAX98373_R20D1_DHT_CFG, 0x01}, 103 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02}, 104 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03}, 105 {MAX98373_R20D4_DHT_EN, 0x00}, 106 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00}, 107 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00}, 108 {MAX98373_R20E2_LIMITER_EN, 0x00}, 109 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00}, 110 {MAX98373_R20FF_GLOBAL_SHDN, 0x00}, 111 {MAX98373_R21FF_REV_ID, 0x42}, 112 }; 113 114 static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 115 { 116 struct snd_soc_component *component = codec_dai->component; 117 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 118 unsigned int format = 0; 119 unsigned int invert = 0; 120 121 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt); 122 123 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 124 case SND_SOC_DAIFMT_NB_NF: 125 break; 126 case SND_SOC_DAIFMT_IB_NF: 127 invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE; 128 break; 129 default: 130 dev_err(component->dev, "DAI invert mode unsupported\n"); 131 return -EINVAL; 132 } 133 134 regmap_update_bits(max98373->regmap, 135 MAX98373_R2026_PCM_CLOCK_RATIO, 136 MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE, 137 invert); 138 139 /* interface format */ 140 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 141 case SND_SOC_DAIFMT_I2S: 142 format = MAX98373_PCM_FORMAT_I2S; 143 break; 144 case SND_SOC_DAIFMT_LEFT_J: 145 format = MAX98373_PCM_FORMAT_LJ; 146 break; 147 case SND_SOC_DAIFMT_DSP_A: 148 format = MAX98373_PCM_FORMAT_TDM_MODE1; 149 break; 150 case SND_SOC_DAIFMT_DSP_B: 151 format = MAX98373_PCM_FORMAT_TDM_MODE0; 152 break; 153 default: 154 return -EINVAL; 155 } 156 157 regmap_update_bits(max98373->regmap, 158 MAX98373_R2024_PCM_DATA_FMT_CFG, 159 MAX98373_PCM_MODE_CFG_FORMAT_MASK, 160 format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT); 161 162 return 0; 163 } 164 165 /* BCLKs per LRCLK */ 166 static const int bclk_sel_table[] = { 167 32, 48, 64, 96, 128, 192, 256, 384, 512, 320, 168 }; 169 170 static int max98373_get_bclk_sel(int bclk) 171 { 172 int i; 173 /* match BCLKs per LRCLK */ 174 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) { 175 if (bclk_sel_table[i] == bclk) 176 return i + 2; 177 } 178 return 0; 179 } 180 181 static int max98373_set_clock(struct snd_soc_component *component, 182 struct snd_pcm_hw_params *params) 183 { 184 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 185 /* BCLK/LRCLK ratio calculation */ 186 int blr_clk_ratio = params_channels(params) * max98373->ch_size; 187 int value; 188 189 if (!max98373->tdm_mode) { 190 /* BCLK configuration */ 191 value = max98373_get_bclk_sel(blr_clk_ratio); 192 if (!value) { 193 dev_err(component->dev, "format unsupported %d\n", 194 params_format(params)); 195 return -EINVAL; 196 } 197 198 regmap_update_bits(max98373->regmap, 199 MAX98373_R2026_PCM_CLOCK_RATIO, 200 MAX98373_PCM_CLK_SETUP_BSEL_MASK, 201 value); 202 } 203 return 0; 204 } 205 206 static int max98373_dai_hw_params(struct snd_pcm_substream *substream, 207 struct snd_pcm_hw_params *params, 208 struct snd_soc_dai *dai) 209 { 210 struct snd_soc_component *component = dai->component; 211 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 212 unsigned int sampling_rate = 0; 213 unsigned int chan_sz = 0; 214 215 /* pcm mode configuration */ 216 switch (snd_pcm_format_width(params_format(params))) { 217 case 16: 218 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 219 break; 220 case 24: 221 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 222 break; 223 case 32: 224 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 225 break; 226 default: 227 dev_err(component->dev, "format unsupported %d\n", 228 params_format(params)); 229 goto err; 230 } 231 232 max98373->ch_size = snd_pcm_format_width(params_format(params)); 233 234 regmap_update_bits(max98373->regmap, 235 MAX98373_R2024_PCM_DATA_FMT_CFG, 236 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 237 238 dev_dbg(component->dev, "format supported %d", 239 params_format(params)); 240 241 /* sampling rate configuration */ 242 switch (params_rate(params)) { 243 case 8000: 244 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000; 245 break; 246 case 11025: 247 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025; 248 break; 249 case 12000: 250 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000; 251 break; 252 case 16000: 253 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000; 254 break; 255 case 22050: 256 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050; 257 break; 258 case 24000: 259 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000; 260 break; 261 case 32000: 262 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000; 263 break; 264 case 44100: 265 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100; 266 break; 267 case 48000: 268 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000; 269 break; 270 case 88200: 271 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200; 272 break; 273 case 96000: 274 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000; 275 break; 276 default: 277 dev_err(component->dev, "rate %d not supported\n", 278 params_rate(params)); 279 goto err; 280 } 281 282 /* set DAI_SR to correct LRCLK frequency */ 283 regmap_update_bits(max98373->regmap, 284 MAX98373_R2027_PCM_SR_SETUP_1, 285 MAX98373_PCM_SR_SET1_SR_MASK, 286 sampling_rate); 287 regmap_update_bits(max98373->regmap, 288 MAX98373_R2028_PCM_SR_SETUP_2, 289 MAX98373_PCM_SR_SET2_SR_MASK, 290 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT); 291 292 /* set sampling rate of IV */ 293 if (max98373->interleave_mode && 294 sampling_rate > MAX98373_PCM_SR_SET1_SR_16000) 295 regmap_update_bits(max98373->regmap, 296 MAX98373_R2028_PCM_SR_SETUP_2, 297 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 298 sampling_rate - 3); 299 else 300 regmap_update_bits(max98373->regmap, 301 MAX98373_R2028_PCM_SR_SETUP_2, 302 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 303 sampling_rate); 304 305 return max98373_set_clock(component, params); 306 err: 307 return -EINVAL; 308 } 309 310 static int max98373_dai_tdm_slot(struct snd_soc_dai *dai, 311 unsigned int tx_mask, unsigned int rx_mask, 312 int slots, int slot_width) 313 { 314 struct snd_soc_component *component = dai->component; 315 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 316 int bsel = 0; 317 unsigned int chan_sz = 0; 318 unsigned int mask; 319 int x, slot_found; 320 321 if (!tx_mask && !rx_mask && !slots && !slot_width) 322 max98373->tdm_mode = false; 323 else 324 max98373->tdm_mode = true; 325 326 /* BCLK configuration */ 327 bsel = max98373_get_bclk_sel(slots * slot_width); 328 if (bsel == 0) { 329 dev_err(component->dev, "BCLK %d not supported\n", 330 slots * slot_width); 331 return -EINVAL; 332 } 333 334 regmap_update_bits(max98373->regmap, 335 MAX98373_R2026_PCM_CLOCK_RATIO, 336 MAX98373_PCM_CLK_SETUP_BSEL_MASK, 337 bsel); 338 339 /* Channel size configuration */ 340 switch (slot_width) { 341 case 16: 342 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 343 break; 344 case 24: 345 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 346 break; 347 case 32: 348 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 349 break; 350 default: 351 dev_err(component->dev, "format unsupported %d\n", 352 slot_width); 353 return -EINVAL; 354 } 355 356 regmap_update_bits(max98373->regmap, 357 MAX98373_R2024_PCM_DATA_FMT_CFG, 358 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 359 360 /* Rx slot configuration */ 361 slot_found = 0; 362 mask = rx_mask; 363 for (x = 0 ; x < 16 ; x++, mask >>= 1) { 364 if (mask & 0x1) { 365 if (slot_found == 0) 366 regmap_update_bits(max98373->regmap, 367 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 368 MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x); 369 else 370 regmap_write(max98373->regmap, 371 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 372 x); 373 slot_found++; 374 if (slot_found > 1) 375 break; 376 } 377 } 378 379 /* Tx slot Hi-Z configuration */ 380 regmap_write(max98373->regmap, 381 MAX98373_R2020_PCM_TX_HIZ_EN_1, 382 ~tx_mask & 0xFF); 383 regmap_write(max98373->regmap, 384 MAX98373_R2021_PCM_TX_HIZ_EN_2, 385 (~tx_mask & 0xFF00) >> 8); 386 387 return 0; 388 } 389 390 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000 391 392 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 393 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 394 395 static const struct snd_soc_dai_ops max98373_dai_ops = { 396 .set_fmt = max98373_dai_set_fmt, 397 .hw_params = max98373_dai_hw_params, 398 .set_tdm_slot = max98373_dai_tdm_slot, 399 }; 400 401 static int max98373_dac_event(struct snd_soc_dapm_widget *w, 402 struct snd_kcontrol *kcontrol, int event) 403 { 404 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 405 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 406 407 switch (event) { 408 case SND_SOC_DAPM_POST_PMU: 409 regmap_update_bits(max98373->regmap, 410 MAX98373_R20FF_GLOBAL_SHDN, 411 MAX98373_GLOBAL_EN_MASK, 1); 412 break; 413 case SND_SOC_DAPM_POST_PMD: 414 regmap_update_bits(max98373->regmap, 415 MAX98373_R20FF_GLOBAL_SHDN, 416 MAX98373_GLOBAL_EN_MASK, 0); 417 max98373->tdm_mode = false; 418 break; 419 default: 420 return 0; 421 } 422 return 0; 423 } 424 425 static const char * const max98373_switch_text[] = { 426 "Left", "Right", "LeftRight"}; 427 428 static const struct soc_enum dai_sel_enum = 429 SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 430 MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT, 431 3, max98373_switch_text); 432 433 static const struct snd_kcontrol_new max98373_dai_controls = 434 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum); 435 436 static const struct snd_kcontrol_new max98373_vi_control = 437 SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0); 438 439 static const struct snd_kcontrol_new max98373_spkfb_control = 440 SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0); 441 442 static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = { 443 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", 444 MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event, 445 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 446 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, 447 &max98373_dai_controls), 448 SND_SOC_DAPM_OUTPUT("BE_OUT"), 449 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0, 450 MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0), 451 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0, 452 MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0), 453 SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0, 454 SND_SOC_NOPM, 0, 0), 455 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0, 456 &max98373_vi_control), 457 SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0, 458 &max98373_spkfb_control), 459 SND_SOC_DAPM_SIGGEN("VMON"), 460 SND_SOC_DAPM_SIGGEN("IMON"), 461 SND_SOC_DAPM_SIGGEN("FBMON"), 462 }; 463 464 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1); 465 static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv, 466 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0), 467 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0), 468 ); 469 static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv, 470 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 471 ); 472 static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv, 473 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0), 474 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0), 475 ); 476 static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv, 477 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 478 ); 479 static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv, 480 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0), 481 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0), 482 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0), 483 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0), 484 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0), 485 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0), 486 ); 487 static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv, 488 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0), 489 ); 490 491 static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv, 492 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0), 493 ); 494 495 static bool max98373_readable_register(struct device *dev, unsigned int reg) 496 { 497 switch (reg) { 498 case MAX98373_R2000_SW_RESET: 499 case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3: 500 case MAX98373_R2010_IRQ_CTRL: 501 case MAX98373_R2014_THERM_WARN_THRESH 502 ... MAX98373_R2018_THERM_FOLDBACK_EN: 503 case MAX98373_R201E_PIN_DRIVE_STRENGTH 504 ... MAX98373_R2036_SOUNDWIRE_CTRL: 505 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN: 506 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 507 ... MAX98373_R2047_IV_SENSE_ADC_EN: 508 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 509 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN: 510 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE: 511 case MAX98373_R2097_BDE_L1_THRESH 512 ... MAX98373_R209B_BDE_THRESH_HYST: 513 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3: 514 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK: 515 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN: 516 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN: 517 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 518 ... MAX98373_R20FF_GLOBAL_SHDN: 519 case MAX98373_R21FF_REV_ID: 520 return true; 521 default: 522 return false; 523 } 524 }; 525 526 static bool max98373_volatile_reg(struct device *dev, unsigned int reg) 527 { 528 switch (reg) { 529 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3: 530 case MAX98373_R203E_AMP_PATH_GAIN: 531 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK: 532 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK: 533 case MAX98373_R20B6_BDE_CUR_STATE_READBACK: 534 case MAX98373_R21FF_REV_ID: 535 return true; 536 default: 537 return false; 538 } 539 } 540 541 static const char * const max98373_output_voltage_lvl_text[] = { 542 "5.43V", "6.09V", "6.83V", "7.67V", "8.60V", 543 "9.65V", "10.83V", "12.15V", "13.63V", "15.29V" 544 }; 545 546 static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum, 547 MAX98373_R203E_AMP_PATH_GAIN, 0, 548 max98373_output_voltage_lvl_text); 549 550 static const char * const max98373_dht_attack_rate_text[] = { 551 "17.5us", "35us", "70us", "140us", 552 "280us", "560us", "1120us", "2240us" 553 }; 554 555 static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum, 556 MAX98373_R20D2_DHT_ATTACK_CFG, 0, 557 max98373_dht_attack_rate_text); 558 559 static const char * const max98373_dht_release_rate_text[] = { 560 "45ms", "225ms", "450ms", "1150ms", 561 "2250ms", "3100ms", "4500ms", "6750ms" 562 }; 563 564 static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum, 565 MAX98373_R20D3_DHT_RELEASE_CFG, 0, 566 max98373_dht_release_rate_text); 567 568 static const char * const max98373_limiter_attack_rate_text[] = { 569 "10us", "20us", "40us", "80us", 570 "160us", "320us", "640us", "1.28ms", 571 "2.56ms", "5.12ms", "10.24ms", "20.48ms", 572 "40.96ms", "81.92ms", "16.384ms", "32.768ms" 573 }; 574 575 static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum, 576 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4, 577 max98373_limiter_attack_rate_text); 578 579 static const char * const max98373_limiter_release_rate_text[] = { 580 "40us", "80us", "160us", "320us", 581 "640us", "1.28ms", "2.56ms", "5.120ms", 582 "10.24ms", "20.48ms", "40.96ms", "81.92ms", 583 "163.84ms", "327.68ms", "655.36ms", "1310.72ms" 584 }; 585 586 static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum, 587 MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0, 588 max98373_limiter_release_rate_text); 589 590 static const char * const max98373_ADC_samplerate_text[] = { 591 "333kHz", "192kHz", "64kHz", "48kHz" 592 }; 593 594 static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum, 595 MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0, 596 max98373_ADC_samplerate_text); 597 598 static const struct snd_kcontrol_new max98373_snd_controls[] = { 599 SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG, 600 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 601 SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG, 602 MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 603 SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG, 604 MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0), 605 SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG, 606 MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0), 607 SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 608 MAX98373_CLOCK_MON_SHIFT, 1, 0), 609 SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG, 610 MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0), 611 SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG, 612 MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0), 613 SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL, 614 0, 0x7F, 1, max98373_digital_tlv), 615 SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN, 616 MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv), 617 SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN, 618 MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv), 619 SOC_ENUM("Output Voltage", max98373_out_volt_enum), 620 /* Dynamic Headroom Tracking */ 621 SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN, 622 MAX98373_DHT_EN_SHIFT, 1, 0), 623 SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG, 624 MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv), 625 SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG, 626 MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv), 627 SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG, 628 MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 629 SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG, 630 MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 631 SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum), 632 SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum), 633 /* ADC configuration */ 634 SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0), 635 SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 636 MAX98373_FLT_EN_SHIFT, 1, 0), 637 SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 638 MAX98373_FLT_EN_SHIFT, 1, 0), 639 SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0), 640 SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0), 641 SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 642 0, 0x3, 0), 643 SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 644 0, 0x3, 0), 645 SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum), 646 /* Brownout Detection Engine */ 647 SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0), 648 SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2, 649 MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0), 650 SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2, 651 MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0), 652 SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0), 653 SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0), 654 SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0), 655 SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0), 656 SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0), 657 SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0), 658 SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0), 659 SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0), 660 SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0), 661 SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0), 662 SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2, 663 0, 0x3C, 1, max98373_bde_gain_tlv), 664 SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2, 665 0, 0x3C, 1, max98373_bde_gain_tlv), 666 SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2, 667 0, 0x3C, 1, max98373_bde_gain_tlv), 668 SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2, 669 0, 0x3C, 1, max98373_bde_gain_tlv), 670 SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3, 671 0, 0x3C, 1, max98373_bde_gain_tlv), 672 SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3, 673 0, 0x3C, 1, max98373_bde_gain_tlv), 674 SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3, 675 0, 0x3C, 1, max98373_bde_gain_tlv), 676 SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3, 677 0, 0x3C, 1, max98373_bde_gain_tlv), 678 SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1, 679 0, 0xF, 1, max98373_limiter_thresh_tlv), 680 SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1, 681 0, 0xF, 1, max98373_limiter_thresh_tlv), 682 SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1, 683 0, 0xF, 1, max98373_limiter_thresh_tlv), 684 SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1, 685 0, 0xF, 1, max98373_limiter_thresh_tlv), 686 /* Limiter */ 687 SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN, 688 MAX98373_LIMITER_EN_SHIFT, 1, 0), 689 SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG, 690 MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0), 691 SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG, 692 MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv), 693 SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum), 694 SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum), 695 }; 696 697 static const struct snd_soc_dapm_route max98373_audio_map[] = { 698 /* Plabyack */ 699 {"DAI Sel Mux", "Left", "Amp Enable"}, 700 {"DAI Sel Mux", "Right", "Amp Enable"}, 701 {"DAI Sel Mux", "LeftRight", "Amp Enable"}, 702 {"BE_OUT", NULL, "DAI Sel Mux"}, 703 /* Capture */ 704 { "VI Sense", "Switch", "VMON" }, 705 { "VI Sense", "Switch", "IMON" }, 706 { "SpkFB Sense", "Switch", "FBMON" }, 707 { "Voltage Sense", NULL, "VI Sense" }, 708 { "Current Sense", NULL, "VI Sense" }, 709 { "Speaker FB Sense", NULL, "SpkFB Sense" }, 710 }; 711 712 static struct snd_soc_dai_driver max98373_dai[] = { 713 { 714 .name = "max98373-aif1", 715 .playback = { 716 .stream_name = "HiFi Playback", 717 .channels_min = 1, 718 .channels_max = 2, 719 .rates = MAX98373_RATES, 720 .formats = MAX98373_FORMATS, 721 }, 722 .capture = { 723 .stream_name = "HiFi Capture", 724 .channels_min = 1, 725 .channels_max = 2, 726 .rates = MAX98373_RATES, 727 .formats = MAX98373_FORMATS, 728 }, 729 .ops = &max98373_dai_ops, 730 } 731 }; 732 733 static void max98373_reset(struct max98373_priv *max98373, struct device *dev) 734 { 735 int ret, reg, count; 736 737 /* Software Reset */ 738 ret = regmap_update_bits(max98373->regmap, 739 MAX98373_R2000_SW_RESET, 740 MAX98373_SOFT_RESET, 741 MAX98373_SOFT_RESET); 742 if (ret) 743 dev_err(dev, "Reset command failed. (ret:%d)\n", ret); 744 745 count = 0; 746 while (count < 3) { 747 usleep_range(10000, 11000); 748 /* Software Reset Verification */ 749 ret = regmap_read(max98373->regmap, 750 MAX98373_R21FF_REV_ID, ®); 751 if (!ret) { 752 dev_info(dev, "Reset completed (retry:%d)\n", count); 753 return; 754 } 755 count++; 756 } 757 dev_err(dev, "Reset failed. (ret:%d)\n", ret); 758 } 759 760 static int max98373_probe(struct snd_soc_component *component) 761 { 762 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 763 764 /* Software Reset */ 765 max98373_reset(max98373, component->dev); 766 767 /* IV default slot configuration */ 768 regmap_write(max98373->regmap, 769 MAX98373_R2020_PCM_TX_HIZ_EN_1, 770 0xFF); 771 regmap_write(max98373->regmap, 772 MAX98373_R2021_PCM_TX_HIZ_EN_2, 773 0xFF); 774 /* L/R mix configuration */ 775 regmap_write(max98373->regmap, 776 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 777 0x80); 778 regmap_write(max98373->regmap, 779 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 780 0x1); 781 /* Set inital volume (0dB) */ 782 regmap_write(max98373->regmap, 783 MAX98373_R203D_AMP_DIG_VOL_CTRL, 784 0x00); 785 regmap_write(max98373->regmap, 786 MAX98373_R203E_AMP_PATH_GAIN, 787 0x00); 788 /* Enable DC blocker */ 789 regmap_write(max98373->regmap, 790 MAX98373_R203F_AMP_DSP_CFG, 791 0x3); 792 /* Enable IMON VMON DC blocker */ 793 regmap_write(max98373->regmap, 794 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 795 0x7); 796 /* voltage, current slot configuration */ 797 regmap_write(max98373->regmap, 798 MAX98373_R2022_PCM_TX_SRC_1, 799 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT | 800 max98373->v_slot) & 0xFF); 801 if (max98373->v_slot < 8) 802 regmap_update_bits(max98373->regmap, 803 MAX98373_R2020_PCM_TX_HIZ_EN_1, 804 1 << max98373->v_slot, 0); 805 else 806 regmap_update_bits(max98373->regmap, 807 MAX98373_R2021_PCM_TX_HIZ_EN_2, 808 1 << (max98373->v_slot - 8), 0); 809 810 if (max98373->i_slot < 8) 811 regmap_update_bits(max98373->regmap, 812 MAX98373_R2020_PCM_TX_HIZ_EN_1, 813 1 << max98373->i_slot, 0); 814 else 815 regmap_update_bits(max98373->regmap, 816 MAX98373_R2021_PCM_TX_HIZ_EN_2, 817 1 << (max98373->i_slot - 8), 0); 818 819 /* speaker feedback slot configuration */ 820 regmap_write(max98373->regmap, 821 MAX98373_R2023_PCM_TX_SRC_2, 822 max98373->spkfb_slot & 0xFF); 823 824 /* Set interleave mode */ 825 if (max98373->interleave_mode) 826 regmap_update_bits(max98373->regmap, 827 MAX98373_R2024_PCM_DATA_FMT_CFG, 828 MAX98373_PCM_TX_CH_INTERLEAVE_MASK, 829 MAX98373_PCM_TX_CH_INTERLEAVE_MASK); 830 831 /* Speaker enable */ 832 regmap_update_bits(max98373->regmap, 833 MAX98373_R2043_AMP_EN, 834 MAX98373_SPK_EN_MASK, 1); 835 836 return 0; 837 } 838 839 #ifdef CONFIG_PM_SLEEP 840 static int max98373_suspend(struct device *dev) 841 { 842 struct max98373_priv *max98373 = dev_get_drvdata(dev); 843 844 regcache_cache_only(max98373->regmap, true); 845 regcache_mark_dirty(max98373->regmap); 846 return 0; 847 } 848 static int max98373_resume(struct device *dev) 849 { 850 struct max98373_priv *max98373 = dev_get_drvdata(dev); 851 852 max98373_reset(max98373, dev); 853 regcache_cache_only(max98373->regmap, false); 854 regcache_sync(max98373->regmap); 855 return 0; 856 } 857 #endif 858 859 static const struct dev_pm_ops max98373_pm = { 860 SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume) 861 }; 862 863 static const struct snd_soc_component_driver soc_codec_dev_max98373 = { 864 .probe = max98373_probe, 865 .controls = max98373_snd_controls, 866 .num_controls = ARRAY_SIZE(max98373_snd_controls), 867 .dapm_widgets = max98373_dapm_widgets, 868 .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets), 869 .dapm_routes = max98373_audio_map, 870 .num_dapm_routes = ARRAY_SIZE(max98373_audio_map), 871 .idle_bias_on = 1, 872 .use_pmdown_time = 1, 873 .endianness = 1, 874 .non_legacy_dai_naming = 1, 875 }; 876 877 static const struct regmap_config max98373_regmap = { 878 .reg_bits = 16, 879 .val_bits = 8, 880 .max_register = MAX98373_R21FF_REV_ID, 881 .reg_defaults = max98373_reg, 882 .num_reg_defaults = ARRAY_SIZE(max98373_reg), 883 .readable_reg = max98373_readable_register, 884 .volatile_reg = max98373_volatile_reg, 885 .cache_type = REGCACHE_RBTREE, 886 }; 887 888 static void max98373_slot_config(struct i2c_client *i2c, 889 struct max98373_priv *max98373) 890 { 891 int value; 892 struct device *dev = &i2c->dev; 893 894 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value)) 895 max98373->v_slot = value & 0xF; 896 else 897 max98373->v_slot = 0; 898 899 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value)) 900 max98373->i_slot = value & 0xF; 901 else 902 max98373->i_slot = 1; 903 904 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value)) 905 max98373->spkfb_slot = value & 0xF; 906 else 907 max98373->spkfb_slot = 2; 908 } 909 910 static int max98373_i2c_probe(struct i2c_client *i2c, 911 const struct i2c_device_id *id) 912 { 913 914 int ret = 0; 915 int reg = 0; 916 struct max98373_priv *max98373 = NULL; 917 918 max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL); 919 920 if (!max98373) { 921 ret = -ENOMEM; 922 return ret; 923 } 924 i2c_set_clientdata(i2c, max98373); 925 926 /* update interleave mode info */ 927 if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode")) 928 max98373->interleave_mode = true; 929 else 930 max98373->interleave_mode = false; 931 932 933 /* regmap initialization */ 934 max98373->regmap 935 = devm_regmap_init_i2c(i2c, &max98373_regmap); 936 if (IS_ERR(max98373->regmap)) { 937 ret = PTR_ERR(max98373->regmap); 938 dev_err(&i2c->dev, 939 "Failed to allocate regmap: %d\n", ret); 940 return ret; 941 } 942 943 /* Check Revision ID */ 944 ret = regmap_read(max98373->regmap, 945 MAX98373_R21FF_REV_ID, ®); 946 if (ret < 0) { 947 dev_err(&i2c->dev, 948 "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID); 949 return ret; 950 } 951 dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg); 952 953 /* voltage/current slot configuration */ 954 max98373_slot_config(i2c, max98373); 955 956 /* codec registeration */ 957 ret = devm_snd_soc_register_component(&i2c->dev, &soc_codec_dev_max98373, 958 max98373_dai, ARRAY_SIZE(max98373_dai)); 959 if (ret < 0) 960 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 961 962 return ret; 963 } 964 965 static const struct i2c_device_id max98373_i2c_id[] = { 966 { "max98373", 0}, 967 { }, 968 }; 969 970 MODULE_DEVICE_TABLE(i2c, max98373_i2c_id); 971 972 #if defined(CONFIG_OF) 973 static const struct of_device_id max98373_of_match[] = { 974 { .compatible = "maxim,max98373", }, 975 { } 976 }; 977 MODULE_DEVICE_TABLE(of, max98373_of_match); 978 #endif 979 980 #ifdef CONFIG_ACPI 981 static const struct acpi_device_id max98373_acpi_match[] = { 982 { "MX98373", 0 }, 983 {}, 984 }; 985 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match); 986 #endif 987 988 static struct i2c_driver max98373_i2c_driver = { 989 .driver = { 990 .name = "max98373", 991 .of_match_table = of_match_ptr(max98373_of_match), 992 .acpi_match_table = ACPI_PTR(max98373_acpi_match), 993 .pm = &max98373_pm, 994 }, 995 .probe = max98373_i2c_probe, 996 .id_table = max98373_i2c_id, 997 }; 998 999 module_i2c_driver(max98373_i2c_driver) 1000 1001 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver"); 1002 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>"); 1003 MODULE_LICENSE("GPL"); 1004