1180cad3cSRyan Lee // SPDX-License-Identifier: GPL-2.0 2180cad3cSRyan Lee // Copyright (c) 2017, Maxim Integrated 32f3d24a1SRyan Lee 42f3d24a1SRyan Lee #include <linux/acpi.h> 53004136bSGrant Grundler #include <linux/delay.h> 62f3d24a1SRyan Lee #include <linux/i2c.h> 72f3d24a1SRyan Lee #include <linux/module.h> 82f3d24a1SRyan Lee #include <linux/regmap.h> 92f3d24a1SRyan Lee #include <linux/slab.h> 102f3d24a1SRyan Lee #include <linux/cdev.h> 112f3d24a1SRyan Lee #include <sound/pcm.h> 122f3d24a1SRyan Lee #include <sound/pcm_params.h> 132f3d24a1SRyan Lee #include <sound/soc.h> 142f3d24a1SRyan Lee #include <linux/gpio.h> 1596cd3b97Sfengchunguo #include <linux/of.h> 162f3d24a1SRyan Lee #include <linux/of_gpio.h> 172f3d24a1SRyan Lee #include <sound/tlv.h> 182f3d24a1SRyan Lee #include "max98373.h" 192f3d24a1SRyan Lee 202f3d24a1SRyan Lee static int max98373_dac_event(struct snd_soc_dapm_widget *w, 212f3d24a1SRyan Lee struct snd_kcontrol *kcontrol, int event) 222f3d24a1SRyan Lee { 2341572b54SKuninori Morimoto struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 2441572b54SKuninori Morimoto struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 252f3d24a1SRyan Lee 262f3d24a1SRyan Lee switch (event) { 272f3d24a1SRyan Lee case SND_SOC_DAPM_POST_PMU: 282f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 292f3d24a1SRyan Lee MAX98373_R20FF_GLOBAL_SHDN, 302f3d24a1SRyan Lee MAX98373_GLOBAL_EN_MASK, 1); 312f3d24a1SRyan Lee break; 322f3d24a1SRyan Lee case SND_SOC_DAPM_POST_PMD: 332f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 342f3d24a1SRyan Lee MAX98373_R20FF_GLOBAL_SHDN, 352f3d24a1SRyan Lee MAX98373_GLOBAL_EN_MASK, 0); 367c3727baSPierre-Louis Bossart max98373->tdm_mode = false; 372f3d24a1SRyan Lee break; 382f3d24a1SRyan Lee default: 392f3d24a1SRyan Lee return 0; 402f3d24a1SRyan Lee } 412f3d24a1SRyan Lee return 0; 422f3d24a1SRyan Lee } 432f3d24a1SRyan Lee 442f3d24a1SRyan Lee static const char * const max98373_switch_text[] = { 452f3d24a1SRyan Lee "Left", "Right", "LeftRight"}; 462f3d24a1SRyan Lee 472f3d24a1SRyan Lee static const struct soc_enum dai_sel_enum = 482f3d24a1SRyan Lee SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 492f3d24a1SRyan Lee MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT, 502f3d24a1SRyan Lee 3, max98373_switch_text); 512f3d24a1SRyan Lee 522f3d24a1SRyan Lee static const struct snd_kcontrol_new max98373_dai_controls = 532f3d24a1SRyan Lee SOC_DAPM_ENUM("DAI Sel", dai_sel_enum); 542f3d24a1SRyan Lee 552f3d24a1SRyan Lee static const struct snd_kcontrol_new max98373_vi_control = 562f3d24a1SRyan Lee SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0); 572f3d24a1SRyan Lee 582f3d24a1SRyan Lee static const struct snd_kcontrol_new max98373_spkfb_control = 592f3d24a1SRyan Lee SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0); 602f3d24a1SRyan Lee 612f3d24a1SRyan Lee static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = { 622f3d24a1SRyan Lee SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", 632f3d24a1SRyan Lee MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event, 642f3d24a1SRyan Lee SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 652f3d24a1SRyan Lee SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, 662f3d24a1SRyan Lee &max98373_dai_controls), 672f3d24a1SRyan Lee SND_SOC_DAPM_OUTPUT("BE_OUT"), 682f3d24a1SRyan Lee SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0, 692f3d24a1SRyan Lee MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0), 702f3d24a1SRyan Lee SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0, 712f3d24a1SRyan Lee MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0), 722f3d24a1SRyan Lee SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0, 732f3d24a1SRyan Lee SND_SOC_NOPM, 0, 0), 742f3d24a1SRyan Lee SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0, 752f3d24a1SRyan Lee &max98373_vi_control), 762f3d24a1SRyan Lee SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0, 772f3d24a1SRyan Lee &max98373_spkfb_control), 782f3d24a1SRyan Lee SND_SOC_DAPM_SIGGEN("VMON"), 792f3d24a1SRyan Lee SND_SOC_DAPM_SIGGEN("IMON"), 802f3d24a1SRyan Lee SND_SOC_DAPM_SIGGEN("FBMON"), 812f3d24a1SRyan Lee }; 822f3d24a1SRyan Lee 834cbbc916SRyan Lee static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1); 842f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv, 852f3d24a1SRyan Lee 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0), 862f3d24a1SRyan Lee 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0), 872f3d24a1SRyan Lee ); 882f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv, 892f3d24a1SRyan Lee 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 902f3d24a1SRyan Lee ); 912f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv, 922f3d24a1SRyan Lee 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0), 932f3d24a1SRyan Lee 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0), 942f3d24a1SRyan Lee ); 952f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv, 962f3d24a1SRyan Lee 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 972f3d24a1SRyan Lee ); 982f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv, 99a23f5dc8SRyan Lee 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0), 100a23f5dc8SRyan Lee 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0), 101a23f5dc8SRyan Lee 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0), 102a23f5dc8SRyan Lee 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0), 103a23f5dc8SRyan Lee 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0), 104a23f5dc8SRyan Lee 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0), 1052f3d24a1SRyan Lee ); 1062f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv, 1076c3beecaSRyan Lee 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0), 1082f3d24a1SRyan Lee ); 1092f3d24a1SRyan Lee 1102f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv, 111d34c8f37SRyan Lee 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0), 1122f3d24a1SRyan Lee ); 1132f3d24a1SRyan Lee 1142f3d24a1SRyan Lee static const char * const max98373_output_voltage_lvl_text[] = { 1152f3d24a1SRyan Lee "5.43V", "6.09V", "6.83V", "7.67V", "8.60V", 1162f3d24a1SRyan Lee "9.65V", "10.83V", "12.15V", "13.63V", "15.29V" 1172f3d24a1SRyan Lee }; 1182f3d24a1SRyan Lee 1192f3d24a1SRyan Lee static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum, 1202f3d24a1SRyan Lee MAX98373_R203E_AMP_PATH_GAIN, 0, 1212f3d24a1SRyan Lee max98373_output_voltage_lvl_text); 1222f3d24a1SRyan Lee 1232f3d24a1SRyan Lee static const char * const max98373_dht_attack_rate_text[] = { 1242f3d24a1SRyan Lee "17.5us", "35us", "70us", "140us", 1252f3d24a1SRyan Lee "280us", "560us", "1120us", "2240us" 1262f3d24a1SRyan Lee }; 1272f3d24a1SRyan Lee 1282f3d24a1SRyan Lee static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum, 1292f3d24a1SRyan Lee MAX98373_R20D2_DHT_ATTACK_CFG, 0, 1302f3d24a1SRyan Lee max98373_dht_attack_rate_text); 1312f3d24a1SRyan Lee 1322f3d24a1SRyan Lee static const char * const max98373_dht_release_rate_text[] = { 1332f3d24a1SRyan Lee "45ms", "225ms", "450ms", "1150ms", 1342f3d24a1SRyan Lee "2250ms", "3100ms", "4500ms", "6750ms" 1352f3d24a1SRyan Lee }; 1362f3d24a1SRyan Lee 1372f3d24a1SRyan Lee static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum, 1382f3d24a1SRyan Lee MAX98373_R20D3_DHT_RELEASE_CFG, 0, 1392f3d24a1SRyan Lee max98373_dht_release_rate_text); 1402f3d24a1SRyan Lee 1412f3d24a1SRyan Lee static const char * const max98373_limiter_attack_rate_text[] = { 1422f3d24a1SRyan Lee "10us", "20us", "40us", "80us", 1432f3d24a1SRyan Lee "160us", "320us", "640us", "1.28ms", 1442f3d24a1SRyan Lee "2.56ms", "5.12ms", "10.24ms", "20.48ms", 1452f3d24a1SRyan Lee "40.96ms", "81.92ms", "16.384ms", "32.768ms" 1462f3d24a1SRyan Lee }; 1472f3d24a1SRyan Lee 1482f3d24a1SRyan Lee static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum, 1492f3d24a1SRyan Lee MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4, 1502f3d24a1SRyan Lee max98373_limiter_attack_rate_text); 1512f3d24a1SRyan Lee 1522f3d24a1SRyan Lee static const char * const max98373_limiter_release_rate_text[] = { 1532f3d24a1SRyan Lee "40us", "80us", "160us", "320us", 1542f3d24a1SRyan Lee "640us", "1.28ms", "2.56ms", "5.120ms", 1552f3d24a1SRyan Lee "10.24ms", "20.48ms", "40.96ms", "81.92ms", 1562f3d24a1SRyan Lee "163.84ms", "327.68ms", "655.36ms", "1310.72ms" 1572f3d24a1SRyan Lee }; 1582f3d24a1SRyan Lee 1592f3d24a1SRyan Lee static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum, 1602f3d24a1SRyan Lee MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0, 1612f3d24a1SRyan Lee max98373_limiter_release_rate_text); 1622f3d24a1SRyan Lee 1632f3d24a1SRyan Lee static const char * const max98373_ADC_samplerate_text[] = { 1642f3d24a1SRyan Lee "333kHz", "192kHz", "64kHz", "48kHz" 1652f3d24a1SRyan Lee }; 1662f3d24a1SRyan Lee 1672f3d24a1SRyan Lee static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum, 1682f3d24a1SRyan Lee MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0, 1692f3d24a1SRyan Lee max98373_ADC_samplerate_text); 1702f3d24a1SRyan Lee 171349dd239SBard Liao static int max98373_feedback_get(struct snd_kcontrol *kcontrol, 172349dd239SBard Liao struct snd_ctl_elem_value *ucontrol) 173349dd239SBard Liao { 174349dd239SBard Liao struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 175349dd239SBard Liao struct soc_mixer_control *mc = 176349dd239SBard Liao (struct soc_mixer_control *)kcontrol->private_value; 177349dd239SBard Liao struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 178349dd239SBard Liao int i; 179349dd239SBard Liao 180349dd239SBard Liao if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 181349dd239SBard Liao /* 182349dd239SBard Liao * Register values will be cached before suspend. The cached value 183349dd239SBard Liao * will be a valid value and userspace will happy with that. 184349dd239SBard Liao */ 185349dd239SBard Liao for (i = 0; i < max98373->cache_num; i++) { 186349dd239SBard Liao if (mc->reg == max98373->cache[i].reg) { 187349dd239SBard Liao ucontrol->value.integer.value[0] = max98373->cache[i].val; 188349dd239SBard Liao return 0; 189349dd239SBard Liao } 190349dd239SBard Liao } 191349dd239SBard Liao } 192349dd239SBard Liao 193ded055eeSJudy Hsiao return snd_soc_get_volsw(kcontrol, ucontrol); 194349dd239SBard Liao } 195349dd239SBard Liao 1962f3d24a1SRyan Lee static const struct snd_kcontrol_new max98373_snd_controls[] = { 1972f3d24a1SRyan Lee SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG, 1982f3d24a1SRyan Lee MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 1992f3d24a1SRyan Lee SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG, 2002f3d24a1SRyan Lee MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 2012f3d24a1SRyan Lee SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG, 2022f3d24a1SRyan Lee MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0), 2032f3d24a1SRyan Lee SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG, 2042f3d24a1SRyan Lee MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0), 205*7a0d8849SRyan Lee /* Speaker Amplifier Overcurrent Automatic Restart Enable */ 206*7a0d8849SRyan Lee SOC_SINGLE("OVC Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 207*7a0d8849SRyan Lee MAX98373_OVC_AUTORESTART_SHIFT, 1, 0), 208*7a0d8849SRyan Lee /* Thermal Shutdown Automatic Restart Enable */ 209*7a0d8849SRyan Lee SOC_SINGLE("THERM Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 210*7a0d8849SRyan Lee MAX98373_THERM_AUTORESTART_SHIFT, 1, 0), 211*7a0d8849SRyan Lee /* Clock Monitor Automatic Restart Enable */ 212*7a0d8849SRyan Lee SOC_SINGLE("CMON Autorestart Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 213*7a0d8849SRyan Lee MAX98373_CMON_AUTORESTART_SHIFT, 1, 0), 2142f3d24a1SRyan Lee SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 2152f3d24a1SRyan Lee MAX98373_CLOCK_MON_SHIFT, 1, 0), 2162f3d24a1SRyan Lee SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG, 2172f3d24a1SRyan Lee MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0), 2182f3d24a1SRyan Lee SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG, 2192f3d24a1SRyan Lee MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0), 2202f3d24a1SRyan Lee SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL, 2214cbbc916SRyan Lee 0, 0x7F, 1, max98373_digital_tlv), 2222f3d24a1SRyan Lee SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN, 2232f3d24a1SRyan Lee MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv), 2242f3d24a1SRyan Lee SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN, 2252f3d24a1SRyan Lee MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv), 2262f3d24a1SRyan Lee SOC_ENUM("Output Voltage", max98373_out_volt_enum), 2272f3d24a1SRyan Lee /* Dynamic Headroom Tracking */ 2282f3d24a1SRyan Lee SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN, 2292f3d24a1SRyan Lee MAX98373_DHT_EN_SHIFT, 1, 0), 230b6158323SRyan Lee SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG, 2312f3d24a1SRyan Lee MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv), 232b6158323SRyan Lee SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG, 233a23f5dc8SRyan Lee MAX98373_DHT_ROT_PNT_SHIFT, 15, 1, max98373_dht_rotation_point_tlv), 234b6158323SRyan Lee SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG, 2352f3d24a1SRyan Lee MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 236b6158323SRyan Lee SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG, 2372f3d24a1SRyan Lee MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 2382f3d24a1SRyan Lee SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum), 2392f3d24a1SRyan Lee SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum), 2402f3d24a1SRyan Lee /* ADC configuration */ 2412f3d24a1SRyan Lee SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0), 2422f3d24a1SRyan Lee SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 2432f3d24a1SRyan Lee MAX98373_FLT_EN_SHIFT, 1, 0), 2442f3d24a1SRyan Lee SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 2452f3d24a1SRyan Lee MAX98373_FLT_EN_SHIFT, 1, 0), 246349dd239SBard Liao SOC_SINGLE_EXT("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0, 247349dd239SBard Liao max98373_feedback_get, NULL), 248349dd239SBard Liao SOC_SINGLE_EXT("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0, 249349dd239SBard Liao max98373_feedback_get, NULL), 2502f3d24a1SRyan Lee SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 2512f3d24a1SRyan Lee 0, 0x3, 0), 2522f3d24a1SRyan Lee SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 2532f3d24a1SRyan Lee 0, 0x3, 0), 2542f3d24a1SRyan Lee SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum), 2552f3d24a1SRyan Lee /* Brownout Detection Engine */ 2562f3d24a1SRyan Lee SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0), 2572f3d24a1SRyan Lee SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2, 2582f3d24a1SRyan Lee MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0), 2592f3d24a1SRyan Lee SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2, 2602f3d24a1SRyan Lee MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0), 2612f3d24a1SRyan Lee SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0), 2622f3d24a1SRyan Lee SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0), 2632f3d24a1SRyan Lee SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0), 2642f3d24a1SRyan Lee SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0), 265349dd239SBard Liao SOC_SINGLE_EXT("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0, 266349dd239SBard Liao max98373_feedback_get, NULL), 2672f3d24a1SRyan Lee SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0), 2682f3d24a1SRyan Lee SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0), 2692f3d24a1SRyan Lee SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0), 2702f3d24a1SRyan Lee SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0), 2712f3d24a1SRyan Lee SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0), 272b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2, 273d34c8f37SRyan Lee 0, 0x3C, 1, max98373_bde_gain_tlv), 274b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2, 275d34c8f37SRyan Lee 0, 0x3C, 1, max98373_bde_gain_tlv), 276b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2, 277d34c8f37SRyan Lee 0, 0x3C, 1, max98373_bde_gain_tlv), 278b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2, 279d34c8f37SRyan Lee 0, 0x3C, 1, max98373_bde_gain_tlv), 280b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3, 281d34c8f37SRyan Lee 0, 0x3C, 1, max98373_bde_gain_tlv), 282b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3, 283d34c8f37SRyan Lee 0, 0x3C, 1, max98373_bde_gain_tlv), 284b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3, 285d34c8f37SRyan Lee 0, 0x3C, 1, max98373_bde_gain_tlv), 286b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3, 287d34c8f37SRyan Lee 0, 0x3C, 1, max98373_bde_gain_tlv), 288b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1, 2896c3beecaSRyan Lee 0, 0xF, 1, max98373_limiter_thresh_tlv), 290b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1, 2916c3beecaSRyan Lee 0, 0xF, 1, max98373_limiter_thresh_tlv), 292b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1, 2936c3beecaSRyan Lee 0, 0xF, 1, max98373_limiter_thresh_tlv), 294b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1, 2956c3beecaSRyan Lee 0, 0xF, 1, max98373_limiter_thresh_tlv), 2962f3d24a1SRyan Lee /* Limiter */ 2972f3d24a1SRyan Lee SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN, 2982f3d24a1SRyan Lee MAX98373_LIMITER_EN_SHIFT, 1, 0), 2992f3d24a1SRyan Lee SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG, 3002f3d24a1SRyan Lee MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0), 301b6158323SRyan Lee SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG, 3022f3d24a1SRyan Lee MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv), 3032f3d24a1SRyan Lee SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum), 3042f3d24a1SRyan Lee SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum), 3052f3d24a1SRyan Lee }; 3062f3d24a1SRyan Lee 3072f3d24a1SRyan Lee static const struct snd_soc_dapm_route max98373_audio_map[] = { 3082f3d24a1SRyan Lee /* Plabyack */ 3092f3d24a1SRyan Lee {"DAI Sel Mux", "Left", "Amp Enable"}, 3102f3d24a1SRyan Lee {"DAI Sel Mux", "Right", "Amp Enable"}, 3112f3d24a1SRyan Lee {"DAI Sel Mux", "LeftRight", "Amp Enable"}, 3122f3d24a1SRyan Lee {"BE_OUT", NULL, "DAI Sel Mux"}, 3132f3d24a1SRyan Lee /* Capture */ 3142f3d24a1SRyan Lee { "VI Sense", "Switch", "VMON" }, 3152f3d24a1SRyan Lee { "VI Sense", "Switch", "IMON" }, 3162f3d24a1SRyan Lee { "SpkFB Sense", "Switch", "FBMON" }, 3172f3d24a1SRyan Lee { "Voltage Sense", NULL, "VI Sense" }, 3182f3d24a1SRyan Lee { "Current Sense", NULL, "VI Sense" }, 3192f3d24a1SRyan Lee { "Speaker FB Sense", NULL, "SpkFB Sense" }, 3202f3d24a1SRyan Lee }; 3212f3d24a1SRyan Lee 322d7ee0c72SPierre-Louis Bossart void max98373_reset(struct max98373_priv *max98373, struct device *dev) 32320f2ab24SRyan Lee { 32420f2ab24SRyan Lee int ret, reg, count; 32520f2ab24SRyan Lee 32620f2ab24SRyan Lee /* Software Reset */ 32720f2ab24SRyan Lee ret = regmap_update_bits(max98373->regmap, 32820f2ab24SRyan Lee MAX98373_R2000_SW_RESET, 32920f2ab24SRyan Lee MAX98373_SOFT_RESET, 33020f2ab24SRyan Lee MAX98373_SOFT_RESET); 33120f2ab24SRyan Lee if (ret) 33220f2ab24SRyan Lee dev_err(dev, "Reset command failed. (ret:%d)\n", ret); 33320f2ab24SRyan Lee 33420f2ab24SRyan Lee count = 0; 33520f2ab24SRyan Lee while (count < 3) { 33620f2ab24SRyan Lee usleep_range(10000, 11000); 33720f2ab24SRyan Lee /* Software Reset Verification */ 33820f2ab24SRyan Lee ret = regmap_read(max98373->regmap, 33920f2ab24SRyan Lee MAX98373_R21FF_REV_ID, ®); 34020f2ab24SRyan Lee if (!ret) { 34120f2ab24SRyan Lee dev_info(dev, "Reset completed (retry:%d)\n", count); 34220f2ab24SRyan Lee return; 34320f2ab24SRyan Lee } 34420f2ab24SRyan Lee count++; 34520f2ab24SRyan Lee } 34620f2ab24SRyan Lee dev_err(dev, "Reset failed. (ret:%d)\n", ret); 34720f2ab24SRyan Lee } 348d7ee0c72SPierre-Louis Bossart EXPORT_SYMBOL_GPL(max98373_reset); 34920f2ab24SRyan Lee 35041572b54SKuninori Morimoto static int max98373_probe(struct snd_soc_component *component) 3512f3d24a1SRyan Lee { 35241572b54SKuninori Morimoto struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 3532f3d24a1SRyan Lee 3542f3d24a1SRyan Lee /* Software Reset */ 35520f2ab24SRyan Lee max98373_reset(max98373, component->dev); 3562f3d24a1SRyan Lee 3572f3d24a1SRyan Lee /* IV default slot configuration */ 3582f3d24a1SRyan Lee regmap_write(max98373->regmap, 3592f3d24a1SRyan Lee MAX98373_R2020_PCM_TX_HIZ_EN_1, 3602f3d24a1SRyan Lee 0xFF); 3612f3d24a1SRyan Lee regmap_write(max98373->regmap, 3622f3d24a1SRyan Lee MAX98373_R2021_PCM_TX_HIZ_EN_2, 3632f3d24a1SRyan Lee 0xFF); 3642f3d24a1SRyan Lee /* L/R mix configuration */ 3652f3d24a1SRyan Lee regmap_write(max98373->regmap, 3662f3d24a1SRyan Lee MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 3672f3d24a1SRyan Lee 0x80); 3682f3d24a1SRyan Lee regmap_write(max98373->regmap, 3692f3d24a1SRyan Lee MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 3702f3d24a1SRyan Lee 0x1); 3712f3d24a1SRyan Lee /* Enable DC blocker */ 3722f3d24a1SRyan Lee regmap_write(max98373->regmap, 3732f3d24a1SRyan Lee MAX98373_R203F_AMP_DSP_CFG, 3742f3d24a1SRyan Lee 0x3); 3752f3d24a1SRyan Lee /* Enable IMON VMON DC blocker */ 3762f3d24a1SRyan Lee regmap_write(max98373->regmap, 3772f3d24a1SRyan Lee MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 3782f3d24a1SRyan Lee 0x7); 3792f3d24a1SRyan Lee /* voltage, current slot configuration */ 3802f3d24a1SRyan Lee regmap_write(max98373->regmap, 3812f3d24a1SRyan Lee MAX98373_R2022_PCM_TX_SRC_1, 3822f3d24a1SRyan Lee (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT | 3832f3d24a1SRyan Lee max98373->v_slot) & 0xFF); 3842f3d24a1SRyan Lee if (max98373->v_slot < 8) 3852f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 3862f3d24a1SRyan Lee MAX98373_R2020_PCM_TX_HIZ_EN_1, 3872f3d24a1SRyan Lee 1 << max98373->v_slot, 0); 3882f3d24a1SRyan Lee else 3892f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 3902f3d24a1SRyan Lee MAX98373_R2021_PCM_TX_HIZ_EN_2, 3912f3d24a1SRyan Lee 1 << (max98373->v_slot - 8), 0); 3922f3d24a1SRyan Lee 3932f3d24a1SRyan Lee if (max98373->i_slot < 8) 3942f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 3952f3d24a1SRyan Lee MAX98373_R2020_PCM_TX_HIZ_EN_1, 3962f3d24a1SRyan Lee 1 << max98373->i_slot, 0); 3972f3d24a1SRyan Lee else 3982f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 3992f3d24a1SRyan Lee MAX98373_R2021_PCM_TX_HIZ_EN_2, 4002f3d24a1SRyan Lee 1 << (max98373->i_slot - 8), 0); 4012f3d24a1SRyan Lee 402*7a0d8849SRyan Lee /* enable auto restart function by default */ 403*7a0d8849SRyan Lee regmap_write(max98373->regmap, 404*7a0d8849SRyan Lee MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 405*7a0d8849SRyan Lee 0xF); 406*7a0d8849SRyan Lee 4072f3d24a1SRyan Lee /* speaker feedback slot configuration */ 4082f3d24a1SRyan Lee regmap_write(max98373->regmap, 4092f3d24a1SRyan Lee MAX98373_R2023_PCM_TX_SRC_2, 4102f3d24a1SRyan Lee max98373->spkfb_slot & 0xFF); 4112f3d24a1SRyan Lee 4122f3d24a1SRyan Lee /* Set interleave mode */ 4132f3d24a1SRyan Lee if (max98373->interleave_mode) 4142f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 4152f3d24a1SRyan Lee MAX98373_R2024_PCM_DATA_FMT_CFG, 4162f3d24a1SRyan Lee MAX98373_PCM_TX_CH_INTERLEAVE_MASK, 4172f3d24a1SRyan Lee MAX98373_PCM_TX_CH_INTERLEAVE_MASK); 4182f3d24a1SRyan Lee 4192f3d24a1SRyan Lee /* Speaker enable */ 4202f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 4212f3d24a1SRyan Lee MAX98373_R2043_AMP_EN, 4222f3d24a1SRyan Lee MAX98373_SPK_EN_MASK, 1); 4232f3d24a1SRyan Lee 4242f3d24a1SRyan Lee return 0; 4252f3d24a1SRyan Lee } 4262f3d24a1SRyan Lee 427d7ee0c72SPierre-Louis Bossart const struct snd_soc_component_driver soc_codec_dev_max98373 = { 4282f3d24a1SRyan Lee .probe = max98373_probe, 4292f3d24a1SRyan Lee .controls = max98373_snd_controls, 4302f3d24a1SRyan Lee .num_controls = ARRAY_SIZE(max98373_snd_controls), 4312f3d24a1SRyan Lee .dapm_widgets = max98373_dapm_widgets, 4322f3d24a1SRyan Lee .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets), 4332f3d24a1SRyan Lee .dapm_routes = max98373_audio_map, 4342f3d24a1SRyan Lee .num_dapm_routes = ARRAY_SIZE(max98373_audio_map), 43541572b54SKuninori Morimoto .use_pmdown_time = 1, 43641572b54SKuninori Morimoto .endianness = 1, 43741572b54SKuninori Morimoto .non_legacy_dai_naming = 1, 4382f3d24a1SRyan Lee }; 439d7ee0c72SPierre-Louis Bossart EXPORT_SYMBOL_GPL(soc_codec_dev_max98373); 4402f3d24a1SRyan Lee 44156a5b791SRyan Lee const struct snd_soc_component_driver soc_codec_dev_max98373_sdw = { 44256a5b791SRyan Lee .probe = NULL, 44356a5b791SRyan Lee .controls = max98373_snd_controls, 44456a5b791SRyan Lee .num_controls = ARRAY_SIZE(max98373_snd_controls), 44556a5b791SRyan Lee .dapm_widgets = max98373_dapm_widgets, 44656a5b791SRyan Lee .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets), 44756a5b791SRyan Lee .dapm_routes = max98373_audio_map, 44856a5b791SRyan Lee .num_dapm_routes = ARRAY_SIZE(max98373_audio_map), 44956a5b791SRyan Lee .use_pmdown_time = 1, 45056a5b791SRyan Lee .endianness = 1, 45156a5b791SRyan Lee .non_legacy_dai_naming = 1, 45256a5b791SRyan Lee }; 45356a5b791SRyan Lee EXPORT_SYMBOL_GPL(soc_codec_dev_max98373_sdw); 45456a5b791SRyan Lee 455d7ee0c72SPierre-Louis Bossart void max98373_slot_config(struct device *dev, 4562f3d24a1SRyan Lee struct max98373_priv *max98373) 4572f3d24a1SRyan Lee { 4582f3d24a1SRyan Lee int value; 4592f3d24a1SRyan Lee 4602f3d24a1SRyan Lee if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value)) 4612f3d24a1SRyan Lee max98373->v_slot = value & 0xF; 4622f3d24a1SRyan Lee else 4632f3d24a1SRyan Lee max98373->v_slot = 0; 4642f3d24a1SRyan Lee 4652f3d24a1SRyan Lee if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value)) 4662f3d24a1SRyan Lee max98373->i_slot = value & 0xF; 4672f3d24a1SRyan Lee else 4682f3d24a1SRyan Lee max98373->i_slot = 1; 4694bb41984SSathyanarayana Nujella if (dev->of_node) { 47096cd3b97Sfengchunguo max98373->reset_gpio = of_get_named_gpio(dev->of_node, 47196cd3b97Sfengchunguo "maxim,reset-gpio", 0); 47296cd3b97Sfengchunguo if (!gpio_is_valid(max98373->reset_gpio)) { 47396cd3b97Sfengchunguo dev_err(dev, "Looking up %s property in node %s failed %d\n", 47496cd3b97Sfengchunguo "maxim,reset-gpio", dev->of_node->full_name, 47596cd3b97Sfengchunguo max98373->reset_gpio); 47696cd3b97Sfengchunguo } else { 47796cd3b97Sfengchunguo dev_dbg(dev, "maxim,reset-gpio=%d", 47896cd3b97Sfengchunguo max98373->reset_gpio); 47996cd3b97Sfengchunguo } 4804bb41984SSathyanarayana Nujella } else { 4814bb41984SSathyanarayana Nujella /* this makes reset_gpio as invalid */ 4824bb41984SSathyanarayana Nujella max98373->reset_gpio = -1; 4834bb41984SSathyanarayana Nujella } 48496cd3b97Sfengchunguo 4852f3d24a1SRyan Lee if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value)) 4862f3d24a1SRyan Lee max98373->spkfb_slot = value & 0xF; 4872f3d24a1SRyan Lee else 4882f3d24a1SRyan Lee max98373->spkfb_slot = 2; 4892f3d24a1SRyan Lee } 490d7ee0c72SPierre-Louis Bossart EXPORT_SYMBOL_GPL(max98373_slot_config); 4912f3d24a1SRyan Lee 4922f3d24a1SRyan Lee MODULE_DESCRIPTION("ALSA SoC MAX98373 driver"); 4932f3d24a1SRyan Lee MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>"); 4942f3d24a1SRyan Lee MODULE_LICENSE("GPL"); 495