1180cad3cSRyan Lee // SPDX-License-Identifier: GPL-2.0 2180cad3cSRyan Lee // Copyright (c) 2017, Maxim Integrated 32f3d24a1SRyan Lee 42f3d24a1SRyan Lee #include <linux/acpi.h> 52f3d24a1SRyan Lee #include <linux/i2c.h> 62f3d24a1SRyan Lee #include <linux/module.h> 72f3d24a1SRyan Lee #include <linux/regmap.h> 82f3d24a1SRyan Lee #include <linux/slab.h> 92f3d24a1SRyan Lee #include <linux/cdev.h> 102f3d24a1SRyan Lee #include <sound/pcm.h> 112f3d24a1SRyan Lee #include <sound/pcm_params.h> 122f3d24a1SRyan Lee #include <sound/soc.h> 132f3d24a1SRyan Lee #include <linux/gpio.h> 142f3d24a1SRyan Lee #include <linux/of_gpio.h> 152f3d24a1SRyan Lee #include <sound/tlv.h> 162f3d24a1SRyan Lee #include "max98373.h" 172f3d24a1SRyan Lee 182f3d24a1SRyan Lee static struct reg_default max98373_reg[] = { 192f3d24a1SRyan Lee {MAX98373_R2000_SW_RESET, 0x00}, 202f3d24a1SRyan Lee {MAX98373_R2001_INT_RAW1, 0x00}, 212f3d24a1SRyan Lee {MAX98373_R2002_INT_RAW2, 0x00}, 222f3d24a1SRyan Lee {MAX98373_R2003_INT_RAW3, 0x00}, 232f3d24a1SRyan Lee {MAX98373_R2004_INT_STATE1, 0x00}, 242f3d24a1SRyan Lee {MAX98373_R2005_INT_STATE2, 0x00}, 252f3d24a1SRyan Lee {MAX98373_R2006_INT_STATE3, 0x00}, 262f3d24a1SRyan Lee {MAX98373_R2007_INT_FLAG1, 0x00}, 272f3d24a1SRyan Lee {MAX98373_R2008_INT_FLAG2, 0x00}, 282f3d24a1SRyan Lee {MAX98373_R2009_INT_FLAG3, 0x00}, 292f3d24a1SRyan Lee {MAX98373_R200A_INT_EN1, 0x00}, 302f3d24a1SRyan Lee {MAX98373_R200B_INT_EN2, 0x00}, 312f3d24a1SRyan Lee {MAX98373_R200C_INT_EN3, 0x00}, 322f3d24a1SRyan Lee {MAX98373_R200D_INT_FLAG_CLR1, 0x00}, 332f3d24a1SRyan Lee {MAX98373_R200E_INT_FLAG_CLR2, 0x00}, 342f3d24a1SRyan Lee {MAX98373_R200F_INT_FLAG_CLR3, 0x00}, 352f3d24a1SRyan Lee {MAX98373_R2010_IRQ_CTRL, 0x00}, 362f3d24a1SRyan Lee {MAX98373_R2014_THERM_WARN_THRESH, 0x10}, 372f3d24a1SRyan Lee {MAX98373_R2015_THERM_SHDN_THRESH, 0x27}, 382f3d24a1SRyan Lee {MAX98373_R2016_THERM_HYSTERESIS, 0x01}, 392f3d24a1SRyan Lee {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0}, 402f3d24a1SRyan Lee {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00}, 412f3d24a1SRyan Lee {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55}, 422f3d24a1SRyan Lee {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE}, 432f3d24a1SRyan Lee {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF}, 442f3d24a1SRyan Lee {MAX98373_R2022_PCM_TX_SRC_1, 0x00}, 452f3d24a1SRyan Lee {MAX98373_R2023_PCM_TX_SRC_2, 0x00}, 462f3d24a1SRyan Lee {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0}, 472f3d24a1SRyan Lee {MAX98373_R2025_AUDIO_IF_MODE, 0x00}, 482f3d24a1SRyan Lee {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04}, 492f3d24a1SRyan Lee {MAX98373_R2027_PCM_SR_SETUP_1, 0x08}, 502f3d24a1SRyan Lee {MAX98373_R2028_PCM_SR_SETUP_2, 0x88}, 512f3d24a1SRyan Lee {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00}, 522f3d24a1SRyan Lee {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00}, 532f3d24a1SRyan Lee {MAX98373_R202B_PCM_RX_EN, 0x00}, 542f3d24a1SRyan Lee {MAX98373_R202C_PCM_TX_EN, 0x00}, 552f3d24a1SRyan Lee {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00}, 562f3d24a1SRyan Lee {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00}, 572f3d24a1SRyan Lee {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF}, 582f3d24a1SRyan Lee {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF}, 592f3d24a1SRyan Lee {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30}, 602f3d24a1SRyan Lee {MAX98373_R2034_ICC_TX_CNTL, 0x00}, 612f3d24a1SRyan Lee {MAX98373_R2035_ICC_TX_EN, 0x00}, 622f3d24a1SRyan Lee {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05}, 632f3d24a1SRyan Lee {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00}, 642f3d24a1SRyan Lee {MAX98373_R203E_AMP_PATH_GAIN, 0x08}, 652f3d24a1SRyan Lee {MAX98373_R203F_AMP_DSP_CFG, 0x02}, 662f3d24a1SRyan Lee {MAX98373_R2040_TONE_GEN_CFG, 0x00}, 672f3d24a1SRyan Lee {MAX98373_R2041_AMP_CFG, 0x03}, 682f3d24a1SRyan Lee {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00}, 692f3d24a1SRyan Lee {MAX98373_R2043_AMP_EN, 0x00}, 702f3d24a1SRyan Lee {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04}, 712f3d24a1SRyan Lee {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00}, 722f3d24a1SRyan Lee {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00}, 732f3d24a1SRyan Lee {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00}, 742f3d24a1SRyan Lee {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00}, 752f3d24a1SRyan Lee {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00}, 762f3d24a1SRyan Lee {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00}, 772f3d24a1SRyan Lee {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00}, 782f3d24a1SRyan Lee {MAX98373_R2090_BDE_LVL_HOLD, 0x00}, 792f3d24a1SRyan Lee {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00}, 802f3d24a1SRyan Lee {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00}, 812f3d24a1SRyan Lee {MAX98373_R2097_BDE_L1_THRESH, 0x00}, 822f3d24a1SRyan Lee {MAX98373_R2098_BDE_L2_THRESH, 0x00}, 832f3d24a1SRyan Lee {MAX98373_R2099_BDE_L3_THRESH, 0x00}, 842f3d24a1SRyan Lee {MAX98373_R209A_BDE_L4_THRESH, 0x00}, 852f3d24a1SRyan Lee {MAX98373_R209B_BDE_THRESH_HYST, 0x00}, 862f3d24a1SRyan Lee {MAX98373_R20A8_BDE_L1_CFG_1, 0x00}, 872f3d24a1SRyan Lee {MAX98373_R20A9_BDE_L1_CFG_2, 0x00}, 882f3d24a1SRyan Lee {MAX98373_R20AA_BDE_L1_CFG_3, 0x00}, 892f3d24a1SRyan Lee {MAX98373_R20AB_BDE_L2_CFG_1, 0x00}, 902f3d24a1SRyan Lee {MAX98373_R20AC_BDE_L2_CFG_2, 0x00}, 912f3d24a1SRyan Lee {MAX98373_R20AD_BDE_L2_CFG_3, 0x00}, 922f3d24a1SRyan Lee {MAX98373_R20AE_BDE_L3_CFG_1, 0x00}, 932f3d24a1SRyan Lee {MAX98373_R20AF_BDE_L3_CFG_2, 0x00}, 942f3d24a1SRyan Lee {MAX98373_R20B0_BDE_L3_CFG_3, 0x00}, 952f3d24a1SRyan Lee {MAX98373_R20B1_BDE_L4_CFG_1, 0x00}, 962f3d24a1SRyan Lee {MAX98373_R20B2_BDE_L4_CFG_2, 0x00}, 972f3d24a1SRyan Lee {MAX98373_R20B3_BDE_L4_CFG_3, 0x00}, 982f3d24a1SRyan Lee {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00}, 992f3d24a1SRyan Lee {MAX98373_R20B5_BDE_EN, 0x00}, 1002f3d24a1SRyan Lee {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00}, 1012f3d24a1SRyan Lee {MAX98373_R20D1_DHT_CFG, 0x01}, 1022f3d24a1SRyan Lee {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02}, 1032f3d24a1SRyan Lee {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03}, 1042f3d24a1SRyan Lee {MAX98373_R20D4_DHT_EN, 0x00}, 1052f3d24a1SRyan Lee {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00}, 1062f3d24a1SRyan Lee {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00}, 1072f3d24a1SRyan Lee {MAX98373_R20E2_LIMITER_EN, 0x00}, 1082f3d24a1SRyan Lee {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00}, 1092f3d24a1SRyan Lee {MAX98373_R20FF_GLOBAL_SHDN, 0x00}, 1102f3d24a1SRyan Lee {MAX98373_R21FF_REV_ID, 0x42}, 1112f3d24a1SRyan Lee }; 1122f3d24a1SRyan Lee 1132f3d24a1SRyan Lee static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1142f3d24a1SRyan Lee { 11541572b54SKuninori Morimoto struct snd_soc_component *component = codec_dai->component; 11641572b54SKuninori Morimoto struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 1172f3d24a1SRyan Lee unsigned int format = 0; 1182f3d24a1SRyan Lee unsigned int invert = 0; 1192f3d24a1SRyan Lee 12041572b54SKuninori Morimoto dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt); 1212f3d24a1SRyan Lee 1222f3d24a1SRyan Lee switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1232f3d24a1SRyan Lee case SND_SOC_DAIFMT_NB_NF: 1242f3d24a1SRyan Lee break; 1252f3d24a1SRyan Lee case SND_SOC_DAIFMT_IB_NF: 1262f3d24a1SRyan Lee invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE; 1272f3d24a1SRyan Lee break; 1282f3d24a1SRyan Lee default: 12941572b54SKuninori Morimoto dev_err(component->dev, "DAI invert mode unsupported\n"); 1302f3d24a1SRyan Lee return -EINVAL; 1312f3d24a1SRyan Lee } 1322f3d24a1SRyan Lee 1332f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 1342f3d24a1SRyan Lee MAX98373_R2026_PCM_CLOCK_RATIO, 1352f3d24a1SRyan Lee MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE, 1362f3d24a1SRyan Lee invert); 1372f3d24a1SRyan Lee 1382f3d24a1SRyan Lee /* interface format */ 1392f3d24a1SRyan Lee switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1402f3d24a1SRyan Lee case SND_SOC_DAIFMT_I2S: 1412f3d24a1SRyan Lee format = MAX98373_PCM_FORMAT_I2S; 1422f3d24a1SRyan Lee break; 1432f3d24a1SRyan Lee case SND_SOC_DAIFMT_LEFT_J: 1442f3d24a1SRyan Lee format = MAX98373_PCM_FORMAT_LJ; 1452f3d24a1SRyan Lee break; 1462f3d24a1SRyan Lee case SND_SOC_DAIFMT_DSP_A: 1472f3d24a1SRyan Lee format = MAX98373_PCM_FORMAT_TDM_MODE1; 1482f3d24a1SRyan Lee break; 1492f3d24a1SRyan Lee case SND_SOC_DAIFMT_DSP_B: 1502f3d24a1SRyan Lee format = MAX98373_PCM_FORMAT_TDM_MODE0; 1512f3d24a1SRyan Lee break; 1522f3d24a1SRyan Lee default: 1532f3d24a1SRyan Lee return -EINVAL; 1542f3d24a1SRyan Lee } 1552f3d24a1SRyan Lee 1562f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 1572f3d24a1SRyan Lee MAX98373_R2024_PCM_DATA_FMT_CFG, 1582f3d24a1SRyan Lee MAX98373_PCM_MODE_CFG_FORMAT_MASK, 1592f3d24a1SRyan Lee format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT); 1602f3d24a1SRyan Lee 1612f3d24a1SRyan Lee return 0; 1622f3d24a1SRyan Lee } 1632f3d24a1SRyan Lee 1642f3d24a1SRyan Lee /* BCLKs per LRCLK */ 1652f3d24a1SRyan Lee static const int bclk_sel_table[] = { 1662f3d24a1SRyan Lee 32, 48, 64, 96, 128, 192, 256, 384, 512, 320, 1672f3d24a1SRyan Lee }; 1682f3d24a1SRyan Lee 1692f3d24a1SRyan Lee static int max98373_get_bclk_sel(int bclk) 1702f3d24a1SRyan Lee { 1712f3d24a1SRyan Lee int i; 1722f3d24a1SRyan Lee /* match BCLKs per LRCLK */ 1732f3d24a1SRyan Lee for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) { 1742f3d24a1SRyan Lee if (bclk_sel_table[i] == bclk) 1752f3d24a1SRyan Lee return i + 2; 1762f3d24a1SRyan Lee } 1772f3d24a1SRyan Lee return 0; 1782f3d24a1SRyan Lee } 179e1053262SRyan Lee 18041572b54SKuninori Morimoto static int max98373_set_clock(struct snd_soc_component *component, 1812f3d24a1SRyan Lee struct snd_pcm_hw_params *params) 1822f3d24a1SRyan Lee { 18341572b54SKuninori Morimoto struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 1842f3d24a1SRyan Lee /* BCLK/LRCLK ratio calculation */ 1852f3d24a1SRyan Lee int blr_clk_ratio = params_channels(params) * max98373->ch_size; 1862f3d24a1SRyan Lee int value; 1872f3d24a1SRyan Lee 1882f3d24a1SRyan Lee if (!max98373->tdm_mode) { 1892f3d24a1SRyan Lee /* BCLK configuration */ 1902f3d24a1SRyan Lee value = max98373_get_bclk_sel(blr_clk_ratio); 1912f3d24a1SRyan Lee if (!value) { 19241572b54SKuninori Morimoto dev_err(component->dev, "format unsupported %d\n", 1932f3d24a1SRyan Lee params_format(params)); 1942f3d24a1SRyan Lee return -EINVAL; 1952f3d24a1SRyan Lee } 1962f3d24a1SRyan Lee 1972f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 1982f3d24a1SRyan Lee MAX98373_R2026_PCM_CLOCK_RATIO, 1992f3d24a1SRyan Lee MAX98373_PCM_CLK_SETUP_BSEL_MASK, 2002f3d24a1SRyan Lee value); 2012f3d24a1SRyan Lee } 2022f3d24a1SRyan Lee return 0; 2032f3d24a1SRyan Lee } 2042f3d24a1SRyan Lee 2052f3d24a1SRyan Lee static int max98373_dai_hw_params(struct snd_pcm_substream *substream, 2062f3d24a1SRyan Lee struct snd_pcm_hw_params *params, 2072f3d24a1SRyan Lee struct snd_soc_dai *dai) 2082f3d24a1SRyan Lee { 20941572b54SKuninori Morimoto struct snd_soc_component *component = dai->component; 21041572b54SKuninori Morimoto struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 2112f3d24a1SRyan Lee unsigned int sampling_rate = 0; 2122f3d24a1SRyan Lee unsigned int chan_sz = 0; 2132f3d24a1SRyan Lee 2142f3d24a1SRyan Lee /* pcm mode configuration */ 2152f3d24a1SRyan Lee switch (snd_pcm_format_width(params_format(params))) { 2162f3d24a1SRyan Lee case 16: 2172f3d24a1SRyan Lee chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 2182f3d24a1SRyan Lee break; 2192f3d24a1SRyan Lee case 24: 2202f3d24a1SRyan Lee chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 2212f3d24a1SRyan Lee break; 2222f3d24a1SRyan Lee case 32: 2232f3d24a1SRyan Lee chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 2242f3d24a1SRyan Lee break; 2252f3d24a1SRyan Lee default: 22641572b54SKuninori Morimoto dev_err(component->dev, "format unsupported %d\n", 2272f3d24a1SRyan Lee params_format(params)); 2282f3d24a1SRyan Lee goto err; 2292f3d24a1SRyan Lee } 2302f3d24a1SRyan Lee 2312f3d24a1SRyan Lee max98373->ch_size = snd_pcm_format_width(params_format(params)); 2322f3d24a1SRyan Lee 2332f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 2342f3d24a1SRyan Lee MAX98373_R2024_PCM_DATA_FMT_CFG, 2352f3d24a1SRyan Lee MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 2362f3d24a1SRyan Lee 23741572b54SKuninori Morimoto dev_dbg(component->dev, "format supported %d", 2382f3d24a1SRyan Lee params_format(params)); 2392f3d24a1SRyan Lee 2402f3d24a1SRyan Lee /* sampling rate configuration */ 2412f3d24a1SRyan Lee switch (params_rate(params)) { 2422f3d24a1SRyan Lee case 8000: 2432f3d24a1SRyan Lee sampling_rate = MAX98373_PCM_SR_SET1_SR_8000; 2442f3d24a1SRyan Lee break; 2452f3d24a1SRyan Lee case 11025: 2462f3d24a1SRyan Lee sampling_rate = MAX98373_PCM_SR_SET1_SR_11025; 2472f3d24a1SRyan Lee break; 2482f3d24a1SRyan Lee case 12000: 2492f3d24a1SRyan Lee sampling_rate = MAX98373_PCM_SR_SET1_SR_12000; 2502f3d24a1SRyan Lee break; 2512f3d24a1SRyan Lee case 16000: 2522f3d24a1SRyan Lee sampling_rate = MAX98373_PCM_SR_SET1_SR_16000; 2532f3d24a1SRyan Lee break; 2542f3d24a1SRyan Lee case 22050: 2552f3d24a1SRyan Lee sampling_rate = MAX98373_PCM_SR_SET1_SR_22050; 2562f3d24a1SRyan Lee break; 2572f3d24a1SRyan Lee case 24000: 2582f3d24a1SRyan Lee sampling_rate = MAX98373_PCM_SR_SET1_SR_24000; 2592f3d24a1SRyan Lee break; 2602f3d24a1SRyan Lee case 32000: 2612f3d24a1SRyan Lee sampling_rate = MAX98373_PCM_SR_SET1_SR_32000; 2622f3d24a1SRyan Lee break; 2632f3d24a1SRyan Lee case 44100: 2642f3d24a1SRyan Lee sampling_rate = MAX98373_PCM_SR_SET1_SR_44100; 2652f3d24a1SRyan Lee break; 2662f3d24a1SRyan Lee case 48000: 2672f3d24a1SRyan Lee sampling_rate = MAX98373_PCM_SR_SET1_SR_48000; 2682f3d24a1SRyan Lee break; 2692f3d24a1SRyan Lee default: 27041572b54SKuninori Morimoto dev_err(component->dev, "rate %d not supported\n", 2712f3d24a1SRyan Lee params_rate(params)); 2722f3d24a1SRyan Lee goto err; 2732f3d24a1SRyan Lee } 274e1053262SRyan Lee 2752f3d24a1SRyan Lee /* set DAI_SR to correct LRCLK frequency */ 2762f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 2772f3d24a1SRyan Lee MAX98373_R2027_PCM_SR_SETUP_1, 2782f3d24a1SRyan Lee MAX98373_PCM_SR_SET1_SR_MASK, 2792f3d24a1SRyan Lee sampling_rate); 2802f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 2812f3d24a1SRyan Lee MAX98373_R2028_PCM_SR_SETUP_2, 2822f3d24a1SRyan Lee MAX98373_PCM_SR_SET2_SR_MASK, 2832f3d24a1SRyan Lee sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT); 2842f3d24a1SRyan Lee 2852f3d24a1SRyan Lee /* set sampling rate of IV */ 2862f3d24a1SRyan Lee if (max98373->interleave_mode && 2872f3d24a1SRyan Lee sampling_rate > MAX98373_PCM_SR_SET1_SR_16000) 2882f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 2892f3d24a1SRyan Lee MAX98373_R2028_PCM_SR_SETUP_2, 2902f3d24a1SRyan Lee MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 2912f3d24a1SRyan Lee sampling_rate - 3); 2922f3d24a1SRyan Lee else 2932f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 2942f3d24a1SRyan Lee MAX98373_R2028_PCM_SR_SETUP_2, 2952f3d24a1SRyan Lee MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 2962f3d24a1SRyan Lee sampling_rate); 2972f3d24a1SRyan Lee 29841572b54SKuninori Morimoto return max98373_set_clock(component, params); 2992f3d24a1SRyan Lee err: 3002f3d24a1SRyan Lee return -EINVAL; 3012f3d24a1SRyan Lee } 3022f3d24a1SRyan Lee 3032f3d24a1SRyan Lee static int max98373_dai_tdm_slot(struct snd_soc_dai *dai, 3042f3d24a1SRyan Lee unsigned int tx_mask, unsigned int rx_mask, 3052f3d24a1SRyan Lee int slots, int slot_width) 3062f3d24a1SRyan Lee { 30741572b54SKuninori Morimoto struct snd_soc_component *component = dai->component; 30841572b54SKuninori Morimoto struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 3092f3d24a1SRyan Lee int bsel = 0; 3102f3d24a1SRyan Lee unsigned int chan_sz = 0; 3112f3d24a1SRyan Lee unsigned int mask; 3122f3d24a1SRyan Lee int x, slot_found; 3132f3d24a1SRyan Lee 3143831a5b8SRyan Lee if (!tx_mask && !rx_mask && !slots && !slot_width) 3153831a5b8SRyan Lee max98373->tdm_mode = false; 3163831a5b8SRyan Lee else 3172f3d24a1SRyan Lee max98373->tdm_mode = true; 3182f3d24a1SRyan Lee 3192f3d24a1SRyan Lee /* BCLK configuration */ 3202f3d24a1SRyan Lee bsel = max98373_get_bclk_sel(slots * slot_width); 3212f3d24a1SRyan Lee if (bsel == 0) { 32241572b54SKuninori Morimoto dev_err(component->dev, "BCLK %d not supported\n", 3232f3d24a1SRyan Lee slots * slot_width); 3242f3d24a1SRyan Lee return -EINVAL; 3252f3d24a1SRyan Lee } 3262f3d24a1SRyan Lee 3272f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 3282f3d24a1SRyan Lee MAX98373_R2026_PCM_CLOCK_RATIO, 3292f3d24a1SRyan Lee MAX98373_PCM_CLK_SETUP_BSEL_MASK, 3302f3d24a1SRyan Lee bsel); 3312f3d24a1SRyan Lee 3322f3d24a1SRyan Lee /* Channel size configuration */ 3332f3d24a1SRyan Lee switch (slot_width) { 3342f3d24a1SRyan Lee case 16: 3352f3d24a1SRyan Lee chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 3362f3d24a1SRyan Lee break; 3372f3d24a1SRyan Lee case 24: 3382f3d24a1SRyan Lee chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 3392f3d24a1SRyan Lee break; 3402f3d24a1SRyan Lee case 32: 3412f3d24a1SRyan Lee chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 3422f3d24a1SRyan Lee break; 3432f3d24a1SRyan Lee default: 34441572b54SKuninori Morimoto dev_err(component->dev, "format unsupported %d\n", 3452f3d24a1SRyan Lee slot_width); 3462f3d24a1SRyan Lee return -EINVAL; 3472f3d24a1SRyan Lee } 3482f3d24a1SRyan Lee 3492f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 3502f3d24a1SRyan Lee MAX98373_R2024_PCM_DATA_FMT_CFG, 3512f3d24a1SRyan Lee MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 3522f3d24a1SRyan Lee 3532f3d24a1SRyan Lee /* Rx slot configuration */ 3542f3d24a1SRyan Lee slot_found = 0; 3552f3d24a1SRyan Lee mask = rx_mask; 3562f3d24a1SRyan Lee for (x = 0 ; x < 16 ; x++, mask >>= 1) { 3572f3d24a1SRyan Lee if (mask & 0x1) { 3582f3d24a1SRyan Lee if (slot_found == 0) 3592f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 3602f3d24a1SRyan Lee MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 3612f3d24a1SRyan Lee MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x); 3622f3d24a1SRyan Lee else 3632f3d24a1SRyan Lee regmap_write(max98373->regmap, 3642f3d24a1SRyan Lee MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 3652f3d24a1SRyan Lee x); 3662f3d24a1SRyan Lee slot_found++; 3672f3d24a1SRyan Lee if (slot_found > 1) 3682f3d24a1SRyan Lee break; 3692f3d24a1SRyan Lee } 3702f3d24a1SRyan Lee } 3712f3d24a1SRyan Lee 3722f3d24a1SRyan Lee /* Tx slot Hi-Z configuration */ 3732f3d24a1SRyan Lee regmap_write(max98373->regmap, 3742f3d24a1SRyan Lee MAX98373_R2020_PCM_TX_HIZ_EN_1, 3752f3d24a1SRyan Lee ~tx_mask & 0xFF); 3762f3d24a1SRyan Lee regmap_write(max98373->regmap, 3772f3d24a1SRyan Lee MAX98373_R2021_PCM_TX_HIZ_EN_2, 3782f3d24a1SRyan Lee (~tx_mask & 0xFF00) >> 8); 3792f3d24a1SRyan Lee 3802f3d24a1SRyan Lee return 0; 3812f3d24a1SRyan Lee } 3822f3d24a1SRyan Lee 3832f3d24a1SRyan Lee #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000 3842f3d24a1SRyan Lee 3852f3d24a1SRyan Lee #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 3862f3d24a1SRyan Lee SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 3872f3d24a1SRyan Lee 3882f3d24a1SRyan Lee static const struct snd_soc_dai_ops max98373_dai_ops = { 3892f3d24a1SRyan Lee .set_fmt = max98373_dai_set_fmt, 3902f3d24a1SRyan Lee .hw_params = max98373_dai_hw_params, 3912f3d24a1SRyan Lee .set_tdm_slot = max98373_dai_tdm_slot, 3922f3d24a1SRyan Lee }; 3932f3d24a1SRyan Lee 3942f3d24a1SRyan Lee static int max98373_dac_event(struct snd_soc_dapm_widget *w, 3952f3d24a1SRyan Lee struct snd_kcontrol *kcontrol, int event) 3962f3d24a1SRyan Lee { 39741572b54SKuninori Morimoto struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 39841572b54SKuninori Morimoto struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 3992f3d24a1SRyan Lee 4002f3d24a1SRyan Lee switch (event) { 4012f3d24a1SRyan Lee case SND_SOC_DAPM_POST_PMU: 4022f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 4032f3d24a1SRyan Lee MAX98373_R20FF_GLOBAL_SHDN, 4042f3d24a1SRyan Lee MAX98373_GLOBAL_EN_MASK, 1); 4052f3d24a1SRyan Lee break; 4062f3d24a1SRyan Lee case SND_SOC_DAPM_POST_PMD: 4072f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 4082f3d24a1SRyan Lee MAX98373_R20FF_GLOBAL_SHDN, 4092f3d24a1SRyan Lee MAX98373_GLOBAL_EN_MASK, 0); 4102f3d24a1SRyan Lee max98373->tdm_mode = 0; 4112f3d24a1SRyan Lee break; 4122f3d24a1SRyan Lee default: 4132f3d24a1SRyan Lee return 0; 4142f3d24a1SRyan Lee } 4152f3d24a1SRyan Lee return 0; 4162f3d24a1SRyan Lee } 4172f3d24a1SRyan Lee 4182f3d24a1SRyan Lee static const char * const max98373_switch_text[] = { 4192f3d24a1SRyan Lee "Left", "Right", "LeftRight"}; 4202f3d24a1SRyan Lee 4212f3d24a1SRyan Lee static const struct soc_enum dai_sel_enum = 4222f3d24a1SRyan Lee SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 4232f3d24a1SRyan Lee MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT, 4242f3d24a1SRyan Lee 3, max98373_switch_text); 4252f3d24a1SRyan Lee 4262f3d24a1SRyan Lee static const struct snd_kcontrol_new max98373_dai_controls = 4272f3d24a1SRyan Lee SOC_DAPM_ENUM("DAI Sel", dai_sel_enum); 4282f3d24a1SRyan Lee 4292f3d24a1SRyan Lee static const struct snd_kcontrol_new max98373_vi_control = 4302f3d24a1SRyan Lee SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0); 4312f3d24a1SRyan Lee 4322f3d24a1SRyan Lee static const struct snd_kcontrol_new max98373_spkfb_control = 4332f3d24a1SRyan Lee SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0); 4342f3d24a1SRyan Lee 4352f3d24a1SRyan Lee static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = { 4362f3d24a1SRyan Lee SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", 4372f3d24a1SRyan Lee MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event, 4382f3d24a1SRyan Lee SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 4392f3d24a1SRyan Lee SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0, 4402f3d24a1SRyan Lee &max98373_dai_controls), 4412f3d24a1SRyan Lee SND_SOC_DAPM_OUTPUT("BE_OUT"), 4422f3d24a1SRyan Lee SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0, 4432f3d24a1SRyan Lee MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0), 4442f3d24a1SRyan Lee SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0, 4452f3d24a1SRyan Lee MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0), 4462f3d24a1SRyan Lee SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0, 4472f3d24a1SRyan Lee SND_SOC_NOPM, 0, 0), 4482f3d24a1SRyan Lee SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0, 4492f3d24a1SRyan Lee &max98373_vi_control), 4502f3d24a1SRyan Lee SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0, 4512f3d24a1SRyan Lee &max98373_spkfb_control), 4522f3d24a1SRyan Lee SND_SOC_DAPM_SIGGEN("VMON"), 4532f3d24a1SRyan Lee SND_SOC_DAPM_SIGGEN("IMON"), 4542f3d24a1SRyan Lee SND_SOC_DAPM_SIGGEN("FBMON"), 4552f3d24a1SRyan Lee }; 4562f3d24a1SRyan Lee 4572f3d24a1SRyan Lee static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, 0, -50, 0); 4582f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv, 4592f3d24a1SRyan Lee 0, 8, TLV_DB_SCALE_ITEM(0, 50, 0), 4602f3d24a1SRyan Lee 9, 10, TLV_DB_SCALE_ITEM(500, 100, 0), 4612f3d24a1SRyan Lee ); 4622f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv, 4632f3d24a1SRyan Lee 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 4642f3d24a1SRyan Lee ); 4652f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv, 4662f3d24a1SRyan Lee 0, 1, TLV_DB_SCALE_ITEM(25, 25, 0), 4672f3d24a1SRyan Lee 2, 4, TLV_DB_SCALE_ITEM(100, 100, 0), 4682f3d24a1SRyan Lee ); 4692f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv, 4702f3d24a1SRyan Lee 0, 9, TLV_DB_SCALE_ITEM(800, 100, 0), 4712f3d24a1SRyan Lee ); 4722f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv, 4732f3d24a1SRyan Lee 0, 1, TLV_DB_SCALE_ITEM(-50, -50, 0), 4742f3d24a1SRyan Lee 2, 7, TLV_DB_SCALE_ITEM(-200, -100, 0), 4752f3d24a1SRyan Lee 8, 9, TLV_DB_SCALE_ITEM(-1000, -200, 0), 4762f3d24a1SRyan Lee 10, 11, TLV_DB_SCALE_ITEM(-1500, -300, 0), 4772f3d24a1SRyan Lee 12, 13, TLV_DB_SCALE_ITEM(-2000, -200, 0), 4782f3d24a1SRyan Lee 14, 15, TLV_DB_SCALE_ITEM(-2500, -500, 0), 4792f3d24a1SRyan Lee ); 4802f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv, 4812f3d24a1SRyan Lee 0, 15, TLV_DB_SCALE_ITEM(0, -100, 0), 4822f3d24a1SRyan Lee ); 4832f3d24a1SRyan Lee 4842f3d24a1SRyan Lee static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv, 4852f3d24a1SRyan Lee 0, 60, TLV_DB_SCALE_ITEM(0, -25, 0), 4862f3d24a1SRyan Lee ); 4872f3d24a1SRyan Lee 4882f3d24a1SRyan Lee static bool max98373_readable_register(struct device *dev, unsigned int reg) 4892f3d24a1SRyan Lee { 4902f3d24a1SRyan Lee switch (reg) { 4912f3d24a1SRyan Lee case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3: 4922f3d24a1SRyan Lee case MAX98373_R2010_IRQ_CTRL: 4932f3d24a1SRyan Lee case MAX98373_R2014_THERM_WARN_THRESH 4942f3d24a1SRyan Lee ... MAX98373_R2018_THERM_FOLDBACK_EN: 4952f3d24a1SRyan Lee case MAX98373_R201E_PIN_DRIVE_STRENGTH 4962f3d24a1SRyan Lee ... MAX98373_R2036_SOUNDWIRE_CTRL: 4972f3d24a1SRyan Lee case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN: 4982f3d24a1SRyan Lee case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 4992f3d24a1SRyan Lee ... MAX98373_R2047_IV_SENSE_ADC_EN: 5002f3d24a1SRyan Lee case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 5012f3d24a1SRyan Lee ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN: 5022f3d24a1SRyan Lee case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE: 5032f3d24a1SRyan Lee case MAX98373_R2097_BDE_L1_THRESH 5042f3d24a1SRyan Lee ... MAX98373_R209B_BDE_THRESH_HYST: 5052f3d24a1SRyan Lee case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3: 5062f3d24a1SRyan Lee case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK: 5072f3d24a1SRyan Lee case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN: 5082f3d24a1SRyan Lee case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN: 5092f3d24a1SRyan Lee case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 5102f3d24a1SRyan Lee ... MAX98373_R20FF_GLOBAL_SHDN: 5112f3d24a1SRyan Lee case MAX98373_R21FF_REV_ID: 5122f3d24a1SRyan Lee return true; 5132f3d24a1SRyan Lee default: 5142f3d24a1SRyan Lee return false; 5152f3d24a1SRyan Lee } 5162f3d24a1SRyan Lee }; 5172f3d24a1SRyan Lee 5182f3d24a1SRyan Lee static bool max98373_volatile_reg(struct device *dev, unsigned int reg) 5192f3d24a1SRyan Lee { 5202f3d24a1SRyan Lee switch (reg) { 5212f3d24a1SRyan Lee case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3: 5222f3d24a1SRyan Lee case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK: 5232f3d24a1SRyan Lee case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK: 5242f3d24a1SRyan Lee case MAX98373_R20B6_BDE_CUR_STATE_READBACK: 5252f3d24a1SRyan Lee case MAX98373_R21FF_REV_ID: 5262f3d24a1SRyan Lee return true; 5272f3d24a1SRyan Lee default: 5282f3d24a1SRyan Lee return false; 5292f3d24a1SRyan Lee } 5302f3d24a1SRyan Lee } 5312f3d24a1SRyan Lee 5322f3d24a1SRyan Lee static const char * const max98373_output_voltage_lvl_text[] = { 5332f3d24a1SRyan Lee "5.43V", "6.09V", "6.83V", "7.67V", "8.60V", 5342f3d24a1SRyan Lee "9.65V", "10.83V", "12.15V", "13.63V", "15.29V" 5352f3d24a1SRyan Lee }; 5362f3d24a1SRyan Lee 5372f3d24a1SRyan Lee static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum, 5382f3d24a1SRyan Lee MAX98373_R203E_AMP_PATH_GAIN, 0, 5392f3d24a1SRyan Lee max98373_output_voltage_lvl_text); 5402f3d24a1SRyan Lee 5412f3d24a1SRyan Lee static const char * const max98373_dht_attack_rate_text[] = { 5422f3d24a1SRyan Lee "17.5us", "35us", "70us", "140us", 5432f3d24a1SRyan Lee "280us", "560us", "1120us", "2240us" 5442f3d24a1SRyan Lee }; 5452f3d24a1SRyan Lee 5462f3d24a1SRyan Lee static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum, 5472f3d24a1SRyan Lee MAX98373_R20D2_DHT_ATTACK_CFG, 0, 5482f3d24a1SRyan Lee max98373_dht_attack_rate_text); 5492f3d24a1SRyan Lee 5502f3d24a1SRyan Lee static const char * const max98373_dht_release_rate_text[] = { 5512f3d24a1SRyan Lee "45ms", "225ms", "450ms", "1150ms", 5522f3d24a1SRyan Lee "2250ms", "3100ms", "4500ms", "6750ms" 5532f3d24a1SRyan Lee }; 5542f3d24a1SRyan Lee 5552f3d24a1SRyan Lee static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum, 5562f3d24a1SRyan Lee MAX98373_R20D3_DHT_RELEASE_CFG, 0, 5572f3d24a1SRyan Lee max98373_dht_release_rate_text); 5582f3d24a1SRyan Lee 5592f3d24a1SRyan Lee static const char * const max98373_limiter_attack_rate_text[] = { 5602f3d24a1SRyan Lee "10us", "20us", "40us", "80us", 5612f3d24a1SRyan Lee "160us", "320us", "640us", "1.28ms", 5622f3d24a1SRyan Lee "2.56ms", "5.12ms", "10.24ms", "20.48ms", 5632f3d24a1SRyan Lee "40.96ms", "81.92ms", "16.384ms", "32.768ms" 5642f3d24a1SRyan Lee }; 5652f3d24a1SRyan Lee 5662f3d24a1SRyan Lee static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum, 5672f3d24a1SRyan Lee MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4, 5682f3d24a1SRyan Lee max98373_limiter_attack_rate_text); 5692f3d24a1SRyan Lee 5702f3d24a1SRyan Lee static const char * const max98373_limiter_release_rate_text[] = { 5712f3d24a1SRyan Lee "40us", "80us", "160us", "320us", 5722f3d24a1SRyan Lee "640us", "1.28ms", "2.56ms", "5.120ms", 5732f3d24a1SRyan Lee "10.24ms", "20.48ms", "40.96ms", "81.92ms", 5742f3d24a1SRyan Lee "163.84ms", "327.68ms", "655.36ms", "1310.72ms" 5752f3d24a1SRyan Lee }; 5762f3d24a1SRyan Lee 5772f3d24a1SRyan Lee static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum, 5782f3d24a1SRyan Lee MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0, 5792f3d24a1SRyan Lee max98373_limiter_release_rate_text); 5802f3d24a1SRyan Lee 5812f3d24a1SRyan Lee static const char * const max98373_ADC_samplerate_text[] = { 5822f3d24a1SRyan Lee "333kHz", "192kHz", "64kHz", "48kHz" 5832f3d24a1SRyan Lee }; 5842f3d24a1SRyan Lee 5852f3d24a1SRyan Lee static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum, 5862f3d24a1SRyan Lee MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0, 5872f3d24a1SRyan Lee max98373_ADC_samplerate_text); 5882f3d24a1SRyan Lee 5892f3d24a1SRyan Lee static const struct snd_kcontrol_new max98373_snd_controls[] = { 5902f3d24a1SRyan Lee SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG, 5912f3d24a1SRyan Lee MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 5922f3d24a1SRyan Lee SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG, 5932f3d24a1SRyan Lee MAX98373_AMP_VOL_SEL_SHIFT, 1, 0), 5942f3d24a1SRyan Lee SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG, 5952f3d24a1SRyan Lee MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0), 5962f3d24a1SRyan Lee SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG, 5972f3d24a1SRyan Lee MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0), 5982f3d24a1SRyan Lee SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 5992f3d24a1SRyan Lee MAX98373_CLOCK_MON_SHIFT, 1, 0), 6002f3d24a1SRyan Lee SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG, 6012f3d24a1SRyan Lee MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0), 6022f3d24a1SRyan Lee SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG, 6032f3d24a1SRyan Lee MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0), 6042f3d24a1SRyan Lee SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL, 6052f3d24a1SRyan Lee 0, 0x7F, 0, max98373_digital_tlv), 6062f3d24a1SRyan Lee SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN, 6072f3d24a1SRyan Lee MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv), 6082f3d24a1SRyan Lee SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN, 6092f3d24a1SRyan Lee MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv), 6102f3d24a1SRyan Lee SOC_ENUM("Output Voltage", max98373_out_volt_enum), 6112f3d24a1SRyan Lee /* Dynamic Headroom Tracking */ 6122f3d24a1SRyan Lee SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN, 6132f3d24a1SRyan Lee MAX98373_DHT_EN_SHIFT, 1, 0), 614b6158323SRyan Lee SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG, 6152f3d24a1SRyan Lee MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv), 616b6158323SRyan Lee SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG, 6172f3d24a1SRyan Lee MAX98373_DHT_ROT_PNT_SHIFT, 15, 0, max98373_dht_rotation_point_tlv), 618b6158323SRyan Lee SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG, 6192f3d24a1SRyan Lee MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 620b6158323SRyan Lee SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG, 6212f3d24a1SRyan Lee MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv), 6222f3d24a1SRyan Lee SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum), 6232f3d24a1SRyan Lee SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum), 6242f3d24a1SRyan Lee /* ADC configuration */ 6252f3d24a1SRyan Lee SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0), 6262f3d24a1SRyan Lee SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 6272f3d24a1SRyan Lee MAX98373_FLT_EN_SHIFT, 1, 0), 6282f3d24a1SRyan Lee SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 6292f3d24a1SRyan Lee MAX98373_FLT_EN_SHIFT, 1, 0), 6302f3d24a1SRyan Lee SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0), 6312f3d24a1SRyan Lee SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0), 6322f3d24a1SRyan Lee SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 6332f3d24a1SRyan Lee 0, 0x3, 0), 6342f3d24a1SRyan Lee SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 6352f3d24a1SRyan Lee 0, 0x3, 0), 6362f3d24a1SRyan Lee SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum), 6372f3d24a1SRyan Lee /* Brownout Detection Engine */ 6382f3d24a1SRyan Lee SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0), 6392f3d24a1SRyan Lee SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2, 6402f3d24a1SRyan Lee MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0), 6412f3d24a1SRyan Lee SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2, 6422f3d24a1SRyan Lee MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0), 6432f3d24a1SRyan Lee SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0), 6442f3d24a1SRyan Lee SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0), 6452f3d24a1SRyan Lee SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0), 6462f3d24a1SRyan Lee SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0), 6472f3d24a1SRyan Lee SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0), 6482f3d24a1SRyan Lee SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0), 6492f3d24a1SRyan Lee SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0), 6502f3d24a1SRyan Lee SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0), 6512f3d24a1SRyan Lee SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0), 6522f3d24a1SRyan Lee SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0), 653b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2, 6542f3d24a1SRyan Lee 0, 0x3C, 0, max98373_bde_gain_tlv), 655b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2, 6562f3d24a1SRyan Lee 0, 0x3C, 0, max98373_bde_gain_tlv), 657b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2, 6582f3d24a1SRyan Lee 0, 0x3C, 0, max98373_bde_gain_tlv), 659b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2, 6602f3d24a1SRyan Lee 0, 0x3C, 0, max98373_bde_gain_tlv), 661b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3, 6622f3d24a1SRyan Lee 0, 0x3C, 0, max98373_bde_gain_tlv), 663b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3, 6642f3d24a1SRyan Lee 0, 0x3C, 0, max98373_bde_gain_tlv), 665b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3, 6662f3d24a1SRyan Lee 0, 0x3C, 0, max98373_bde_gain_tlv), 667b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3, 6682f3d24a1SRyan Lee 0, 0x3C, 0, max98373_bde_gain_tlv), 669b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1, 6702f3d24a1SRyan Lee 0, 0xF, 0, max98373_limiter_thresh_tlv), 671b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1, 6722f3d24a1SRyan Lee 0, 0xF, 0, max98373_limiter_thresh_tlv), 673b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1, 6742f3d24a1SRyan Lee 0, 0xF, 0, max98373_limiter_thresh_tlv), 675b6158323SRyan Lee SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1, 6762f3d24a1SRyan Lee 0, 0xF, 0, max98373_limiter_thresh_tlv), 6772f3d24a1SRyan Lee /* Limiter */ 6782f3d24a1SRyan Lee SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN, 6792f3d24a1SRyan Lee MAX98373_LIMITER_EN_SHIFT, 1, 0), 6802f3d24a1SRyan Lee SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG, 6812f3d24a1SRyan Lee MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0), 682b6158323SRyan Lee SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG, 6832f3d24a1SRyan Lee MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv), 6842f3d24a1SRyan Lee SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum), 6852f3d24a1SRyan Lee SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum), 6862f3d24a1SRyan Lee }; 6872f3d24a1SRyan Lee 6882f3d24a1SRyan Lee static const struct snd_soc_dapm_route max98373_audio_map[] = { 6892f3d24a1SRyan Lee /* Plabyack */ 6902f3d24a1SRyan Lee {"DAI Sel Mux", "Left", "Amp Enable"}, 6912f3d24a1SRyan Lee {"DAI Sel Mux", "Right", "Amp Enable"}, 6922f3d24a1SRyan Lee {"DAI Sel Mux", "LeftRight", "Amp Enable"}, 6932f3d24a1SRyan Lee {"BE_OUT", NULL, "DAI Sel Mux"}, 6942f3d24a1SRyan Lee /* Capture */ 6952f3d24a1SRyan Lee { "VI Sense", "Switch", "VMON" }, 6962f3d24a1SRyan Lee { "VI Sense", "Switch", "IMON" }, 6972f3d24a1SRyan Lee { "SpkFB Sense", "Switch", "FBMON" }, 6982f3d24a1SRyan Lee { "Voltage Sense", NULL, "VI Sense" }, 6992f3d24a1SRyan Lee { "Current Sense", NULL, "VI Sense" }, 7002f3d24a1SRyan Lee { "Speaker FB Sense", NULL, "SpkFB Sense" }, 7012f3d24a1SRyan Lee }; 7022f3d24a1SRyan Lee 7032f3d24a1SRyan Lee static struct snd_soc_dai_driver max98373_dai[] = { 7042f3d24a1SRyan Lee { 7052f3d24a1SRyan Lee .name = "max98373-aif1", 7062f3d24a1SRyan Lee .playback = { 7072f3d24a1SRyan Lee .stream_name = "HiFi Playback", 7082f3d24a1SRyan Lee .channels_min = 1, 7092f3d24a1SRyan Lee .channels_max = 2, 7102f3d24a1SRyan Lee .rates = MAX98373_RATES, 7112f3d24a1SRyan Lee .formats = MAX98373_FORMATS, 7122f3d24a1SRyan Lee }, 7132f3d24a1SRyan Lee .capture = { 7142f3d24a1SRyan Lee .stream_name = "HiFi Capture", 7152f3d24a1SRyan Lee .channels_min = 1, 7162f3d24a1SRyan Lee .channels_max = 2, 7172f3d24a1SRyan Lee .rates = MAX98373_RATES, 7182f3d24a1SRyan Lee .formats = MAX98373_FORMATS, 7192f3d24a1SRyan Lee }, 7202f3d24a1SRyan Lee .ops = &max98373_dai_ops, 7212f3d24a1SRyan Lee } 7222f3d24a1SRyan Lee }; 7232f3d24a1SRyan Lee 72441572b54SKuninori Morimoto static int max98373_probe(struct snd_soc_component *component) 7252f3d24a1SRyan Lee { 72641572b54SKuninori Morimoto struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 7272f3d24a1SRyan Lee 7282f3d24a1SRyan Lee /* Software Reset */ 7292f3d24a1SRyan Lee regmap_write(max98373->regmap, 7302f3d24a1SRyan Lee MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET); 7312f3d24a1SRyan Lee 7322f3d24a1SRyan Lee /* IV default slot configuration */ 7332f3d24a1SRyan Lee regmap_write(max98373->regmap, 7342f3d24a1SRyan Lee MAX98373_R2020_PCM_TX_HIZ_EN_1, 7352f3d24a1SRyan Lee 0xFF); 7362f3d24a1SRyan Lee regmap_write(max98373->regmap, 7372f3d24a1SRyan Lee MAX98373_R2021_PCM_TX_HIZ_EN_2, 7382f3d24a1SRyan Lee 0xFF); 7392f3d24a1SRyan Lee /* L/R mix configuration */ 7402f3d24a1SRyan Lee regmap_write(max98373->regmap, 7412f3d24a1SRyan Lee MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 7422f3d24a1SRyan Lee 0x80); 7432f3d24a1SRyan Lee regmap_write(max98373->regmap, 7442f3d24a1SRyan Lee MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 7452f3d24a1SRyan Lee 0x1); 7462f3d24a1SRyan Lee /* Set inital volume (0dB) */ 7472f3d24a1SRyan Lee regmap_write(max98373->regmap, 7482f3d24a1SRyan Lee MAX98373_R203D_AMP_DIG_VOL_CTRL, 7492f3d24a1SRyan Lee 0x00); 7502f3d24a1SRyan Lee regmap_write(max98373->regmap, 7512f3d24a1SRyan Lee MAX98373_R203E_AMP_PATH_GAIN, 7522f3d24a1SRyan Lee 0x00); 7532f3d24a1SRyan Lee /* Enable DC blocker */ 7542f3d24a1SRyan Lee regmap_write(max98373->regmap, 7552f3d24a1SRyan Lee MAX98373_R203F_AMP_DSP_CFG, 7562f3d24a1SRyan Lee 0x3); 7572f3d24a1SRyan Lee /* Enable IMON VMON DC blocker */ 7582f3d24a1SRyan Lee regmap_write(max98373->regmap, 7592f3d24a1SRyan Lee MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 7602f3d24a1SRyan Lee 0x7); 7612f3d24a1SRyan Lee /* voltage, current slot configuration */ 7622f3d24a1SRyan Lee regmap_write(max98373->regmap, 7632f3d24a1SRyan Lee MAX98373_R2022_PCM_TX_SRC_1, 7642f3d24a1SRyan Lee (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT | 7652f3d24a1SRyan Lee max98373->v_slot) & 0xFF); 7662f3d24a1SRyan Lee if (max98373->v_slot < 8) 7672f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 7682f3d24a1SRyan Lee MAX98373_R2020_PCM_TX_HIZ_EN_1, 7692f3d24a1SRyan Lee 1 << max98373->v_slot, 0); 7702f3d24a1SRyan Lee else 7712f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 7722f3d24a1SRyan Lee MAX98373_R2021_PCM_TX_HIZ_EN_2, 7732f3d24a1SRyan Lee 1 << (max98373->v_slot - 8), 0); 7742f3d24a1SRyan Lee 7752f3d24a1SRyan Lee if (max98373->i_slot < 8) 7762f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 7772f3d24a1SRyan Lee MAX98373_R2020_PCM_TX_HIZ_EN_1, 7782f3d24a1SRyan Lee 1 << max98373->i_slot, 0); 7792f3d24a1SRyan Lee else 7802f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 7812f3d24a1SRyan Lee MAX98373_R2021_PCM_TX_HIZ_EN_2, 7822f3d24a1SRyan Lee 1 << (max98373->i_slot - 8), 0); 7832f3d24a1SRyan Lee 7842f3d24a1SRyan Lee /* speaker feedback slot configuration */ 7852f3d24a1SRyan Lee regmap_write(max98373->regmap, 7862f3d24a1SRyan Lee MAX98373_R2023_PCM_TX_SRC_2, 7872f3d24a1SRyan Lee max98373->spkfb_slot & 0xFF); 7882f3d24a1SRyan Lee 7892f3d24a1SRyan Lee /* Set interleave mode */ 7902f3d24a1SRyan Lee if (max98373->interleave_mode) 7912f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 7922f3d24a1SRyan Lee MAX98373_R2024_PCM_DATA_FMT_CFG, 7932f3d24a1SRyan Lee MAX98373_PCM_TX_CH_INTERLEAVE_MASK, 7942f3d24a1SRyan Lee MAX98373_PCM_TX_CH_INTERLEAVE_MASK); 7952f3d24a1SRyan Lee 7962f3d24a1SRyan Lee /* Speaker enable */ 7972f3d24a1SRyan Lee regmap_update_bits(max98373->regmap, 7982f3d24a1SRyan Lee MAX98373_R2043_AMP_EN, 7992f3d24a1SRyan Lee MAX98373_SPK_EN_MASK, 1); 8002f3d24a1SRyan Lee 8012f3d24a1SRyan Lee return 0; 8022f3d24a1SRyan Lee } 8032f3d24a1SRyan Lee 8042f3d24a1SRyan Lee #ifdef CONFIG_PM_SLEEP 8052f3d24a1SRyan Lee static int max98373_suspend(struct device *dev) 8062f3d24a1SRyan Lee { 8072f3d24a1SRyan Lee struct max98373_priv *max98373 = dev_get_drvdata(dev); 8082f3d24a1SRyan Lee 8092f3d24a1SRyan Lee regcache_cache_only(max98373->regmap, true); 8102f3d24a1SRyan Lee regcache_mark_dirty(max98373->regmap); 8112f3d24a1SRyan Lee return 0; 8122f3d24a1SRyan Lee } 8132f3d24a1SRyan Lee static int max98373_resume(struct device *dev) 8142f3d24a1SRyan Lee { 8152f3d24a1SRyan Lee struct max98373_priv *max98373 = dev_get_drvdata(dev); 8162f3d24a1SRyan Lee 8172f3d24a1SRyan Lee regmap_write(max98373->regmap, 8182f3d24a1SRyan Lee MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET); 8192f3d24a1SRyan Lee regcache_cache_only(max98373->regmap, false); 8202f3d24a1SRyan Lee regcache_sync(max98373->regmap); 8212f3d24a1SRyan Lee return 0; 8222f3d24a1SRyan Lee } 8232f3d24a1SRyan Lee #endif 8242f3d24a1SRyan Lee 8252f3d24a1SRyan Lee static const struct dev_pm_ops max98373_pm = { 8262f3d24a1SRyan Lee SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume) 8272f3d24a1SRyan Lee }; 8282f3d24a1SRyan Lee 82941572b54SKuninori Morimoto static const struct snd_soc_component_driver soc_codec_dev_max98373 = { 8302f3d24a1SRyan Lee .probe = max98373_probe, 8312f3d24a1SRyan Lee .controls = max98373_snd_controls, 8322f3d24a1SRyan Lee .num_controls = ARRAY_SIZE(max98373_snd_controls), 8332f3d24a1SRyan Lee .dapm_widgets = max98373_dapm_widgets, 8342f3d24a1SRyan Lee .num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets), 8352f3d24a1SRyan Lee .dapm_routes = max98373_audio_map, 8362f3d24a1SRyan Lee .num_dapm_routes = ARRAY_SIZE(max98373_audio_map), 83741572b54SKuninori Morimoto .idle_bias_on = 1, 83841572b54SKuninori Morimoto .use_pmdown_time = 1, 83941572b54SKuninori Morimoto .endianness = 1, 84041572b54SKuninori Morimoto .non_legacy_dai_naming = 1, 8412f3d24a1SRyan Lee }; 8422f3d24a1SRyan Lee 8432f3d24a1SRyan Lee static const struct regmap_config max98373_regmap = { 8442f3d24a1SRyan Lee .reg_bits = 16, 8452f3d24a1SRyan Lee .val_bits = 8, 8462f3d24a1SRyan Lee .max_register = MAX98373_R21FF_REV_ID, 8472f3d24a1SRyan Lee .reg_defaults = max98373_reg, 8482f3d24a1SRyan Lee .num_reg_defaults = ARRAY_SIZE(max98373_reg), 8492f3d24a1SRyan Lee .readable_reg = max98373_readable_register, 8502f3d24a1SRyan Lee .volatile_reg = max98373_volatile_reg, 8512f3d24a1SRyan Lee .cache_type = REGCACHE_RBTREE, 8522f3d24a1SRyan Lee }; 8532f3d24a1SRyan Lee 8542f3d24a1SRyan Lee static void max98373_slot_config(struct i2c_client *i2c, 8552f3d24a1SRyan Lee struct max98373_priv *max98373) 8562f3d24a1SRyan Lee { 8572f3d24a1SRyan Lee int value; 8582f3d24a1SRyan Lee struct device *dev = &i2c->dev; 8592f3d24a1SRyan Lee 8602f3d24a1SRyan Lee if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value)) 8612f3d24a1SRyan Lee max98373->v_slot = value & 0xF; 8622f3d24a1SRyan Lee else 8632f3d24a1SRyan Lee max98373->v_slot = 0; 8642f3d24a1SRyan Lee 8652f3d24a1SRyan Lee if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value)) 8662f3d24a1SRyan Lee max98373->i_slot = value & 0xF; 8672f3d24a1SRyan Lee else 8682f3d24a1SRyan Lee max98373->i_slot = 1; 8692f3d24a1SRyan Lee 8702f3d24a1SRyan Lee if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value)) 8712f3d24a1SRyan Lee max98373->spkfb_slot = value & 0xF; 8722f3d24a1SRyan Lee else 8732f3d24a1SRyan Lee max98373->spkfb_slot = 2; 8742f3d24a1SRyan Lee } 8752f3d24a1SRyan Lee 8762f3d24a1SRyan Lee static int max98373_i2c_probe(struct i2c_client *i2c, 8772f3d24a1SRyan Lee const struct i2c_device_id *id) 8782f3d24a1SRyan Lee { 8792f3d24a1SRyan Lee 8802f3d24a1SRyan Lee int ret = 0; 8812f3d24a1SRyan Lee int reg = 0; 8822f3d24a1SRyan Lee struct max98373_priv *max98373 = NULL; 8832f3d24a1SRyan Lee 8842f3d24a1SRyan Lee max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL); 8852f3d24a1SRyan Lee 8862f3d24a1SRyan Lee if (!max98373) { 8872f3d24a1SRyan Lee ret = -ENOMEM; 8882f3d24a1SRyan Lee return ret; 8892f3d24a1SRyan Lee } 8902f3d24a1SRyan Lee i2c_set_clientdata(i2c, max98373); 8912f3d24a1SRyan Lee 8922f3d24a1SRyan Lee /* update interleave mode info */ 8932f3d24a1SRyan Lee if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode")) 8942f3d24a1SRyan Lee max98373->interleave_mode = 1; 8952f3d24a1SRyan Lee else 8962f3d24a1SRyan Lee max98373->interleave_mode = 0; 8972f3d24a1SRyan Lee 8982f3d24a1SRyan Lee 8992f3d24a1SRyan Lee /* regmap initialization */ 9002f3d24a1SRyan Lee max98373->regmap 9012f3d24a1SRyan Lee = devm_regmap_init_i2c(i2c, &max98373_regmap); 9022f3d24a1SRyan Lee if (IS_ERR(max98373->regmap)) { 9032f3d24a1SRyan Lee ret = PTR_ERR(max98373->regmap); 9042f3d24a1SRyan Lee dev_err(&i2c->dev, 9052f3d24a1SRyan Lee "Failed to allocate regmap: %d\n", ret); 9062f3d24a1SRyan Lee return ret; 9072f3d24a1SRyan Lee } 9082f3d24a1SRyan Lee 9092f3d24a1SRyan Lee /* Check Revision ID */ 9102f3d24a1SRyan Lee ret = regmap_read(max98373->regmap, 9112f3d24a1SRyan Lee MAX98373_R21FF_REV_ID, ®); 9122f3d24a1SRyan Lee if (ret < 0) { 9132f3d24a1SRyan Lee dev_err(&i2c->dev, 9142f3d24a1SRyan Lee "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID); 9152f3d24a1SRyan Lee return ret; 9162f3d24a1SRyan Lee } 9172f3d24a1SRyan Lee dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg); 9182f3d24a1SRyan Lee 9192f3d24a1SRyan Lee /* voltage/current slot configuration */ 9202f3d24a1SRyan Lee max98373_slot_config(i2c, max98373); 9212f3d24a1SRyan Lee 9222f3d24a1SRyan Lee /* codec registeration */ 92341572b54SKuninori Morimoto ret = devm_snd_soc_register_component(&i2c->dev, &soc_codec_dev_max98373, 9242f3d24a1SRyan Lee max98373_dai, ARRAY_SIZE(max98373_dai)); 9252f3d24a1SRyan Lee if (ret < 0) 9262f3d24a1SRyan Lee dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 9272f3d24a1SRyan Lee 9282f3d24a1SRyan Lee return ret; 9292f3d24a1SRyan Lee } 9302f3d24a1SRyan Lee 9312f3d24a1SRyan Lee static const struct i2c_device_id max98373_i2c_id[] = { 9322f3d24a1SRyan Lee { "max98373", 0}, 9332f3d24a1SRyan Lee { }, 9342f3d24a1SRyan Lee }; 9352f3d24a1SRyan Lee 9362f3d24a1SRyan Lee MODULE_DEVICE_TABLE(i2c, max98373_i2c_id); 9372f3d24a1SRyan Lee 9382f3d24a1SRyan Lee #if defined(CONFIG_OF) 9392f3d24a1SRyan Lee static const struct of_device_id max98373_of_match[] = { 9402f3d24a1SRyan Lee { .compatible = "maxim,max98373", }, 9412f3d24a1SRyan Lee { } 9422f3d24a1SRyan Lee }; 9432f3d24a1SRyan Lee MODULE_DEVICE_TABLE(of, max98373_of_match); 9442f3d24a1SRyan Lee #endif 9452f3d24a1SRyan Lee 9462f3d24a1SRyan Lee #ifdef CONFIG_ACPI 9472f3d24a1SRyan Lee static const struct acpi_device_id max98373_acpi_match[] = { 9482f3d24a1SRyan Lee { "MX98373", 0 }, 9492f3d24a1SRyan Lee {}, 9502f3d24a1SRyan Lee }; 9512f3d24a1SRyan Lee MODULE_DEVICE_TABLE(acpi, max98373_acpi_match); 9522f3d24a1SRyan Lee #endif 9532f3d24a1SRyan Lee 9542f3d24a1SRyan Lee static struct i2c_driver max98373_i2c_driver = { 9552f3d24a1SRyan Lee .driver = { 9562f3d24a1SRyan Lee .name = "max98373", 9572f3d24a1SRyan Lee .of_match_table = of_match_ptr(max98373_of_match), 9582f3d24a1SRyan Lee .acpi_match_table = ACPI_PTR(max98373_acpi_match), 9592f3d24a1SRyan Lee .pm = &max98373_pm, 9602f3d24a1SRyan Lee }, 9612f3d24a1SRyan Lee .probe = max98373_i2c_probe, 9622f3d24a1SRyan Lee .id_table = max98373_i2c_id, 9632f3d24a1SRyan Lee }; 9642f3d24a1SRyan Lee 9652f3d24a1SRyan Lee module_i2c_driver(max98373_i2c_driver) 9662f3d24a1SRyan Lee 9672f3d24a1SRyan Lee MODULE_DESCRIPTION("ALSA SoC MAX98373 driver"); 9682f3d24a1SRyan Lee MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>"); 9692f3d24a1SRyan Lee MODULE_LICENSE("GPL"); 970