1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2020 Maxim Integrated */ 3 4 #ifndef _MAX98373_SDW_H 5 #define _MAX98373_SDW_H 6 7 #include "max98373.h" 8 9 /* SoundWire Slave Control Port (SCP) */ 10 #define MAX98373_R0040_SCP_INIT_STAT_1 0x0040 11 #define MAX98373_R0041_SCP_INIT_MASK_1 0x0041 12 #define MAX98373_R0042_SCP_INIT_STAT_2 0x0042 13 #define MAX98373_R0044_SCP_CTRL 0x0044 14 #define MAX98373_R0045_SCP_SYSTEM_CTRL 0x0045 15 #define MAX98373_R0046_SCP_DEV_NUMBER 0x0046 16 #define MAX98373_R0050_SCP_DEV_ID_0 0x0050 17 #define MAX98373_R0051_SCP_DEV_ID_1 0x0051 18 #define MAX98373_R0052_SCP_DEV_ID_2 0x0052 19 #define MAX98373_R0053_SCP_DEV_ID_3 0x0053 20 #define MAX98373_R0054_SCP_DEV_ID_4 0x0054 21 #define MAX98373_R0055_SCP_DEV_ID_5 0x0055 22 #define MAX98373_R0060_SCP_FRAME_CTLR 0x0060 23 #define MAX98373_R0070_SCP_FRAME_CTLR 0x0070 24 25 /* SoundWire Device Data Port (DP) */ 26 /* Data Port 1 Registers */ 27 #define MAX98373_R0100_DP1_INIT_STAT 0x0100 28 #define MAX98373_R0101_DP1_INIT_MASK 0x0101 29 #define MAX98373_R0102_DP1_PORT_CTRL 0x0102 30 #define MAX98373_R0103_DP1_BLOCK_CTRL_1 0x0103 31 #define MAX98373_R0104_DP1_PREPARE_STATUS 0x0104 32 #define MAX98373_R0105_DP1_PREPARE_CTRL 0x0105 33 /* Data Port 1 Bank 0 Registers */ 34 #define MAX98373_R0120_DP1_CHANNEL_EN 0x0120 35 #define MAX98373_R0122_DP1_SAMPLE_CTRL1 0x0122 36 #define MAX98373_R0123_DP1_SAMPLE_CTRL2 0x0123 37 #define MAX98373_R0124_DP1_OFFSET_CTRL1 0x0124 38 #define MAX98373_R0125_DP1_OFFSET_CTRL2 0x0125 39 #define MAX98373_R0126_DP1_HCTRL 0x0126 40 #define MAX98373_R0127_DP1_BLOCK_CTRL3 0x0127 41 /* Data Port 1 Bank 1 Registers */ 42 #define MAX98373_R0130_DP1_CHANNEL_EN 0x0130 43 #define MAX98373_R0132_DP1_SAMPLE_CTRL1 0x0132 44 #define MAX98373_R0133_DP1_SAMPLE_CTRL2 0x0133 45 #define MAX98373_R0134_DP1_OFFSET_CTRL1 0x0134 46 #define MAX98373_R0135_DP1_OFFSET_CTRL2 0x0135 47 #define MAX98373_R0136_DP1_HCTRL 0x0136 48 #define MAX98373_R0137_DP1_BLOCK_CTRL3 0x0137 49 /* Data Port 3 Registers */ 50 #define MAX98373_R0300_DP3_INIT_STAT 0x0300 51 #define MAX98373_R0301_DP3_INIT_MASK 0x0301 52 #define MAX98373_R0302_DP3_PORT_CTRL 0x0302 53 #define MAX98373_R0303_DP3_BLOCK_CTRL_1 0x0303 54 #define MAX98373_R0304_DP3_PREPARE_STATUS 0x0304 55 #define MAX98373_R0305_DP3_PREPARE_CTRL 0x0305 56 /* Data Port 3 Bank 0 Registers */ 57 #define MAX98373_R0320_DP3_CHANNEL_EN 0x0320 58 #define MAX98373_R0322_DP3_SAMPLE_CTRL1 0x0322 59 #define MAX98373_R0323_DP3_SAMPLE_CTRL2 0x0323 60 #define MAX98373_R0324_DP3_OFFSET_CTRL1 0x0324 61 #define MAX98373_R0325_DP3_OFFSET_CTRL2 0x0325 62 #define MAX98373_R0326_DP3_HCTRL 0x0326 63 #define MAX98373_R0327_DP3_BLOCK_CTRL3 0x0327 64 /* Data Port 3 Bank 1 Registers */ 65 #define MAX98373_R0330_DP3_CHANNEL_EN 0x0330 66 #define MAX98373_R0332_DP3_SAMPLE_CTRL1 0x0332 67 #define MAX98373_R0333_DP3_SAMPLE_CTRL2 0x0333 68 #define MAX98373_R0334_DP3_OFFSET_CTRL1 0x0334 69 #define MAX98373_R0335_DP3_OFFSET_CTRL2 0x0335 70 #define MAX98373_R0336_DP3_HCTRL 0x0336 71 #define MAX98373_R0337_DP3_BLOCK_CTRL3 0x0337 72 #endif 73