1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2020, Maxim Integrated 3 4 #include <linux/acpi.h> 5 #include <linux/delay.h> 6 #include <linux/module.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/pm_runtime.h> 9 #include <linux/regmap.h> 10 #include <linux/slab.h> 11 #include <sound/pcm.h> 12 #include <sound/pcm_params.h> 13 #include <sound/sdw.h> 14 #include <sound/soc.h> 15 #include <sound/tlv.h> 16 #include <linux/of.h> 17 #include <linux/soundwire/sdw.h> 18 #include <linux/soundwire/sdw_type.h> 19 #include <linux/soundwire/sdw_registers.h> 20 #include "max98373.h" 21 #include "max98373-sdw.h" 22 23 static const u32 max98373_sdw_cache_reg[] = { 24 MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 25 MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 26 MAX98373_R20B6_BDE_CUR_STATE_READBACK, 27 }; 28 29 static struct reg_default max98373_reg[] = { 30 {MAX98373_R0040_SCP_INIT_STAT_1, 0x00}, 31 {MAX98373_R0041_SCP_INIT_MASK_1, 0x00}, 32 {MAX98373_R0042_SCP_INIT_STAT_2, 0x00}, 33 {MAX98373_R0044_SCP_CTRL, 0x00}, 34 {MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00}, 35 {MAX98373_R0046_SCP_DEV_NUMBER, 0x00}, 36 {MAX98373_R0050_SCP_DEV_ID_0, 0x21}, 37 {MAX98373_R0051_SCP_DEV_ID_1, 0x01}, 38 {MAX98373_R0052_SCP_DEV_ID_2, 0x9F}, 39 {MAX98373_R0053_SCP_DEV_ID_3, 0x87}, 40 {MAX98373_R0054_SCP_DEV_ID_4, 0x08}, 41 {MAX98373_R0055_SCP_DEV_ID_5, 0x00}, 42 {MAX98373_R0060_SCP_FRAME_CTLR, 0x00}, 43 {MAX98373_R0070_SCP_FRAME_CTLR, 0x00}, 44 {MAX98373_R0100_DP1_INIT_STAT, 0x00}, 45 {MAX98373_R0101_DP1_INIT_MASK, 0x00}, 46 {MAX98373_R0102_DP1_PORT_CTRL, 0x00}, 47 {MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00}, 48 {MAX98373_R0104_DP1_PREPARE_STATUS, 0x00}, 49 {MAX98373_R0105_DP1_PREPARE_CTRL, 0x00}, 50 {MAX98373_R0120_DP1_CHANNEL_EN, 0x00}, 51 {MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00}, 52 {MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00}, 53 {MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00}, 54 {MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00}, 55 {MAX98373_R0126_DP1_HCTRL, 0x00}, 56 {MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00}, 57 {MAX98373_R0130_DP1_CHANNEL_EN, 0x00}, 58 {MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00}, 59 {MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00}, 60 {MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00}, 61 {MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00}, 62 {MAX98373_R0136_DP1_HCTRL, 0x0136}, 63 {MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00}, 64 {MAX98373_R0300_DP3_INIT_STAT, 0x00}, 65 {MAX98373_R0301_DP3_INIT_MASK, 0x00}, 66 {MAX98373_R0302_DP3_PORT_CTRL, 0x00}, 67 {MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00}, 68 {MAX98373_R0304_DP3_PREPARE_STATUS, 0x00}, 69 {MAX98373_R0305_DP3_PREPARE_CTRL, 0x00}, 70 {MAX98373_R0320_DP3_CHANNEL_EN, 0x00}, 71 {MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00}, 72 {MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00}, 73 {MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00}, 74 {MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00}, 75 {MAX98373_R0326_DP3_HCTRL, 0x00}, 76 {MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00}, 77 {MAX98373_R0330_DP3_CHANNEL_EN, 0x00}, 78 {MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00}, 79 {MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00}, 80 {MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00}, 81 {MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00}, 82 {MAX98373_R0336_DP3_HCTRL, 0x00}, 83 {MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00}, 84 {MAX98373_R2000_SW_RESET, 0x00}, 85 {MAX98373_R2001_INT_RAW1, 0x00}, 86 {MAX98373_R2002_INT_RAW2, 0x00}, 87 {MAX98373_R2003_INT_RAW3, 0x00}, 88 {MAX98373_R2004_INT_STATE1, 0x00}, 89 {MAX98373_R2005_INT_STATE2, 0x00}, 90 {MAX98373_R2006_INT_STATE3, 0x00}, 91 {MAX98373_R2007_INT_FLAG1, 0x00}, 92 {MAX98373_R2008_INT_FLAG2, 0x00}, 93 {MAX98373_R2009_INT_FLAG3, 0x00}, 94 {MAX98373_R200A_INT_EN1, 0x00}, 95 {MAX98373_R200B_INT_EN2, 0x00}, 96 {MAX98373_R200C_INT_EN3, 0x00}, 97 {MAX98373_R200D_INT_FLAG_CLR1, 0x00}, 98 {MAX98373_R200E_INT_FLAG_CLR2, 0x00}, 99 {MAX98373_R200F_INT_FLAG_CLR3, 0x00}, 100 {MAX98373_R2010_IRQ_CTRL, 0x00}, 101 {MAX98373_R2014_THERM_WARN_THRESH, 0x10}, 102 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27}, 103 {MAX98373_R2016_THERM_HYSTERESIS, 0x01}, 104 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0}, 105 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00}, 106 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55}, 107 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE}, 108 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF}, 109 {MAX98373_R2022_PCM_TX_SRC_1, 0x00}, 110 {MAX98373_R2023_PCM_TX_SRC_2, 0x00}, 111 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0}, 112 {MAX98373_R2025_AUDIO_IF_MODE, 0x00}, 113 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04}, 114 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08}, 115 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88}, 116 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00}, 117 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00}, 118 {MAX98373_R202B_PCM_RX_EN, 0x00}, 119 {MAX98373_R202C_PCM_TX_EN, 0x00}, 120 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00}, 121 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00}, 122 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF}, 123 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF}, 124 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30}, 125 {MAX98373_R2034_ICC_TX_CNTL, 0x00}, 126 {MAX98373_R2035_ICC_TX_EN, 0x00}, 127 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05}, 128 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00}, 129 {MAX98373_R203E_AMP_PATH_GAIN, 0x08}, 130 {MAX98373_R203F_AMP_DSP_CFG, 0x02}, 131 {MAX98373_R2040_TONE_GEN_CFG, 0x00}, 132 {MAX98373_R2041_AMP_CFG, 0x03}, 133 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00}, 134 {MAX98373_R2043_AMP_EN, 0x00}, 135 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04}, 136 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00}, 137 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00}, 138 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00}, 139 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00}, 140 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00}, 141 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00}, 142 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00}, 143 {MAX98373_R2090_BDE_LVL_HOLD, 0x00}, 144 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00}, 145 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00}, 146 {MAX98373_R2097_BDE_L1_THRESH, 0x00}, 147 {MAX98373_R2098_BDE_L2_THRESH, 0x00}, 148 {MAX98373_R2099_BDE_L3_THRESH, 0x00}, 149 {MAX98373_R209A_BDE_L4_THRESH, 0x00}, 150 {MAX98373_R209B_BDE_THRESH_HYST, 0x00}, 151 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00}, 152 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00}, 153 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00}, 154 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00}, 155 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00}, 156 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00}, 157 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00}, 158 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00}, 159 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00}, 160 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00}, 161 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00}, 162 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00}, 163 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00}, 164 {MAX98373_R20B5_BDE_EN, 0x00}, 165 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00}, 166 {MAX98373_R20D1_DHT_CFG, 0x01}, 167 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02}, 168 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03}, 169 {MAX98373_R20D4_DHT_EN, 0x00}, 170 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00}, 171 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00}, 172 {MAX98373_R20E2_LIMITER_EN, 0x00}, 173 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00}, 174 {MAX98373_R20FF_GLOBAL_SHDN, 0x00}, 175 {MAX98373_R21FF_REV_ID, 0x42}, 176 }; 177 178 static bool max98373_readable_register(struct device *dev, unsigned int reg) 179 { 180 switch (reg) { 181 case MAX98373_R21FF_REV_ID: 182 case MAX98373_R2010_IRQ_CTRL: 183 /* SoundWire Control Port Registers */ 184 case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR: 185 /* Soundwire Data Port 1 Registers */ 186 case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3: 187 /* Soundwire Data Port 3 Registers */ 188 case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3: 189 case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3: 190 case MAX98373_R2014_THERM_WARN_THRESH 191 ... MAX98373_R2018_THERM_FOLDBACK_EN: 192 case MAX98373_R201E_PIN_DRIVE_STRENGTH 193 ... MAX98373_R2036_SOUNDWIRE_CTRL: 194 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN: 195 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 196 ... MAX98373_R2047_IV_SENSE_ADC_EN: 197 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 198 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN: 199 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE: 200 case MAX98373_R2097_BDE_L1_THRESH 201 ... MAX98373_R209B_BDE_THRESH_HYST: 202 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3: 203 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK: 204 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN: 205 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN: 206 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 207 ... MAX98373_R20FF_GLOBAL_SHDN: 208 return true; 209 default: 210 return false; 211 } 212 }; 213 214 static bool max98373_volatile_reg(struct device *dev, unsigned int reg) 215 { 216 switch (reg) { 217 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK: 218 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK: 219 case MAX98373_R20B6_BDE_CUR_STATE_READBACK: 220 case MAX98373_R20FF_GLOBAL_SHDN: 221 case MAX98373_R21FF_REV_ID: 222 /* SoundWire Control Port Registers */ 223 case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR: 224 /* Soundwire Data Port 1 Registers */ 225 case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3: 226 /* Soundwire Data Port 3 Registers */ 227 case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3: 228 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3: 229 return true; 230 default: 231 return false; 232 } 233 } 234 235 static const struct regmap_config max98373_sdw_regmap = { 236 .reg_bits = 32, 237 .val_bits = 8, 238 .max_register = MAX98373_R21FF_REV_ID, 239 .reg_defaults = max98373_reg, 240 .num_reg_defaults = ARRAY_SIZE(max98373_reg), 241 .readable_reg = max98373_readable_register, 242 .volatile_reg = max98373_volatile_reg, 243 .cache_type = REGCACHE_RBTREE, 244 .use_single_read = true, 245 .use_single_write = true, 246 }; 247 248 /* Power management functions and structure */ 249 static __maybe_unused int max98373_suspend(struct device *dev) 250 { 251 struct max98373_priv *max98373 = dev_get_drvdata(dev); 252 int i; 253 254 /* cache feedback register values before suspend */ 255 for (i = 0; i < max98373->cache_num; i++) 256 regmap_read(max98373->regmap, max98373->cache[i].reg, &max98373->cache[i].val); 257 258 regcache_cache_only(max98373->regmap, true); 259 260 return 0; 261 } 262 263 #define MAX98373_PROBE_TIMEOUT 5000 264 265 static __maybe_unused int max98373_resume(struct device *dev) 266 { 267 struct sdw_slave *slave = dev_to_sdw_dev(dev); 268 struct max98373_priv *max98373 = dev_get_drvdata(dev); 269 unsigned long time; 270 271 if (!max98373->first_hw_init) 272 return 0; 273 274 if (!slave->unattach_request) 275 goto regmap_sync; 276 277 time = wait_for_completion_timeout(&slave->initialization_complete, 278 msecs_to_jiffies(MAX98373_PROBE_TIMEOUT)); 279 if (!time) { 280 dev_err(dev, "Initialization not complete, timed out\n"); 281 sdw_show_ping_status(slave->bus, true); 282 283 return -ETIMEDOUT; 284 } 285 286 regmap_sync: 287 slave->unattach_request = 0; 288 regcache_cache_only(max98373->regmap, false); 289 regcache_sync(max98373->regmap); 290 291 return 0; 292 } 293 294 static const struct dev_pm_ops max98373_pm = { 295 SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume) 296 SET_RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL) 297 }; 298 299 static int max98373_read_prop(struct sdw_slave *slave) 300 { 301 struct sdw_slave_prop *prop = &slave->prop; 302 int nval, i; 303 u32 bit; 304 unsigned long addr; 305 struct sdw_dpn_prop *dpn; 306 307 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 308 309 /* BITMAP: 00001000 Dataport 3 is active */ 310 prop->source_ports = BIT(3); 311 /* BITMAP: 00000010 Dataport 1 is active */ 312 prop->sink_ports = BIT(1); 313 prop->paging_support = true; 314 prop->clk_stop_timeout = 20; 315 316 nval = hweight32(prop->source_ports); 317 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 318 sizeof(*prop->src_dpn_prop), 319 GFP_KERNEL); 320 if (!prop->src_dpn_prop) 321 return -ENOMEM; 322 323 i = 0; 324 dpn = prop->src_dpn_prop; 325 addr = prop->source_ports; 326 for_each_set_bit(bit, &addr, 32) { 327 dpn[i].num = bit; 328 dpn[i].type = SDW_DPN_FULL; 329 dpn[i].simple_ch_prep_sm = true; 330 dpn[i].ch_prep_timeout = 10; 331 i++; 332 } 333 334 /* do this again for sink now */ 335 nval = hweight32(prop->sink_ports); 336 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 337 sizeof(*prop->sink_dpn_prop), 338 GFP_KERNEL); 339 if (!prop->sink_dpn_prop) 340 return -ENOMEM; 341 342 i = 0; 343 dpn = prop->sink_dpn_prop; 344 addr = prop->sink_ports; 345 for_each_set_bit(bit, &addr, 32) { 346 dpn[i].num = bit; 347 dpn[i].type = SDW_DPN_FULL; 348 dpn[i].simple_ch_prep_sm = true; 349 dpn[i].ch_prep_timeout = 10; 350 i++; 351 } 352 353 /* set the timeout values */ 354 prop->clk_stop_timeout = 20; 355 356 return 0; 357 } 358 359 static int max98373_io_init(struct sdw_slave *slave) 360 { 361 struct device *dev = &slave->dev; 362 struct max98373_priv *max98373 = dev_get_drvdata(dev); 363 364 if (max98373->first_hw_init) { 365 regcache_cache_only(max98373->regmap, false); 366 regcache_cache_bypass(max98373->regmap, true); 367 } 368 369 /* 370 * PM runtime is only enabled when a Slave reports as Attached 371 */ 372 if (!max98373->first_hw_init) { 373 /* set autosuspend parameters */ 374 pm_runtime_set_autosuspend_delay(dev, 3000); 375 pm_runtime_use_autosuspend(dev); 376 377 /* update count of parent 'active' children */ 378 pm_runtime_set_active(dev); 379 380 /* make sure the device does not suspend immediately */ 381 pm_runtime_mark_last_busy(dev); 382 383 pm_runtime_enable(dev); 384 } 385 386 pm_runtime_get_noresume(dev); 387 388 /* Software Reset */ 389 max98373_reset(max98373, dev); 390 391 /* Set soundwire mode */ 392 regmap_write(max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, 3); 393 /* Enable ADC */ 394 regmap_write(max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, 3); 395 /* Set default Soundwire clock */ 396 regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, 5); 397 /* Set default sampling rate for speaker and IVDAC */ 398 regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88); 399 /* IV default slot configuration */ 400 regmap_write(max98373->regmap, 401 MAX98373_R2020_PCM_TX_HIZ_EN_1, 402 0xFF); 403 regmap_write(max98373->regmap, 404 MAX98373_R2021_PCM_TX_HIZ_EN_2, 405 0xFF); 406 /* L/R mix configuration */ 407 regmap_write(max98373->regmap, 408 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 409 0x80); 410 regmap_write(max98373->regmap, 411 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 412 0x1); 413 /* Enable DC blocker */ 414 regmap_write(max98373->regmap, 415 MAX98373_R203F_AMP_DSP_CFG, 416 0x3); 417 /* Enable IMON VMON DC blocker */ 418 regmap_write(max98373->regmap, 419 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 420 0x7); 421 /* voltage, current slot configuration */ 422 regmap_write(max98373->regmap, 423 MAX98373_R2022_PCM_TX_SRC_1, 424 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT | 425 max98373->v_slot) & 0xFF); 426 if (max98373->v_slot < 8) 427 regmap_update_bits(max98373->regmap, 428 MAX98373_R2020_PCM_TX_HIZ_EN_1, 429 1 << max98373->v_slot, 0); 430 else 431 regmap_update_bits(max98373->regmap, 432 MAX98373_R2021_PCM_TX_HIZ_EN_2, 433 1 << (max98373->v_slot - 8), 0); 434 435 if (max98373->i_slot < 8) 436 regmap_update_bits(max98373->regmap, 437 MAX98373_R2020_PCM_TX_HIZ_EN_1, 438 1 << max98373->i_slot, 0); 439 else 440 regmap_update_bits(max98373->regmap, 441 MAX98373_R2021_PCM_TX_HIZ_EN_2, 442 1 << (max98373->i_slot - 8), 0); 443 444 /* speaker feedback slot configuration */ 445 regmap_write(max98373->regmap, 446 MAX98373_R2023_PCM_TX_SRC_2, 447 max98373->spkfb_slot & 0xFF); 448 449 /* Set interleave mode */ 450 if (max98373->interleave_mode) 451 regmap_update_bits(max98373->regmap, 452 MAX98373_R2024_PCM_DATA_FMT_CFG, 453 MAX98373_PCM_TX_CH_INTERLEAVE_MASK, 454 MAX98373_PCM_TX_CH_INTERLEAVE_MASK); 455 456 /* Speaker enable */ 457 regmap_update_bits(max98373->regmap, 458 MAX98373_R2043_AMP_EN, 459 MAX98373_SPK_EN_MASK, 1); 460 461 regmap_write(max98373->regmap, MAX98373_R20B5_BDE_EN, 1); 462 regmap_write(max98373->regmap, MAX98373_R20E2_LIMITER_EN, 1); 463 464 if (max98373->first_hw_init) { 465 regcache_cache_bypass(max98373->regmap, false); 466 regcache_mark_dirty(max98373->regmap); 467 } 468 469 max98373->first_hw_init = true; 470 max98373->hw_init = true; 471 472 pm_runtime_mark_last_busy(dev); 473 pm_runtime_put_autosuspend(dev); 474 475 return 0; 476 } 477 478 static int max98373_clock_calculate(struct sdw_slave *slave, 479 unsigned int clk_freq) 480 { 481 int x, y; 482 static const int max98373_clk_family[] = { 483 7680000, 8400000, 9600000, 11289600, 484 12000000, 12288000, 13000000 485 }; 486 487 for (x = 0; x < 4; x++) 488 for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++) 489 if (clk_freq == (max98373_clk_family[y] >> x)) 490 return (x << 3) + y; 491 492 /* Set default clock (12.288 Mhz) if the value is not in the list */ 493 dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n", 494 clk_freq); 495 return 0x5; 496 } 497 498 static int max98373_clock_config(struct sdw_slave *slave, 499 struct sdw_bus_params *params) 500 { 501 struct device *dev = &slave->dev; 502 struct max98373_priv *max98373 = dev_get_drvdata(dev); 503 unsigned int clk_freq, value; 504 505 clk_freq = (params->curr_dr_freq >> 1); 506 507 /* 508 * Select the proper value for the register based on the 509 * requested clock. If the value is not in the list, 510 * use reasonable default - 12.288 Mhz 511 */ 512 value = max98373_clock_calculate(slave, clk_freq); 513 514 /* SWCLK */ 515 regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, value); 516 517 /* The default Sampling Rate value for IV is 48KHz*/ 518 regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88); 519 520 return 0; 521 } 522 523 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000 524 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) 525 526 static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream, 527 struct snd_pcm_hw_params *params, 528 struct snd_soc_dai *dai) 529 { 530 struct snd_soc_component *component = dai->component; 531 struct max98373_priv *max98373 = 532 snd_soc_component_get_drvdata(component); 533 struct sdw_stream_config stream_config = {0}; 534 struct sdw_port_config port_config = {0}; 535 struct sdw_stream_runtime *sdw_stream; 536 int ret, chan_sz, sampling_rate; 537 538 sdw_stream = snd_soc_dai_get_dma_data(dai, substream); 539 540 if (!sdw_stream) 541 return -EINVAL; 542 543 if (!max98373->slave) 544 return -EINVAL; 545 546 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 547 548 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 549 port_config.num = 1; 550 551 if (max98373->slot) { 552 stream_config.ch_count = max98373->slot; 553 port_config.ch_mask = max98373->rx_mask; 554 } 555 } else { 556 port_config.num = 3; 557 558 /* only IV are supported by capture */ 559 stream_config.ch_count = 2; 560 port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0); 561 } 562 563 ret = sdw_stream_add_slave(max98373->slave, &stream_config, 564 &port_config, 1, sdw_stream); 565 if (ret) { 566 dev_err(dai->dev, "Unable to configure port\n"); 567 return ret; 568 } 569 570 if (params_channels(params) > 16) { 571 dev_err(component->dev, "Unsupported channels %d\n", 572 params_channels(params)); 573 return -EINVAL; 574 } 575 576 /* Channel size configuration */ 577 switch (snd_pcm_format_width(params_format(params))) { 578 case 16: 579 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 580 break; 581 case 24: 582 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 583 break; 584 case 32: 585 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 586 break; 587 default: 588 dev_err(component->dev, "Channel size unsupported %d\n", 589 params_format(params)); 590 return -EINVAL; 591 } 592 593 max98373->ch_size = snd_pcm_format_width(params_format(params)); 594 595 regmap_update_bits(max98373->regmap, 596 MAX98373_R2024_PCM_DATA_FMT_CFG, 597 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 598 599 dev_dbg(component->dev, "Format supported %d", params_format(params)); 600 601 /* Sampling rate configuration */ 602 switch (params_rate(params)) { 603 case 8000: 604 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000; 605 break; 606 case 11025: 607 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025; 608 break; 609 case 12000: 610 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000; 611 break; 612 case 16000: 613 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000; 614 break; 615 case 22050: 616 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050; 617 break; 618 case 24000: 619 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000; 620 break; 621 case 32000: 622 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000; 623 break; 624 case 44100: 625 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100; 626 break; 627 case 48000: 628 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000; 629 break; 630 case 88200: 631 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200; 632 break; 633 case 96000: 634 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000; 635 break; 636 default: 637 dev_err(component->dev, "Rate %d is not supported\n", 638 params_rate(params)); 639 return -EINVAL; 640 } 641 642 /* set correct sampling frequency */ 643 regmap_update_bits(max98373->regmap, 644 MAX98373_R2028_PCM_SR_SETUP_2, 645 MAX98373_PCM_SR_SET2_SR_MASK, 646 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT); 647 648 /* set sampling rate of IV */ 649 regmap_update_bits(max98373->regmap, 650 MAX98373_R2028_PCM_SR_SETUP_2, 651 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 652 sampling_rate); 653 654 return 0; 655 } 656 657 static int max98373_pcm_hw_free(struct snd_pcm_substream *substream, 658 struct snd_soc_dai *dai) 659 { 660 struct snd_soc_component *component = dai->component; 661 struct max98373_priv *max98373 = 662 snd_soc_component_get_drvdata(component); 663 struct sdw_stream_runtime *sdw_stream = 664 snd_soc_dai_get_dma_data(dai, substream); 665 666 if (!max98373->slave) 667 return -EINVAL; 668 669 sdw_stream_remove_slave(max98373->slave, sdw_stream); 670 return 0; 671 } 672 673 static int max98373_set_sdw_stream(struct snd_soc_dai *dai, 674 void *sdw_stream, int direction) 675 { 676 snd_soc_dai_dma_data_set(dai, direction, sdw_stream); 677 678 return 0; 679 } 680 681 static void max98373_shutdown(struct snd_pcm_substream *substream, 682 struct snd_soc_dai *dai) 683 { 684 snd_soc_dai_set_dma_data(dai, substream, NULL); 685 } 686 687 static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai, 688 unsigned int tx_mask, 689 unsigned int rx_mask, 690 int slots, int slot_width) 691 { 692 struct snd_soc_component *component = dai->component; 693 struct max98373_priv *max98373 = 694 snd_soc_component_get_drvdata(component); 695 696 /* tx_mask is unused since it's irrelevant for I/V feedback */ 697 if (tx_mask) 698 return -EINVAL; 699 700 if (!rx_mask && !slots && !slot_width) 701 max98373->tdm_mode = false; 702 else 703 max98373->tdm_mode = true; 704 705 max98373->rx_mask = rx_mask; 706 max98373->slot = slots; 707 708 return 0; 709 } 710 711 static const struct snd_soc_dai_ops max98373_dai_sdw_ops = { 712 .hw_params = max98373_sdw_dai_hw_params, 713 .hw_free = max98373_pcm_hw_free, 714 .set_stream = max98373_set_sdw_stream, 715 .shutdown = max98373_shutdown, 716 .set_tdm_slot = max98373_sdw_set_tdm_slot, 717 }; 718 719 static struct snd_soc_dai_driver max98373_sdw_dai[] = { 720 { 721 .name = "max98373-aif1", 722 .playback = { 723 .stream_name = "HiFi Playback", 724 .channels_min = 1, 725 .channels_max = 2, 726 .rates = MAX98373_RATES, 727 .formats = MAX98373_FORMATS, 728 }, 729 .capture = { 730 .stream_name = "HiFi Capture", 731 .channels_min = 1, 732 .channels_max = 2, 733 .rates = MAX98373_RATES, 734 .formats = MAX98373_FORMATS, 735 }, 736 .ops = &max98373_dai_sdw_ops, 737 } 738 }; 739 740 static int max98373_init(struct sdw_slave *slave, struct regmap *regmap) 741 { 742 struct max98373_priv *max98373; 743 int ret; 744 int i; 745 struct device *dev = &slave->dev; 746 747 /* Allocate and assign private driver data structure */ 748 max98373 = devm_kzalloc(dev, sizeof(*max98373), GFP_KERNEL); 749 if (!max98373) 750 return -ENOMEM; 751 752 dev_set_drvdata(dev, max98373); 753 max98373->regmap = regmap; 754 max98373->slave = slave; 755 756 max98373->cache_num = ARRAY_SIZE(max98373_sdw_cache_reg); 757 max98373->cache = devm_kcalloc(dev, max98373->cache_num, 758 sizeof(*max98373->cache), 759 GFP_KERNEL); 760 if (!max98373->cache) 761 return -ENOMEM; 762 763 for (i = 0; i < max98373->cache_num; i++) 764 max98373->cache[i].reg = max98373_sdw_cache_reg[i]; 765 766 /* Read voltage and slot configuration */ 767 max98373_slot_config(dev, max98373); 768 769 max98373->hw_init = false; 770 max98373->first_hw_init = false; 771 772 /* codec registration */ 773 ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98373_sdw, 774 max98373_sdw_dai, 775 ARRAY_SIZE(max98373_sdw_dai)); 776 if (ret < 0) 777 dev_err(dev, "Failed to register codec: %d\n", ret); 778 779 return ret; 780 } 781 782 static int max98373_update_status(struct sdw_slave *slave, 783 enum sdw_slave_status status) 784 { 785 struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev); 786 787 if (status == SDW_SLAVE_UNATTACHED) 788 max98373->hw_init = false; 789 790 /* 791 * Perform initialization only if slave status is SDW_SLAVE_ATTACHED 792 */ 793 if (max98373->hw_init || status != SDW_SLAVE_ATTACHED) 794 return 0; 795 796 /* perform I/O transfers required for Slave initialization */ 797 return max98373_io_init(slave); 798 } 799 800 static int max98373_bus_config(struct sdw_slave *slave, 801 struct sdw_bus_params *params) 802 { 803 int ret; 804 805 ret = max98373_clock_config(slave, params); 806 if (ret < 0) 807 dev_err(&slave->dev, "Invalid clk config"); 808 809 return ret; 810 } 811 812 /* 813 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 814 * port_prep are not defined for now 815 */ 816 static struct sdw_slave_ops max98373_slave_ops = { 817 .read_prop = max98373_read_prop, 818 .update_status = max98373_update_status, 819 .bus_config = max98373_bus_config, 820 }; 821 822 static int max98373_sdw_probe(struct sdw_slave *slave, 823 const struct sdw_device_id *id) 824 { 825 struct regmap *regmap; 826 827 /* Regmap Initialization */ 828 regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap); 829 if (IS_ERR(regmap)) 830 return PTR_ERR(regmap); 831 832 return max98373_init(slave, regmap); 833 } 834 835 static int max98373_sdw_remove(struct sdw_slave *slave) 836 { 837 struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev); 838 839 if (max98373->first_hw_init) 840 pm_runtime_disable(&slave->dev); 841 842 return 0; 843 } 844 845 #if defined(CONFIG_OF) 846 static const struct of_device_id max98373_of_match[] = { 847 { .compatible = "maxim,max98373", }, 848 {}, 849 }; 850 MODULE_DEVICE_TABLE(of, max98373_of_match); 851 #endif 852 853 #ifdef CONFIG_ACPI 854 static const struct acpi_device_id max98373_acpi_match[] = { 855 { "MX98373", 0 }, 856 {}, 857 }; 858 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match); 859 #endif 860 861 static const struct sdw_device_id max98373_id[] = { 862 SDW_SLAVE_ENTRY(0x019F, 0x8373, 0), 863 {}, 864 }; 865 MODULE_DEVICE_TABLE(sdw, max98373_id); 866 867 static struct sdw_driver max98373_sdw_driver = { 868 .driver = { 869 .name = "max98373", 870 .owner = THIS_MODULE, 871 .of_match_table = of_match_ptr(max98373_of_match), 872 .acpi_match_table = ACPI_PTR(max98373_acpi_match), 873 .pm = &max98373_pm, 874 }, 875 .probe = max98373_sdw_probe, 876 .remove = max98373_sdw_remove, 877 .ops = &max98373_slave_ops, 878 .id_table = max98373_id, 879 }; 880 881 module_sdw_driver(max98373_sdw_driver); 882 883 MODULE_DESCRIPTION("ASoC MAX98373 driver SDW"); 884 MODULE_AUTHOR("Oleg Sherbakov <oleg.sherbakov@maximintegrated.com>"); 885 MODULE_LICENSE("GPL v2"); 886