1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2020, Maxim Integrated 3 4 #include <linux/acpi.h> 5 #include <linux/delay.h> 6 #include <linux/module.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/pm_runtime.h> 9 #include <linux/regmap.h> 10 #include <linux/slab.h> 11 #include <sound/pcm.h> 12 #include <sound/pcm_params.h> 13 #include <sound/soc.h> 14 #include <sound/tlv.h> 15 #include <linux/of.h> 16 #include <linux/soundwire/sdw.h> 17 #include <linux/soundwire/sdw_type.h> 18 #include <linux/soundwire/sdw_registers.h> 19 #include "max98373.h" 20 #include "max98373-sdw.h" 21 22 struct sdw_stream_data { 23 struct sdw_stream_runtime *sdw_stream; 24 }; 25 26 static struct reg_default max98373_reg[] = { 27 {MAX98373_R0040_SCP_INIT_STAT_1, 0x00}, 28 {MAX98373_R0041_SCP_INIT_MASK_1, 0x00}, 29 {MAX98373_R0042_SCP_INIT_STAT_2, 0x00}, 30 {MAX98373_R0044_SCP_CTRL, 0x00}, 31 {MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00}, 32 {MAX98373_R0046_SCP_DEV_NUMBER, 0x00}, 33 {MAX98373_R0050_SCP_DEV_ID_0, 0x21}, 34 {MAX98373_R0051_SCP_DEV_ID_1, 0x01}, 35 {MAX98373_R0052_SCP_DEV_ID_2, 0x9F}, 36 {MAX98373_R0053_SCP_DEV_ID_3, 0x87}, 37 {MAX98373_R0054_SCP_DEV_ID_4, 0x08}, 38 {MAX98373_R0055_SCP_DEV_ID_5, 0x00}, 39 {MAX98373_R0060_SCP_FRAME_CTLR, 0x00}, 40 {MAX98373_R0070_SCP_FRAME_CTLR, 0x00}, 41 {MAX98373_R0100_DP1_INIT_STAT, 0x00}, 42 {MAX98373_R0101_DP1_INIT_MASK, 0x00}, 43 {MAX98373_R0102_DP1_PORT_CTRL, 0x00}, 44 {MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00}, 45 {MAX98373_R0104_DP1_PREPARE_STATUS, 0x00}, 46 {MAX98373_R0105_DP1_PREPARE_CTRL, 0x00}, 47 {MAX98373_R0120_DP1_CHANNEL_EN, 0x00}, 48 {MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00}, 49 {MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00}, 50 {MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00}, 51 {MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00}, 52 {MAX98373_R0126_DP1_HCTRL, 0x00}, 53 {MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00}, 54 {MAX98373_R0130_DP1_CHANNEL_EN, 0x00}, 55 {MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00}, 56 {MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00}, 57 {MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00}, 58 {MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00}, 59 {MAX98373_R0136_DP1_HCTRL, 0x0136}, 60 {MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00}, 61 {MAX98373_R0300_DP3_INIT_STAT, 0x00}, 62 {MAX98373_R0301_DP3_INIT_MASK, 0x00}, 63 {MAX98373_R0302_DP3_PORT_CTRL, 0x00}, 64 {MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00}, 65 {MAX98373_R0304_DP3_PREPARE_STATUS, 0x00}, 66 {MAX98373_R0305_DP3_PREPARE_CTRL, 0x00}, 67 {MAX98373_R0320_DP3_CHANNEL_EN, 0x00}, 68 {MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00}, 69 {MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00}, 70 {MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00}, 71 {MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00}, 72 {MAX98373_R0326_DP3_HCTRL, 0x00}, 73 {MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00}, 74 {MAX98373_R0330_DP3_CHANNEL_EN, 0x00}, 75 {MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00}, 76 {MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00}, 77 {MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00}, 78 {MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00}, 79 {MAX98373_R0336_DP3_HCTRL, 0x00}, 80 {MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00}, 81 {MAX98373_R2000_SW_RESET, 0x00}, 82 {MAX98373_R2001_INT_RAW1, 0x00}, 83 {MAX98373_R2002_INT_RAW2, 0x00}, 84 {MAX98373_R2003_INT_RAW3, 0x00}, 85 {MAX98373_R2004_INT_STATE1, 0x00}, 86 {MAX98373_R2005_INT_STATE2, 0x00}, 87 {MAX98373_R2006_INT_STATE3, 0x00}, 88 {MAX98373_R2007_INT_FLAG1, 0x00}, 89 {MAX98373_R2008_INT_FLAG2, 0x00}, 90 {MAX98373_R2009_INT_FLAG3, 0x00}, 91 {MAX98373_R200A_INT_EN1, 0x00}, 92 {MAX98373_R200B_INT_EN2, 0x00}, 93 {MAX98373_R200C_INT_EN3, 0x00}, 94 {MAX98373_R200D_INT_FLAG_CLR1, 0x00}, 95 {MAX98373_R200E_INT_FLAG_CLR2, 0x00}, 96 {MAX98373_R200F_INT_FLAG_CLR3, 0x00}, 97 {MAX98373_R2010_IRQ_CTRL, 0x00}, 98 {MAX98373_R2014_THERM_WARN_THRESH, 0x10}, 99 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27}, 100 {MAX98373_R2016_THERM_HYSTERESIS, 0x01}, 101 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0}, 102 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00}, 103 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55}, 104 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE}, 105 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF}, 106 {MAX98373_R2022_PCM_TX_SRC_1, 0x00}, 107 {MAX98373_R2023_PCM_TX_SRC_2, 0x00}, 108 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0}, 109 {MAX98373_R2025_AUDIO_IF_MODE, 0x00}, 110 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04}, 111 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08}, 112 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88}, 113 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00}, 114 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00}, 115 {MAX98373_R202B_PCM_RX_EN, 0x00}, 116 {MAX98373_R202C_PCM_TX_EN, 0x00}, 117 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00}, 118 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00}, 119 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF}, 120 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF}, 121 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30}, 122 {MAX98373_R2034_ICC_TX_CNTL, 0x00}, 123 {MAX98373_R2035_ICC_TX_EN, 0x00}, 124 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05}, 125 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00}, 126 {MAX98373_R203E_AMP_PATH_GAIN, 0x08}, 127 {MAX98373_R203F_AMP_DSP_CFG, 0x02}, 128 {MAX98373_R2040_TONE_GEN_CFG, 0x00}, 129 {MAX98373_R2041_AMP_CFG, 0x03}, 130 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00}, 131 {MAX98373_R2043_AMP_EN, 0x00}, 132 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04}, 133 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00}, 134 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00}, 135 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00}, 136 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00}, 137 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00}, 138 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00}, 139 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00}, 140 {MAX98373_R2090_BDE_LVL_HOLD, 0x00}, 141 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00}, 142 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00}, 143 {MAX98373_R2097_BDE_L1_THRESH, 0x00}, 144 {MAX98373_R2098_BDE_L2_THRESH, 0x00}, 145 {MAX98373_R2099_BDE_L3_THRESH, 0x00}, 146 {MAX98373_R209A_BDE_L4_THRESH, 0x00}, 147 {MAX98373_R209B_BDE_THRESH_HYST, 0x00}, 148 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00}, 149 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00}, 150 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00}, 151 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00}, 152 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00}, 153 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00}, 154 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00}, 155 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00}, 156 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00}, 157 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00}, 158 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00}, 159 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00}, 160 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00}, 161 {MAX98373_R20B5_BDE_EN, 0x00}, 162 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00}, 163 {MAX98373_R20D1_DHT_CFG, 0x01}, 164 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02}, 165 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03}, 166 {MAX98373_R20D4_DHT_EN, 0x00}, 167 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00}, 168 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00}, 169 {MAX98373_R20E2_LIMITER_EN, 0x00}, 170 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00}, 171 {MAX98373_R20FF_GLOBAL_SHDN, 0x00}, 172 {MAX98373_R21FF_REV_ID, 0x42}, 173 }; 174 175 static bool max98373_readable_register(struct device *dev, unsigned int reg) 176 { 177 switch (reg) { 178 case MAX98373_R21FF_REV_ID: 179 case MAX98373_R2010_IRQ_CTRL: 180 /* SoundWire Control Port Registers */ 181 case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR: 182 /* Soundwire Data Port 1 Registers */ 183 case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3: 184 /* Soundwire Data Port 3 Registers */ 185 case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3: 186 case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3: 187 case MAX98373_R2014_THERM_WARN_THRESH 188 ... MAX98373_R2018_THERM_FOLDBACK_EN: 189 case MAX98373_R201E_PIN_DRIVE_STRENGTH 190 ... MAX98373_R2036_SOUNDWIRE_CTRL: 191 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN: 192 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 193 ... MAX98373_R2047_IV_SENSE_ADC_EN: 194 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 195 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN: 196 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE: 197 case MAX98373_R2097_BDE_L1_THRESH 198 ... MAX98373_R209B_BDE_THRESH_HYST: 199 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3: 200 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK: 201 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN: 202 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN: 203 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 204 ... MAX98373_R20FF_GLOBAL_SHDN: 205 return true; 206 default: 207 return false; 208 } 209 }; 210 211 static bool max98373_volatile_reg(struct device *dev, unsigned int reg) 212 { 213 switch (reg) { 214 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK: 215 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK: 216 case MAX98373_R20B6_BDE_CUR_STATE_READBACK: 217 case MAX98373_R21FF_REV_ID: 218 /* SoundWire Control Port Registers */ 219 case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR: 220 /* Soundwire Data Port 1 Registers */ 221 case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3: 222 /* Soundwire Data Port 3 Registers */ 223 case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3: 224 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3: 225 return true; 226 default: 227 return false; 228 } 229 } 230 231 static const struct regmap_config max98373_sdw_regmap = { 232 .reg_bits = 32, 233 .val_bits = 8, 234 .max_register = MAX98373_R21FF_REV_ID, 235 .reg_defaults = max98373_reg, 236 .num_reg_defaults = ARRAY_SIZE(max98373_reg), 237 .readable_reg = max98373_readable_register, 238 .volatile_reg = max98373_volatile_reg, 239 .cache_type = REGCACHE_RBTREE, 240 .use_single_read = true, 241 .use_single_write = true, 242 }; 243 244 /* Power management functions and structure */ 245 static __maybe_unused int max98373_suspend(struct device *dev) 246 { 247 struct max98373_priv *max98373 = dev_get_drvdata(dev); 248 249 regcache_cache_only(max98373->regmap, true); 250 251 return 0; 252 } 253 254 static __maybe_unused int max98373_resume(struct device *dev) 255 { 256 struct sdw_slave *slave = dev_to_sdw_dev(dev); 257 struct max98373_priv *max98373 = dev_get_drvdata(dev); 258 unsigned long time; 259 260 if (!max98373->hw_init) 261 return 0; 262 263 if (!slave->unattach_request) 264 goto regmap_sync; 265 266 time = wait_for_completion_timeout(&slave->initialization_complete, 267 msecs_to_jiffies(2000)); 268 if (!time) { 269 dev_err(dev, "Initialization not complete, timed out\n"); 270 return -ETIMEDOUT; 271 } 272 273 regmap_sync: 274 slave->unattach_request = 0; 275 regcache_cache_only(max98373->regmap, false); 276 regcache_sync(max98373->regmap); 277 278 return 0; 279 } 280 281 static const struct dev_pm_ops max98373_pm = { 282 SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume) 283 SET_RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL) 284 }; 285 286 static int max98373_read_prop(struct sdw_slave *slave) 287 { 288 struct sdw_slave_prop *prop = &slave->prop; 289 int nval, i; 290 u32 bit; 291 unsigned long addr; 292 struct sdw_dpn_prop *dpn; 293 294 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 295 296 /* BITMAP: 00001000 Dataport 3 is active */ 297 prop->source_ports = BIT(3); 298 /* BITMAP: 00000010 Dataport 1 is active */ 299 prop->sink_ports = BIT(1); 300 prop->paging_support = true; 301 prop->clk_stop_timeout = 20; 302 303 nval = hweight32(prop->source_ports); 304 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 305 sizeof(*prop->src_dpn_prop), 306 GFP_KERNEL); 307 if (!prop->src_dpn_prop) 308 return -ENOMEM; 309 310 i = 0; 311 dpn = prop->src_dpn_prop; 312 addr = prop->source_ports; 313 for_each_set_bit(bit, &addr, 32) { 314 dpn[i].num = bit; 315 dpn[i].type = SDW_DPN_FULL; 316 dpn[i].simple_ch_prep_sm = true; 317 dpn[i].ch_prep_timeout = 10; 318 i++; 319 } 320 321 /* do this again for sink now */ 322 nval = hweight32(prop->sink_ports); 323 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 324 sizeof(*prop->sink_dpn_prop), 325 GFP_KERNEL); 326 if (!prop->sink_dpn_prop) 327 return -ENOMEM; 328 329 i = 0; 330 dpn = prop->sink_dpn_prop; 331 addr = prop->sink_ports; 332 for_each_set_bit(bit, &addr, 32) { 333 dpn[i].num = bit; 334 dpn[i].type = SDW_DPN_FULL; 335 dpn[i].simple_ch_prep_sm = true; 336 dpn[i].ch_prep_timeout = 10; 337 i++; 338 } 339 340 /* set the timeout values */ 341 prop->clk_stop_timeout = 20; 342 343 return 0; 344 } 345 346 static int max98373_io_init(struct sdw_slave *slave) 347 { 348 struct device *dev = &slave->dev; 349 struct max98373_priv *max98373 = dev_get_drvdata(dev); 350 351 if (max98373->pm_init_once) { 352 regcache_cache_only(max98373->regmap, false); 353 regcache_cache_bypass(max98373->regmap, true); 354 } 355 356 /* 357 * PM runtime is only enabled when a Slave reports as Attached 358 */ 359 if (!max98373->pm_init_once) { 360 /* set autosuspend parameters */ 361 pm_runtime_set_autosuspend_delay(dev, 3000); 362 pm_runtime_use_autosuspend(dev); 363 364 /* update count of parent 'active' children */ 365 pm_runtime_set_active(dev); 366 367 /* make sure the device does not suspend immediately */ 368 pm_runtime_mark_last_busy(dev); 369 370 pm_runtime_enable(dev); 371 } 372 373 pm_runtime_get_noresume(dev); 374 375 /* Software Reset */ 376 max98373_reset(max98373, dev); 377 378 /* Set soundwire mode */ 379 regmap_write(max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, 3); 380 /* Enable ADC */ 381 regmap_write(max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, 3); 382 /* Set default Soundwire clock */ 383 regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, 5); 384 /* Set default sampling rate for speaker and IVDAC */ 385 regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88); 386 /* IV default slot configuration */ 387 regmap_write(max98373->regmap, 388 MAX98373_R2020_PCM_TX_HIZ_EN_1, 389 0xFF); 390 regmap_write(max98373->regmap, 391 MAX98373_R2021_PCM_TX_HIZ_EN_2, 392 0xFF); 393 /* L/R mix configuration */ 394 regmap_write(max98373->regmap, 395 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 396 0x80); 397 regmap_write(max98373->regmap, 398 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 399 0x1); 400 /* Enable DC blocker */ 401 regmap_write(max98373->regmap, 402 MAX98373_R203F_AMP_DSP_CFG, 403 0x3); 404 /* Enable IMON VMON DC blocker */ 405 regmap_write(max98373->regmap, 406 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 407 0x7); 408 /* voltage, current slot configuration */ 409 regmap_write(max98373->regmap, 410 MAX98373_R2022_PCM_TX_SRC_1, 411 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT | 412 max98373->v_slot) & 0xFF); 413 if (max98373->v_slot < 8) 414 regmap_update_bits(max98373->regmap, 415 MAX98373_R2020_PCM_TX_HIZ_EN_1, 416 1 << max98373->v_slot, 0); 417 else 418 regmap_update_bits(max98373->regmap, 419 MAX98373_R2021_PCM_TX_HIZ_EN_2, 420 1 << (max98373->v_slot - 8), 0); 421 422 if (max98373->i_slot < 8) 423 regmap_update_bits(max98373->regmap, 424 MAX98373_R2020_PCM_TX_HIZ_EN_1, 425 1 << max98373->i_slot, 0); 426 else 427 regmap_update_bits(max98373->regmap, 428 MAX98373_R2021_PCM_TX_HIZ_EN_2, 429 1 << (max98373->i_slot - 8), 0); 430 431 /* speaker feedback slot configuration */ 432 regmap_write(max98373->regmap, 433 MAX98373_R2023_PCM_TX_SRC_2, 434 max98373->spkfb_slot & 0xFF); 435 436 /* Set interleave mode */ 437 if (max98373->interleave_mode) 438 regmap_update_bits(max98373->regmap, 439 MAX98373_R2024_PCM_DATA_FMT_CFG, 440 MAX98373_PCM_TX_CH_INTERLEAVE_MASK, 441 MAX98373_PCM_TX_CH_INTERLEAVE_MASK); 442 443 /* Speaker enable */ 444 regmap_update_bits(max98373->regmap, 445 MAX98373_R2043_AMP_EN, 446 MAX98373_SPK_EN_MASK, 1); 447 448 regmap_write(max98373->regmap, MAX98373_R20B5_BDE_EN, 1); 449 regmap_write(max98373->regmap, MAX98373_R20E2_LIMITER_EN, 1); 450 451 if (max98373->pm_init_once) { 452 regcache_cache_bypass(max98373->regmap, false); 453 regcache_mark_dirty(max98373->regmap); 454 } 455 456 max98373->pm_init_once = true; 457 max98373->hw_init = true; 458 459 pm_runtime_mark_last_busy(dev); 460 pm_runtime_put_autosuspend(dev); 461 462 return 0; 463 } 464 465 static int max98373_clock_calculate(struct sdw_slave *slave, 466 unsigned int clk_freq) 467 { 468 int x, y; 469 static const int max98373_clk_family[] = { 470 7680000, 8400000, 9600000, 11289600, 471 12000000, 12288000, 13000000 472 }; 473 474 for (x = 0; x < 4; x++) 475 for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++) 476 if (clk_freq == (max98373_clk_family[y] >> x)) 477 return (x << 3) + y; 478 479 /* Set default clock (12.288 Mhz) if the value is not in the list */ 480 dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n", 481 clk_freq); 482 return 0x5; 483 } 484 485 static int max98373_clock_config(struct sdw_slave *slave, 486 struct sdw_bus_params *params) 487 { 488 struct device *dev = &slave->dev; 489 struct max98373_priv *max98373 = dev_get_drvdata(dev); 490 unsigned int clk_freq, value; 491 492 clk_freq = (params->curr_dr_freq >> 1); 493 494 /* 495 * Select the proper value for the register based on the 496 * requested clock. If the value is not in the list, 497 * use reasonable default - 12.288 Mhz 498 */ 499 value = max98373_clock_calculate(slave, clk_freq); 500 501 /* SWCLK */ 502 regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, value); 503 504 /* The default Sampling Rate value for IV is 48KHz*/ 505 regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88); 506 507 return 0; 508 } 509 510 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000 511 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) 512 513 static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream, 514 struct snd_pcm_hw_params *params, 515 struct snd_soc_dai *dai) 516 { 517 struct snd_soc_component *component = dai->component; 518 struct max98373_priv *max98373 = 519 snd_soc_component_get_drvdata(component); 520 521 struct sdw_stream_config stream_config; 522 struct sdw_port_config port_config; 523 enum sdw_data_direction direction; 524 struct sdw_stream_data *stream; 525 int ret, chan_sz, sampling_rate; 526 527 stream = snd_soc_dai_get_dma_data(dai, substream); 528 529 if (!stream) 530 return -EINVAL; 531 532 if (!max98373->slave) 533 return -EINVAL; 534 535 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 536 direction = SDW_DATA_DIR_RX; 537 port_config.num = 1; 538 } else { 539 direction = SDW_DATA_DIR_TX; 540 port_config.num = 3; 541 } 542 543 stream_config.frame_rate = params_rate(params); 544 stream_config.bps = snd_pcm_format_width(params_format(params)); 545 stream_config.direction = direction; 546 547 if (max98373->slot && direction == SDW_DATA_DIR_RX) { 548 stream_config.ch_count = max98373->slot; 549 port_config.ch_mask = max98373->rx_mask; 550 } else { 551 /* only IV are supported by capture */ 552 if (direction == SDW_DATA_DIR_TX) 553 stream_config.ch_count = 2; 554 else 555 stream_config.ch_count = params_channels(params); 556 557 port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0); 558 } 559 560 ret = sdw_stream_add_slave(max98373->slave, &stream_config, 561 &port_config, 1, stream->sdw_stream); 562 if (ret) { 563 dev_err(dai->dev, "Unable to configure port\n"); 564 return ret; 565 } 566 567 if (params_channels(params) > 16) { 568 dev_err(component->dev, "Unsupported channels %d\n", 569 params_channels(params)); 570 return -EINVAL; 571 } 572 573 /* Channel size configuration */ 574 switch (snd_pcm_format_width(params_format(params))) { 575 case 16: 576 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 577 break; 578 case 24: 579 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 580 break; 581 case 32: 582 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 583 break; 584 default: 585 dev_err(component->dev, "Channel size unsupported %d\n", 586 params_format(params)); 587 return -EINVAL; 588 } 589 590 max98373->ch_size = snd_pcm_format_width(params_format(params)); 591 592 regmap_update_bits(max98373->regmap, 593 MAX98373_R2024_PCM_DATA_FMT_CFG, 594 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 595 596 dev_dbg(component->dev, "Format supported %d", params_format(params)); 597 598 /* Sampling rate configuration */ 599 switch (params_rate(params)) { 600 case 8000: 601 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000; 602 break; 603 case 11025: 604 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025; 605 break; 606 case 12000: 607 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000; 608 break; 609 case 16000: 610 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000; 611 break; 612 case 22050: 613 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050; 614 break; 615 case 24000: 616 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000; 617 break; 618 case 32000: 619 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000; 620 break; 621 case 44100: 622 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100; 623 break; 624 case 48000: 625 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000; 626 break; 627 case 88200: 628 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200; 629 break; 630 case 96000: 631 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000; 632 break; 633 default: 634 dev_err(component->dev, "Rate %d is not supported\n", 635 params_rate(params)); 636 return -EINVAL; 637 } 638 639 /* set correct sampling frequency */ 640 regmap_update_bits(max98373->regmap, 641 MAX98373_R2028_PCM_SR_SETUP_2, 642 MAX98373_PCM_SR_SET2_SR_MASK, 643 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT); 644 645 /* set sampling rate of IV */ 646 regmap_update_bits(max98373->regmap, 647 MAX98373_R2028_PCM_SR_SETUP_2, 648 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 649 sampling_rate); 650 651 return 0; 652 } 653 654 static int max98373_pcm_hw_free(struct snd_pcm_substream *substream, 655 struct snd_soc_dai *dai) 656 { 657 struct snd_soc_component *component = dai->component; 658 struct max98373_priv *max98373 = 659 snd_soc_component_get_drvdata(component); 660 struct sdw_stream_data *stream = 661 snd_soc_dai_get_dma_data(dai, substream); 662 663 if (!max98373->slave) 664 return -EINVAL; 665 666 sdw_stream_remove_slave(max98373->slave, stream->sdw_stream); 667 return 0; 668 } 669 670 static int max98373_set_sdw_stream(struct snd_soc_dai *dai, 671 void *sdw_stream, int direction) 672 { 673 struct sdw_stream_data *stream; 674 675 if (!sdw_stream) 676 return 0; 677 678 stream = kzalloc(sizeof(*stream), GFP_KERNEL); 679 if (!stream) 680 return -ENOMEM; 681 682 stream->sdw_stream = sdw_stream; 683 684 /* Use tx_mask or rx_mask to configure stream tag and set dma_data */ 685 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 686 dai->playback_dma_data = stream; 687 else 688 dai->capture_dma_data = stream; 689 690 return 0; 691 } 692 693 static void max98373_shutdown(struct snd_pcm_substream *substream, 694 struct snd_soc_dai *dai) 695 { 696 struct sdw_stream_data *stream; 697 698 stream = snd_soc_dai_get_dma_data(dai, substream); 699 snd_soc_dai_set_dma_data(dai, substream, NULL); 700 kfree(stream); 701 } 702 703 static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai, 704 unsigned int tx_mask, 705 unsigned int rx_mask, 706 int slots, int slot_width) 707 { 708 struct snd_soc_component *component = dai->component; 709 struct max98373_priv *max98373 = 710 snd_soc_component_get_drvdata(component); 711 712 /* tx_mask is unused since it's irrelevant for I/V feedback */ 713 if (tx_mask) 714 return -EINVAL; 715 716 if (!rx_mask && !slots && !slot_width) 717 max98373->tdm_mode = false; 718 else 719 max98373->tdm_mode = true; 720 721 max98373->rx_mask = rx_mask; 722 max98373->slot = slots; 723 724 return 0; 725 } 726 727 static const struct snd_soc_dai_ops max98373_dai_sdw_ops = { 728 .hw_params = max98373_sdw_dai_hw_params, 729 .hw_free = max98373_pcm_hw_free, 730 .set_sdw_stream = max98373_set_sdw_stream, 731 .shutdown = max98373_shutdown, 732 .set_tdm_slot = max98373_sdw_set_tdm_slot, 733 }; 734 735 static struct snd_soc_dai_driver max98373_sdw_dai[] = { 736 { 737 .name = "max98373-aif1", 738 .playback = { 739 .stream_name = "HiFi Playback", 740 .channels_min = 1, 741 .channels_max = 2, 742 .rates = MAX98373_RATES, 743 .formats = MAX98373_FORMATS, 744 }, 745 .capture = { 746 .stream_name = "HiFi Capture", 747 .channels_min = 1, 748 .channels_max = 2, 749 .rates = MAX98373_RATES, 750 .formats = MAX98373_FORMATS, 751 }, 752 .ops = &max98373_dai_sdw_ops, 753 } 754 }; 755 756 static int max98373_init(struct sdw_slave *slave, struct regmap *regmap) 757 { 758 struct max98373_priv *max98373; 759 int ret; 760 struct device *dev = &slave->dev; 761 762 /* Allocate and assign private driver data structure */ 763 max98373 = devm_kzalloc(dev, sizeof(*max98373), GFP_KERNEL); 764 if (!max98373) 765 return -ENOMEM; 766 767 dev_set_drvdata(dev, max98373); 768 max98373->regmap = regmap; 769 max98373->slave = slave; 770 771 /* Read voltage and slot configuration */ 772 max98373_slot_config(dev, max98373); 773 774 max98373->hw_init = false; 775 max98373->pm_init_once = false; 776 777 /* codec registration */ 778 ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98373_sdw, 779 max98373_sdw_dai, 780 ARRAY_SIZE(max98373_sdw_dai)); 781 if (ret < 0) 782 dev_err(dev, "Failed to register codec: %d\n", ret); 783 784 return ret; 785 } 786 787 static int max98373_update_status(struct sdw_slave *slave, 788 enum sdw_slave_status status) 789 { 790 struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev); 791 792 if (status == SDW_SLAVE_UNATTACHED) 793 max98373->hw_init = false; 794 795 /* 796 * Perform initialization only if slave status is SDW_SLAVE_ATTACHED 797 */ 798 if (max98373->hw_init || status != SDW_SLAVE_ATTACHED) 799 return 0; 800 801 /* perform I/O transfers required for Slave initialization */ 802 return max98373_io_init(slave); 803 } 804 805 static int max98373_bus_config(struct sdw_slave *slave, 806 struct sdw_bus_params *params) 807 { 808 int ret; 809 810 ret = max98373_clock_config(slave, params); 811 if (ret < 0) 812 dev_err(&slave->dev, "Invalid clk config"); 813 814 return ret; 815 } 816 817 /* 818 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 819 * port_prep are not defined for now 820 */ 821 static struct sdw_slave_ops max98373_slave_ops = { 822 .read_prop = max98373_read_prop, 823 .update_status = max98373_update_status, 824 .bus_config = max98373_bus_config, 825 }; 826 827 static int max98373_sdw_probe(struct sdw_slave *slave, 828 const struct sdw_device_id *id) 829 { 830 struct regmap *regmap; 831 832 /* Regmap Initialization */ 833 regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap); 834 if (IS_ERR(regmap)) 835 return PTR_ERR(regmap); 836 837 return max98373_init(slave, regmap); 838 } 839 840 #if defined(CONFIG_OF) 841 static const struct of_device_id max98373_of_match[] = { 842 { .compatible = "maxim,max98373", }, 843 {}, 844 }; 845 MODULE_DEVICE_TABLE(of, max98373_of_match); 846 #endif 847 848 #ifdef CONFIG_ACPI 849 static const struct acpi_device_id max98373_acpi_match[] = { 850 { "MX98373", 0 }, 851 {}, 852 }; 853 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match); 854 #endif 855 856 static const struct sdw_device_id max98373_id[] = { 857 SDW_SLAVE_ENTRY(0x019F, 0x8373, 0), 858 {}, 859 }; 860 MODULE_DEVICE_TABLE(sdw, max98373_id); 861 862 static struct sdw_driver max98373_sdw_driver = { 863 .driver = { 864 .name = "max98373", 865 .owner = THIS_MODULE, 866 .of_match_table = of_match_ptr(max98373_of_match), 867 .acpi_match_table = ACPI_PTR(max98373_acpi_match), 868 .pm = &max98373_pm, 869 }, 870 .probe = max98373_sdw_probe, 871 .remove = NULL, 872 .ops = &max98373_slave_ops, 873 .id_table = max98373_id, 874 }; 875 876 module_sdw_driver(max98373_sdw_driver); 877 878 MODULE_DESCRIPTION("ASoC MAX98373 driver SDW"); 879 MODULE_AUTHOR("Oleg Sherbakov <oleg.sherbakov@maximintegrated.com>"); 880 MODULE_LICENSE("GPL v2"); 881