1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2020, Maxim Integrated 3 4 #include <linux/acpi.h> 5 #include <linux/delay.h> 6 #include <linux/module.h> 7 #include <linux/mod_devicetable.h> 8 #include <linux/pm_runtime.h> 9 #include <linux/regmap.h> 10 #include <linux/slab.h> 11 #include <sound/pcm.h> 12 #include <sound/pcm_params.h> 13 #include <sound/sdw.h> 14 #include <sound/soc.h> 15 #include <sound/tlv.h> 16 #include <linux/of.h> 17 #include <linux/soundwire/sdw.h> 18 #include <linux/soundwire/sdw_type.h> 19 #include <linux/soundwire/sdw_registers.h> 20 #include "max98373.h" 21 #include "max98373-sdw.h" 22 23 struct sdw_stream_data { 24 struct sdw_stream_runtime *sdw_stream; 25 }; 26 27 static const u32 max98373_sdw_cache_reg[] = { 28 MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 29 MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 30 MAX98373_R20B6_BDE_CUR_STATE_READBACK, 31 }; 32 33 static struct reg_default max98373_reg[] = { 34 {MAX98373_R0040_SCP_INIT_STAT_1, 0x00}, 35 {MAX98373_R0041_SCP_INIT_MASK_1, 0x00}, 36 {MAX98373_R0042_SCP_INIT_STAT_2, 0x00}, 37 {MAX98373_R0044_SCP_CTRL, 0x00}, 38 {MAX98373_R0045_SCP_SYSTEM_CTRL, 0x00}, 39 {MAX98373_R0046_SCP_DEV_NUMBER, 0x00}, 40 {MAX98373_R0050_SCP_DEV_ID_0, 0x21}, 41 {MAX98373_R0051_SCP_DEV_ID_1, 0x01}, 42 {MAX98373_R0052_SCP_DEV_ID_2, 0x9F}, 43 {MAX98373_R0053_SCP_DEV_ID_3, 0x87}, 44 {MAX98373_R0054_SCP_DEV_ID_4, 0x08}, 45 {MAX98373_R0055_SCP_DEV_ID_5, 0x00}, 46 {MAX98373_R0060_SCP_FRAME_CTLR, 0x00}, 47 {MAX98373_R0070_SCP_FRAME_CTLR, 0x00}, 48 {MAX98373_R0100_DP1_INIT_STAT, 0x00}, 49 {MAX98373_R0101_DP1_INIT_MASK, 0x00}, 50 {MAX98373_R0102_DP1_PORT_CTRL, 0x00}, 51 {MAX98373_R0103_DP1_BLOCK_CTRL_1, 0x00}, 52 {MAX98373_R0104_DP1_PREPARE_STATUS, 0x00}, 53 {MAX98373_R0105_DP1_PREPARE_CTRL, 0x00}, 54 {MAX98373_R0120_DP1_CHANNEL_EN, 0x00}, 55 {MAX98373_R0122_DP1_SAMPLE_CTRL1, 0x00}, 56 {MAX98373_R0123_DP1_SAMPLE_CTRL2, 0x00}, 57 {MAX98373_R0124_DP1_OFFSET_CTRL1, 0x00}, 58 {MAX98373_R0125_DP1_OFFSET_CTRL2, 0x00}, 59 {MAX98373_R0126_DP1_HCTRL, 0x00}, 60 {MAX98373_R0127_DP1_BLOCK_CTRL3, 0x00}, 61 {MAX98373_R0130_DP1_CHANNEL_EN, 0x00}, 62 {MAX98373_R0132_DP1_SAMPLE_CTRL1, 0x00}, 63 {MAX98373_R0133_DP1_SAMPLE_CTRL2, 0x00}, 64 {MAX98373_R0134_DP1_OFFSET_CTRL1, 0x00}, 65 {MAX98373_R0135_DP1_OFFSET_CTRL2, 0x00}, 66 {MAX98373_R0136_DP1_HCTRL, 0x0136}, 67 {MAX98373_R0137_DP1_BLOCK_CTRL3, 0x00}, 68 {MAX98373_R0300_DP3_INIT_STAT, 0x00}, 69 {MAX98373_R0301_DP3_INIT_MASK, 0x00}, 70 {MAX98373_R0302_DP3_PORT_CTRL, 0x00}, 71 {MAX98373_R0303_DP3_BLOCK_CTRL_1, 0x00}, 72 {MAX98373_R0304_DP3_PREPARE_STATUS, 0x00}, 73 {MAX98373_R0305_DP3_PREPARE_CTRL, 0x00}, 74 {MAX98373_R0320_DP3_CHANNEL_EN, 0x00}, 75 {MAX98373_R0322_DP3_SAMPLE_CTRL1, 0x00}, 76 {MAX98373_R0323_DP3_SAMPLE_CTRL2, 0x00}, 77 {MAX98373_R0324_DP3_OFFSET_CTRL1, 0x00}, 78 {MAX98373_R0325_DP3_OFFSET_CTRL2, 0x00}, 79 {MAX98373_R0326_DP3_HCTRL, 0x00}, 80 {MAX98373_R0327_DP3_BLOCK_CTRL3, 0x00}, 81 {MAX98373_R0330_DP3_CHANNEL_EN, 0x00}, 82 {MAX98373_R0332_DP3_SAMPLE_CTRL1, 0x00}, 83 {MAX98373_R0333_DP3_SAMPLE_CTRL2, 0x00}, 84 {MAX98373_R0334_DP3_OFFSET_CTRL1, 0x00}, 85 {MAX98373_R0335_DP3_OFFSET_CTRL2, 0x00}, 86 {MAX98373_R0336_DP3_HCTRL, 0x00}, 87 {MAX98373_R0337_DP3_BLOCK_CTRL3, 0x00}, 88 {MAX98373_R2000_SW_RESET, 0x00}, 89 {MAX98373_R2001_INT_RAW1, 0x00}, 90 {MAX98373_R2002_INT_RAW2, 0x00}, 91 {MAX98373_R2003_INT_RAW3, 0x00}, 92 {MAX98373_R2004_INT_STATE1, 0x00}, 93 {MAX98373_R2005_INT_STATE2, 0x00}, 94 {MAX98373_R2006_INT_STATE3, 0x00}, 95 {MAX98373_R2007_INT_FLAG1, 0x00}, 96 {MAX98373_R2008_INT_FLAG2, 0x00}, 97 {MAX98373_R2009_INT_FLAG3, 0x00}, 98 {MAX98373_R200A_INT_EN1, 0x00}, 99 {MAX98373_R200B_INT_EN2, 0x00}, 100 {MAX98373_R200C_INT_EN3, 0x00}, 101 {MAX98373_R200D_INT_FLAG_CLR1, 0x00}, 102 {MAX98373_R200E_INT_FLAG_CLR2, 0x00}, 103 {MAX98373_R200F_INT_FLAG_CLR3, 0x00}, 104 {MAX98373_R2010_IRQ_CTRL, 0x00}, 105 {MAX98373_R2014_THERM_WARN_THRESH, 0x10}, 106 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27}, 107 {MAX98373_R2016_THERM_HYSTERESIS, 0x01}, 108 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0}, 109 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00}, 110 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55}, 111 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE}, 112 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF}, 113 {MAX98373_R2022_PCM_TX_SRC_1, 0x00}, 114 {MAX98373_R2023_PCM_TX_SRC_2, 0x00}, 115 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0}, 116 {MAX98373_R2025_AUDIO_IF_MODE, 0x00}, 117 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04}, 118 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08}, 119 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88}, 120 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00}, 121 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00}, 122 {MAX98373_R202B_PCM_RX_EN, 0x00}, 123 {MAX98373_R202C_PCM_TX_EN, 0x00}, 124 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00}, 125 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00}, 126 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF}, 127 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF}, 128 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30}, 129 {MAX98373_R2034_ICC_TX_CNTL, 0x00}, 130 {MAX98373_R2035_ICC_TX_EN, 0x00}, 131 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05}, 132 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00}, 133 {MAX98373_R203E_AMP_PATH_GAIN, 0x08}, 134 {MAX98373_R203F_AMP_DSP_CFG, 0x02}, 135 {MAX98373_R2040_TONE_GEN_CFG, 0x00}, 136 {MAX98373_R2041_AMP_CFG, 0x03}, 137 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00}, 138 {MAX98373_R2043_AMP_EN, 0x00}, 139 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04}, 140 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00}, 141 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00}, 142 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00}, 143 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00}, 144 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00}, 145 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00}, 146 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00}, 147 {MAX98373_R2090_BDE_LVL_HOLD, 0x00}, 148 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00}, 149 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00}, 150 {MAX98373_R2097_BDE_L1_THRESH, 0x00}, 151 {MAX98373_R2098_BDE_L2_THRESH, 0x00}, 152 {MAX98373_R2099_BDE_L3_THRESH, 0x00}, 153 {MAX98373_R209A_BDE_L4_THRESH, 0x00}, 154 {MAX98373_R209B_BDE_THRESH_HYST, 0x00}, 155 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00}, 156 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00}, 157 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00}, 158 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00}, 159 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00}, 160 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00}, 161 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00}, 162 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00}, 163 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00}, 164 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00}, 165 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00}, 166 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00}, 167 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00}, 168 {MAX98373_R20B5_BDE_EN, 0x00}, 169 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00}, 170 {MAX98373_R20D1_DHT_CFG, 0x01}, 171 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02}, 172 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03}, 173 {MAX98373_R20D4_DHT_EN, 0x00}, 174 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00}, 175 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00}, 176 {MAX98373_R20E2_LIMITER_EN, 0x00}, 177 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00}, 178 {MAX98373_R20FF_GLOBAL_SHDN, 0x00}, 179 {MAX98373_R21FF_REV_ID, 0x42}, 180 }; 181 182 static bool max98373_readable_register(struct device *dev, unsigned int reg) 183 { 184 switch (reg) { 185 case MAX98373_R21FF_REV_ID: 186 case MAX98373_R2010_IRQ_CTRL: 187 /* SoundWire Control Port Registers */ 188 case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR: 189 /* Soundwire Data Port 1 Registers */ 190 case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3: 191 /* Soundwire Data Port 3 Registers */ 192 case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3: 193 case MAX98373_R2000_SW_RESET ... MAX98373_R200C_INT_EN3: 194 case MAX98373_R2014_THERM_WARN_THRESH 195 ... MAX98373_R2018_THERM_FOLDBACK_EN: 196 case MAX98373_R201E_PIN_DRIVE_STRENGTH 197 ... MAX98373_R2036_SOUNDWIRE_CTRL: 198 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN: 199 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 200 ... MAX98373_R2047_IV_SENSE_ADC_EN: 201 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 202 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN: 203 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE: 204 case MAX98373_R2097_BDE_L1_THRESH 205 ... MAX98373_R209B_BDE_THRESH_HYST: 206 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3: 207 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK: 208 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN: 209 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN: 210 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 211 ... MAX98373_R20FF_GLOBAL_SHDN: 212 return true; 213 default: 214 return false; 215 } 216 }; 217 218 static bool max98373_volatile_reg(struct device *dev, unsigned int reg) 219 { 220 switch (reg) { 221 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK: 222 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK: 223 case MAX98373_R20B6_BDE_CUR_STATE_READBACK: 224 case MAX98373_R20FF_GLOBAL_SHDN: 225 case MAX98373_R21FF_REV_ID: 226 /* SoundWire Control Port Registers */ 227 case MAX98373_R0040_SCP_INIT_STAT_1 ... MAX98373_R0070_SCP_FRAME_CTLR: 228 /* Soundwire Data Port 1 Registers */ 229 case MAX98373_R0100_DP1_INIT_STAT ... MAX98373_R0137_DP1_BLOCK_CTRL3: 230 /* Soundwire Data Port 3 Registers */ 231 case MAX98373_R0300_DP3_INIT_STAT ... MAX98373_R0337_DP3_BLOCK_CTRL3: 232 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3: 233 return true; 234 default: 235 return false; 236 } 237 } 238 239 static const struct regmap_config max98373_sdw_regmap = { 240 .reg_bits = 32, 241 .val_bits = 8, 242 .max_register = MAX98373_R21FF_REV_ID, 243 .reg_defaults = max98373_reg, 244 .num_reg_defaults = ARRAY_SIZE(max98373_reg), 245 .readable_reg = max98373_readable_register, 246 .volatile_reg = max98373_volatile_reg, 247 .cache_type = REGCACHE_RBTREE, 248 .use_single_read = true, 249 .use_single_write = true, 250 }; 251 252 /* Power management functions and structure */ 253 static __maybe_unused int max98373_suspend(struct device *dev) 254 { 255 struct max98373_priv *max98373 = dev_get_drvdata(dev); 256 int i; 257 258 /* cache feedback register values before suspend */ 259 for (i = 0; i < max98373->cache_num; i++) 260 regmap_read(max98373->regmap, max98373->cache[i].reg, &max98373->cache[i].val); 261 262 regcache_cache_only(max98373->regmap, true); 263 264 return 0; 265 } 266 267 #define MAX98373_PROBE_TIMEOUT 5000 268 269 static __maybe_unused int max98373_resume(struct device *dev) 270 { 271 struct sdw_slave *slave = dev_to_sdw_dev(dev); 272 struct max98373_priv *max98373 = dev_get_drvdata(dev); 273 unsigned long time; 274 275 if (!max98373->first_hw_init) 276 return 0; 277 278 if (!slave->unattach_request) 279 goto regmap_sync; 280 281 time = wait_for_completion_timeout(&slave->initialization_complete, 282 msecs_to_jiffies(MAX98373_PROBE_TIMEOUT)); 283 if (!time) { 284 dev_err(dev, "Initialization not complete, timed out\n"); 285 sdw_show_ping_status(slave->bus, true); 286 287 return -ETIMEDOUT; 288 } 289 290 regmap_sync: 291 slave->unattach_request = 0; 292 regcache_cache_only(max98373->regmap, false); 293 regcache_sync(max98373->regmap); 294 295 return 0; 296 } 297 298 static const struct dev_pm_ops max98373_pm = { 299 SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume) 300 SET_RUNTIME_PM_OPS(max98373_suspend, max98373_resume, NULL) 301 }; 302 303 static int max98373_read_prop(struct sdw_slave *slave) 304 { 305 struct sdw_slave_prop *prop = &slave->prop; 306 int nval, i; 307 u32 bit; 308 unsigned long addr; 309 struct sdw_dpn_prop *dpn; 310 311 prop->scp_int1_mask = SDW_SCP_INT1_BUS_CLASH | SDW_SCP_INT1_PARITY; 312 313 /* BITMAP: 00001000 Dataport 3 is active */ 314 prop->source_ports = BIT(3); 315 /* BITMAP: 00000010 Dataport 1 is active */ 316 prop->sink_ports = BIT(1); 317 prop->paging_support = true; 318 prop->clk_stop_timeout = 20; 319 320 nval = hweight32(prop->source_ports); 321 prop->src_dpn_prop = devm_kcalloc(&slave->dev, nval, 322 sizeof(*prop->src_dpn_prop), 323 GFP_KERNEL); 324 if (!prop->src_dpn_prop) 325 return -ENOMEM; 326 327 i = 0; 328 dpn = prop->src_dpn_prop; 329 addr = prop->source_ports; 330 for_each_set_bit(bit, &addr, 32) { 331 dpn[i].num = bit; 332 dpn[i].type = SDW_DPN_FULL; 333 dpn[i].simple_ch_prep_sm = true; 334 dpn[i].ch_prep_timeout = 10; 335 i++; 336 } 337 338 /* do this again for sink now */ 339 nval = hweight32(prop->sink_ports); 340 prop->sink_dpn_prop = devm_kcalloc(&slave->dev, nval, 341 sizeof(*prop->sink_dpn_prop), 342 GFP_KERNEL); 343 if (!prop->sink_dpn_prop) 344 return -ENOMEM; 345 346 i = 0; 347 dpn = prop->sink_dpn_prop; 348 addr = prop->sink_ports; 349 for_each_set_bit(bit, &addr, 32) { 350 dpn[i].num = bit; 351 dpn[i].type = SDW_DPN_FULL; 352 dpn[i].simple_ch_prep_sm = true; 353 dpn[i].ch_prep_timeout = 10; 354 i++; 355 } 356 357 /* set the timeout values */ 358 prop->clk_stop_timeout = 20; 359 360 return 0; 361 } 362 363 static int max98373_io_init(struct sdw_slave *slave) 364 { 365 struct device *dev = &slave->dev; 366 struct max98373_priv *max98373 = dev_get_drvdata(dev); 367 368 if (max98373->first_hw_init) { 369 regcache_cache_only(max98373->regmap, false); 370 regcache_cache_bypass(max98373->regmap, true); 371 } 372 373 /* 374 * PM runtime is only enabled when a Slave reports as Attached 375 */ 376 if (!max98373->first_hw_init) { 377 /* set autosuspend parameters */ 378 pm_runtime_set_autosuspend_delay(dev, 3000); 379 pm_runtime_use_autosuspend(dev); 380 381 /* update count of parent 'active' children */ 382 pm_runtime_set_active(dev); 383 384 /* make sure the device does not suspend immediately */ 385 pm_runtime_mark_last_busy(dev); 386 387 pm_runtime_enable(dev); 388 } 389 390 pm_runtime_get_noresume(dev); 391 392 /* Software Reset */ 393 max98373_reset(max98373, dev); 394 395 /* Set soundwire mode */ 396 regmap_write(max98373->regmap, MAX98373_R2025_AUDIO_IF_MODE, 3); 397 /* Enable ADC */ 398 regmap_write(max98373->regmap, MAX98373_R2047_IV_SENSE_ADC_EN, 3); 399 /* Set default Soundwire clock */ 400 regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, 5); 401 /* Set default sampling rate for speaker and IVDAC */ 402 regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88); 403 /* IV default slot configuration */ 404 regmap_write(max98373->regmap, 405 MAX98373_R2020_PCM_TX_HIZ_EN_1, 406 0xFF); 407 regmap_write(max98373->regmap, 408 MAX98373_R2021_PCM_TX_HIZ_EN_2, 409 0xFF); 410 /* L/R mix configuration */ 411 regmap_write(max98373->regmap, 412 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 413 0x80); 414 regmap_write(max98373->regmap, 415 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 416 0x1); 417 /* Enable DC blocker */ 418 regmap_write(max98373->regmap, 419 MAX98373_R203F_AMP_DSP_CFG, 420 0x3); 421 /* Enable IMON VMON DC blocker */ 422 regmap_write(max98373->regmap, 423 MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 424 0x7); 425 /* voltage, current slot configuration */ 426 regmap_write(max98373->regmap, 427 MAX98373_R2022_PCM_TX_SRC_1, 428 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT | 429 max98373->v_slot) & 0xFF); 430 if (max98373->v_slot < 8) 431 regmap_update_bits(max98373->regmap, 432 MAX98373_R2020_PCM_TX_HIZ_EN_1, 433 1 << max98373->v_slot, 0); 434 else 435 regmap_update_bits(max98373->regmap, 436 MAX98373_R2021_PCM_TX_HIZ_EN_2, 437 1 << (max98373->v_slot - 8), 0); 438 439 if (max98373->i_slot < 8) 440 regmap_update_bits(max98373->regmap, 441 MAX98373_R2020_PCM_TX_HIZ_EN_1, 442 1 << max98373->i_slot, 0); 443 else 444 regmap_update_bits(max98373->regmap, 445 MAX98373_R2021_PCM_TX_HIZ_EN_2, 446 1 << (max98373->i_slot - 8), 0); 447 448 /* speaker feedback slot configuration */ 449 regmap_write(max98373->regmap, 450 MAX98373_R2023_PCM_TX_SRC_2, 451 max98373->spkfb_slot & 0xFF); 452 453 /* Set interleave mode */ 454 if (max98373->interleave_mode) 455 regmap_update_bits(max98373->regmap, 456 MAX98373_R2024_PCM_DATA_FMT_CFG, 457 MAX98373_PCM_TX_CH_INTERLEAVE_MASK, 458 MAX98373_PCM_TX_CH_INTERLEAVE_MASK); 459 460 /* Speaker enable */ 461 regmap_update_bits(max98373->regmap, 462 MAX98373_R2043_AMP_EN, 463 MAX98373_SPK_EN_MASK, 1); 464 465 regmap_write(max98373->regmap, MAX98373_R20B5_BDE_EN, 1); 466 regmap_write(max98373->regmap, MAX98373_R20E2_LIMITER_EN, 1); 467 468 if (max98373->first_hw_init) { 469 regcache_cache_bypass(max98373->regmap, false); 470 regcache_mark_dirty(max98373->regmap); 471 } 472 473 max98373->first_hw_init = true; 474 max98373->hw_init = true; 475 476 pm_runtime_mark_last_busy(dev); 477 pm_runtime_put_autosuspend(dev); 478 479 return 0; 480 } 481 482 static int max98373_clock_calculate(struct sdw_slave *slave, 483 unsigned int clk_freq) 484 { 485 int x, y; 486 static const int max98373_clk_family[] = { 487 7680000, 8400000, 9600000, 11289600, 488 12000000, 12288000, 13000000 489 }; 490 491 for (x = 0; x < 4; x++) 492 for (y = 0; y < ARRAY_SIZE(max98373_clk_family); y++) 493 if (clk_freq == (max98373_clk_family[y] >> x)) 494 return (x << 3) + y; 495 496 /* Set default clock (12.288 Mhz) if the value is not in the list */ 497 dev_err(&slave->dev, "Requested clock not found. (clk_freq = %d)\n", 498 clk_freq); 499 return 0x5; 500 } 501 502 static int max98373_clock_config(struct sdw_slave *slave, 503 struct sdw_bus_params *params) 504 { 505 struct device *dev = &slave->dev; 506 struct max98373_priv *max98373 = dev_get_drvdata(dev); 507 unsigned int clk_freq, value; 508 509 clk_freq = (params->curr_dr_freq >> 1); 510 511 /* 512 * Select the proper value for the register based on the 513 * requested clock. If the value is not in the list, 514 * use reasonable default - 12.288 Mhz 515 */ 516 value = max98373_clock_calculate(slave, clk_freq); 517 518 /* SWCLK */ 519 regmap_write(max98373->regmap, MAX98373_R2036_SOUNDWIRE_CTRL, value); 520 521 /* The default Sampling Rate value for IV is 48KHz*/ 522 regmap_write(max98373->regmap, MAX98373_R2028_PCM_SR_SETUP_2, 0x88); 523 524 return 0; 525 } 526 527 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000 528 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S32_LE) 529 530 static int max98373_sdw_dai_hw_params(struct snd_pcm_substream *substream, 531 struct snd_pcm_hw_params *params, 532 struct snd_soc_dai *dai) 533 { 534 struct snd_soc_component *component = dai->component; 535 struct max98373_priv *max98373 = 536 snd_soc_component_get_drvdata(component); 537 struct sdw_stream_config stream_config = {0}; 538 struct sdw_port_config port_config = {0}; 539 struct sdw_stream_data *stream; 540 int ret, chan_sz, sampling_rate; 541 542 stream = snd_soc_dai_get_dma_data(dai, substream); 543 544 if (!stream) 545 return -EINVAL; 546 547 if (!max98373->slave) 548 return -EINVAL; 549 550 snd_sdw_params_to_config(substream, params, &stream_config, &port_config); 551 552 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 553 port_config.num = 1; 554 555 if (max98373->slot) { 556 stream_config.ch_count = max98373->slot; 557 port_config.ch_mask = max98373->rx_mask; 558 } 559 } else { 560 port_config.num = 3; 561 562 /* only IV are supported by capture */ 563 stream_config.ch_count = 2; 564 port_config.ch_mask = GENMASK((int)stream_config.ch_count - 1, 0); 565 } 566 567 ret = sdw_stream_add_slave(max98373->slave, &stream_config, 568 &port_config, 1, stream->sdw_stream); 569 if (ret) { 570 dev_err(dai->dev, "Unable to configure port\n"); 571 return ret; 572 } 573 574 if (params_channels(params) > 16) { 575 dev_err(component->dev, "Unsupported channels %d\n", 576 params_channels(params)); 577 return -EINVAL; 578 } 579 580 /* Channel size configuration */ 581 switch (snd_pcm_format_width(params_format(params))) { 582 case 16: 583 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 584 break; 585 case 24: 586 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 587 break; 588 case 32: 589 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 590 break; 591 default: 592 dev_err(component->dev, "Channel size unsupported %d\n", 593 params_format(params)); 594 return -EINVAL; 595 } 596 597 max98373->ch_size = snd_pcm_format_width(params_format(params)); 598 599 regmap_update_bits(max98373->regmap, 600 MAX98373_R2024_PCM_DATA_FMT_CFG, 601 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 602 603 dev_dbg(component->dev, "Format supported %d", params_format(params)); 604 605 /* Sampling rate configuration */ 606 switch (params_rate(params)) { 607 case 8000: 608 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000; 609 break; 610 case 11025: 611 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025; 612 break; 613 case 12000: 614 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000; 615 break; 616 case 16000: 617 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000; 618 break; 619 case 22050: 620 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050; 621 break; 622 case 24000: 623 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000; 624 break; 625 case 32000: 626 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000; 627 break; 628 case 44100: 629 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100; 630 break; 631 case 48000: 632 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000; 633 break; 634 case 88200: 635 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200; 636 break; 637 case 96000: 638 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000; 639 break; 640 default: 641 dev_err(component->dev, "Rate %d is not supported\n", 642 params_rate(params)); 643 return -EINVAL; 644 } 645 646 /* set correct sampling frequency */ 647 regmap_update_bits(max98373->regmap, 648 MAX98373_R2028_PCM_SR_SETUP_2, 649 MAX98373_PCM_SR_SET2_SR_MASK, 650 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT); 651 652 /* set sampling rate of IV */ 653 regmap_update_bits(max98373->regmap, 654 MAX98373_R2028_PCM_SR_SETUP_2, 655 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 656 sampling_rate); 657 658 return 0; 659 } 660 661 static int max98373_pcm_hw_free(struct snd_pcm_substream *substream, 662 struct snd_soc_dai *dai) 663 { 664 struct snd_soc_component *component = dai->component; 665 struct max98373_priv *max98373 = 666 snd_soc_component_get_drvdata(component); 667 struct sdw_stream_data *stream = 668 snd_soc_dai_get_dma_data(dai, substream); 669 670 if (!max98373->slave) 671 return -EINVAL; 672 673 sdw_stream_remove_slave(max98373->slave, stream->sdw_stream); 674 return 0; 675 } 676 677 static int max98373_set_sdw_stream(struct snd_soc_dai *dai, 678 void *sdw_stream, int direction) 679 { 680 struct sdw_stream_data *stream; 681 682 if (!sdw_stream) 683 return 0; 684 685 stream = kzalloc(sizeof(*stream), GFP_KERNEL); 686 if (!stream) 687 return -ENOMEM; 688 689 stream->sdw_stream = sdw_stream; 690 691 /* Use tx_mask or rx_mask to configure stream tag and set dma_data */ 692 snd_soc_dai_dma_data_set(dai, direction, stream); 693 694 return 0; 695 } 696 697 static void max98373_shutdown(struct snd_pcm_substream *substream, 698 struct snd_soc_dai *dai) 699 { 700 struct sdw_stream_data *stream; 701 702 stream = snd_soc_dai_get_dma_data(dai, substream); 703 snd_soc_dai_set_dma_data(dai, substream, NULL); 704 kfree(stream); 705 } 706 707 static int max98373_sdw_set_tdm_slot(struct snd_soc_dai *dai, 708 unsigned int tx_mask, 709 unsigned int rx_mask, 710 int slots, int slot_width) 711 { 712 struct snd_soc_component *component = dai->component; 713 struct max98373_priv *max98373 = 714 snd_soc_component_get_drvdata(component); 715 716 /* tx_mask is unused since it's irrelevant for I/V feedback */ 717 if (tx_mask) 718 return -EINVAL; 719 720 if (!rx_mask && !slots && !slot_width) 721 max98373->tdm_mode = false; 722 else 723 max98373->tdm_mode = true; 724 725 max98373->rx_mask = rx_mask; 726 max98373->slot = slots; 727 728 return 0; 729 } 730 731 static const struct snd_soc_dai_ops max98373_dai_sdw_ops = { 732 .hw_params = max98373_sdw_dai_hw_params, 733 .hw_free = max98373_pcm_hw_free, 734 .set_stream = max98373_set_sdw_stream, 735 .shutdown = max98373_shutdown, 736 .set_tdm_slot = max98373_sdw_set_tdm_slot, 737 }; 738 739 static struct snd_soc_dai_driver max98373_sdw_dai[] = { 740 { 741 .name = "max98373-aif1", 742 .playback = { 743 .stream_name = "HiFi Playback", 744 .channels_min = 1, 745 .channels_max = 2, 746 .rates = MAX98373_RATES, 747 .formats = MAX98373_FORMATS, 748 }, 749 .capture = { 750 .stream_name = "HiFi Capture", 751 .channels_min = 1, 752 .channels_max = 2, 753 .rates = MAX98373_RATES, 754 .formats = MAX98373_FORMATS, 755 }, 756 .ops = &max98373_dai_sdw_ops, 757 } 758 }; 759 760 static int max98373_init(struct sdw_slave *slave, struct regmap *regmap) 761 { 762 struct max98373_priv *max98373; 763 int ret; 764 int i; 765 struct device *dev = &slave->dev; 766 767 /* Allocate and assign private driver data structure */ 768 max98373 = devm_kzalloc(dev, sizeof(*max98373), GFP_KERNEL); 769 if (!max98373) 770 return -ENOMEM; 771 772 dev_set_drvdata(dev, max98373); 773 max98373->regmap = regmap; 774 max98373->slave = slave; 775 776 max98373->cache_num = ARRAY_SIZE(max98373_sdw_cache_reg); 777 max98373->cache = devm_kcalloc(dev, max98373->cache_num, 778 sizeof(*max98373->cache), 779 GFP_KERNEL); 780 if (!max98373->cache) 781 return -ENOMEM; 782 783 for (i = 0; i < max98373->cache_num; i++) 784 max98373->cache[i].reg = max98373_sdw_cache_reg[i]; 785 786 /* Read voltage and slot configuration */ 787 max98373_slot_config(dev, max98373); 788 789 max98373->hw_init = false; 790 max98373->first_hw_init = false; 791 792 /* codec registration */ 793 ret = devm_snd_soc_register_component(dev, &soc_codec_dev_max98373_sdw, 794 max98373_sdw_dai, 795 ARRAY_SIZE(max98373_sdw_dai)); 796 if (ret < 0) 797 dev_err(dev, "Failed to register codec: %d\n", ret); 798 799 return ret; 800 } 801 802 static int max98373_update_status(struct sdw_slave *slave, 803 enum sdw_slave_status status) 804 { 805 struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev); 806 807 if (status == SDW_SLAVE_UNATTACHED) 808 max98373->hw_init = false; 809 810 /* 811 * Perform initialization only if slave status is SDW_SLAVE_ATTACHED 812 */ 813 if (max98373->hw_init || status != SDW_SLAVE_ATTACHED) 814 return 0; 815 816 /* perform I/O transfers required for Slave initialization */ 817 return max98373_io_init(slave); 818 } 819 820 static int max98373_bus_config(struct sdw_slave *slave, 821 struct sdw_bus_params *params) 822 { 823 int ret; 824 825 ret = max98373_clock_config(slave, params); 826 if (ret < 0) 827 dev_err(&slave->dev, "Invalid clk config"); 828 829 return ret; 830 } 831 832 /* 833 * slave_ops: callbacks for get_clock_stop_mode, clock_stop and 834 * port_prep are not defined for now 835 */ 836 static struct sdw_slave_ops max98373_slave_ops = { 837 .read_prop = max98373_read_prop, 838 .update_status = max98373_update_status, 839 .bus_config = max98373_bus_config, 840 }; 841 842 static int max98373_sdw_probe(struct sdw_slave *slave, 843 const struct sdw_device_id *id) 844 { 845 struct regmap *regmap; 846 847 /* Regmap Initialization */ 848 regmap = devm_regmap_init_sdw(slave, &max98373_sdw_regmap); 849 if (IS_ERR(regmap)) 850 return PTR_ERR(regmap); 851 852 return max98373_init(slave, regmap); 853 } 854 855 static int max98373_sdw_remove(struct sdw_slave *slave) 856 { 857 struct max98373_priv *max98373 = dev_get_drvdata(&slave->dev); 858 859 if (max98373->first_hw_init) 860 pm_runtime_disable(&slave->dev); 861 862 return 0; 863 } 864 865 #if defined(CONFIG_OF) 866 static const struct of_device_id max98373_of_match[] = { 867 { .compatible = "maxim,max98373", }, 868 {}, 869 }; 870 MODULE_DEVICE_TABLE(of, max98373_of_match); 871 #endif 872 873 #ifdef CONFIG_ACPI 874 static const struct acpi_device_id max98373_acpi_match[] = { 875 { "MX98373", 0 }, 876 {}, 877 }; 878 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match); 879 #endif 880 881 static const struct sdw_device_id max98373_id[] = { 882 SDW_SLAVE_ENTRY(0x019F, 0x8373, 0), 883 {}, 884 }; 885 MODULE_DEVICE_TABLE(sdw, max98373_id); 886 887 static struct sdw_driver max98373_sdw_driver = { 888 .driver = { 889 .name = "max98373", 890 .owner = THIS_MODULE, 891 .of_match_table = of_match_ptr(max98373_of_match), 892 .acpi_match_table = ACPI_PTR(max98373_acpi_match), 893 .pm = &max98373_pm, 894 }, 895 .probe = max98373_sdw_probe, 896 .remove = max98373_sdw_remove, 897 .ops = &max98373_slave_ops, 898 .id_table = max98373_id, 899 }; 900 901 module_sdw_driver(max98373_sdw_driver); 902 903 MODULE_DESCRIPTION("ASoC MAX98373 driver SDW"); 904 MODULE_AUTHOR("Oleg Sherbakov <oleg.sherbakov@maximintegrated.com>"); 905 MODULE_LICENSE("GPL v2"); 906