1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017, Maxim Integrated 3 4 #include <linux/acpi.h> 5 #include <linux/delay.h> 6 #include <linux/gpio.h> 7 #include <linux/i2c.h> 8 #include <linux/module.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/of.h> 11 #include <linux/of_gpio.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/slab.h> 15 #include <linux/cdev.h> 16 #include <sound/pcm.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc.h> 19 #include <sound/tlv.h> 20 #include "max98373.h" 21 22 static struct reg_default max98373_reg[] = { 23 {MAX98373_R2000_SW_RESET, 0x00}, 24 {MAX98373_R2001_INT_RAW1, 0x00}, 25 {MAX98373_R2002_INT_RAW2, 0x00}, 26 {MAX98373_R2003_INT_RAW3, 0x00}, 27 {MAX98373_R2004_INT_STATE1, 0x00}, 28 {MAX98373_R2005_INT_STATE2, 0x00}, 29 {MAX98373_R2006_INT_STATE3, 0x00}, 30 {MAX98373_R2007_INT_FLAG1, 0x00}, 31 {MAX98373_R2008_INT_FLAG2, 0x00}, 32 {MAX98373_R2009_INT_FLAG3, 0x00}, 33 {MAX98373_R200A_INT_EN1, 0x00}, 34 {MAX98373_R200B_INT_EN2, 0x00}, 35 {MAX98373_R200C_INT_EN3, 0x00}, 36 {MAX98373_R200D_INT_FLAG_CLR1, 0x00}, 37 {MAX98373_R200E_INT_FLAG_CLR2, 0x00}, 38 {MAX98373_R200F_INT_FLAG_CLR3, 0x00}, 39 {MAX98373_R2010_IRQ_CTRL, 0x00}, 40 {MAX98373_R2014_THERM_WARN_THRESH, 0x10}, 41 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27}, 42 {MAX98373_R2016_THERM_HYSTERESIS, 0x01}, 43 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0}, 44 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00}, 45 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55}, 46 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE}, 47 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF}, 48 {MAX98373_R2022_PCM_TX_SRC_1, 0x00}, 49 {MAX98373_R2023_PCM_TX_SRC_2, 0x00}, 50 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0}, 51 {MAX98373_R2025_AUDIO_IF_MODE, 0x00}, 52 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04}, 53 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08}, 54 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88}, 55 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00}, 56 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00}, 57 {MAX98373_R202B_PCM_RX_EN, 0x00}, 58 {MAX98373_R202C_PCM_TX_EN, 0x00}, 59 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00}, 60 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00}, 61 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF}, 62 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF}, 63 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30}, 64 {MAX98373_R2034_ICC_TX_CNTL, 0x00}, 65 {MAX98373_R2035_ICC_TX_EN, 0x00}, 66 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05}, 67 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00}, 68 {MAX98373_R203E_AMP_PATH_GAIN, 0x08}, 69 {MAX98373_R203F_AMP_DSP_CFG, 0x02}, 70 {MAX98373_R2040_TONE_GEN_CFG, 0x00}, 71 {MAX98373_R2041_AMP_CFG, 0x03}, 72 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00}, 73 {MAX98373_R2043_AMP_EN, 0x00}, 74 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04}, 75 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00}, 76 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00}, 77 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00}, 78 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00}, 79 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00}, 80 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00}, 81 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00}, 82 {MAX98373_R2090_BDE_LVL_HOLD, 0x00}, 83 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00}, 84 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00}, 85 {MAX98373_R2097_BDE_L1_THRESH, 0x00}, 86 {MAX98373_R2098_BDE_L2_THRESH, 0x00}, 87 {MAX98373_R2099_BDE_L3_THRESH, 0x00}, 88 {MAX98373_R209A_BDE_L4_THRESH, 0x00}, 89 {MAX98373_R209B_BDE_THRESH_HYST, 0x00}, 90 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00}, 91 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00}, 92 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00}, 93 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00}, 94 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00}, 95 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00}, 96 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00}, 97 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00}, 98 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00}, 99 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00}, 100 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00}, 101 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00}, 102 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00}, 103 {MAX98373_R20B5_BDE_EN, 0x00}, 104 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00}, 105 {MAX98373_R20D1_DHT_CFG, 0x01}, 106 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02}, 107 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03}, 108 {MAX98373_R20D4_DHT_EN, 0x00}, 109 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00}, 110 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00}, 111 {MAX98373_R20E2_LIMITER_EN, 0x00}, 112 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00}, 113 {MAX98373_R20FF_GLOBAL_SHDN, 0x00}, 114 {MAX98373_R21FF_REV_ID, 0x42}, 115 }; 116 117 static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 118 { 119 struct snd_soc_component *component = codec_dai->component; 120 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 121 unsigned int format = 0; 122 unsigned int invert = 0; 123 124 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt); 125 126 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 127 case SND_SOC_DAIFMT_NB_NF: 128 break; 129 case SND_SOC_DAIFMT_IB_NF: 130 invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE; 131 break; 132 default: 133 dev_err(component->dev, "DAI invert mode unsupported\n"); 134 return -EINVAL; 135 } 136 137 regmap_update_bits(max98373->regmap, 138 MAX98373_R2026_PCM_CLOCK_RATIO, 139 MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE, 140 invert); 141 142 /* interface format */ 143 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 144 case SND_SOC_DAIFMT_I2S: 145 format = MAX98373_PCM_FORMAT_I2S; 146 break; 147 case SND_SOC_DAIFMT_LEFT_J: 148 format = MAX98373_PCM_FORMAT_LJ; 149 break; 150 case SND_SOC_DAIFMT_DSP_A: 151 format = MAX98373_PCM_FORMAT_TDM_MODE1; 152 break; 153 case SND_SOC_DAIFMT_DSP_B: 154 format = MAX98373_PCM_FORMAT_TDM_MODE0; 155 break; 156 default: 157 return -EINVAL; 158 } 159 160 regmap_update_bits(max98373->regmap, 161 MAX98373_R2024_PCM_DATA_FMT_CFG, 162 MAX98373_PCM_MODE_CFG_FORMAT_MASK, 163 format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT); 164 165 return 0; 166 } 167 168 /* BCLKs per LRCLK */ 169 static const int bclk_sel_table[] = { 170 32, 48, 64, 96, 128, 192, 256, 384, 512, 320, 171 }; 172 173 static int max98373_get_bclk_sel(int bclk) 174 { 175 int i; 176 /* match BCLKs per LRCLK */ 177 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) { 178 if (bclk_sel_table[i] == bclk) 179 return i + 2; 180 } 181 return 0; 182 } 183 184 static int max98373_set_clock(struct snd_soc_component *component, 185 struct snd_pcm_hw_params *params) 186 { 187 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 188 /* BCLK/LRCLK ratio calculation */ 189 int blr_clk_ratio = params_channels(params) * max98373->ch_size; 190 int value; 191 192 if (!max98373->tdm_mode) { 193 /* BCLK configuration */ 194 value = max98373_get_bclk_sel(blr_clk_ratio); 195 if (!value) { 196 dev_err(component->dev, "format unsupported %d\n", 197 params_format(params)); 198 return -EINVAL; 199 } 200 201 regmap_update_bits(max98373->regmap, 202 MAX98373_R2026_PCM_CLOCK_RATIO, 203 MAX98373_PCM_CLK_SETUP_BSEL_MASK, 204 value); 205 } 206 return 0; 207 } 208 209 static int max98373_dai_hw_params(struct snd_pcm_substream *substream, 210 struct snd_pcm_hw_params *params, 211 struct snd_soc_dai *dai) 212 { 213 struct snd_soc_component *component = dai->component; 214 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 215 unsigned int sampling_rate = 0; 216 unsigned int chan_sz = 0; 217 218 /* pcm mode configuration */ 219 switch (snd_pcm_format_width(params_format(params))) { 220 case 16: 221 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 222 break; 223 case 24: 224 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 225 break; 226 case 32: 227 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 228 break; 229 default: 230 dev_err(component->dev, "format unsupported %d\n", 231 params_format(params)); 232 goto err; 233 } 234 235 max98373->ch_size = snd_pcm_format_width(params_format(params)); 236 237 regmap_update_bits(max98373->regmap, 238 MAX98373_R2024_PCM_DATA_FMT_CFG, 239 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 240 241 dev_dbg(component->dev, "format supported %d", 242 params_format(params)); 243 244 /* sampling rate configuration */ 245 switch (params_rate(params)) { 246 case 8000: 247 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000; 248 break; 249 case 11025: 250 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025; 251 break; 252 case 12000: 253 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000; 254 break; 255 case 16000: 256 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000; 257 break; 258 case 22050: 259 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050; 260 break; 261 case 24000: 262 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000; 263 break; 264 case 32000: 265 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000; 266 break; 267 case 44100: 268 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100; 269 break; 270 case 48000: 271 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000; 272 break; 273 case 88200: 274 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200; 275 break; 276 case 96000: 277 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000; 278 break; 279 default: 280 dev_err(component->dev, "rate %d not supported\n", 281 params_rate(params)); 282 goto err; 283 } 284 285 /* set DAI_SR to correct LRCLK frequency */ 286 regmap_update_bits(max98373->regmap, 287 MAX98373_R2027_PCM_SR_SETUP_1, 288 MAX98373_PCM_SR_SET1_SR_MASK, 289 sampling_rate); 290 regmap_update_bits(max98373->regmap, 291 MAX98373_R2028_PCM_SR_SETUP_2, 292 MAX98373_PCM_SR_SET2_SR_MASK, 293 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT); 294 295 /* set sampling rate of IV */ 296 if (max98373->interleave_mode && 297 sampling_rate > MAX98373_PCM_SR_SET1_SR_16000) 298 regmap_update_bits(max98373->regmap, 299 MAX98373_R2028_PCM_SR_SETUP_2, 300 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 301 sampling_rate - 3); 302 else 303 regmap_update_bits(max98373->regmap, 304 MAX98373_R2028_PCM_SR_SETUP_2, 305 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 306 sampling_rate); 307 308 return max98373_set_clock(component, params); 309 err: 310 return -EINVAL; 311 } 312 313 static int max98373_dai_tdm_slot(struct snd_soc_dai *dai, 314 unsigned int tx_mask, unsigned int rx_mask, 315 int slots, int slot_width) 316 { 317 struct snd_soc_component *component = dai->component; 318 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 319 int bsel = 0; 320 unsigned int chan_sz = 0; 321 unsigned int mask; 322 int x, slot_found; 323 324 if (!tx_mask && !rx_mask && !slots && !slot_width) 325 max98373->tdm_mode = false; 326 else 327 max98373->tdm_mode = true; 328 329 /* BCLK configuration */ 330 bsel = max98373_get_bclk_sel(slots * slot_width); 331 if (bsel == 0) { 332 dev_err(component->dev, "BCLK %d not supported\n", 333 slots * slot_width); 334 return -EINVAL; 335 } 336 337 regmap_update_bits(max98373->regmap, 338 MAX98373_R2026_PCM_CLOCK_RATIO, 339 MAX98373_PCM_CLK_SETUP_BSEL_MASK, 340 bsel); 341 342 /* Channel size configuration */ 343 switch (slot_width) { 344 case 16: 345 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 346 break; 347 case 24: 348 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 349 break; 350 case 32: 351 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 352 break; 353 default: 354 dev_err(component->dev, "format unsupported %d\n", 355 slot_width); 356 return -EINVAL; 357 } 358 359 regmap_update_bits(max98373->regmap, 360 MAX98373_R2024_PCM_DATA_FMT_CFG, 361 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 362 363 /* Rx slot configuration */ 364 slot_found = 0; 365 mask = rx_mask; 366 for (x = 0 ; x < 16 ; x++, mask >>= 1) { 367 if (mask & 0x1) { 368 if (slot_found == 0) 369 regmap_update_bits(max98373->regmap, 370 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 371 MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x); 372 else 373 regmap_write(max98373->regmap, 374 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 375 x); 376 slot_found++; 377 if (slot_found > 1) 378 break; 379 } 380 } 381 382 /* Tx slot Hi-Z configuration */ 383 regmap_write(max98373->regmap, 384 MAX98373_R2020_PCM_TX_HIZ_EN_1, 385 ~tx_mask & 0xFF); 386 regmap_write(max98373->regmap, 387 MAX98373_R2021_PCM_TX_HIZ_EN_2, 388 (~tx_mask & 0xFF00) >> 8); 389 390 return 0; 391 } 392 393 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000 394 395 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 396 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 397 398 static const struct snd_soc_dai_ops max98373_dai_ops = { 399 .set_fmt = max98373_dai_set_fmt, 400 .hw_params = max98373_dai_hw_params, 401 .set_tdm_slot = max98373_dai_tdm_slot, 402 }; 403 404 static bool max98373_readable_register(struct device *dev, unsigned int reg) 405 { 406 switch (reg) { 407 case MAX98373_R2000_SW_RESET: 408 case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3: 409 case MAX98373_R2010_IRQ_CTRL: 410 case MAX98373_R2014_THERM_WARN_THRESH 411 ... MAX98373_R2018_THERM_FOLDBACK_EN: 412 case MAX98373_R201E_PIN_DRIVE_STRENGTH 413 ... MAX98373_R2036_SOUNDWIRE_CTRL: 414 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN: 415 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 416 ... MAX98373_R2047_IV_SENSE_ADC_EN: 417 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 418 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN: 419 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE: 420 case MAX98373_R2097_BDE_L1_THRESH 421 ... MAX98373_R209B_BDE_THRESH_HYST: 422 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3: 423 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK: 424 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN: 425 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN: 426 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 427 ... MAX98373_R20FF_GLOBAL_SHDN: 428 case MAX98373_R21FF_REV_ID: 429 return true; 430 default: 431 return false; 432 } 433 }; 434 435 static bool max98373_volatile_reg(struct device *dev, unsigned int reg) 436 { 437 switch (reg) { 438 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3: 439 case MAX98373_R203E_AMP_PATH_GAIN: 440 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK: 441 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK: 442 case MAX98373_R20B6_BDE_CUR_STATE_READBACK: 443 case MAX98373_R21FF_REV_ID: 444 return true; 445 default: 446 return false; 447 } 448 } 449 450 static struct snd_soc_dai_driver max98373_dai[] = { 451 { 452 .name = "max98373-aif1", 453 .playback = { 454 .stream_name = "HiFi Playback", 455 .channels_min = 1, 456 .channels_max = 2, 457 .rates = MAX98373_RATES, 458 .formats = MAX98373_FORMATS, 459 }, 460 .capture = { 461 .stream_name = "HiFi Capture", 462 .channels_min = 1, 463 .channels_max = 2, 464 .rates = MAX98373_RATES, 465 .formats = MAX98373_FORMATS, 466 }, 467 .ops = &max98373_dai_ops, 468 } 469 }; 470 471 #ifdef CONFIG_PM_SLEEP 472 static int max98373_suspend(struct device *dev) 473 { 474 struct max98373_priv *max98373 = dev_get_drvdata(dev); 475 476 regcache_cache_only(max98373->regmap, true); 477 regcache_mark_dirty(max98373->regmap); 478 return 0; 479 } 480 481 static int max98373_resume(struct device *dev) 482 { 483 struct max98373_priv *max98373 = dev_get_drvdata(dev); 484 485 regcache_cache_only(max98373->regmap, false); 486 max98373_reset(max98373, dev); 487 regcache_sync(max98373->regmap); 488 return 0; 489 } 490 #endif 491 492 static const struct dev_pm_ops max98373_pm = { 493 SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume) 494 }; 495 496 static const struct regmap_config max98373_regmap = { 497 .reg_bits = 16, 498 .val_bits = 8, 499 .max_register = MAX98373_R21FF_REV_ID, 500 .reg_defaults = max98373_reg, 501 .num_reg_defaults = ARRAY_SIZE(max98373_reg), 502 .readable_reg = max98373_readable_register, 503 .volatile_reg = max98373_volatile_reg, 504 .cache_type = REGCACHE_RBTREE, 505 }; 506 507 static int max98373_i2c_probe(struct i2c_client *i2c, 508 const struct i2c_device_id *id) 509 { 510 int ret = 0; 511 int reg = 0; 512 struct max98373_priv *max98373 = NULL; 513 514 max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL); 515 516 if (!max98373) { 517 ret = -ENOMEM; 518 return ret; 519 } 520 i2c_set_clientdata(i2c, max98373); 521 522 /* update interleave mode info */ 523 if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode")) 524 max98373->interleave_mode = true; 525 else 526 max98373->interleave_mode = false; 527 528 /* regmap initialization */ 529 max98373->regmap = devm_regmap_init_i2c(i2c, &max98373_regmap); 530 if (IS_ERR(max98373->regmap)) { 531 ret = PTR_ERR(max98373->regmap); 532 dev_err(&i2c->dev, 533 "Failed to allocate regmap: %d\n", ret); 534 return ret; 535 } 536 537 /* voltage/current slot & gpio configuration */ 538 max98373_slot_config(&i2c->dev, max98373); 539 540 /* Power on device */ 541 if (gpio_is_valid(max98373->reset_gpio)) { 542 ret = devm_gpio_request(&i2c->dev, max98373->reset_gpio, 543 "MAX98373_RESET"); 544 if (ret) { 545 dev_err(&i2c->dev, "%s: Failed to request gpio %d\n", 546 __func__, max98373->reset_gpio); 547 return -EINVAL; 548 } 549 gpio_direction_output(max98373->reset_gpio, 0); 550 msleep(50); 551 gpio_direction_output(max98373->reset_gpio, 1); 552 msleep(20); 553 } 554 555 /* Check Revision ID */ 556 ret = regmap_read(max98373->regmap, 557 MAX98373_R21FF_REV_ID, ®); 558 if (ret < 0) { 559 dev_err(&i2c->dev, 560 "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID); 561 return ret; 562 } 563 dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg); 564 565 /* codec registration */ 566 ret = devm_snd_soc_register_component(&i2c->dev, &soc_codec_dev_max98373, 567 max98373_dai, ARRAY_SIZE(max98373_dai)); 568 if (ret < 0) 569 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 570 571 return ret; 572 } 573 574 static const struct i2c_device_id max98373_i2c_id[] = { 575 { "max98373", 0}, 576 { }, 577 }; 578 579 MODULE_DEVICE_TABLE(i2c, max98373_i2c_id); 580 581 #if defined(CONFIG_OF) 582 static const struct of_device_id max98373_of_match[] = { 583 { .compatible = "maxim,max98373", }, 584 { } 585 }; 586 MODULE_DEVICE_TABLE(of, max98373_of_match); 587 #endif 588 589 #ifdef CONFIG_ACPI 590 static const struct acpi_device_id max98373_acpi_match[] = { 591 { "MX98373", 0 }, 592 {}, 593 }; 594 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match); 595 #endif 596 597 static struct i2c_driver max98373_i2c_driver = { 598 .driver = { 599 .name = "max98373", 600 .of_match_table = of_match_ptr(max98373_of_match), 601 .acpi_match_table = ACPI_PTR(max98373_acpi_match), 602 .pm = &max98373_pm, 603 }, 604 .probe = max98373_i2c_probe, 605 .id_table = max98373_i2c_id, 606 }; 607 608 module_i2c_driver(max98373_i2c_driver) 609 610 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver"); 611 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>"); 612 MODULE_LICENSE("GPL"); 613