1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2017, Maxim Integrated 3 4 #include <linux/acpi.h> 5 #include <linux/delay.h> 6 #include <linux/gpio.h> 7 #include <linux/i2c.h> 8 #include <linux/module.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/of.h> 11 #include <linux/of_gpio.h> 12 #include <linux/pm.h> 13 #include <linux/regmap.h> 14 #include <linux/slab.h> 15 #include <linux/cdev.h> 16 #include <sound/pcm.h> 17 #include <sound/pcm_params.h> 18 #include <sound/soc.h> 19 #include <sound/tlv.h> 20 #include "max98373.h" 21 22 static const u32 max98373_i2c_cache_reg[] = { 23 MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 24 MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 25 MAX98373_R20B6_BDE_CUR_STATE_READBACK, 26 }; 27 28 static struct reg_default max98373_reg[] = { 29 {MAX98373_R2000_SW_RESET, 0x00}, 30 {MAX98373_R2001_INT_RAW1, 0x00}, 31 {MAX98373_R2002_INT_RAW2, 0x00}, 32 {MAX98373_R2003_INT_RAW3, 0x00}, 33 {MAX98373_R2004_INT_STATE1, 0x00}, 34 {MAX98373_R2005_INT_STATE2, 0x00}, 35 {MAX98373_R2006_INT_STATE3, 0x00}, 36 {MAX98373_R2007_INT_FLAG1, 0x00}, 37 {MAX98373_R2008_INT_FLAG2, 0x00}, 38 {MAX98373_R2009_INT_FLAG3, 0x00}, 39 {MAX98373_R200A_INT_EN1, 0x00}, 40 {MAX98373_R200B_INT_EN2, 0x00}, 41 {MAX98373_R200C_INT_EN3, 0x00}, 42 {MAX98373_R200D_INT_FLAG_CLR1, 0x00}, 43 {MAX98373_R200E_INT_FLAG_CLR2, 0x00}, 44 {MAX98373_R200F_INT_FLAG_CLR3, 0x00}, 45 {MAX98373_R2010_IRQ_CTRL, 0x00}, 46 {MAX98373_R2014_THERM_WARN_THRESH, 0x10}, 47 {MAX98373_R2015_THERM_SHDN_THRESH, 0x27}, 48 {MAX98373_R2016_THERM_HYSTERESIS, 0x01}, 49 {MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0}, 50 {MAX98373_R2018_THERM_FOLDBACK_EN, 0x00}, 51 {MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55}, 52 {MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE}, 53 {MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF}, 54 {MAX98373_R2022_PCM_TX_SRC_1, 0x00}, 55 {MAX98373_R2023_PCM_TX_SRC_2, 0x00}, 56 {MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0}, 57 {MAX98373_R2025_AUDIO_IF_MODE, 0x00}, 58 {MAX98373_R2026_PCM_CLOCK_RATIO, 0x04}, 59 {MAX98373_R2027_PCM_SR_SETUP_1, 0x08}, 60 {MAX98373_R2028_PCM_SR_SETUP_2, 0x88}, 61 {MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00}, 62 {MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00}, 63 {MAX98373_R202B_PCM_RX_EN, 0x00}, 64 {MAX98373_R202C_PCM_TX_EN, 0x00}, 65 {MAX98373_R202E_ICC_RX_CH_EN_1, 0x00}, 66 {MAX98373_R202F_ICC_RX_CH_EN_2, 0x00}, 67 {MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF}, 68 {MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF}, 69 {MAX98373_R2032_ICC_LINK_EN_CFG, 0x30}, 70 {MAX98373_R2034_ICC_TX_CNTL, 0x00}, 71 {MAX98373_R2035_ICC_TX_EN, 0x00}, 72 {MAX98373_R2036_SOUNDWIRE_CTRL, 0x05}, 73 {MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00}, 74 {MAX98373_R203E_AMP_PATH_GAIN, 0x08}, 75 {MAX98373_R203F_AMP_DSP_CFG, 0x02}, 76 {MAX98373_R2040_TONE_GEN_CFG, 0x00}, 77 {MAX98373_R2041_AMP_CFG, 0x03}, 78 {MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00}, 79 {MAX98373_R2043_AMP_EN, 0x00}, 80 {MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04}, 81 {MAX98373_R2047_IV_SENSE_ADC_EN, 0x00}, 82 {MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00}, 83 {MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00}, 84 {MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00}, 85 {MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00}, 86 {MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00}, 87 {MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00}, 88 {MAX98373_R2090_BDE_LVL_HOLD, 0x00}, 89 {MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00}, 90 {MAX98373_R2092_BDE_CLIPPER_MODE, 0x00}, 91 {MAX98373_R2097_BDE_L1_THRESH, 0x00}, 92 {MAX98373_R2098_BDE_L2_THRESH, 0x00}, 93 {MAX98373_R2099_BDE_L3_THRESH, 0x00}, 94 {MAX98373_R209A_BDE_L4_THRESH, 0x00}, 95 {MAX98373_R209B_BDE_THRESH_HYST, 0x00}, 96 {MAX98373_R20A8_BDE_L1_CFG_1, 0x00}, 97 {MAX98373_R20A9_BDE_L1_CFG_2, 0x00}, 98 {MAX98373_R20AA_BDE_L1_CFG_3, 0x00}, 99 {MAX98373_R20AB_BDE_L2_CFG_1, 0x00}, 100 {MAX98373_R20AC_BDE_L2_CFG_2, 0x00}, 101 {MAX98373_R20AD_BDE_L2_CFG_3, 0x00}, 102 {MAX98373_R20AE_BDE_L3_CFG_1, 0x00}, 103 {MAX98373_R20AF_BDE_L3_CFG_2, 0x00}, 104 {MAX98373_R20B0_BDE_L3_CFG_3, 0x00}, 105 {MAX98373_R20B1_BDE_L4_CFG_1, 0x00}, 106 {MAX98373_R20B2_BDE_L4_CFG_2, 0x00}, 107 {MAX98373_R20B3_BDE_L4_CFG_3, 0x00}, 108 {MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00}, 109 {MAX98373_R20B5_BDE_EN, 0x00}, 110 {MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00}, 111 {MAX98373_R20D1_DHT_CFG, 0x01}, 112 {MAX98373_R20D2_DHT_ATTACK_CFG, 0x02}, 113 {MAX98373_R20D3_DHT_RELEASE_CFG, 0x03}, 114 {MAX98373_R20D4_DHT_EN, 0x00}, 115 {MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00}, 116 {MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00}, 117 {MAX98373_R20E2_LIMITER_EN, 0x00}, 118 {MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00}, 119 {MAX98373_R20FF_GLOBAL_SHDN, 0x00}, 120 {MAX98373_R21FF_REV_ID, 0x42}, 121 }; 122 123 static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 124 { 125 struct snd_soc_component *component = codec_dai->component; 126 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 127 unsigned int format = 0; 128 unsigned int invert = 0; 129 130 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt); 131 132 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 133 case SND_SOC_DAIFMT_NB_NF: 134 break; 135 case SND_SOC_DAIFMT_IB_NF: 136 invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE; 137 break; 138 default: 139 dev_err(component->dev, "DAI invert mode unsupported\n"); 140 return -EINVAL; 141 } 142 143 regmap_update_bits(max98373->regmap, 144 MAX98373_R2026_PCM_CLOCK_RATIO, 145 MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE, 146 invert); 147 148 /* interface format */ 149 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 150 case SND_SOC_DAIFMT_I2S: 151 format = MAX98373_PCM_FORMAT_I2S; 152 break; 153 case SND_SOC_DAIFMT_LEFT_J: 154 format = MAX98373_PCM_FORMAT_LJ; 155 break; 156 case SND_SOC_DAIFMT_DSP_A: 157 format = MAX98373_PCM_FORMAT_TDM_MODE1; 158 break; 159 case SND_SOC_DAIFMT_DSP_B: 160 format = MAX98373_PCM_FORMAT_TDM_MODE0; 161 break; 162 default: 163 return -EINVAL; 164 } 165 166 regmap_update_bits(max98373->regmap, 167 MAX98373_R2024_PCM_DATA_FMT_CFG, 168 MAX98373_PCM_MODE_CFG_FORMAT_MASK, 169 format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT); 170 171 return 0; 172 } 173 174 /* BCLKs per LRCLK */ 175 static const int bclk_sel_table[] = { 176 32, 48, 64, 96, 128, 192, 256, 384, 512, 320, 177 }; 178 179 static int max98373_get_bclk_sel(int bclk) 180 { 181 int i; 182 /* match BCLKs per LRCLK */ 183 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) { 184 if (bclk_sel_table[i] == bclk) 185 return i + 2; 186 } 187 return 0; 188 } 189 190 static int max98373_set_clock(struct snd_soc_component *component, 191 struct snd_pcm_hw_params *params) 192 { 193 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 194 /* BCLK/LRCLK ratio calculation */ 195 int blr_clk_ratio = params_channels(params) * max98373->ch_size; 196 int value; 197 198 if (!max98373->tdm_mode) { 199 /* BCLK configuration */ 200 value = max98373_get_bclk_sel(blr_clk_ratio); 201 if (!value) { 202 dev_err(component->dev, "format unsupported %d\n", 203 params_format(params)); 204 return -EINVAL; 205 } 206 207 regmap_update_bits(max98373->regmap, 208 MAX98373_R2026_PCM_CLOCK_RATIO, 209 MAX98373_PCM_CLK_SETUP_BSEL_MASK, 210 value); 211 } 212 return 0; 213 } 214 215 static int max98373_dai_hw_params(struct snd_pcm_substream *substream, 216 struct snd_pcm_hw_params *params, 217 struct snd_soc_dai *dai) 218 { 219 struct snd_soc_component *component = dai->component; 220 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 221 unsigned int sampling_rate = 0; 222 unsigned int chan_sz = 0; 223 224 /* pcm mode configuration */ 225 switch (snd_pcm_format_width(params_format(params))) { 226 case 16: 227 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 228 break; 229 case 24: 230 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 231 break; 232 case 32: 233 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 234 break; 235 default: 236 dev_err(component->dev, "format unsupported %d\n", 237 params_format(params)); 238 goto err; 239 } 240 241 max98373->ch_size = snd_pcm_format_width(params_format(params)); 242 243 regmap_update_bits(max98373->regmap, 244 MAX98373_R2024_PCM_DATA_FMT_CFG, 245 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 246 247 dev_dbg(component->dev, "format supported %d", 248 params_format(params)); 249 250 /* sampling rate configuration */ 251 switch (params_rate(params)) { 252 case 8000: 253 sampling_rate = MAX98373_PCM_SR_SET1_SR_8000; 254 break; 255 case 11025: 256 sampling_rate = MAX98373_PCM_SR_SET1_SR_11025; 257 break; 258 case 12000: 259 sampling_rate = MAX98373_PCM_SR_SET1_SR_12000; 260 break; 261 case 16000: 262 sampling_rate = MAX98373_PCM_SR_SET1_SR_16000; 263 break; 264 case 22050: 265 sampling_rate = MAX98373_PCM_SR_SET1_SR_22050; 266 break; 267 case 24000: 268 sampling_rate = MAX98373_PCM_SR_SET1_SR_24000; 269 break; 270 case 32000: 271 sampling_rate = MAX98373_PCM_SR_SET1_SR_32000; 272 break; 273 case 44100: 274 sampling_rate = MAX98373_PCM_SR_SET1_SR_44100; 275 break; 276 case 48000: 277 sampling_rate = MAX98373_PCM_SR_SET1_SR_48000; 278 break; 279 case 88200: 280 sampling_rate = MAX98373_PCM_SR_SET1_SR_88200; 281 break; 282 case 96000: 283 sampling_rate = MAX98373_PCM_SR_SET1_SR_96000; 284 break; 285 default: 286 dev_err(component->dev, "rate %d not supported\n", 287 params_rate(params)); 288 goto err; 289 } 290 291 /* set DAI_SR to correct LRCLK frequency */ 292 regmap_update_bits(max98373->regmap, 293 MAX98373_R2027_PCM_SR_SETUP_1, 294 MAX98373_PCM_SR_SET1_SR_MASK, 295 sampling_rate); 296 regmap_update_bits(max98373->regmap, 297 MAX98373_R2028_PCM_SR_SETUP_2, 298 MAX98373_PCM_SR_SET2_SR_MASK, 299 sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT); 300 301 /* set sampling rate of IV */ 302 if (max98373->interleave_mode && 303 sampling_rate > MAX98373_PCM_SR_SET1_SR_16000) 304 regmap_update_bits(max98373->regmap, 305 MAX98373_R2028_PCM_SR_SETUP_2, 306 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 307 sampling_rate - 3); 308 else 309 regmap_update_bits(max98373->regmap, 310 MAX98373_R2028_PCM_SR_SETUP_2, 311 MAX98373_PCM_SR_SET2_IVADC_SR_MASK, 312 sampling_rate); 313 314 return max98373_set_clock(component, params); 315 err: 316 return -EINVAL; 317 } 318 319 static int max98373_dai_tdm_slot(struct snd_soc_dai *dai, 320 unsigned int tx_mask, unsigned int rx_mask, 321 int slots, int slot_width) 322 { 323 struct snd_soc_component *component = dai->component; 324 struct max98373_priv *max98373 = snd_soc_component_get_drvdata(component); 325 int bsel = 0; 326 unsigned int chan_sz = 0; 327 unsigned int mask; 328 int x, slot_found; 329 330 if (!tx_mask && !rx_mask && !slots && !slot_width) 331 max98373->tdm_mode = false; 332 else 333 max98373->tdm_mode = true; 334 335 /* BCLK configuration */ 336 bsel = max98373_get_bclk_sel(slots * slot_width); 337 if (bsel == 0) { 338 dev_err(component->dev, "BCLK %d not supported\n", 339 slots * slot_width); 340 return -EINVAL; 341 } 342 343 regmap_update_bits(max98373->regmap, 344 MAX98373_R2026_PCM_CLOCK_RATIO, 345 MAX98373_PCM_CLK_SETUP_BSEL_MASK, 346 bsel); 347 348 /* Channel size configuration */ 349 switch (slot_width) { 350 case 16: 351 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16; 352 break; 353 case 24: 354 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24; 355 break; 356 case 32: 357 chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32; 358 break; 359 default: 360 dev_err(component->dev, "format unsupported %d\n", 361 slot_width); 362 return -EINVAL; 363 } 364 365 regmap_update_bits(max98373->regmap, 366 MAX98373_R2024_PCM_DATA_FMT_CFG, 367 MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz); 368 369 /* Rx slot configuration */ 370 slot_found = 0; 371 mask = rx_mask; 372 for (x = 0 ; x < 16 ; x++, mask >>= 1) { 373 if (mask & 0x1) { 374 if (slot_found == 0) 375 regmap_update_bits(max98373->regmap, 376 MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 377 MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x); 378 else 379 regmap_write(max98373->regmap, 380 MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 381 x); 382 slot_found++; 383 if (slot_found > 1) 384 break; 385 } 386 } 387 388 /* Tx slot Hi-Z configuration */ 389 regmap_write(max98373->regmap, 390 MAX98373_R2020_PCM_TX_HIZ_EN_1, 391 ~tx_mask & 0xFF); 392 regmap_write(max98373->regmap, 393 MAX98373_R2021_PCM_TX_HIZ_EN_2, 394 (~tx_mask & 0xFF00) >> 8); 395 396 return 0; 397 } 398 399 #define MAX98373_RATES SNDRV_PCM_RATE_8000_96000 400 401 #define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 402 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 403 404 static const struct snd_soc_dai_ops max98373_dai_ops = { 405 .set_fmt = max98373_dai_set_fmt, 406 .hw_params = max98373_dai_hw_params, 407 .set_tdm_slot = max98373_dai_tdm_slot, 408 }; 409 410 static bool max98373_readable_register(struct device *dev, unsigned int reg) 411 { 412 switch (reg) { 413 case MAX98373_R2000_SW_RESET: 414 case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3: 415 case MAX98373_R2010_IRQ_CTRL: 416 case MAX98373_R2014_THERM_WARN_THRESH 417 ... MAX98373_R2018_THERM_FOLDBACK_EN: 418 case MAX98373_R201E_PIN_DRIVE_STRENGTH 419 ... MAX98373_R2036_SOUNDWIRE_CTRL: 420 case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN: 421 case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 422 ... MAX98373_R2047_IV_SENSE_ADC_EN: 423 case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 424 ... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN: 425 case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE: 426 case MAX98373_R2097_BDE_L1_THRESH 427 ... MAX98373_R209B_BDE_THRESH_HYST: 428 case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3: 429 case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK: 430 case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN: 431 case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN: 432 case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 433 ... MAX98373_R20FF_GLOBAL_SHDN: 434 case MAX98373_R21FF_REV_ID: 435 return true; 436 default: 437 return false; 438 } 439 }; 440 441 static bool max98373_volatile_reg(struct device *dev, unsigned int reg) 442 { 443 switch (reg) { 444 case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3: 445 case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK: 446 case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK: 447 case MAX98373_R20B6_BDE_CUR_STATE_READBACK: 448 case MAX98373_R20FF_GLOBAL_SHDN: 449 case MAX98373_R21FF_REV_ID: 450 return true; 451 default: 452 return false; 453 } 454 } 455 456 static struct snd_soc_dai_driver max98373_dai[] = { 457 { 458 .name = "max98373-aif1", 459 .playback = { 460 .stream_name = "HiFi Playback", 461 .channels_min = 1, 462 .channels_max = 2, 463 .rates = MAX98373_RATES, 464 .formats = MAX98373_FORMATS, 465 }, 466 .capture = { 467 .stream_name = "HiFi Capture", 468 .channels_min = 1, 469 .channels_max = 2, 470 .rates = MAX98373_RATES, 471 .formats = MAX98373_FORMATS, 472 }, 473 .ops = &max98373_dai_ops, 474 } 475 }; 476 477 #ifdef CONFIG_PM_SLEEP 478 static int max98373_suspend(struct device *dev) 479 { 480 struct max98373_priv *max98373 = dev_get_drvdata(dev); 481 int i; 482 483 /* cache feedback register values before suspend */ 484 for (i = 0; i < max98373->cache_num; i++) 485 regmap_read(max98373->regmap, max98373->cache[i].reg, &max98373->cache[i].val); 486 487 regcache_cache_only(max98373->regmap, true); 488 regcache_mark_dirty(max98373->regmap); 489 return 0; 490 } 491 492 static int max98373_resume(struct device *dev) 493 { 494 struct max98373_priv *max98373 = dev_get_drvdata(dev); 495 496 regcache_cache_only(max98373->regmap, false); 497 max98373_reset(max98373, dev); 498 regcache_sync(max98373->regmap); 499 return 0; 500 } 501 #endif 502 503 static const struct dev_pm_ops max98373_pm = { 504 SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume) 505 }; 506 507 static const struct regmap_config max98373_regmap = { 508 .reg_bits = 16, 509 .val_bits = 8, 510 .max_register = MAX98373_R21FF_REV_ID, 511 .reg_defaults = max98373_reg, 512 .num_reg_defaults = ARRAY_SIZE(max98373_reg), 513 .readable_reg = max98373_readable_register, 514 .volatile_reg = max98373_volatile_reg, 515 .cache_type = REGCACHE_RBTREE, 516 }; 517 518 static int max98373_i2c_probe(struct i2c_client *i2c) 519 { 520 int ret = 0; 521 int reg = 0; 522 int i; 523 struct max98373_priv *max98373 = NULL; 524 525 max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL); 526 527 if (!max98373) { 528 ret = -ENOMEM; 529 return ret; 530 } 531 i2c_set_clientdata(i2c, max98373); 532 533 /* update interleave mode info */ 534 if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode")) 535 max98373->interleave_mode = true; 536 else 537 max98373->interleave_mode = false; 538 539 /* regmap initialization */ 540 max98373->regmap = devm_regmap_init_i2c(i2c, &max98373_regmap); 541 if (IS_ERR(max98373->regmap)) { 542 ret = PTR_ERR(max98373->regmap); 543 dev_err(&i2c->dev, 544 "Failed to allocate regmap: %d\n", ret); 545 return ret; 546 } 547 548 max98373->cache_num = ARRAY_SIZE(max98373_i2c_cache_reg); 549 max98373->cache = devm_kcalloc(&i2c->dev, max98373->cache_num, 550 sizeof(*max98373->cache), 551 GFP_KERNEL); 552 if (!max98373->cache) { 553 ret = -ENOMEM; 554 return ret; 555 } 556 557 for (i = 0; i < max98373->cache_num; i++) 558 max98373->cache[i].reg = max98373_i2c_cache_reg[i]; 559 560 /* voltage/current slot & gpio configuration */ 561 max98373_slot_config(&i2c->dev, max98373); 562 563 /* Power on device */ 564 if (gpio_is_valid(max98373->reset_gpio)) { 565 ret = devm_gpio_request(&i2c->dev, max98373->reset_gpio, 566 "MAX98373_RESET"); 567 if (ret) { 568 dev_err(&i2c->dev, "%s: Failed to request gpio %d\n", 569 __func__, max98373->reset_gpio); 570 return -EINVAL; 571 } 572 gpio_direction_output(max98373->reset_gpio, 0); 573 msleep(50); 574 gpio_direction_output(max98373->reset_gpio, 1); 575 msleep(20); 576 } 577 578 /* Check Revision ID */ 579 ret = regmap_read(max98373->regmap, 580 MAX98373_R21FF_REV_ID, ®); 581 if (ret < 0) { 582 dev_err(&i2c->dev, 583 "Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID); 584 return ret; 585 } 586 dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg); 587 588 /* codec registration */ 589 ret = devm_snd_soc_register_component(&i2c->dev, &soc_codec_dev_max98373, 590 max98373_dai, ARRAY_SIZE(max98373_dai)); 591 if (ret < 0) 592 dev_err(&i2c->dev, "Failed to register codec: %d\n", ret); 593 594 return ret; 595 } 596 597 static const struct i2c_device_id max98373_i2c_id[] = { 598 { "max98373", 0}, 599 { }, 600 }; 601 602 MODULE_DEVICE_TABLE(i2c, max98373_i2c_id); 603 604 #if defined(CONFIG_OF) 605 static const struct of_device_id max98373_of_match[] = { 606 { .compatible = "maxim,max98373", }, 607 { } 608 }; 609 MODULE_DEVICE_TABLE(of, max98373_of_match); 610 #endif 611 612 #ifdef CONFIG_ACPI 613 static const struct acpi_device_id max98373_acpi_match[] = { 614 { "MX98373", 0 }, 615 {}, 616 }; 617 MODULE_DEVICE_TABLE(acpi, max98373_acpi_match); 618 #endif 619 620 static struct i2c_driver max98373_i2c_driver = { 621 .driver = { 622 .name = "max98373", 623 .of_match_table = of_match_ptr(max98373_of_match), 624 .acpi_match_table = ACPI_PTR(max98373_acpi_match), 625 .pm = &max98373_pm, 626 }, 627 .probe = max98373_i2c_probe, 628 .id_table = max98373_i2c_id, 629 }; 630 631 module_i2c_driver(max98373_i2c_driver) 632 633 MODULE_DESCRIPTION("ALSA SoC MAX98373 driver"); 634 MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>"); 635 MODULE_LICENSE("GPL"); 636