1*18c0af94SRyan Lee /* SPDX-License-Identifier: GPL-2.0-only */ 2*18c0af94SRyan Lee /* Copyright (c) 2022 Analog Devices Inc. */ 3*18c0af94SRyan Lee 4*18c0af94SRyan Lee #ifndef _MAX98363_H 5*18c0af94SRyan Lee #define _MAX98363_H 6*18c0af94SRyan Lee 7*18c0af94SRyan Lee #define MAX98363_R2000_SW_RESET 0x2000 8*18c0af94SRyan Lee #define MAX98363_R2001_INTR_RAW 0x2001 9*18c0af94SRyan Lee #define MAX98363_R2003_INTR_STATE 0x2003 10*18c0af94SRyan Lee #define MAX98363_R2005_INTR_FALG 0x2005 11*18c0af94SRyan Lee #define MAX98363_R2007_INTR_EN 0x2007 12*18c0af94SRyan Lee #define MAX98363_R2009_INTR_CLR 0x2009 13*18c0af94SRyan Lee #define MAX98363_R2021_ERR_MON_CTRL 0x2021 14*18c0af94SRyan Lee #define MAX98363_R2022_SPK_MON_THRESH 0x2022 15*18c0af94SRyan Lee #define MAX98363_R2023_SPK_MON_DURATION 0x2023 16*18c0af94SRyan Lee #define MAX98363_R2030_TONE_GEN_CFG 0x2030 17*18c0af94SRyan Lee #define MAX98363_R203F_TONE_GEN_EN 0x203F 18*18c0af94SRyan Lee #define MAX98363_R2040_AMP_VOL 0x2040 19*18c0af94SRyan Lee #define MAX98363_R2041_AMP_GAIN 0x2041 20*18c0af94SRyan Lee #define MAX98363_R2042_DSP_CFG 0x2042 21*18c0af94SRyan Lee #define MAX98363_R21FF_REV_ID 0x21FF 22*18c0af94SRyan Lee 23*18c0af94SRyan Lee /* MAX98363_R2021_ERR_MON_CTRL */ 24*18c0af94SRyan Lee #define MAX98363_SPKMON_SHIFT (3) 25*18c0af94SRyan Lee #define MAX98363_CLOCK_MON_SHIFT (0) 26*18c0af94SRyan Lee 27*18c0af94SRyan Lee /* MAX98363_R2042_DSP_CFG */ 28*18c0af94SRyan Lee #define MAX98363_AMP_DSP_CFG_RMP_SHIFT (3) 29*18c0af94SRyan Lee 30*18c0af94SRyan Lee struct max98363_priv { 31*18c0af94SRyan Lee struct regmap *regmap; 32*18c0af94SRyan Lee struct sdw_slave *slave; 33*18c0af94SRyan Lee bool hw_init; 34*18c0af94SRyan Lee bool first_hw_init; 35*18c0af94SRyan Lee }; 36*18c0af94SRyan Lee #endif 37