1 /* 2 * max98095.c -- MAX98095 ALSA SoC Audio driver 3 * 4 * Copyright 2011 Maxim Integrated Products 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/clk.h> 19 #include <linux/mutex.h> 20 #include <sound/core.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include <sound/soc.h> 24 #include <sound/initval.h> 25 #include <sound/tlv.h> 26 #include <linux/slab.h> 27 #include <asm/div64.h> 28 #include <sound/max98095.h> 29 #include <sound/jack.h> 30 #include "max98095.h" 31 32 enum max98095_type { 33 MAX98095, 34 }; 35 36 struct max98095_cdata { 37 unsigned int rate; 38 unsigned int fmt; 39 int eq_sel; 40 int bq_sel; 41 }; 42 43 struct max98095_priv { 44 struct regmap *regmap; 45 enum max98095_type devtype; 46 struct max98095_pdata *pdata; 47 struct clk *mclk; 48 unsigned int sysclk; 49 struct max98095_cdata dai[3]; 50 const char **eq_texts; 51 const char **bq_texts; 52 struct soc_enum eq_enum; 53 struct soc_enum bq_enum; 54 int eq_textcnt; 55 int bq_textcnt; 56 u8 lin_state; 57 unsigned int mic1pre; 58 unsigned int mic2pre; 59 struct snd_soc_jack *headphone_jack; 60 struct snd_soc_jack *mic_jack; 61 struct mutex lock; 62 }; 63 64 static const struct reg_default max98095_reg_def[] = { 65 { 0xf, 0x00 }, /* 0F */ 66 { 0x10, 0x00 }, /* 10 */ 67 { 0x11, 0x00 }, /* 11 */ 68 { 0x12, 0x00 }, /* 12 */ 69 { 0x13, 0x00 }, /* 13 */ 70 { 0x14, 0x00 }, /* 14 */ 71 { 0x15, 0x00 }, /* 15 */ 72 { 0x16, 0x00 }, /* 16 */ 73 { 0x17, 0x00 }, /* 17 */ 74 { 0x18, 0x00 }, /* 18 */ 75 { 0x19, 0x00 }, /* 19 */ 76 { 0x1a, 0x00 }, /* 1A */ 77 { 0x1b, 0x00 }, /* 1B */ 78 { 0x1c, 0x00 }, /* 1C */ 79 { 0x1d, 0x00 }, /* 1D */ 80 { 0x1e, 0x00 }, /* 1E */ 81 { 0x1f, 0x00 }, /* 1F */ 82 { 0x20, 0x00 }, /* 20 */ 83 { 0x21, 0x00 }, /* 21 */ 84 { 0x22, 0x00 }, /* 22 */ 85 { 0x23, 0x00 }, /* 23 */ 86 { 0x24, 0x00 }, /* 24 */ 87 { 0x25, 0x00 }, /* 25 */ 88 { 0x26, 0x00 }, /* 26 */ 89 { 0x27, 0x00 }, /* 27 */ 90 { 0x28, 0x00 }, /* 28 */ 91 { 0x29, 0x00 }, /* 29 */ 92 { 0x2a, 0x00 }, /* 2A */ 93 { 0x2b, 0x00 }, /* 2B */ 94 { 0x2c, 0x00 }, /* 2C */ 95 { 0x2d, 0x00 }, /* 2D */ 96 { 0x2e, 0x00 }, /* 2E */ 97 { 0x2f, 0x00 }, /* 2F */ 98 { 0x30, 0x00 }, /* 30 */ 99 { 0x31, 0x00 }, /* 31 */ 100 { 0x32, 0x00 }, /* 32 */ 101 { 0x33, 0x00 }, /* 33 */ 102 { 0x34, 0x00 }, /* 34 */ 103 { 0x35, 0x00 }, /* 35 */ 104 { 0x36, 0x00 }, /* 36 */ 105 { 0x37, 0x00 }, /* 37 */ 106 { 0x38, 0x00 }, /* 38 */ 107 { 0x39, 0x00 }, /* 39 */ 108 { 0x3a, 0x00 }, /* 3A */ 109 { 0x3b, 0x00 }, /* 3B */ 110 { 0x3c, 0x00 }, /* 3C */ 111 { 0x3d, 0x00 }, /* 3D */ 112 { 0x3e, 0x00 }, /* 3E */ 113 { 0x3f, 0x00 }, /* 3F */ 114 { 0x40, 0x00 }, /* 40 */ 115 { 0x41, 0x00 }, /* 41 */ 116 { 0x42, 0x00 }, /* 42 */ 117 { 0x43, 0x00 }, /* 43 */ 118 { 0x44, 0x00 }, /* 44 */ 119 { 0x45, 0x00 }, /* 45 */ 120 { 0x46, 0x00 }, /* 46 */ 121 { 0x47, 0x00 }, /* 47 */ 122 { 0x48, 0x00 }, /* 48 */ 123 { 0x49, 0x00 }, /* 49 */ 124 { 0x4a, 0x00 }, /* 4A */ 125 { 0x4b, 0x00 }, /* 4B */ 126 { 0x4c, 0x00 }, /* 4C */ 127 { 0x4d, 0x00 }, /* 4D */ 128 { 0x4e, 0x00 }, /* 4E */ 129 { 0x4f, 0x00 }, /* 4F */ 130 { 0x50, 0x00 }, /* 50 */ 131 { 0x51, 0x00 }, /* 51 */ 132 { 0x52, 0x00 }, /* 52 */ 133 { 0x53, 0x00 }, /* 53 */ 134 { 0x54, 0x00 }, /* 54 */ 135 { 0x55, 0x00 }, /* 55 */ 136 { 0x56, 0x00 }, /* 56 */ 137 { 0x57, 0x00 }, /* 57 */ 138 { 0x58, 0x00 }, /* 58 */ 139 { 0x59, 0x00 }, /* 59 */ 140 { 0x5a, 0x00 }, /* 5A */ 141 { 0x5b, 0x00 }, /* 5B */ 142 { 0x5c, 0x00 }, /* 5C */ 143 { 0x5d, 0x00 }, /* 5D */ 144 { 0x5e, 0x00 }, /* 5E */ 145 { 0x5f, 0x00 }, /* 5F */ 146 { 0x60, 0x00 }, /* 60 */ 147 { 0x61, 0x00 }, /* 61 */ 148 { 0x62, 0x00 }, /* 62 */ 149 { 0x63, 0x00 }, /* 63 */ 150 { 0x64, 0x00 }, /* 64 */ 151 { 0x65, 0x00 }, /* 65 */ 152 { 0x66, 0x00 }, /* 66 */ 153 { 0x67, 0x00 }, /* 67 */ 154 { 0x68, 0x00 }, /* 68 */ 155 { 0x69, 0x00 }, /* 69 */ 156 { 0x6a, 0x00 }, /* 6A */ 157 { 0x6b, 0x00 }, /* 6B */ 158 { 0x6c, 0x00 }, /* 6C */ 159 { 0x6d, 0x00 }, /* 6D */ 160 { 0x6e, 0x00 }, /* 6E */ 161 { 0x6f, 0x00 }, /* 6F */ 162 { 0x70, 0x00 }, /* 70 */ 163 { 0x71, 0x00 }, /* 71 */ 164 { 0x72, 0x00 }, /* 72 */ 165 { 0x73, 0x00 }, /* 73 */ 166 { 0x74, 0x00 }, /* 74 */ 167 { 0x75, 0x00 }, /* 75 */ 168 { 0x76, 0x00 }, /* 76 */ 169 { 0x77, 0x00 }, /* 77 */ 170 { 0x78, 0x00 }, /* 78 */ 171 { 0x79, 0x00 }, /* 79 */ 172 { 0x7a, 0x00 }, /* 7A */ 173 { 0x7b, 0x00 }, /* 7B */ 174 { 0x7c, 0x00 }, /* 7C */ 175 { 0x7d, 0x00 }, /* 7D */ 176 { 0x7e, 0x00 }, /* 7E */ 177 { 0x7f, 0x00 }, /* 7F */ 178 { 0x80, 0x00 }, /* 80 */ 179 { 0x81, 0x00 }, /* 81 */ 180 { 0x82, 0x00 }, /* 82 */ 181 { 0x83, 0x00 }, /* 83 */ 182 { 0x84, 0x00 }, /* 84 */ 183 { 0x85, 0x00 }, /* 85 */ 184 { 0x86, 0x00 }, /* 86 */ 185 { 0x87, 0x00 }, /* 87 */ 186 { 0x88, 0x00 }, /* 88 */ 187 { 0x89, 0x00 }, /* 89 */ 188 { 0x8a, 0x00 }, /* 8A */ 189 { 0x8b, 0x00 }, /* 8B */ 190 { 0x8c, 0x00 }, /* 8C */ 191 { 0x8d, 0x00 }, /* 8D */ 192 { 0x8e, 0x00 }, /* 8E */ 193 { 0x8f, 0x00 }, /* 8F */ 194 { 0x90, 0x00 }, /* 90 */ 195 { 0x91, 0x00 }, /* 91 */ 196 { 0x92, 0x30 }, /* 92 */ 197 { 0x93, 0xF0 }, /* 93 */ 198 { 0x94, 0x00 }, /* 94 */ 199 { 0x95, 0x00 }, /* 95 */ 200 { 0x96, 0x3F }, /* 96 */ 201 { 0x97, 0x00 }, /* 97 */ 202 { 0xff, 0x00 }, /* FF */ 203 }; 204 205 static bool max98095_readable(struct device *dev, unsigned int reg) 206 { 207 switch (reg) { 208 case M98095_001_HOST_INT_STS ... M98095_097_PWR_SYS: 209 case M98095_0FF_REV_ID: 210 return true; 211 default: 212 return false; 213 } 214 } 215 216 static bool max98095_writeable(struct device *dev, unsigned int reg) 217 { 218 switch (reg) { 219 case M98095_00F_HOST_CFG ... M98095_097_PWR_SYS: 220 return true; 221 default: 222 return false; 223 } 224 } 225 226 static bool max98095_volatile(struct device *dev, unsigned int reg) 227 { 228 switch (reg) { 229 case M98095_000_HOST_DATA ... M98095_00E_TEMP_SENSOR_STS: 230 case M98095_REG_MAX_CACHED + 1 ... M98095_0FF_REV_ID: 231 return true; 232 default: 233 return false; 234 } 235 } 236 237 static const struct regmap_config max98095_regmap = { 238 .reg_bits = 8, 239 .val_bits = 8, 240 241 .reg_defaults = max98095_reg_def, 242 .num_reg_defaults = ARRAY_SIZE(max98095_reg_def), 243 .max_register = M98095_0FF_REV_ID, 244 .cache_type = REGCACHE_RBTREE, 245 246 .readable_reg = max98095_readable, 247 .writeable_reg = max98095_writeable, 248 .volatile_reg = max98095_volatile, 249 }; 250 251 /* 252 * Load equalizer DSP coefficient configurations registers 253 */ 254 static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai, 255 unsigned int band, u16 *coefs) 256 { 257 unsigned int eq_reg; 258 unsigned int i; 259 260 if (WARN_ON(band > 4) || 261 WARN_ON(dai > 1)) 262 return; 263 264 /* Load the base register address */ 265 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE; 266 267 /* Add the band address offset, note adjustment for word address */ 268 eq_reg += band * (M98095_COEFS_PER_BAND << 1); 269 270 /* Step through the registers and coefs */ 271 for (i = 0; i < M98095_COEFS_PER_BAND; i++) { 272 snd_soc_write(codec, eq_reg++, M98095_BYTE1(coefs[i])); 273 snd_soc_write(codec, eq_reg++, M98095_BYTE0(coefs[i])); 274 } 275 } 276 277 /* 278 * Load biquad filter coefficient configurations registers 279 */ 280 static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai, 281 unsigned int band, u16 *coefs) 282 { 283 unsigned int bq_reg; 284 unsigned int i; 285 286 if (WARN_ON(band > 1) || 287 WARN_ON(dai > 1)) 288 return; 289 290 /* Load the base register address */ 291 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE; 292 293 /* Add the band address offset, note adjustment for word address */ 294 bq_reg += band * (M98095_COEFS_PER_BAND << 1); 295 296 /* Step through the registers and coefs */ 297 for (i = 0; i < M98095_COEFS_PER_BAND; i++) { 298 snd_soc_write(codec, bq_reg++, M98095_BYTE1(coefs[i])); 299 snd_soc_write(codec, bq_reg++, M98095_BYTE0(coefs[i])); 300 } 301 } 302 303 static const char * const max98095_fltr_mode[] = { "Voice", "Music" }; 304 static SOC_ENUM_SINGLE_DECL(max98095_dai1_filter_mode_enum, 305 M98095_02E_DAI1_FILTERS, 7, 306 max98095_fltr_mode); 307 static SOC_ENUM_SINGLE_DECL(max98095_dai2_filter_mode_enum, 308 M98095_038_DAI2_FILTERS, 7, 309 max98095_fltr_mode); 310 311 static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" }; 312 313 static SOC_ENUM_SINGLE_DECL(max98095_extmic_enum, 314 M98095_087_CFG_MIC, 0, 315 max98095_extmic_text); 316 317 static const struct snd_kcontrol_new max98095_extmic_mux = 318 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum); 319 320 static const char * const max98095_linein_text[] = { "INA", "INB" }; 321 322 static SOC_ENUM_SINGLE_DECL(max98095_linein_enum, 323 M98095_086_CFG_LINE, 6, 324 max98095_linein_text); 325 326 static const struct snd_kcontrol_new max98095_linein_mux = 327 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum); 328 329 static const char * const max98095_line_mode_text[] = { 330 "Stereo", "Differential"}; 331 332 static SOC_ENUM_SINGLE_DECL(max98095_linein_mode_enum, 333 M98095_086_CFG_LINE, 7, 334 max98095_line_mode_text); 335 336 static SOC_ENUM_SINGLE_DECL(max98095_lineout_mode_enum, 337 M98095_086_CFG_LINE, 4, 338 max98095_line_mode_text); 339 340 static const char * const max98095_dai_fltr[] = { 341 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k", 342 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"}; 343 static SOC_ENUM_SINGLE_DECL(max98095_dai1_dac_filter_enum, 344 M98095_02E_DAI1_FILTERS, 0, 345 max98095_dai_fltr); 346 static SOC_ENUM_SINGLE_DECL(max98095_dai2_dac_filter_enum, 347 M98095_038_DAI2_FILTERS, 0, 348 max98095_dai_fltr); 349 static SOC_ENUM_SINGLE_DECL(max98095_dai3_dac_filter_enum, 350 M98095_042_DAI3_FILTERS, 0, 351 max98095_dai_fltr); 352 353 static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol, 354 struct snd_ctl_elem_value *ucontrol) 355 { 356 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 357 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 358 unsigned int sel = ucontrol->value.integer.value[0]; 359 360 max98095->mic1pre = sel; 361 snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK, 362 (1+sel)<<M98095_MICPRE_SHIFT); 363 364 return 0; 365 } 366 367 static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol, 368 struct snd_ctl_elem_value *ucontrol) 369 { 370 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 371 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 372 373 ucontrol->value.integer.value[0] = max98095->mic1pre; 374 return 0; 375 } 376 377 static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol, 378 struct snd_ctl_elem_value *ucontrol) 379 { 380 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 381 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 382 unsigned int sel = ucontrol->value.integer.value[0]; 383 384 max98095->mic2pre = sel; 385 snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK, 386 (1+sel)<<M98095_MICPRE_SHIFT); 387 388 return 0; 389 } 390 391 static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol, 392 struct snd_ctl_elem_value *ucontrol) 393 { 394 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 395 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 396 397 ucontrol->value.integer.value[0] = max98095->mic2pre; 398 return 0; 399 } 400 401 static const DECLARE_TLV_DB_RANGE(max98095_micboost_tlv, 402 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 403 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0) 404 ); 405 406 static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0); 407 static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0); 408 static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0); 409 410 static const DECLARE_TLV_DB_RANGE(max98095_hp_tlv, 411 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 412 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 413 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 414 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 415 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0) 416 ); 417 418 static const DECLARE_TLV_DB_RANGE(max98095_spk_tlv, 419 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0), 420 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0), 421 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0), 422 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0) 423 ); 424 425 static const DECLARE_TLV_DB_RANGE(max98095_rcv_lout_tlv, 426 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 427 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 428 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 429 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 430 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0) 431 ); 432 433 static const DECLARE_TLV_DB_RANGE(max98095_lin_tlv, 434 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0), 435 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0), 436 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0) 437 ); 438 439 static const struct snd_kcontrol_new max98095_snd_controls[] = { 440 441 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L, 442 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv), 443 444 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L, 445 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv), 446 447 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV, 448 0, 31, 0, max98095_rcv_lout_tlv), 449 450 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1, 451 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv), 452 453 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L, 454 M98095_065_LVL_HP_R, 7, 1, 1), 455 456 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L, 457 M98095_068_LVL_SPK_R, 7, 1, 1), 458 459 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1), 460 461 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1, 462 M98095_063_LVL_LINEOUT2, 7, 1, 1), 463 464 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1, 465 max98095_mic_tlv), 466 467 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1, 468 max98095_mic_tlv), 469 470 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 471 M98095_05F_LVL_MIC1, 5, 2, 0, 472 max98095_mic1pre_get, max98095_mic1pre_set, 473 max98095_micboost_tlv), 474 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 475 M98095_060_LVL_MIC2, 5, 2, 0, 476 max98095_mic2pre_get, max98095_mic2pre_set, 477 max98095_micboost_tlv), 478 479 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1, 480 max98095_lin_tlv), 481 482 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1, 483 max98095_adc_tlv), 484 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1, 485 max98095_adc_tlv), 486 487 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0, 488 max98095_adcboost_tlv), 489 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0, 490 max98095_adcboost_tlv), 491 492 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0), 493 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0), 494 495 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0), 496 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0), 497 498 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum), 499 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum), 500 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum), 501 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum), 502 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum), 503 504 SOC_ENUM("Linein Mode", max98095_linein_mode_enum), 505 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum), 506 }; 507 508 /* Left speaker mixer switch */ 509 static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = { 510 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0), 511 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0), 512 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), 513 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), 514 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0), 515 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0), 516 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0), 517 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0), 518 }; 519 520 /* Right speaker mixer switch */ 521 static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = { 522 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0), 523 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0), 524 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), 525 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), 526 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0), 527 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0), 528 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0), 529 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0), 530 }; 531 532 /* Left headphone mixer switch */ 533 static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = { 534 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0), 535 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0), 536 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0), 537 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0), 538 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0), 539 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0), 540 }; 541 542 /* Right headphone mixer switch */ 543 static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = { 544 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0), 545 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0), 546 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0), 547 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0), 548 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0), 549 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0), 550 }; 551 552 /* Receiver earpiece mixer switch */ 553 static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = { 554 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0), 555 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0), 556 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0), 557 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0), 558 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0), 559 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0), 560 }; 561 562 /* Left lineout mixer switch */ 563 static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = { 564 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0), 565 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0), 566 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0), 567 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0), 568 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0), 569 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0), 570 }; 571 572 /* Right lineout mixer switch */ 573 static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = { 574 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0), 575 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0), 576 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0), 577 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0), 578 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0), 579 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0), 580 }; 581 582 /* Left ADC mixer switch */ 583 static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = { 584 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0), 585 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0), 586 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0), 587 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0), 588 }; 589 590 /* Right ADC mixer switch */ 591 static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = { 592 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0), 593 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0), 594 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0), 595 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0), 596 }; 597 598 static int max98095_mic_event(struct snd_soc_dapm_widget *w, 599 struct snd_kcontrol *kcontrol, int event) 600 { 601 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 602 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 603 604 switch (event) { 605 case SND_SOC_DAPM_POST_PMU: 606 if (w->reg == M98095_05F_LVL_MIC1) { 607 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 608 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT); 609 } else { 610 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 611 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT); 612 } 613 break; 614 case SND_SOC_DAPM_POST_PMD: 615 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0); 616 break; 617 default: 618 return -EINVAL; 619 } 620 621 return 0; 622 } 623 624 /* 625 * The line inputs are stereo inputs with the left and right 626 * channels sharing a common PGA power control signal. 627 */ 628 static int max98095_line_pga(struct snd_soc_dapm_widget *w, 629 int event, u8 channel) 630 { 631 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 632 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 633 u8 *state; 634 635 if (WARN_ON(!(channel == 1 || channel == 2))) 636 return -EINVAL; 637 638 state = &max98095->lin_state; 639 640 switch (event) { 641 case SND_SOC_DAPM_POST_PMU: 642 *state |= channel; 643 snd_soc_update_bits(codec, w->reg, 644 (1 << w->shift), (1 << w->shift)); 645 break; 646 case SND_SOC_DAPM_POST_PMD: 647 *state &= ~channel; 648 if (*state == 0) { 649 snd_soc_update_bits(codec, w->reg, 650 (1 << w->shift), 0); 651 } 652 break; 653 default: 654 return -EINVAL; 655 } 656 657 return 0; 658 } 659 660 static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w, 661 struct snd_kcontrol *k, int event) 662 { 663 return max98095_line_pga(w, event, 1); 664 } 665 666 static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w, 667 struct snd_kcontrol *k, int event) 668 { 669 return max98095_line_pga(w, event, 2); 670 } 671 672 /* 673 * The stereo line out mixer outputs to two stereo line outs. 674 * The 2nd pair has a separate set of enables. 675 */ 676 static int max98095_lineout_event(struct snd_soc_dapm_widget *w, 677 struct snd_kcontrol *kcontrol, int event) 678 { 679 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); 680 681 switch (event) { 682 case SND_SOC_DAPM_POST_PMU: 683 snd_soc_update_bits(codec, w->reg, 684 (1 << (w->shift+2)), (1 << (w->shift+2))); 685 break; 686 case SND_SOC_DAPM_POST_PMD: 687 snd_soc_update_bits(codec, w->reg, 688 (1 << (w->shift+2)), 0); 689 break; 690 default: 691 return -EINVAL; 692 } 693 694 return 0; 695 } 696 697 static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = { 698 699 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0), 700 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0), 701 702 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", 703 M98095_091_PWR_EN_OUT, 0, 0), 704 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", 705 M98095_091_PWR_EN_OUT, 1, 0), 706 SND_SOC_DAPM_DAC("DACM2", "Aux Playback", 707 M98095_091_PWR_EN_OUT, 2, 0), 708 SND_SOC_DAPM_DAC("DACM3", "Voice Playback", 709 M98095_091_PWR_EN_OUT, 2, 0), 710 711 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT, 712 6, 0, NULL, 0), 713 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT, 714 7, 0, NULL, 0), 715 716 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT, 717 4, 0, NULL, 0), 718 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT, 719 5, 0, NULL, 0), 720 721 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT, 722 3, 0, NULL, 0), 723 724 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT, 725 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), 726 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT, 727 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), 728 729 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, 730 &max98095_extmic_mux), 731 732 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0, 733 &max98095_linein_mux), 734 735 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 736 &max98095_left_hp_mixer_controls[0], 737 ARRAY_SIZE(max98095_left_hp_mixer_controls)), 738 739 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 740 &max98095_right_hp_mixer_controls[0], 741 ARRAY_SIZE(max98095_right_hp_mixer_controls)), 742 743 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 744 &max98095_left_speaker_mixer_controls[0], 745 ARRAY_SIZE(max98095_left_speaker_mixer_controls)), 746 747 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 748 &max98095_right_speaker_mixer_controls[0], 749 ARRAY_SIZE(max98095_right_speaker_mixer_controls)), 750 751 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0, 752 &max98095_mono_rcv_mixer_controls[0], 753 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)), 754 755 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0, 756 &max98095_left_lineout_mixer_controls[0], 757 ARRAY_SIZE(max98095_left_lineout_mixer_controls)), 758 759 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0, 760 &max98095_right_lineout_mixer_controls[0], 761 ARRAY_SIZE(max98095_right_lineout_mixer_controls)), 762 763 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 764 &max98095_left_ADC_mixer_controls[0], 765 ARRAY_SIZE(max98095_left_ADC_mixer_controls)), 766 767 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 768 &max98095_right_ADC_mixer_controls[0], 769 ARRAY_SIZE(max98095_right_ADC_mixer_controls)), 770 771 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1, 772 5, 0, NULL, 0, max98095_mic_event, 773 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 774 775 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2, 776 5, 0, NULL, 0, max98095_mic_event, 777 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 778 779 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN, 780 7, 0, NULL, 0, max98095_pga_in1_event, 781 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 782 783 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN, 784 7, 0, NULL, 0, max98095_pga_in2_event, 785 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 786 787 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0), 788 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0), 789 790 SND_SOC_DAPM_OUTPUT("HPL"), 791 SND_SOC_DAPM_OUTPUT("HPR"), 792 SND_SOC_DAPM_OUTPUT("SPKL"), 793 SND_SOC_DAPM_OUTPUT("SPKR"), 794 SND_SOC_DAPM_OUTPUT("RCV"), 795 SND_SOC_DAPM_OUTPUT("OUT1"), 796 SND_SOC_DAPM_OUTPUT("OUT2"), 797 SND_SOC_DAPM_OUTPUT("OUT3"), 798 SND_SOC_DAPM_OUTPUT("OUT4"), 799 800 SND_SOC_DAPM_INPUT("MIC1"), 801 SND_SOC_DAPM_INPUT("MIC2"), 802 SND_SOC_DAPM_INPUT("INA1"), 803 SND_SOC_DAPM_INPUT("INA2"), 804 SND_SOC_DAPM_INPUT("INB1"), 805 SND_SOC_DAPM_INPUT("INB2"), 806 }; 807 808 static const struct snd_soc_dapm_route max98095_audio_map[] = { 809 /* Left headphone output mixer */ 810 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"}, 811 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"}, 812 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 813 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 814 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"}, 815 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"}, 816 817 /* Right headphone output mixer */ 818 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"}, 819 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"}, 820 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 821 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 822 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"}, 823 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"}, 824 825 /* Left speaker output mixer */ 826 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"}, 827 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"}, 828 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, 829 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, 830 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 831 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 832 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"}, 833 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"}, 834 835 /* Right speaker output mixer */ 836 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"}, 837 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"}, 838 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, 839 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, 840 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 841 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 842 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"}, 843 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"}, 844 845 /* Earpiece/Receiver output mixer */ 846 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"}, 847 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"}, 848 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 849 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 850 {"Receiver Mixer", "IN1 Switch", "IN1 Input"}, 851 {"Receiver Mixer", "IN2 Switch", "IN2 Input"}, 852 853 /* Left Lineout output mixer */ 854 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"}, 855 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"}, 856 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, 857 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, 858 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"}, 859 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"}, 860 861 /* Right lineout output mixer */ 862 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"}, 863 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"}, 864 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, 865 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, 866 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"}, 867 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"}, 868 869 {"HP Left Out", NULL, "Left Headphone Mixer"}, 870 {"HP Right Out", NULL, "Right Headphone Mixer"}, 871 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 872 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 873 {"RCV Mono Out", NULL, "Receiver Mixer"}, 874 {"LINE Left Out", NULL, "Left Lineout Mixer"}, 875 {"LINE Right Out", NULL, "Right Lineout Mixer"}, 876 877 {"HPL", NULL, "HP Left Out"}, 878 {"HPR", NULL, "HP Right Out"}, 879 {"SPKL", NULL, "SPK Left Out"}, 880 {"SPKR", NULL, "SPK Right Out"}, 881 {"RCV", NULL, "RCV Mono Out"}, 882 {"OUT1", NULL, "LINE Left Out"}, 883 {"OUT2", NULL, "LINE Right Out"}, 884 {"OUT3", NULL, "LINE Left Out"}, 885 {"OUT4", NULL, "LINE Right Out"}, 886 887 /* Left ADC input mixer */ 888 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 889 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 890 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"}, 891 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"}, 892 893 /* Right ADC input mixer */ 894 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 895 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 896 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"}, 897 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"}, 898 899 /* Inputs */ 900 {"ADCL", NULL, "Left ADC Mixer"}, 901 {"ADCR", NULL, "Right ADC Mixer"}, 902 903 {"IN1 Input", NULL, "INA1"}, 904 {"IN2 Input", NULL, "INA2"}, 905 906 {"MIC1 Input", NULL, "MIC1"}, 907 {"MIC2 Input", NULL, "MIC2"}, 908 }; 909 910 /* codec mclk clock divider coefficients */ 911 static const struct { 912 u32 rate; 913 u8 sr; 914 } rate_table[] = { 915 {8000, 0x01}, 916 {11025, 0x02}, 917 {16000, 0x03}, 918 {22050, 0x04}, 919 {24000, 0x05}, 920 {32000, 0x06}, 921 {44100, 0x07}, 922 {48000, 0x08}, 923 {88200, 0x09}, 924 {96000, 0x0A}, 925 }; 926 927 static int rate_value(int rate, u8 *value) 928 { 929 int i; 930 931 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 932 if (rate_table[i].rate >= rate) { 933 *value = rate_table[i].sr; 934 return 0; 935 } 936 } 937 *value = rate_table[0].sr; 938 return -EINVAL; 939 } 940 941 static int max98095_dai1_hw_params(struct snd_pcm_substream *substream, 942 struct snd_pcm_hw_params *params, 943 struct snd_soc_dai *dai) 944 { 945 struct snd_soc_codec *codec = dai->codec; 946 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 947 struct max98095_cdata *cdata; 948 unsigned long long ni; 949 unsigned int rate; 950 u8 regval; 951 952 cdata = &max98095->dai[0]; 953 954 rate = params_rate(params); 955 956 switch (params_width(params)) { 957 case 16: 958 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, 959 M98095_DAI_WS, 0); 960 break; 961 case 24: 962 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, 963 M98095_DAI_WS, M98095_DAI_WS); 964 break; 965 default: 966 return -EINVAL; 967 } 968 969 if (rate_value(rate, ®val)) 970 return -EINVAL; 971 972 snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE, 973 M98095_CLKMODE_MASK, regval); 974 cdata->rate = rate; 975 976 /* Configure NI when operating as master */ 977 if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) { 978 if (max98095->sysclk == 0) { 979 dev_err(codec->dev, "Invalid system clock frequency\n"); 980 return -EINVAL; 981 } 982 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 983 * (unsigned long long int)rate; 984 do_div(ni, (unsigned long long int)max98095->sysclk); 985 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, 986 (ni >> 8) & 0x7F); 987 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, 988 ni & 0xFF); 989 } 990 991 /* Update sample rate mode */ 992 if (rate < 50000) 993 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, 994 M98095_DAI_DHF, 0); 995 else 996 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, 997 M98095_DAI_DHF, M98095_DAI_DHF); 998 999 return 0; 1000 } 1001 1002 static int max98095_dai2_hw_params(struct snd_pcm_substream *substream, 1003 struct snd_pcm_hw_params *params, 1004 struct snd_soc_dai *dai) 1005 { 1006 struct snd_soc_codec *codec = dai->codec; 1007 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1008 struct max98095_cdata *cdata; 1009 unsigned long long ni; 1010 unsigned int rate; 1011 u8 regval; 1012 1013 cdata = &max98095->dai[1]; 1014 1015 rate = params_rate(params); 1016 1017 switch (params_width(params)) { 1018 case 16: 1019 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, 1020 M98095_DAI_WS, 0); 1021 break; 1022 case 24: 1023 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, 1024 M98095_DAI_WS, M98095_DAI_WS); 1025 break; 1026 default: 1027 return -EINVAL; 1028 } 1029 1030 if (rate_value(rate, ®val)) 1031 return -EINVAL; 1032 1033 snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE, 1034 M98095_CLKMODE_MASK, regval); 1035 cdata->rate = rate; 1036 1037 /* Configure NI when operating as master */ 1038 if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) { 1039 if (max98095->sysclk == 0) { 1040 dev_err(codec->dev, "Invalid system clock frequency\n"); 1041 return -EINVAL; 1042 } 1043 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1044 * (unsigned long long int)rate; 1045 do_div(ni, (unsigned long long int)max98095->sysclk); 1046 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, 1047 (ni >> 8) & 0x7F); 1048 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, 1049 ni & 0xFF); 1050 } 1051 1052 /* Update sample rate mode */ 1053 if (rate < 50000) 1054 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, 1055 M98095_DAI_DHF, 0); 1056 else 1057 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, 1058 M98095_DAI_DHF, M98095_DAI_DHF); 1059 1060 return 0; 1061 } 1062 1063 static int max98095_dai3_hw_params(struct snd_pcm_substream *substream, 1064 struct snd_pcm_hw_params *params, 1065 struct snd_soc_dai *dai) 1066 { 1067 struct snd_soc_codec *codec = dai->codec; 1068 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1069 struct max98095_cdata *cdata; 1070 unsigned long long ni; 1071 unsigned int rate; 1072 u8 regval; 1073 1074 cdata = &max98095->dai[2]; 1075 1076 rate = params_rate(params); 1077 1078 switch (params_width(params)) { 1079 case 16: 1080 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, 1081 M98095_DAI_WS, 0); 1082 break; 1083 case 24: 1084 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, 1085 M98095_DAI_WS, M98095_DAI_WS); 1086 break; 1087 default: 1088 return -EINVAL; 1089 } 1090 1091 if (rate_value(rate, ®val)) 1092 return -EINVAL; 1093 1094 snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE, 1095 M98095_CLKMODE_MASK, regval); 1096 cdata->rate = rate; 1097 1098 /* Configure NI when operating as master */ 1099 if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) { 1100 if (max98095->sysclk == 0) { 1101 dev_err(codec->dev, "Invalid system clock frequency\n"); 1102 return -EINVAL; 1103 } 1104 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1105 * (unsigned long long int)rate; 1106 do_div(ni, (unsigned long long int)max98095->sysclk); 1107 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, 1108 (ni >> 8) & 0x7F); 1109 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, 1110 ni & 0xFF); 1111 } 1112 1113 /* Update sample rate mode */ 1114 if (rate < 50000) 1115 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, 1116 M98095_DAI_DHF, 0); 1117 else 1118 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, 1119 M98095_DAI_DHF, M98095_DAI_DHF); 1120 1121 return 0; 1122 } 1123 1124 static int max98095_dai_set_sysclk(struct snd_soc_dai *dai, 1125 int clk_id, unsigned int freq, int dir) 1126 { 1127 struct snd_soc_codec *codec = dai->codec; 1128 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1129 1130 /* Requested clock frequency is already setup */ 1131 if (freq == max98095->sysclk) 1132 return 0; 1133 1134 if (!IS_ERR(max98095->mclk)) { 1135 freq = clk_round_rate(max98095->mclk, freq); 1136 clk_set_rate(max98095->mclk, freq); 1137 } 1138 1139 /* Setup clocks for slave mode, and using the PLL 1140 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1141 * 0x02 (when master clk is 20MHz to 40MHz).. 1142 * 0x03 (when master clk is 40MHz to 60MHz).. 1143 */ 1144 if ((freq >= 10000000) && (freq < 20000000)) { 1145 snd_soc_write(codec, M98095_026_SYS_CLK, 0x10); 1146 } else if ((freq >= 20000000) && (freq < 40000000)) { 1147 snd_soc_write(codec, M98095_026_SYS_CLK, 0x20); 1148 } else if ((freq >= 40000000) && (freq < 60000000)) { 1149 snd_soc_write(codec, M98095_026_SYS_CLK, 0x30); 1150 } else { 1151 dev_err(codec->dev, "Invalid master clock frequency\n"); 1152 return -EINVAL; 1153 } 1154 1155 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1156 1157 max98095->sysclk = freq; 1158 return 0; 1159 } 1160 1161 static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai, 1162 unsigned int fmt) 1163 { 1164 struct snd_soc_codec *codec = codec_dai->codec; 1165 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1166 struct max98095_cdata *cdata; 1167 u8 regval = 0; 1168 1169 cdata = &max98095->dai[0]; 1170 1171 if (fmt != cdata->fmt) { 1172 cdata->fmt = fmt; 1173 1174 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1175 case SND_SOC_DAIFMT_CBS_CFS: 1176 /* Slave mode PLL */ 1177 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, 1178 0x80); 1179 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, 1180 0x00); 1181 break; 1182 case SND_SOC_DAIFMT_CBM_CFM: 1183 /* Set to master mode */ 1184 regval |= M98095_DAI_MAS; 1185 break; 1186 case SND_SOC_DAIFMT_CBS_CFM: 1187 case SND_SOC_DAIFMT_CBM_CFS: 1188 default: 1189 dev_err(codec->dev, "Clock mode unsupported"); 1190 return -EINVAL; 1191 } 1192 1193 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1194 case SND_SOC_DAIFMT_I2S: 1195 regval |= M98095_DAI_DLY; 1196 break; 1197 case SND_SOC_DAIFMT_LEFT_J: 1198 break; 1199 default: 1200 return -EINVAL; 1201 } 1202 1203 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1204 case SND_SOC_DAIFMT_NB_NF: 1205 break; 1206 case SND_SOC_DAIFMT_NB_IF: 1207 regval |= M98095_DAI_WCI; 1208 break; 1209 case SND_SOC_DAIFMT_IB_NF: 1210 regval |= M98095_DAI_BCI; 1211 break; 1212 case SND_SOC_DAIFMT_IB_IF: 1213 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1214 break; 1215 default: 1216 return -EINVAL; 1217 } 1218 1219 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, 1220 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1221 M98095_DAI_WCI, regval); 1222 1223 snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64); 1224 } 1225 1226 return 0; 1227 } 1228 1229 static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai, 1230 unsigned int fmt) 1231 { 1232 struct snd_soc_codec *codec = codec_dai->codec; 1233 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1234 struct max98095_cdata *cdata; 1235 u8 regval = 0; 1236 1237 cdata = &max98095->dai[1]; 1238 1239 if (fmt != cdata->fmt) { 1240 cdata->fmt = fmt; 1241 1242 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1243 case SND_SOC_DAIFMT_CBS_CFS: 1244 /* Slave mode PLL */ 1245 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, 1246 0x80); 1247 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, 1248 0x00); 1249 break; 1250 case SND_SOC_DAIFMT_CBM_CFM: 1251 /* Set to master mode */ 1252 regval |= M98095_DAI_MAS; 1253 break; 1254 case SND_SOC_DAIFMT_CBS_CFM: 1255 case SND_SOC_DAIFMT_CBM_CFS: 1256 default: 1257 dev_err(codec->dev, "Clock mode unsupported"); 1258 return -EINVAL; 1259 } 1260 1261 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1262 case SND_SOC_DAIFMT_I2S: 1263 regval |= M98095_DAI_DLY; 1264 break; 1265 case SND_SOC_DAIFMT_LEFT_J: 1266 break; 1267 default: 1268 return -EINVAL; 1269 } 1270 1271 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1272 case SND_SOC_DAIFMT_NB_NF: 1273 break; 1274 case SND_SOC_DAIFMT_NB_IF: 1275 regval |= M98095_DAI_WCI; 1276 break; 1277 case SND_SOC_DAIFMT_IB_NF: 1278 regval |= M98095_DAI_BCI; 1279 break; 1280 case SND_SOC_DAIFMT_IB_IF: 1281 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1282 break; 1283 default: 1284 return -EINVAL; 1285 } 1286 1287 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, 1288 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1289 M98095_DAI_WCI, regval); 1290 1291 snd_soc_write(codec, M98095_035_DAI2_CLOCK, 1292 M98095_DAI_BSEL64); 1293 } 1294 1295 return 0; 1296 } 1297 1298 static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai, 1299 unsigned int fmt) 1300 { 1301 struct snd_soc_codec *codec = codec_dai->codec; 1302 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1303 struct max98095_cdata *cdata; 1304 u8 regval = 0; 1305 1306 cdata = &max98095->dai[2]; 1307 1308 if (fmt != cdata->fmt) { 1309 cdata->fmt = fmt; 1310 1311 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1312 case SND_SOC_DAIFMT_CBS_CFS: 1313 /* Slave mode PLL */ 1314 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, 1315 0x80); 1316 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, 1317 0x00); 1318 break; 1319 case SND_SOC_DAIFMT_CBM_CFM: 1320 /* Set to master mode */ 1321 regval |= M98095_DAI_MAS; 1322 break; 1323 case SND_SOC_DAIFMT_CBS_CFM: 1324 case SND_SOC_DAIFMT_CBM_CFS: 1325 default: 1326 dev_err(codec->dev, "Clock mode unsupported"); 1327 return -EINVAL; 1328 } 1329 1330 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1331 case SND_SOC_DAIFMT_I2S: 1332 regval |= M98095_DAI_DLY; 1333 break; 1334 case SND_SOC_DAIFMT_LEFT_J: 1335 break; 1336 default: 1337 return -EINVAL; 1338 } 1339 1340 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1341 case SND_SOC_DAIFMT_NB_NF: 1342 break; 1343 case SND_SOC_DAIFMT_NB_IF: 1344 regval |= M98095_DAI_WCI; 1345 break; 1346 case SND_SOC_DAIFMT_IB_NF: 1347 regval |= M98095_DAI_BCI; 1348 break; 1349 case SND_SOC_DAIFMT_IB_IF: 1350 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1351 break; 1352 default: 1353 return -EINVAL; 1354 } 1355 1356 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, 1357 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1358 M98095_DAI_WCI, regval); 1359 1360 snd_soc_write(codec, M98095_03F_DAI3_CLOCK, 1361 M98095_DAI_BSEL64); 1362 } 1363 1364 return 0; 1365 } 1366 1367 static int max98095_set_bias_level(struct snd_soc_codec *codec, 1368 enum snd_soc_bias_level level) 1369 { 1370 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1371 int ret; 1372 1373 switch (level) { 1374 case SND_SOC_BIAS_ON: 1375 break; 1376 1377 case SND_SOC_BIAS_PREPARE: 1378 /* 1379 * SND_SOC_BIAS_PREPARE is called while preparing for a 1380 * transition to ON or away from ON. If current bias_level 1381 * is SND_SOC_BIAS_ON, then it is preparing for a transition 1382 * away from ON. Disable the clock in that case, otherwise 1383 * enable it. 1384 */ 1385 if (IS_ERR(max98095->mclk)) 1386 break; 1387 1388 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) { 1389 clk_disable_unprepare(max98095->mclk); 1390 } else { 1391 ret = clk_prepare_enable(max98095->mclk); 1392 if (ret) 1393 return ret; 1394 } 1395 break; 1396 1397 case SND_SOC_BIAS_STANDBY: 1398 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { 1399 ret = regcache_sync(max98095->regmap); 1400 1401 if (ret != 0) { 1402 dev_err(codec->dev, "Failed to sync cache: %d\n", ret); 1403 return ret; 1404 } 1405 } 1406 1407 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, 1408 M98095_MBEN, M98095_MBEN); 1409 break; 1410 1411 case SND_SOC_BIAS_OFF: 1412 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, 1413 M98095_MBEN, 0); 1414 regcache_mark_dirty(max98095->regmap); 1415 break; 1416 } 1417 return 0; 1418 } 1419 1420 #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000 1421 #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 1422 1423 static const struct snd_soc_dai_ops max98095_dai1_ops = { 1424 .set_sysclk = max98095_dai_set_sysclk, 1425 .set_fmt = max98095_dai1_set_fmt, 1426 .hw_params = max98095_dai1_hw_params, 1427 }; 1428 1429 static const struct snd_soc_dai_ops max98095_dai2_ops = { 1430 .set_sysclk = max98095_dai_set_sysclk, 1431 .set_fmt = max98095_dai2_set_fmt, 1432 .hw_params = max98095_dai2_hw_params, 1433 }; 1434 1435 static const struct snd_soc_dai_ops max98095_dai3_ops = { 1436 .set_sysclk = max98095_dai_set_sysclk, 1437 .set_fmt = max98095_dai3_set_fmt, 1438 .hw_params = max98095_dai3_hw_params, 1439 }; 1440 1441 static struct snd_soc_dai_driver max98095_dai[] = { 1442 { 1443 .name = "HiFi", 1444 .playback = { 1445 .stream_name = "HiFi Playback", 1446 .channels_min = 1, 1447 .channels_max = 2, 1448 .rates = MAX98095_RATES, 1449 .formats = MAX98095_FORMATS, 1450 }, 1451 .capture = { 1452 .stream_name = "HiFi Capture", 1453 .channels_min = 1, 1454 .channels_max = 2, 1455 .rates = MAX98095_RATES, 1456 .formats = MAX98095_FORMATS, 1457 }, 1458 .ops = &max98095_dai1_ops, 1459 }, 1460 { 1461 .name = "Aux", 1462 .playback = { 1463 .stream_name = "Aux Playback", 1464 .channels_min = 1, 1465 .channels_max = 1, 1466 .rates = MAX98095_RATES, 1467 .formats = MAX98095_FORMATS, 1468 }, 1469 .ops = &max98095_dai2_ops, 1470 }, 1471 { 1472 .name = "Voice", 1473 .playback = { 1474 .stream_name = "Voice Playback", 1475 .channels_min = 1, 1476 .channels_max = 1, 1477 .rates = MAX98095_RATES, 1478 .formats = MAX98095_FORMATS, 1479 }, 1480 .ops = &max98095_dai3_ops, 1481 } 1482 1483 }; 1484 1485 static int max98095_get_eq_channel(const char *name) 1486 { 1487 if (strcmp(name, "EQ1 Mode") == 0) 1488 return 0; 1489 if (strcmp(name, "EQ2 Mode") == 0) 1490 return 1; 1491 return -EINVAL; 1492 } 1493 1494 static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol, 1495 struct snd_ctl_elem_value *ucontrol) 1496 { 1497 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1498 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1499 struct max98095_pdata *pdata = max98095->pdata; 1500 int channel = max98095_get_eq_channel(kcontrol->id.name); 1501 struct max98095_cdata *cdata; 1502 unsigned int sel = ucontrol->value.enumerated.item[0]; 1503 struct max98095_eq_cfg *coef_set; 1504 int fs, best, best_val, i; 1505 int regmask, regsave; 1506 1507 if (WARN_ON(channel > 1)) 1508 return -EINVAL; 1509 1510 if (!pdata || !max98095->eq_textcnt) 1511 return 0; 1512 1513 if (sel >= pdata->eq_cfgcnt) 1514 return -EINVAL; 1515 1516 cdata = &max98095->dai[channel]; 1517 cdata->eq_sel = sel; 1518 fs = cdata->rate; 1519 1520 /* Find the selected configuration with nearest sample rate */ 1521 best = 0; 1522 best_val = INT_MAX; 1523 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1524 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 && 1525 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1526 best = i; 1527 best_val = abs(pdata->eq_cfg[i].rate - fs); 1528 } 1529 } 1530 1531 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 1532 pdata->eq_cfg[best].name, 1533 pdata->eq_cfg[best].rate, fs); 1534 1535 coef_set = &pdata->eq_cfg[best]; 1536 1537 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN; 1538 1539 /* Disable filter while configuring, and save current on/off state */ 1540 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); 1541 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); 1542 1543 mutex_lock(&max98095->lock); 1544 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); 1545 m98095_eq_band(codec, channel, 0, coef_set->band1); 1546 m98095_eq_band(codec, channel, 1, coef_set->band2); 1547 m98095_eq_band(codec, channel, 2, coef_set->band3); 1548 m98095_eq_band(codec, channel, 3, coef_set->band4); 1549 m98095_eq_band(codec, channel, 4, coef_set->band5); 1550 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); 1551 mutex_unlock(&max98095->lock); 1552 1553 /* Restore the original on/off state */ 1554 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); 1555 return 0; 1556 } 1557 1558 static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol, 1559 struct snd_ctl_elem_value *ucontrol) 1560 { 1561 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1562 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1563 int channel = max98095_get_eq_channel(kcontrol->id.name); 1564 struct max98095_cdata *cdata; 1565 1566 cdata = &max98095->dai[channel]; 1567 ucontrol->value.enumerated.item[0] = cdata->eq_sel; 1568 1569 return 0; 1570 } 1571 1572 static void max98095_handle_eq_pdata(struct snd_soc_codec *codec) 1573 { 1574 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1575 struct max98095_pdata *pdata = max98095->pdata; 1576 struct max98095_eq_cfg *cfg; 1577 unsigned int cfgcnt; 1578 int i, j; 1579 const char **t; 1580 int ret; 1581 1582 struct snd_kcontrol_new controls[] = { 1583 SOC_ENUM_EXT("EQ1 Mode", 1584 max98095->eq_enum, 1585 max98095_get_eq_enum, 1586 max98095_put_eq_enum), 1587 SOC_ENUM_EXT("EQ2 Mode", 1588 max98095->eq_enum, 1589 max98095_get_eq_enum, 1590 max98095_put_eq_enum), 1591 }; 1592 1593 cfg = pdata->eq_cfg; 1594 cfgcnt = pdata->eq_cfgcnt; 1595 1596 /* Setup an array of texts for the equalizer enum. 1597 * This is based on Mark Brown's equalizer driver code. 1598 */ 1599 max98095->eq_textcnt = 0; 1600 max98095->eq_texts = NULL; 1601 for (i = 0; i < cfgcnt; i++) { 1602 for (j = 0; j < max98095->eq_textcnt; j++) { 1603 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0) 1604 break; 1605 } 1606 1607 if (j != max98095->eq_textcnt) 1608 continue; 1609 1610 /* Expand the array */ 1611 t = krealloc(max98095->eq_texts, 1612 sizeof(char *) * (max98095->eq_textcnt + 1), 1613 GFP_KERNEL); 1614 if (t == NULL) 1615 continue; 1616 1617 /* Store the new entry */ 1618 t[max98095->eq_textcnt] = cfg[i].name; 1619 max98095->eq_textcnt++; 1620 max98095->eq_texts = t; 1621 } 1622 1623 /* Now point the soc_enum to .texts array items */ 1624 max98095->eq_enum.texts = max98095->eq_texts; 1625 max98095->eq_enum.items = max98095->eq_textcnt; 1626 1627 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 1628 if (ret != 0) 1629 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret); 1630 } 1631 1632 static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"}; 1633 1634 static int max98095_get_bq_channel(struct snd_soc_codec *codec, 1635 const char *name) 1636 { 1637 int i; 1638 1639 for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++) 1640 if (strcmp(name, bq_mode_name[i]) == 0) 1641 return i; 1642 1643 /* Shouldn't happen */ 1644 dev_err(codec->dev, "Bad biquad channel name '%s'\n", name); 1645 return -EINVAL; 1646 } 1647 1648 static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol, 1649 struct snd_ctl_elem_value *ucontrol) 1650 { 1651 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1652 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1653 struct max98095_pdata *pdata = max98095->pdata; 1654 int channel = max98095_get_bq_channel(codec, kcontrol->id.name); 1655 struct max98095_cdata *cdata; 1656 unsigned int sel = ucontrol->value.enumerated.item[0]; 1657 struct max98095_biquad_cfg *coef_set; 1658 int fs, best, best_val, i; 1659 int regmask, regsave; 1660 1661 if (channel < 0) 1662 return channel; 1663 1664 if (!pdata || !max98095->bq_textcnt) 1665 return 0; 1666 1667 if (sel >= pdata->bq_cfgcnt) 1668 return -EINVAL; 1669 1670 cdata = &max98095->dai[channel]; 1671 cdata->bq_sel = sel; 1672 fs = cdata->rate; 1673 1674 /* Find the selected configuration with nearest sample rate */ 1675 best = 0; 1676 best_val = INT_MAX; 1677 for (i = 0; i < pdata->bq_cfgcnt; i++) { 1678 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 && 1679 abs(pdata->bq_cfg[i].rate - fs) < best_val) { 1680 best = i; 1681 best_val = abs(pdata->bq_cfg[i].rate - fs); 1682 } 1683 } 1684 1685 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 1686 pdata->bq_cfg[best].name, 1687 pdata->bq_cfg[best].rate, fs); 1688 1689 coef_set = &pdata->bq_cfg[best]; 1690 1691 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN; 1692 1693 /* Disable filter while configuring, and save current on/off state */ 1694 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); 1695 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); 1696 1697 mutex_lock(&max98095->lock); 1698 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); 1699 m98095_biquad_band(codec, channel, 0, coef_set->band1); 1700 m98095_biquad_band(codec, channel, 1, coef_set->band2); 1701 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); 1702 mutex_unlock(&max98095->lock); 1703 1704 /* Restore the original on/off state */ 1705 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); 1706 return 0; 1707 } 1708 1709 static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol, 1710 struct snd_ctl_elem_value *ucontrol) 1711 { 1712 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 1713 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1714 int channel = max98095_get_bq_channel(codec, kcontrol->id.name); 1715 struct max98095_cdata *cdata; 1716 1717 if (channel < 0) 1718 return channel; 1719 1720 cdata = &max98095->dai[channel]; 1721 ucontrol->value.enumerated.item[0] = cdata->bq_sel; 1722 1723 return 0; 1724 } 1725 1726 static void max98095_handle_bq_pdata(struct snd_soc_codec *codec) 1727 { 1728 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1729 struct max98095_pdata *pdata = max98095->pdata; 1730 struct max98095_biquad_cfg *cfg; 1731 unsigned int cfgcnt; 1732 int i, j; 1733 const char **t; 1734 int ret; 1735 1736 struct snd_kcontrol_new controls[] = { 1737 SOC_ENUM_EXT((char *)bq_mode_name[0], 1738 max98095->bq_enum, 1739 max98095_get_bq_enum, 1740 max98095_put_bq_enum), 1741 SOC_ENUM_EXT((char *)bq_mode_name[1], 1742 max98095->bq_enum, 1743 max98095_get_bq_enum, 1744 max98095_put_bq_enum), 1745 }; 1746 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name)); 1747 1748 cfg = pdata->bq_cfg; 1749 cfgcnt = pdata->bq_cfgcnt; 1750 1751 /* Setup an array of texts for the biquad enum. 1752 * This is based on Mark Brown's equalizer driver code. 1753 */ 1754 max98095->bq_textcnt = 0; 1755 max98095->bq_texts = NULL; 1756 for (i = 0; i < cfgcnt; i++) { 1757 for (j = 0; j < max98095->bq_textcnt; j++) { 1758 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0) 1759 break; 1760 } 1761 1762 if (j != max98095->bq_textcnt) 1763 continue; 1764 1765 /* Expand the array */ 1766 t = krealloc(max98095->bq_texts, 1767 sizeof(char *) * (max98095->bq_textcnt + 1), 1768 GFP_KERNEL); 1769 if (t == NULL) 1770 continue; 1771 1772 /* Store the new entry */ 1773 t[max98095->bq_textcnt] = cfg[i].name; 1774 max98095->bq_textcnt++; 1775 max98095->bq_texts = t; 1776 } 1777 1778 /* Now point the soc_enum to .texts array items */ 1779 max98095->bq_enum.texts = max98095->bq_texts; 1780 max98095->bq_enum.items = max98095->bq_textcnt; 1781 1782 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 1783 if (ret != 0) 1784 dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret); 1785 } 1786 1787 static void max98095_handle_pdata(struct snd_soc_codec *codec) 1788 { 1789 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1790 struct max98095_pdata *pdata = max98095->pdata; 1791 u8 regval = 0; 1792 1793 if (!pdata) { 1794 dev_dbg(codec->dev, "No platform data\n"); 1795 return; 1796 } 1797 1798 /* Configure mic for analog/digital mic mode */ 1799 if (pdata->digmic_left_mode) 1800 regval |= M98095_DIGMIC_L; 1801 1802 if (pdata->digmic_right_mode) 1803 regval |= M98095_DIGMIC_R; 1804 1805 snd_soc_write(codec, M98095_087_CFG_MIC, regval); 1806 1807 /* Configure equalizers */ 1808 if (pdata->eq_cfgcnt) 1809 max98095_handle_eq_pdata(codec); 1810 1811 /* Configure bi-quad filters */ 1812 if (pdata->bq_cfgcnt) 1813 max98095_handle_bq_pdata(codec); 1814 } 1815 1816 static irqreturn_t max98095_report_jack(int irq, void *data) 1817 { 1818 struct snd_soc_codec *codec = data; 1819 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1820 unsigned int value; 1821 int hp_report = 0; 1822 int mic_report = 0; 1823 1824 /* Read the Jack Status Register */ 1825 value = snd_soc_read(codec, M98095_007_JACK_AUTO_STS); 1826 1827 /* If ddone is not set, then detection isn't finished yet */ 1828 if ((value & M98095_DDONE) == 0) 1829 return IRQ_NONE; 1830 1831 /* if hp, check its bit, and if set, clear it */ 1832 if ((value & M98095_HP_IN || value & M98095_LO_IN) && 1833 max98095->headphone_jack) 1834 hp_report |= SND_JACK_HEADPHONE; 1835 1836 /* if mic, check its bit, and if set, clear it */ 1837 if ((value & M98095_MIC_IN) && max98095->mic_jack) 1838 mic_report |= SND_JACK_MICROPHONE; 1839 1840 if (max98095->headphone_jack == max98095->mic_jack) { 1841 snd_soc_jack_report(max98095->headphone_jack, 1842 hp_report | mic_report, 1843 SND_JACK_HEADSET); 1844 } else { 1845 if (max98095->headphone_jack) 1846 snd_soc_jack_report(max98095->headphone_jack, 1847 hp_report, SND_JACK_HEADPHONE); 1848 if (max98095->mic_jack) 1849 snd_soc_jack_report(max98095->mic_jack, 1850 mic_report, SND_JACK_MICROPHONE); 1851 } 1852 1853 return IRQ_HANDLED; 1854 } 1855 1856 static int max98095_jack_detect_enable(struct snd_soc_codec *codec) 1857 { 1858 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1859 int ret = 0; 1860 int detect_enable = M98095_JDEN; 1861 unsigned int slew = M98095_DEFAULT_SLEW_DELAY; 1862 1863 if (max98095->pdata->jack_detect_pin5en) 1864 detect_enable |= M98095_PIN5EN; 1865 1866 if (max98095->pdata->jack_detect_delay) 1867 slew = max98095->pdata->jack_detect_delay; 1868 1869 ret = snd_soc_write(codec, M98095_08E_JACK_DC_SLEW, slew); 1870 if (ret < 0) { 1871 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret); 1872 return ret; 1873 } 1874 1875 /* configure auto detection to be enabled */ 1876 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, detect_enable); 1877 if (ret < 0) { 1878 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret); 1879 return ret; 1880 } 1881 1882 return ret; 1883 } 1884 1885 static int max98095_jack_detect_disable(struct snd_soc_codec *codec) 1886 { 1887 int ret = 0; 1888 1889 /* configure auto detection to be disabled */ 1890 ret = snd_soc_write(codec, M98095_089_JACK_DET_AUTO, 0x0); 1891 if (ret < 0) { 1892 dev_err(codec->dev, "Failed to cfg auto detect %d\n", ret); 1893 return ret; 1894 } 1895 1896 return ret; 1897 } 1898 1899 int max98095_jack_detect(struct snd_soc_codec *codec, 1900 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack) 1901 { 1902 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1903 struct i2c_client *client = to_i2c_client(codec->dev); 1904 int ret = 0; 1905 1906 max98095->headphone_jack = hp_jack; 1907 max98095->mic_jack = mic_jack; 1908 1909 /* only progress if we have at least 1 jack pointer */ 1910 if (!hp_jack && !mic_jack) 1911 return -EINVAL; 1912 1913 max98095_jack_detect_enable(codec); 1914 1915 /* enable interrupts for headphone jack detection */ 1916 ret = snd_soc_update_bits(codec, M98095_013_JACK_INT_EN, 1917 M98095_IDDONE, M98095_IDDONE); 1918 if (ret < 0) { 1919 dev_err(codec->dev, "Failed to cfg jack irqs %d\n", ret); 1920 return ret; 1921 } 1922 1923 max98095_report_jack(client->irq, codec); 1924 return 0; 1925 } 1926 EXPORT_SYMBOL_GPL(max98095_jack_detect); 1927 1928 #ifdef CONFIG_PM 1929 static int max98095_suspend(struct snd_soc_codec *codec) 1930 { 1931 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1932 1933 if (max98095->headphone_jack || max98095->mic_jack) 1934 max98095_jack_detect_disable(codec); 1935 1936 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF); 1937 1938 return 0; 1939 } 1940 1941 static int max98095_resume(struct snd_soc_codec *codec) 1942 { 1943 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1944 struct i2c_client *client = to_i2c_client(codec->dev); 1945 1946 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY); 1947 1948 if (max98095->headphone_jack || max98095->mic_jack) { 1949 max98095_jack_detect_enable(codec); 1950 max98095_report_jack(client->irq, codec); 1951 } 1952 1953 return 0; 1954 } 1955 #else 1956 #define max98095_suspend NULL 1957 #define max98095_resume NULL 1958 #endif 1959 1960 static int max98095_reset(struct snd_soc_codec *codec) 1961 { 1962 int i, ret; 1963 1964 /* Gracefully reset the DSP core and the codec hardware 1965 * in a proper sequence */ 1966 ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0); 1967 if (ret < 0) { 1968 dev_err(codec->dev, "Failed to reset DSP: %d\n", ret); 1969 return ret; 1970 } 1971 1972 ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0); 1973 if (ret < 0) { 1974 dev_err(codec->dev, "Failed to reset codec: %d\n", ret); 1975 return ret; 1976 } 1977 1978 /* Reset to hardware default for registers, as there is not 1979 * a soft reset hardware control register */ 1980 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { 1981 ret = snd_soc_write(codec, i, snd_soc_read(codec, i)); 1982 if (ret < 0) { 1983 dev_err(codec->dev, "Failed to reset: %d\n", ret); 1984 return ret; 1985 } 1986 } 1987 1988 return ret; 1989 } 1990 1991 static int max98095_probe(struct snd_soc_codec *codec) 1992 { 1993 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1994 struct max98095_cdata *cdata; 1995 struct i2c_client *client; 1996 int ret = 0; 1997 1998 max98095->mclk = devm_clk_get(codec->dev, "mclk"); 1999 if (PTR_ERR(max98095->mclk) == -EPROBE_DEFER) 2000 return -EPROBE_DEFER; 2001 2002 /* reset the codec, the DSP core, and disable all interrupts */ 2003 max98095_reset(codec); 2004 2005 client = to_i2c_client(codec->dev); 2006 2007 /* initialize private data */ 2008 2009 max98095->sysclk = (unsigned)-1; 2010 max98095->eq_textcnt = 0; 2011 max98095->bq_textcnt = 0; 2012 2013 cdata = &max98095->dai[0]; 2014 cdata->rate = (unsigned)-1; 2015 cdata->fmt = (unsigned)-1; 2016 cdata->eq_sel = 0; 2017 cdata->bq_sel = 0; 2018 2019 cdata = &max98095->dai[1]; 2020 cdata->rate = (unsigned)-1; 2021 cdata->fmt = (unsigned)-1; 2022 cdata->eq_sel = 0; 2023 cdata->bq_sel = 0; 2024 2025 cdata = &max98095->dai[2]; 2026 cdata->rate = (unsigned)-1; 2027 cdata->fmt = (unsigned)-1; 2028 cdata->eq_sel = 0; 2029 cdata->bq_sel = 0; 2030 2031 max98095->lin_state = 0; 2032 max98095->mic1pre = 0; 2033 max98095->mic2pre = 0; 2034 2035 if (client->irq) { 2036 /* register an audio interrupt */ 2037 ret = request_threaded_irq(client->irq, NULL, 2038 max98095_report_jack, 2039 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING | 2040 IRQF_ONESHOT, "max98095", codec); 2041 if (ret) { 2042 dev_err(codec->dev, "Failed to request IRQ: %d\n", ret); 2043 goto err_access; 2044 } 2045 } 2046 2047 ret = snd_soc_read(codec, M98095_0FF_REV_ID); 2048 if (ret < 0) { 2049 dev_err(codec->dev, "Failure reading hardware revision: %d\n", 2050 ret); 2051 goto err_irq; 2052 } 2053 dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A'); 2054 2055 snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV); 2056 2057 snd_soc_write(codec, M98095_048_MIX_DAC_LR, 2058 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR); 2059 2060 snd_soc_write(codec, M98095_049_MIX_DAC_M, 2061 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM); 2062 2063 snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM); 2064 snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL); 2065 snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL); 2066 2067 snd_soc_write(codec, M98095_02C_DAI1_IOCFG, 2068 M98095_S1NORMAL|M98095_SDATA); 2069 2070 snd_soc_write(codec, M98095_036_DAI2_IOCFG, 2071 M98095_S2NORMAL|M98095_SDATA); 2072 2073 snd_soc_write(codec, M98095_040_DAI3_IOCFG, 2074 M98095_S3NORMAL|M98095_SDATA); 2075 2076 max98095_handle_pdata(codec); 2077 2078 /* take the codec out of the shut down */ 2079 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN, 2080 M98095_SHDNRUN); 2081 2082 return 0; 2083 2084 err_irq: 2085 if (client->irq) 2086 free_irq(client->irq, codec); 2087 err_access: 2088 return ret; 2089 } 2090 2091 static int max98095_remove(struct snd_soc_codec *codec) 2092 { 2093 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2094 struct i2c_client *client = to_i2c_client(codec->dev); 2095 2096 if (max98095->headphone_jack || max98095->mic_jack) 2097 max98095_jack_detect_disable(codec); 2098 2099 if (client->irq) 2100 free_irq(client->irq, codec); 2101 2102 return 0; 2103 } 2104 2105 static struct snd_soc_codec_driver soc_codec_dev_max98095 = { 2106 .probe = max98095_probe, 2107 .remove = max98095_remove, 2108 .suspend = max98095_suspend, 2109 .resume = max98095_resume, 2110 .set_bias_level = max98095_set_bias_level, 2111 .component_driver = { 2112 .controls = max98095_snd_controls, 2113 .num_controls = ARRAY_SIZE(max98095_snd_controls), 2114 .dapm_widgets = max98095_dapm_widgets, 2115 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets), 2116 .dapm_routes = max98095_audio_map, 2117 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map), 2118 }, 2119 }; 2120 2121 static int max98095_i2c_probe(struct i2c_client *i2c, 2122 const struct i2c_device_id *id) 2123 { 2124 struct max98095_priv *max98095; 2125 int ret; 2126 2127 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv), 2128 GFP_KERNEL); 2129 if (max98095 == NULL) 2130 return -ENOMEM; 2131 2132 mutex_init(&max98095->lock); 2133 2134 max98095->regmap = devm_regmap_init_i2c(i2c, &max98095_regmap); 2135 if (IS_ERR(max98095->regmap)) { 2136 ret = PTR_ERR(max98095->regmap); 2137 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 2138 return ret; 2139 } 2140 2141 max98095->devtype = id->driver_data; 2142 i2c_set_clientdata(i2c, max98095); 2143 max98095->pdata = i2c->dev.platform_data; 2144 2145 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095, 2146 max98095_dai, ARRAY_SIZE(max98095_dai)); 2147 return ret; 2148 } 2149 2150 static int max98095_i2c_remove(struct i2c_client *client) 2151 { 2152 snd_soc_unregister_codec(&client->dev); 2153 return 0; 2154 } 2155 2156 static const struct i2c_device_id max98095_i2c_id[] = { 2157 { "max98095", MAX98095 }, 2158 { } 2159 }; 2160 MODULE_DEVICE_TABLE(i2c, max98095_i2c_id); 2161 2162 static const struct of_device_id max98095_of_match[] = { 2163 { .compatible = "maxim,max98095", }, 2164 { } 2165 }; 2166 MODULE_DEVICE_TABLE(of, max98095_of_match); 2167 2168 static struct i2c_driver max98095_i2c_driver = { 2169 .driver = { 2170 .name = "max98095", 2171 .of_match_table = of_match_ptr(max98095_of_match), 2172 }, 2173 .probe = max98095_i2c_probe, 2174 .remove = max98095_i2c_remove, 2175 .id_table = max98095_i2c_id, 2176 }; 2177 2178 module_i2c_driver(max98095_i2c_driver); 2179 2180 MODULE_DESCRIPTION("ALSA SoC MAX98095 driver"); 2181 MODULE_AUTHOR("Peter Hsiang"); 2182 MODULE_LICENSE("GPL"); 2183