1 /* 2 * max98095.c -- MAX98095 ALSA SoC Audio driver 3 * 4 * Copyright 2011 Maxim Integrated Products 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/initval.h> 23 #include <sound/tlv.h> 24 #include <linux/slab.h> 25 #include <asm/div64.h> 26 #include <sound/max98095.h> 27 #include "max98095.h" 28 29 enum max98095_type { 30 MAX98095, 31 }; 32 33 struct max98095_cdata { 34 unsigned int rate; 35 unsigned int fmt; 36 int eq_sel; 37 int bq_sel; 38 }; 39 40 struct max98095_priv { 41 enum max98095_type devtype; 42 struct max98095_pdata *pdata; 43 unsigned int sysclk; 44 struct max98095_cdata dai[3]; 45 const char **eq_texts; 46 const char **bq_texts; 47 struct soc_enum eq_enum; 48 struct soc_enum bq_enum; 49 int eq_textcnt; 50 int bq_textcnt; 51 u8 lin_state; 52 unsigned int mic1pre; 53 unsigned int mic2pre; 54 }; 55 56 static const u8 max98095_reg_def[M98095_REG_CNT] = { 57 0x00, /* 00 */ 58 0x00, /* 01 */ 59 0x00, /* 02 */ 60 0x00, /* 03 */ 61 0x00, /* 04 */ 62 0x00, /* 05 */ 63 0x00, /* 06 */ 64 0x00, /* 07 */ 65 0x00, /* 08 */ 66 0x00, /* 09 */ 67 0x00, /* 0A */ 68 0x00, /* 0B */ 69 0x00, /* 0C */ 70 0x00, /* 0D */ 71 0x00, /* 0E */ 72 0x00, /* 0F */ 73 0x00, /* 10 */ 74 0x00, /* 11 */ 75 0x00, /* 12 */ 76 0x00, /* 13 */ 77 0x00, /* 14 */ 78 0x00, /* 15 */ 79 0x00, /* 16 */ 80 0x00, /* 17 */ 81 0x00, /* 18 */ 82 0x00, /* 19 */ 83 0x00, /* 1A */ 84 0x00, /* 1B */ 85 0x00, /* 1C */ 86 0x00, /* 1D */ 87 0x00, /* 1E */ 88 0x00, /* 1F */ 89 0x00, /* 20 */ 90 0x00, /* 21 */ 91 0x00, /* 22 */ 92 0x00, /* 23 */ 93 0x00, /* 24 */ 94 0x00, /* 25 */ 95 0x00, /* 26 */ 96 0x00, /* 27 */ 97 0x00, /* 28 */ 98 0x00, /* 29 */ 99 0x00, /* 2A */ 100 0x00, /* 2B */ 101 0x00, /* 2C */ 102 0x00, /* 2D */ 103 0x00, /* 2E */ 104 0x00, /* 2F */ 105 0x00, /* 30 */ 106 0x00, /* 31 */ 107 0x00, /* 32 */ 108 0x00, /* 33 */ 109 0x00, /* 34 */ 110 0x00, /* 35 */ 111 0x00, /* 36 */ 112 0x00, /* 37 */ 113 0x00, /* 38 */ 114 0x00, /* 39 */ 115 0x00, /* 3A */ 116 0x00, /* 3B */ 117 0x00, /* 3C */ 118 0x00, /* 3D */ 119 0x00, /* 3E */ 120 0x00, /* 3F */ 121 0x00, /* 40 */ 122 0x00, /* 41 */ 123 0x00, /* 42 */ 124 0x00, /* 43 */ 125 0x00, /* 44 */ 126 0x00, /* 45 */ 127 0x00, /* 46 */ 128 0x00, /* 47 */ 129 0x00, /* 48 */ 130 0x00, /* 49 */ 131 0x00, /* 4A */ 132 0x00, /* 4B */ 133 0x00, /* 4C */ 134 0x00, /* 4D */ 135 0x00, /* 4E */ 136 0x00, /* 4F */ 137 0x00, /* 50 */ 138 0x00, /* 51 */ 139 0x00, /* 52 */ 140 0x00, /* 53 */ 141 0x00, /* 54 */ 142 0x00, /* 55 */ 143 0x00, /* 56 */ 144 0x00, /* 57 */ 145 0x00, /* 58 */ 146 0x00, /* 59 */ 147 0x00, /* 5A */ 148 0x00, /* 5B */ 149 0x00, /* 5C */ 150 0x00, /* 5D */ 151 0x00, /* 5E */ 152 0x00, /* 5F */ 153 0x00, /* 60 */ 154 0x00, /* 61 */ 155 0x00, /* 62 */ 156 0x00, /* 63 */ 157 0x00, /* 64 */ 158 0x00, /* 65 */ 159 0x00, /* 66 */ 160 0x00, /* 67 */ 161 0x00, /* 68 */ 162 0x00, /* 69 */ 163 0x00, /* 6A */ 164 0x00, /* 6B */ 165 0x00, /* 6C */ 166 0x00, /* 6D */ 167 0x00, /* 6E */ 168 0x00, /* 6F */ 169 0x00, /* 70 */ 170 0x00, /* 71 */ 171 0x00, /* 72 */ 172 0x00, /* 73 */ 173 0x00, /* 74 */ 174 0x00, /* 75 */ 175 0x00, /* 76 */ 176 0x00, /* 77 */ 177 0x00, /* 78 */ 178 0x00, /* 79 */ 179 0x00, /* 7A */ 180 0x00, /* 7B */ 181 0x00, /* 7C */ 182 0x00, /* 7D */ 183 0x00, /* 7E */ 184 0x00, /* 7F */ 185 0x00, /* 80 */ 186 0x00, /* 81 */ 187 0x00, /* 82 */ 188 0x00, /* 83 */ 189 0x00, /* 84 */ 190 0x00, /* 85 */ 191 0x00, /* 86 */ 192 0x00, /* 87 */ 193 0x00, /* 88 */ 194 0x00, /* 89 */ 195 0x00, /* 8A */ 196 0x00, /* 8B */ 197 0x00, /* 8C */ 198 0x00, /* 8D */ 199 0x00, /* 8E */ 200 0x00, /* 8F */ 201 0x00, /* 90 */ 202 0x00, /* 91 */ 203 0x30, /* 92 */ 204 0xF0, /* 93 */ 205 0x00, /* 94 */ 206 0x00, /* 95 */ 207 0x3F, /* 96 */ 208 0x00, /* 97 */ 209 0x00, /* 98 */ 210 0x00, /* 99 */ 211 0x00, /* 9A */ 212 0x00, /* 9B */ 213 0x00, /* 9C */ 214 0x00, /* 9D */ 215 0x00, /* 9E */ 216 0x00, /* 9F */ 217 0x00, /* A0 */ 218 0x00, /* A1 */ 219 0x00, /* A2 */ 220 0x00, /* A3 */ 221 0x00, /* A4 */ 222 0x00, /* A5 */ 223 0x00, /* A6 */ 224 0x00, /* A7 */ 225 0x00, /* A8 */ 226 0x00, /* A9 */ 227 0x00, /* AA */ 228 0x00, /* AB */ 229 0x00, /* AC */ 230 0x00, /* AD */ 231 0x00, /* AE */ 232 0x00, /* AF */ 233 0x00, /* B0 */ 234 0x00, /* B1 */ 235 0x00, /* B2 */ 236 0x00, /* B3 */ 237 0x00, /* B4 */ 238 0x00, /* B5 */ 239 0x00, /* B6 */ 240 0x00, /* B7 */ 241 0x00, /* B8 */ 242 0x00, /* B9 */ 243 0x00, /* BA */ 244 0x00, /* BB */ 245 0x00, /* BC */ 246 0x00, /* BD */ 247 0x00, /* BE */ 248 0x00, /* BF */ 249 0x00, /* C0 */ 250 0x00, /* C1 */ 251 0x00, /* C2 */ 252 0x00, /* C3 */ 253 0x00, /* C4 */ 254 0x00, /* C5 */ 255 0x00, /* C6 */ 256 0x00, /* C7 */ 257 0x00, /* C8 */ 258 0x00, /* C9 */ 259 0x00, /* CA */ 260 0x00, /* CB */ 261 0x00, /* CC */ 262 0x00, /* CD */ 263 0x00, /* CE */ 264 0x00, /* CF */ 265 0x00, /* D0 */ 266 0x00, /* D1 */ 267 0x00, /* D2 */ 268 0x00, /* D3 */ 269 0x00, /* D4 */ 270 0x00, /* D5 */ 271 0x00, /* D6 */ 272 0x00, /* D7 */ 273 0x00, /* D8 */ 274 0x00, /* D9 */ 275 0x00, /* DA */ 276 0x00, /* DB */ 277 0x00, /* DC */ 278 0x00, /* DD */ 279 0x00, /* DE */ 280 0x00, /* DF */ 281 0x00, /* E0 */ 282 0x00, /* E1 */ 283 0x00, /* E2 */ 284 0x00, /* E3 */ 285 0x00, /* E4 */ 286 0x00, /* E5 */ 287 0x00, /* E6 */ 288 0x00, /* E7 */ 289 0x00, /* E8 */ 290 0x00, /* E9 */ 291 0x00, /* EA */ 292 0x00, /* EB */ 293 0x00, /* EC */ 294 0x00, /* ED */ 295 0x00, /* EE */ 296 0x00, /* EF */ 297 0x00, /* F0 */ 298 0x00, /* F1 */ 299 0x00, /* F2 */ 300 0x00, /* F3 */ 301 0x00, /* F4 */ 302 0x00, /* F5 */ 303 0x00, /* F6 */ 304 0x00, /* F7 */ 305 0x00, /* F8 */ 306 0x00, /* F9 */ 307 0x00, /* FA */ 308 0x00, /* FB */ 309 0x00, /* FC */ 310 0x00, /* FD */ 311 0x00, /* FE */ 312 0x00, /* FF */ 313 }; 314 315 static struct { 316 int readable; 317 int writable; 318 } max98095_access[M98095_REG_CNT] = { 319 { 0x00, 0x00 }, /* 00 */ 320 { 0xFF, 0x00 }, /* 01 */ 321 { 0xFF, 0x00 }, /* 02 */ 322 { 0xFF, 0x00 }, /* 03 */ 323 { 0xFF, 0x00 }, /* 04 */ 324 { 0xFF, 0x00 }, /* 05 */ 325 { 0xFF, 0x00 }, /* 06 */ 326 { 0xFF, 0x00 }, /* 07 */ 327 { 0xFF, 0x00 }, /* 08 */ 328 { 0xFF, 0x00 }, /* 09 */ 329 { 0xFF, 0x00 }, /* 0A */ 330 { 0xFF, 0x00 }, /* 0B */ 331 { 0xFF, 0x00 }, /* 0C */ 332 { 0xFF, 0x00 }, /* 0D */ 333 { 0xFF, 0x00 }, /* 0E */ 334 { 0xFF, 0x9F }, /* 0F */ 335 { 0xFF, 0xFF }, /* 10 */ 336 { 0xFF, 0xFF }, /* 11 */ 337 { 0xFF, 0xFF }, /* 12 */ 338 { 0xFF, 0xFF }, /* 13 */ 339 { 0xFF, 0xFF }, /* 14 */ 340 { 0xFF, 0xFF }, /* 15 */ 341 { 0xFF, 0xFF }, /* 16 */ 342 { 0xFF, 0xFF }, /* 17 */ 343 { 0xFF, 0xFF }, /* 18 */ 344 { 0xFF, 0xFF }, /* 19 */ 345 { 0xFF, 0xFF }, /* 1A */ 346 { 0xFF, 0xFF }, /* 1B */ 347 { 0xFF, 0xFF }, /* 1C */ 348 { 0xFF, 0xFF }, /* 1D */ 349 { 0xFF, 0x77 }, /* 1E */ 350 { 0xFF, 0x77 }, /* 1F */ 351 { 0xFF, 0x77 }, /* 20 */ 352 { 0xFF, 0x77 }, /* 21 */ 353 { 0xFF, 0x77 }, /* 22 */ 354 { 0xFF, 0x77 }, /* 23 */ 355 { 0xFF, 0xFF }, /* 24 */ 356 { 0xFF, 0x7F }, /* 25 */ 357 { 0xFF, 0x31 }, /* 26 */ 358 { 0xFF, 0xFF }, /* 27 */ 359 { 0xFF, 0xFF }, /* 28 */ 360 { 0xFF, 0xFF }, /* 29 */ 361 { 0xFF, 0xF7 }, /* 2A */ 362 { 0xFF, 0x2F }, /* 2B */ 363 { 0xFF, 0xEF }, /* 2C */ 364 { 0xFF, 0xFF }, /* 2D */ 365 { 0xFF, 0xFF }, /* 2E */ 366 { 0xFF, 0xFF }, /* 2F */ 367 { 0xFF, 0xFF }, /* 30 */ 368 { 0xFF, 0xFF }, /* 31 */ 369 { 0xFF, 0xFF }, /* 32 */ 370 { 0xFF, 0xFF }, /* 33 */ 371 { 0xFF, 0xF7 }, /* 34 */ 372 { 0xFF, 0x2F }, /* 35 */ 373 { 0xFF, 0xCF }, /* 36 */ 374 { 0xFF, 0xFF }, /* 37 */ 375 { 0xFF, 0xFF }, /* 38 */ 376 { 0xFF, 0xFF }, /* 39 */ 377 { 0xFF, 0xFF }, /* 3A */ 378 { 0xFF, 0xFF }, /* 3B */ 379 { 0xFF, 0xFF }, /* 3C */ 380 { 0xFF, 0xFF }, /* 3D */ 381 { 0xFF, 0xF7 }, /* 3E */ 382 { 0xFF, 0x2F }, /* 3F */ 383 { 0xFF, 0xCF }, /* 40 */ 384 { 0xFF, 0xFF }, /* 41 */ 385 { 0xFF, 0x77 }, /* 42 */ 386 { 0xFF, 0xFF }, /* 43 */ 387 { 0xFF, 0xFF }, /* 44 */ 388 { 0xFF, 0xFF }, /* 45 */ 389 { 0xFF, 0xFF }, /* 46 */ 390 { 0xFF, 0xFF }, /* 47 */ 391 { 0xFF, 0xFF }, /* 48 */ 392 { 0xFF, 0x0F }, /* 49 */ 393 { 0xFF, 0xFF }, /* 4A */ 394 { 0xFF, 0xFF }, /* 4B */ 395 { 0xFF, 0x3F }, /* 4C */ 396 { 0xFF, 0x3F }, /* 4D */ 397 { 0xFF, 0x3F }, /* 4E */ 398 { 0xFF, 0xFF }, /* 4F */ 399 { 0xFF, 0x7F }, /* 50 */ 400 { 0xFF, 0x7F }, /* 51 */ 401 { 0xFF, 0x0F }, /* 52 */ 402 { 0xFF, 0x3F }, /* 53 */ 403 { 0xFF, 0x3F }, /* 54 */ 404 { 0xFF, 0x3F }, /* 55 */ 405 { 0xFF, 0xFF }, /* 56 */ 406 { 0xFF, 0xFF }, /* 57 */ 407 { 0xFF, 0xBF }, /* 58 */ 408 { 0xFF, 0x1F }, /* 59 */ 409 { 0xFF, 0xBF }, /* 5A */ 410 { 0xFF, 0x1F }, /* 5B */ 411 { 0xFF, 0xBF }, /* 5C */ 412 { 0xFF, 0x3F }, /* 5D */ 413 { 0xFF, 0x3F }, /* 5E */ 414 { 0xFF, 0x7F }, /* 5F */ 415 { 0xFF, 0x7F }, /* 60 */ 416 { 0xFF, 0x47 }, /* 61 */ 417 { 0xFF, 0x9F }, /* 62 */ 418 { 0xFF, 0x9F }, /* 63 */ 419 { 0xFF, 0x9F }, /* 64 */ 420 { 0xFF, 0x9F }, /* 65 */ 421 { 0xFF, 0x9F }, /* 66 */ 422 { 0xFF, 0xBF }, /* 67 */ 423 { 0xFF, 0xBF }, /* 68 */ 424 { 0xFF, 0xFF }, /* 69 */ 425 { 0xFF, 0xFF }, /* 6A */ 426 { 0xFF, 0x7F }, /* 6B */ 427 { 0xFF, 0xF7 }, /* 6C */ 428 { 0xFF, 0xFF }, /* 6D */ 429 { 0xFF, 0xFF }, /* 6E */ 430 { 0xFF, 0x1F }, /* 6F */ 431 { 0xFF, 0xF7 }, /* 70 */ 432 { 0xFF, 0xFF }, /* 71 */ 433 { 0xFF, 0xFF }, /* 72 */ 434 { 0xFF, 0x1F }, /* 73 */ 435 { 0xFF, 0xF7 }, /* 74 */ 436 { 0xFF, 0xFF }, /* 75 */ 437 { 0xFF, 0xFF }, /* 76 */ 438 { 0xFF, 0x1F }, /* 77 */ 439 { 0xFF, 0xF7 }, /* 78 */ 440 { 0xFF, 0xFF }, /* 79 */ 441 { 0xFF, 0xFF }, /* 7A */ 442 { 0xFF, 0x1F }, /* 7B */ 443 { 0xFF, 0xF7 }, /* 7C */ 444 { 0xFF, 0xFF }, /* 7D */ 445 { 0xFF, 0xFF }, /* 7E */ 446 { 0xFF, 0x1F }, /* 7F */ 447 { 0xFF, 0xF7 }, /* 80 */ 448 { 0xFF, 0xFF }, /* 81 */ 449 { 0xFF, 0xFF }, /* 82 */ 450 { 0xFF, 0x1F }, /* 83 */ 451 { 0xFF, 0x7F }, /* 84 */ 452 { 0xFF, 0x0F }, /* 85 */ 453 { 0xFF, 0xD8 }, /* 86 */ 454 { 0xFF, 0xFF }, /* 87 */ 455 { 0xFF, 0xEF }, /* 88 */ 456 { 0xFF, 0xFE }, /* 89 */ 457 { 0xFF, 0xFE }, /* 8A */ 458 { 0xFF, 0xFF }, /* 8B */ 459 { 0xFF, 0xFF }, /* 8C */ 460 { 0xFF, 0x3F }, /* 8D */ 461 { 0xFF, 0xFF }, /* 8E */ 462 { 0xFF, 0x3F }, /* 8F */ 463 { 0xFF, 0x8F }, /* 90 */ 464 { 0xFF, 0xFF }, /* 91 */ 465 { 0xFF, 0x3F }, /* 92 */ 466 { 0xFF, 0xFF }, /* 93 */ 467 { 0xFF, 0xFF }, /* 94 */ 468 { 0xFF, 0x0F }, /* 95 */ 469 { 0xFF, 0x3F }, /* 96 */ 470 { 0xFF, 0x8C }, /* 97 */ 471 { 0x00, 0x00 }, /* 98 */ 472 { 0x00, 0x00 }, /* 99 */ 473 { 0x00, 0x00 }, /* 9A */ 474 { 0x00, 0x00 }, /* 9B */ 475 { 0x00, 0x00 }, /* 9C */ 476 { 0x00, 0x00 }, /* 9D */ 477 { 0x00, 0x00 }, /* 9E */ 478 { 0x00, 0x00 }, /* 9F */ 479 { 0x00, 0x00 }, /* A0 */ 480 { 0x00, 0x00 }, /* A1 */ 481 { 0x00, 0x00 }, /* A2 */ 482 { 0x00, 0x00 }, /* A3 */ 483 { 0x00, 0x00 }, /* A4 */ 484 { 0x00, 0x00 }, /* A5 */ 485 { 0x00, 0x00 }, /* A6 */ 486 { 0x00, 0x00 }, /* A7 */ 487 { 0x00, 0x00 }, /* A8 */ 488 { 0x00, 0x00 }, /* A9 */ 489 { 0x00, 0x00 }, /* AA */ 490 { 0x00, 0x00 }, /* AB */ 491 { 0x00, 0x00 }, /* AC */ 492 { 0x00, 0x00 }, /* AD */ 493 { 0x00, 0x00 }, /* AE */ 494 { 0x00, 0x00 }, /* AF */ 495 { 0x00, 0x00 }, /* B0 */ 496 { 0x00, 0x00 }, /* B1 */ 497 { 0x00, 0x00 }, /* B2 */ 498 { 0x00, 0x00 }, /* B3 */ 499 { 0x00, 0x00 }, /* B4 */ 500 { 0x00, 0x00 }, /* B5 */ 501 { 0x00, 0x00 }, /* B6 */ 502 { 0x00, 0x00 }, /* B7 */ 503 { 0x00, 0x00 }, /* B8 */ 504 { 0x00, 0x00 }, /* B9 */ 505 { 0x00, 0x00 }, /* BA */ 506 { 0x00, 0x00 }, /* BB */ 507 { 0x00, 0x00 }, /* BC */ 508 { 0x00, 0x00 }, /* BD */ 509 { 0x00, 0x00 }, /* BE */ 510 { 0x00, 0x00 }, /* BF */ 511 { 0x00, 0x00 }, /* C0 */ 512 { 0x00, 0x00 }, /* C1 */ 513 { 0x00, 0x00 }, /* C2 */ 514 { 0x00, 0x00 }, /* C3 */ 515 { 0x00, 0x00 }, /* C4 */ 516 { 0x00, 0x00 }, /* C5 */ 517 { 0x00, 0x00 }, /* C6 */ 518 { 0x00, 0x00 }, /* C7 */ 519 { 0x00, 0x00 }, /* C8 */ 520 { 0x00, 0x00 }, /* C9 */ 521 { 0x00, 0x00 }, /* CA */ 522 { 0x00, 0x00 }, /* CB */ 523 { 0x00, 0x00 }, /* CC */ 524 { 0x00, 0x00 }, /* CD */ 525 { 0x00, 0x00 }, /* CE */ 526 { 0x00, 0x00 }, /* CF */ 527 { 0x00, 0x00 }, /* D0 */ 528 { 0x00, 0x00 }, /* D1 */ 529 { 0x00, 0x00 }, /* D2 */ 530 { 0x00, 0x00 }, /* D3 */ 531 { 0x00, 0x00 }, /* D4 */ 532 { 0x00, 0x00 }, /* D5 */ 533 { 0x00, 0x00 }, /* D6 */ 534 { 0x00, 0x00 }, /* D7 */ 535 { 0x00, 0x00 }, /* D8 */ 536 { 0x00, 0x00 }, /* D9 */ 537 { 0x00, 0x00 }, /* DA */ 538 { 0x00, 0x00 }, /* DB */ 539 { 0x00, 0x00 }, /* DC */ 540 { 0x00, 0x00 }, /* DD */ 541 { 0x00, 0x00 }, /* DE */ 542 { 0x00, 0x00 }, /* DF */ 543 { 0x00, 0x00 }, /* E0 */ 544 { 0x00, 0x00 }, /* E1 */ 545 { 0x00, 0x00 }, /* E2 */ 546 { 0x00, 0x00 }, /* E3 */ 547 { 0x00, 0x00 }, /* E4 */ 548 { 0x00, 0x00 }, /* E5 */ 549 { 0x00, 0x00 }, /* E6 */ 550 { 0x00, 0x00 }, /* E7 */ 551 { 0x00, 0x00 }, /* E8 */ 552 { 0x00, 0x00 }, /* E9 */ 553 { 0x00, 0x00 }, /* EA */ 554 { 0x00, 0x00 }, /* EB */ 555 { 0x00, 0x00 }, /* EC */ 556 { 0x00, 0x00 }, /* ED */ 557 { 0x00, 0x00 }, /* EE */ 558 { 0x00, 0x00 }, /* EF */ 559 { 0x00, 0x00 }, /* F0 */ 560 { 0x00, 0x00 }, /* F1 */ 561 { 0x00, 0x00 }, /* F2 */ 562 { 0x00, 0x00 }, /* F3 */ 563 { 0x00, 0x00 }, /* F4 */ 564 { 0x00, 0x00 }, /* F5 */ 565 { 0x00, 0x00 }, /* F6 */ 566 { 0x00, 0x00 }, /* F7 */ 567 { 0x00, 0x00 }, /* F8 */ 568 { 0x00, 0x00 }, /* F9 */ 569 { 0x00, 0x00 }, /* FA */ 570 { 0x00, 0x00 }, /* FB */ 571 { 0x00, 0x00 }, /* FC */ 572 { 0x00, 0x00 }, /* FD */ 573 { 0x00, 0x00 }, /* FE */ 574 { 0xFF, 0x00 }, /* FF */ 575 }; 576 577 static int max98095_readable(struct snd_soc_codec *codec, unsigned int reg) 578 { 579 if (reg >= M98095_REG_CNT) 580 return 0; 581 return max98095_access[reg].readable != 0; 582 } 583 584 static int max98095_volatile(struct snd_soc_codec *codec, unsigned int reg) 585 { 586 if (reg > M98095_REG_MAX_CACHED) 587 return 1; 588 589 switch (reg) { 590 case M98095_000_HOST_DATA: 591 case M98095_001_HOST_INT_STS: 592 case M98095_002_HOST_RSP_STS: 593 case M98095_003_HOST_CMD_STS: 594 case M98095_004_CODEC_STS: 595 case M98095_005_DAI1_ALC_STS: 596 case M98095_006_DAI2_ALC_STS: 597 case M98095_007_JACK_AUTO_STS: 598 case M98095_008_JACK_MANUAL_STS: 599 case M98095_009_JACK_VBAT_STS: 600 case M98095_00A_ACC_ADC_STS: 601 case M98095_00B_MIC_NG_AGC_STS: 602 case M98095_00C_SPK_L_VOLT_STS: 603 case M98095_00D_SPK_R_VOLT_STS: 604 case M98095_00E_TEMP_SENSOR_STS: 605 return 1; 606 } 607 608 return 0; 609 } 610 611 /* 612 * Filter coefficients are in a separate register segment 613 * and they share the address space of the normal registers. 614 * The coefficient registers do not need or share the cache. 615 */ 616 static int max98095_hw_write(struct snd_soc_codec *codec, unsigned int reg, 617 unsigned int value) 618 { 619 int ret; 620 621 codec->cache_bypass = 1; 622 ret = snd_soc_write(codec, reg, value); 623 codec->cache_bypass = 0; 624 625 return ret ? -EIO : 0; 626 } 627 628 /* 629 * Load equalizer DSP coefficient configurations registers 630 */ 631 static void m98095_eq_band(struct snd_soc_codec *codec, unsigned int dai, 632 unsigned int band, u16 *coefs) 633 { 634 unsigned int eq_reg; 635 unsigned int i; 636 637 BUG_ON(band > 4); 638 BUG_ON(dai > 1); 639 640 /* Load the base register address */ 641 eq_reg = dai ? M98095_142_DAI2_EQ_BASE : M98095_110_DAI1_EQ_BASE; 642 643 /* Add the band address offset, note adjustment for word address */ 644 eq_reg += band * (M98095_COEFS_PER_BAND << 1); 645 646 /* Step through the registers and coefs */ 647 for (i = 0; i < M98095_COEFS_PER_BAND; i++) { 648 max98095_hw_write(codec, eq_reg++, M98095_BYTE1(coefs[i])); 649 max98095_hw_write(codec, eq_reg++, M98095_BYTE0(coefs[i])); 650 } 651 } 652 653 /* 654 * Load biquad filter coefficient configurations registers 655 */ 656 static void m98095_biquad_band(struct snd_soc_codec *codec, unsigned int dai, 657 unsigned int band, u16 *coefs) 658 { 659 unsigned int bq_reg; 660 unsigned int i; 661 662 BUG_ON(band > 1); 663 BUG_ON(dai > 1); 664 665 /* Load the base register address */ 666 bq_reg = dai ? M98095_17E_DAI2_BQ_BASE : M98095_174_DAI1_BQ_BASE; 667 668 /* Add the band address offset, note adjustment for word address */ 669 bq_reg += band * (M98095_COEFS_PER_BAND << 1); 670 671 /* Step through the registers and coefs */ 672 for (i = 0; i < M98095_COEFS_PER_BAND; i++) { 673 max98095_hw_write(codec, bq_reg++, M98095_BYTE1(coefs[i])); 674 max98095_hw_write(codec, bq_reg++, M98095_BYTE0(coefs[i])); 675 } 676 } 677 678 static const char * const max98095_fltr_mode[] = { "Voice", "Music" }; 679 static const struct soc_enum max98095_dai1_filter_mode_enum[] = { 680 SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 7, 2, max98095_fltr_mode), 681 }; 682 static const struct soc_enum max98095_dai2_filter_mode_enum[] = { 683 SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 7, 2, max98095_fltr_mode), 684 }; 685 686 static const char * const max98095_extmic_text[] = { "None", "MIC1", "MIC2" }; 687 688 static const struct soc_enum max98095_extmic_enum = 689 SOC_ENUM_SINGLE(M98095_087_CFG_MIC, 0, 3, max98095_extmic_text); 690 691 static const struct snd_kcontrol_new max98095_extmic_mux = 692 SOC_DAPM_ENUM("External MIC Mux", max98095_extmic_enum); 693 694 static const char * const max98095_linein_text[] = { "INA", "INB" }; 695 696 static const struct soc_enum max98095_linein_enum = 697 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 6, 2, max98095_linein_text); 698 699 static const struct snd_kcontrol_new max98095_linein_mux = 700 SOC_DAPM_ENUM("Linein Input Mux", max98095_linein_enum); 701 702 static const char * const max98095_line_mode_text[] = { 703 "Stereo", "Differential"}; 704 705 static const struct soc_enum max98095_linein_mode_enum = 706 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 7, 2, max98095_line_mode_text); 707 708 static const struct soc_enum max98095_lineout_mode_enum = 709 SOC_ENUM_SINGLE(M98095_086_CFG_LINE, 4, 2, max98095_line_mode_text); 710 711 static const char * const max98095_dai_fltr[] = { 712 "Off", "Elliptical-HPF-16k", "Butterworth-HPF-16k", 713 "Elliptical-HPF-8k", "Butterworth-HPF-8k", "Butterworth-HPF-Fs/240"}; 714 static const struct soc_enum max98095_dai1_dac_filter_enum[] = { 715 SOC_ENUM_SINGLE(M98095_02E_DAI1_FILTERS, 0, 6, max98095_dai_fltr), 716 }; 717 static const struct soc_enum max98095_dai2_dac_filter_enum[] = { 718 SOC_ENUM_SINGLE(M98095_038_DAI2_FILTERS, 0, 6, max98095_dai_fltr), 719 }; 720 static const struct soc_enum max98095_dai3_dac_filter_enum[] = { 721 SOC_ENUM_SINGLE(M98095_042_DAI3_FILTERS, 0, 6, max98095_dai_fltr), 722 }; 723 724 static int max98095_mic1pre_set(struct snd_kcontrol *kcontrol, 725 struct snd_ctl_elem_value *ucontrol) 726 { 727 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 728 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 729 unsigned int sel = ucontrol->value.integer.value[0]; 730 731 max98095->mic1pre = sel; 732 snd_soc_update_bits(codec, M98095_05F_LVL_MIC1, M98095_MICPRE_MASK, 733 (1+sel)<<M98095_MICPRE_SHIFT); 734 735 return 0; 736 } 737 738 static int max98095_mic1pre_get(struct snd_kcontrol *kcontrol, 739 struct snd_ctl_elem_value *ucontrol) 740 { 741 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 742 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 743 744 ucontrol->value.integer.value[0] = max98095->mic1pre; 745 return 0; 746 } 747 748 static int max98095_mic2pre_set(struct snd_kcontrol *kcontrol, 749 struct snd_ctl_elem_value *ucontrol) 750 { 751 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 752 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 753 unsigned int sel = ucontrol->value.integer.value[0]; 754 755 max98095->mic2pre = sel; 756 snd_soc_update_bits(codec, M98095_060_LVL_MIC2, M98095_MICPRE_MASK, 757 (1+sel)<<M98095_MICPRE_SHIFT); 758 759 return 0; 760 } 761 762 static int max98095_mic2pre_get(struct snd_kcontrol *kcontrol, 763 struct snd_ctl_elem_value *ucontrol) 764 { 765 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 766 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 767 768 ucontrol->value.integer.value[0] = max98095->mic2pre; 769 return 0; 770 } 771 772 static const unsigned int max98095_micboost_tlv[] = { 773 TLV_DB_RANGE_HEAD(2), 774 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 775 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), 776 }; 777 778 static const DECLARE_TLV_DB_SCALE(max98095_mic_tlv, 0, 100, 0); 779 static const DECLARE_TLV_DB_SCALE(max98095_adc_tlv, -1200, 100, 0); 780 static const DECLARE_TLV_DB_SCALE(max98095_adcboost_tlv, 0, 600, 0); 781 782 static const unsigned int max98095_hp_tlv[] = { 783 TLV_DB_RANGE_HEAD(5), 784 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 785 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 786 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 787 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 788 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), 789 }; 790 791 static const unsigned int max98095_spk_tlv[] = { 792 TLV_DB_RANGE_HEAD(4), 793 0, 10, TLV_DB_SCALE_ITEM(-5900, 400, 0), 794 11, 18, TLV_DB_SCALE_ITEM(-1700, 200, 0), 795 19, 27, TLV_DB_SCALE_ITEM(-200, 100, 0), 796 28, 39, TLV_DB_SCALE_ITEM(650, 50, 0), 797 }; 798 799 static const unsigned int max98095_rcv_lout_tlv[] = { 800 TLV_DB_RANGE_HEAD(5), 801 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 802 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 803 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 804 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 805 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), 806 }; 807 808 static const unsigned int max98095_lin_tlv[] = { 809 TLV_DB_RANGE_HEAD(3), 810 0, 2, TLV_DB_SCALE_ITEM(-600, 300, 0), 811 3, 3, TLV_DB_SCALE_ITEM(300, 1100, 0), 812 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), 813 }; 814 815 static const struct snd_kcontrol_new max98095_snd_controls[] = { 816 817 SOC_DOUBLE_R_TLV("Headphone Volume", M98095_064_LVL_HP_L, 818 M98095_065_LVL_HP_R, 0, 31, 0, max98095_hp_tlv), 819 820 SOC_DOUBLE_R_TLV("Speaker Volume", M98095_067_LVL_SPK_L, 821 M98095_068_LVL_SPK_R, 0, 39, 0, max98095_spk_tlv), 822 823 SOC_SINGLE_TLV("Receiver Volume", M98095_066_LVL_RCV, 824 0, 31, 0, max98095_rcv_lout_tlv), 825 826 SOC_DOUBLE_R_TLV("Lineout Volume", M98095_062_LVL_LINEOUT1, 827 M98095_063_LVL_LINEOUT2, 0, 31, 0, max98095_rcv_lout_tlv), 828 829 SOC_DOUBLE_R("Headphone Switch", M98095_064_LVL_HP_L, 830 M98095_065_LVL_HP_R, 7, 1, 1), 831 832 SOC_DOUBLE_R("Speaker Switch", M98095_067_LVL_SPK_L, 833 M98095_068_LVL_SPK_R, 7, 1, 1), 834 835 SOC_SINGLE("Receiver Switch", M98095_066_LVL_RCV, 7, 1, 1), 836 837 SOC_DOUBLE_R("Lineout Switch", M98095_062_LVL_LINEOUT1, 838 M98095_063_LVL_LINEOUT2, 7, 1, 1), 839 840 SOC_SINGLE_TLV("MIC1 Volume", M98095_05F_LVL_MIC1, 0, 20, 1, 841 max98095_mic_tlv), 842 843 SOC_SINGLE_TLV("MIC2 Volume", M98095_060_LVL_MIC2, 0, 20, 1, 844 max98095_mic_tlv), 845 846 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 847 M98095_05F_LVL_MIC1, 5, 2, 0, 848 max98095_mic1pre_get, max98095_mic1pre_set, 849 max98095_micboost_tlv), 850 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 851 M98095_060_LVL_MIC2, 5, 2, 0, 852 max98095_mic2pre_get, max98095_mic2pre_set, 853 max98095_micboost_tlv), 854 855 SOC_SINGLE_TLV("Linein Volume", M98095_061_LVL_LINEIN, 0, 5, 1, 856 max98095_lin_tlv), 857 858 SOC_SINGLE_TLV("ADCL Volume", M98095_05D_LVL_ADC_L, 0, 15, 1, 859 max98095_adc_tlv), 860 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1, 861 max98095_adc_tlv), 862 863 SOC_SINGLE_TLV("ADCL Boost Volume", M98095_05D_LVL_ADC_L, 4, 3, 0, 864 max98095_adcboost_tlv), 865 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0, 866 max98095_adcboost_tlv), 867 868 SOC_SINGLE("EQ1 Switch", M98095_088_CFG_LEVEL, 0, 1, 0), 869 SOC_SINGLE("EQ2 Switch", M98095_088_CFG_LEVEL, 1, 1, 0), 870 871 SOC_SINGLE("Biquad1 Switch", M98095_088_CFG_LEVEL, 2, 1, 0), 872 SOC_SINGLE("Biquad2 Switch", M98095_088_CFG_LEVEL, 3, 1, 0), 873 874 SOC_ENUM("DAI1 Filter Mode", max98095_dai1_filter_mode_enum), 875 SOC_ENUM("DAI2 Filter Mode", max98095_dai2_filter_mode_enum), 876 SOC_ENUM("DAI1 DAC Filter", max98095_dai1_dac_filter_enum), 877 SOC_ENUM("DAI2 DAC Filter", max98095_dai2_dac_filter_enum), 878 SOC_ENUM("DAI3 DAC Filter", max98095_dai3_dac_filter_enum), 879 880 SOC_ENUM("Linein Mode", max98095_linein_mode_enum), 881 SOC_ENUM("Lineout Mode", max98095_lineout_mode_enum), 882 }; 883 884 /* Left speaker mixer switch */ 885 static const struct snd_kcontrol_new max98095_left_speaker_mixer_controls[] = { 886 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_050_MIX_SPK_LEFT, 0, 1, 0), 887 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_050_MIX_SPK_LEFT, 6, 1, 0), 888 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), 889 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_050_MIX_SPK_LEFT, 3, 1, 0), 890 SOC_DAPM_SINGLE("MIC1 Switch", M98095_050_MIX_SPK_LEFT, 4, 1, 0), 891 SOC_DAPM_SINGLE("MIC2 Switch", M98095_050_MIX_SPK_LEFT, 5, 1, 0), 892 SOC_DAPM_SINGLE("IN1 Switch", M98095_050_MIX_SPK_LEFT, 1, 1, 0), 893 SOC_DAPM_SINGLE("IN2 Switch", M98095_050_MIX_SPK_LEFT, 2, 1, 0), 894 }; 895 896 /* Right speaker mixer switch */ 897 static const struct snd_kcontrol_new max98095_right_speaker_mixer_controls[] = { 898 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 6, 1, 0), 899 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_051_MIX_SPK_RIGHT, 0, 1, 0), 900 SOC_DAPM_SINGLE("Mono DAC2 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), 901 SOC_DAPM_SINGLE("Mono DAC3 Switch", M98095_051_MIX_SPK_RIGHT, 3, 1, 0), 902 SOC_DAPM_SINGLE("MIC1 Switch", M98095_051_MIX_SPK_RIGHT, 5, 1, 0), 903 SOC_DAPM_SINGLE("MIC2 Switch", M98095_051_MIX_SPK_RIGHT, 4, 1, 0), 904 SOC_DAPM_SINGLE("IN1 Switch", M98095_051_MIX_SPK_RIGHT, 1, 1, 0), 905 SOC_DAPM_SINGLE("IN2 Switch", M98095_051_MIX_SPK_RIGHT, 2, 1, 0), 906 }; 907 908 /* Left headphone mixer switch */ 909 static const struct snd_kcontrol_new max98095_left_hp_mixer_controls[] = { 910 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04C_MIX_HP_LEFT, 0, 1, 0), 911 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04C_MIX_HP_LEFT, 5, 1, 0), 912 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04C_MIX_HP_LEFT, 3, 1, 0), 913 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04C_MIX_HP_LEFT, 4, 1, 0), 914 SOC_DAPM_SINGLE("IN1 Switch", M98095_04C_MIX_HP_LEFT, 1, 1, 0), 915 SOC_DAPM_SINGLE("IN2 Switch", M98095_04C_MIX_HP_LEFT, 2, 1, 0), 916 }; 917 918 /* Right headphone mixer switch */ 919 static const struct snd_kcontrol_new max98095_right_hp_mixer_controls[] = { 920 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 5, 1, 0), 921 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04D_MIX_HP_RIGHT, 0, 1, 0), 922 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04D_MIX_HP_RIGHT, 3, 1, 0), 923 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04D_MIX_HP_RIGHT, 4, 1, 0), 924 SOC_DAPM_SINGLE("IN1 Switch", M98095_04D_MIX_HP_RIGHT, 1, 1, 0), 925 SOC_DAPM_SINGLE("IN2 Switch", M98095_04D_MIX_HP_RIGHT, 2, 1, 0), 926 }; 927 928 /* Receiver earpiece mixer switch */ 929 static const struct snd_kcontrol_new max98095_mono_rcv_mixer_controls[] = { 930 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_04F_MIX_RCV, 0, 1, 0), 931 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_04F_MIX_RCV, 5, 1, 0), 932 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04F_MIX_RCV, 3, 1, 0), 933 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04F_MIX_RCV, 4, 1, 0), 934 SOC_DAPM_SINGLE("IN1 Switch", M98095_04F_MIX_RCV, 1, 1, 0), 935 SOC_DAPM_SINGLE("IN2 Switch", M98095_04F_MIX_RCV, 2, 1, 0), 936 }; 937 938 /* Left lineout mixer switch */ 939 static const struct snd_kcontrol_new max98095_left_lineout_mixer_controls[] = { 940 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_053_MIX_LINEOUT1, 5, 1, 0), 941 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_053_MIX_LINEOUT1, 0, 1, 0), 942 SOC_DAPM_SINGLE("MIC1 Switch", M98095_053_MIX_LINEOUT1, 3, 1, 0), 943 SOC_DAPM_SINGLE("MIC2 Switch", M98095_053_MIX_LINEOUT1, 4, 1, 0), 944 SOC_DAPM_SINGLE("IN1 Switch", M98095_053_MIX_LINEOUT1, 1, 1, 0), 945 SOC_DAPM_SINGLE("IN2 Switch", M98095_053_MIX_LINEOUT1, 2, 1, 0), 946 }; 947 948 /* Right lineout mixer switch */ 949 static const struct snd_kcontrol_new max98095_right_lineout_mixer_controls[] = { 950 SOC_DAPM_SINGLE("Left DAC1 Switch", M98095_054_MIX_LINEOUT2, 0, 1, 0), 951 SOC_DAPM_SINGLE("Right DAC1 Switch", M98095_054_MIX_LINEOUT2, 5, 1, 0), 952 SOC_DAPM_SINGLE("MIC1 Switch", M98095_054_MIX_LINEOUT2, 3, 1, 0), 953 SOC_DAPM_SINGLE("MIC2 Switch", M98095_054_MIX_LINEOUT2, 4, 1, 0), 954 SOC_DAPM_SINGLE("IN1 Switch", M98095_054_MIX_LINEOUT2, 1, 1, 0), 955 SOC_DAPM_SINGLE("IN2 Switch", M98095_054_MIX_LINEOUT2, 2, 1, 0), 956 }; 957 958 /* Left ADC mixer switch */ 959 static const struct snd_kcontrol_new max98095_left_ADC_mixer_controls[] = { 960 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04A_MIX_ADC_LEFT, 7, 1, 0), 961 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04A_MIX_ADC_LEFT, 6, 1, 0), 962 SOC_DAPM_SINGLE("IN1 Switch", M98095_04A_MIX_ADC_LEFT, 3, 1, 0), 963 SOC_DAPM_SINGLE("IN2 Switch", M98095_04A_MIX_ADC_LEFT, 2, 1, 0), 964 }; 965 966 /* Right ADC mixer switch */ 967 static const struct snd_kcontrol_new max98095_right_ADC_mixer_controls[] = { 968 SOC_DAPM_SINGLE("MIC1 Switch", M98095_04B_MIX_ADC_RIGHT, 7, 1, 0), 969 SOC_DAPM_SINGLE("MIC2 Switch", M98095_04B_MIX_ADC_RIGHT, 6, 1, 0), 970 SOC_DAPM_SINGLE("IN1 Switch", M98095_04B_MIX_ADC_RIGHT, 3, 1, 0), 971 SOC_DAPM_SINGLE("IN2 Switch", M98095_04B_MIX_ADC_RIGHT, 2, 1, 0), 972 }; 973 974 static int max98095_mic_event(struct snd_soc_dapm_widget *w, 975 struct snd_kcontrol *kcontrol, int event) 976 { 977 struct snd_soc_codec *codec = w->codec; 978 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 979 980 switch (event) { 981 case SND_SOC_DAPM_POST_PMU: 982 if (w->reg == M98095_05F_LVL_MIC1) { 983 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 984 (1+max98095->mic1pre)<<M98095_MICPRE_SHIFT); 985 } else { 986 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 987 (1+max98095->mic2pre)<<M98095_MICPRE_SHIFT); 988 } 989 break; 990 case SND_SOC_DAPM_POST_PMD: 991 snd_soc_update_bits(codec, w->reg, M98095_MICPRE_MASK, 0); 992 break; 993 default: 994 return -EINVAL; 995 } 996 997 return 0; 998 } 999 1000 /* 1001 * The line inputs are stereo inputs with the left and right 1002 * channels sharing a common PGA power control signal. 1003 */ 1004 static int max98095_line_pga(struct snd_soc_dapm_widget *w, 1005 int event, u8 channel) 1006 { 1007 struct snd_soc_codec *codec = w->codec; 1008 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1009 u8 *state; 1010 1011 BUG_ON(!((channel == 1) || (channel == 2))); 1012 1013 state = &max98095->lin_state; 1014 1015 switch (event) { 1016 case SND_SOC_DAPM_POST_PMU: 1017 *state |= channel; 1018 snd_soc_update_bits(codec, w->reg, 1019 (1 << w->shift), (1 << w->shift)); 1020 break; 1021 case SND_SOC_DAPM_POST_PMD: 1022 *state &= ~channel; 1023 if (*state == 0) { 1024 snd_soc_update_bits(codec, w->reg, 1025 (1 << w->shift), 0); 1026 } 1027 break; 1028 default: 1029 return -EINVAL; 1030 } 1031 1032 return 0; 1033 } 1034 1035 static int max98095_pga_in1_event(struct snd_soc_dapm_widget *w, 1036 struct snd_kcontrol *k, int event) 1037 { 1038 return max98095_line_pga(w, event, 1); 1039 } 1040 1041 static int max98095_pga_in2_event(struct snd_soc_dapm_widget *w, 1042 struct snd_kcontrol *k, int event) 1043 { 1044 return max98095_line_pga(w, event, 2); 1045 } 1046 1047 /* 1048 * The stereo line out mixer outputs to two stereo line outs. 1049 * The 2nd pair has a separate set of enables. 1050 */ 1051 static int max98095_lineout_event(struct snd_soc_dapm_widget *w, 1052 struct snd_kcontrol *kcontrol, int event) 1053 { 1054 struct snd_soc_codec *codec = w->codec; 1055 1056 switch (event) { 1057 case SND_SOC_DAPM_POST_PMU: 1058 snd_soc_update_bits(codec, w->reg, 1059 (1 << (w->shift+2)), (1 << (w->shift+2))); 1060 break; 1061 case SND_SOC_DAPM_POST_PMD: 1062 snd_soc_update_bits(codec, w->reg, 1063 (1 << (w->shift+2)), 0); 1064 break; 1065 default: 1066 return -EINVAL; 1067 } 1068 1069 return 0; 1070 } 1071 1072 static const struct snd_soc_dapm_widget max98095_dapm_widgets[] = { 1073 1074 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98095_090_PWR_EN_IN, 0, 0), 1075 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0), 1076 1077 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", 1078 M98095_091_PWR_EN_OUT, 0, 0), 1079 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", 1080 M98095_091_PWR_EN_OUT, 1, 0), 1081 SND_SOC_DAPM_DAC("DACM2", "Aux Playback", 1082 M98095_091_PWR_EN_OUT, 2, 0), 1083 SND_SOC_DAPM_DAC("DACM3", "Voice Playback", 1084 M98095_091_PWR_EN_OUT, 2, 0), 1085 1086 SND_SOC_DAPM_PGA("HP Left Out", M98095_091_PWR_EN_OUT, 1087 6, 0, NULL, 0), 1088 SND_SOC_DAPM_PGA("HP Right Out", M98095_091_PWR_EN_OUT, 1089 7, 0, NULL, 0), 1090 1091 SND_SOC_DAPM_PGA("SPK Left Out", M98095_091_PWR_EN_OUT, 1092 4, 0, NULL, 0), 1093 SND_SOC_DAPM_PGA("SPK Right Out", M98095_091_PWR_EN_OUT, 1094 5, 0, NULL, 0), 1095 1096 SND_SOC_DAPM_PGA("RCV Mono Out", M98095_091_PWR_EN_OUT, 1097 3, 0, NULL, 0), 1098 1099 SND_SOC_DAPM_PGA_E("LINE Left Out", M98095_092_PWR_EN_OUT, 1100 0, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), 1101 SND_SOC_DAPM_PGA_E("LINE Right Out", M98095_092_PWR_EN_OUT, 1102 1, 0, NULL, 0, max98095_lineout_event, SND_SOC_DAPM_PRE_PMD), 1103 1104 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, 1105 &max98095_extmic_mux), 1106 1107 SND_SOC_DAPM_MUX("Linein Mux", SND_SOC_NOPM, 0, 0, 1108 &max98095_linein_mux), 1109 1110 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 1111 &max98095_left_hp_mixer_controls[0], 1112 ARRAY_SIZE(max98095_left_hp_mixer_controls)), 1113 1114 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 1115 &max98095_right_hp_mixer_controls[0], 1116 ARRAY_SIZE(max98095_right_hp_mixer_controls)), 1117 1118 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 1119 &max98095_left_speaker_mixer_controls[0], 1120 ARRAY_SIZE(max98095_left_speaker_mixer_controls)), 1121 1122 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 1123 &max98095_right_speaker_mixer_controls[0], 1124 ARRAY_SIZE(max98095_right_speaker_mixer_controls)), 1125 1126 SND_SOC_DAPM_MIXER("Receiver Mixer", SND_SOC_NOPM, 0, 0, 1127 &max98095_mono_rcv_mixer_controls[0], 1128 ARRAY_SIZE(max98095_mono_rcv_mixer_controls)), 1129 1130 SND_SOC_DAPM_MIXER("Left Lineout Mixer", SND_SOC_NOPM, 0, 0, 1131 &max98095_left_lineout_mixer_controls[0], 1132 ARRAY_SIZE(max98095_left_lineout_mixer_controls)), 1133 1134 SND_SOC_DAPM_MIXER("Right Lineout Mixer", SND_SOC_NOPM, 0, 0, 1135 &max98095_right_lineout_mixer_controls[0], 1136 ARRAY_SIZE(max98095_right_lineout_mixer_controls)), 1137 1138 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1139 &max98095_left_ADC_mixer_controls[0], 1140 ARRAY_SIZE(max98095_left_ADC_mixer_controls)), 1141 1142 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1143 &max98095_right_ADC_mixer_controls[0], 1144 ARRAY_SIZE(max98095_right_ADC_mixer_controls)), 1145 1146 SND_SOC_DAPM_PGA_E("MIC1 Input", M98095_05F_LVL_MIC1, 1147 5, 0, NULL, 0, max98095_mic_event, 1148 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1149 1150 SND_SOC_DAPM_PGA_E("MIC2 Input", M98095_060_LVL_MIC2, 1151 5, 0, NULL, 0, max98095_mic_event, 1152 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1153 1154 SND_SOC_DAPM_PGA_E("IN1 Input", M98095_090_PWR_EN_IN, 1155 7, 0, NULL, 0, max98095_pga_in1_event, 1156 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1157 1158 SND_SOC_DAPM_PGA_E("IN2 Input", M98095_090_PWR_EN_IN, 1159 7, 0, NULL, 0, max98095_pga_in2_event, 1160 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1161 1162 SND_SOC_DAPM_MICBIAS("MICBIAS1", M98095_090_PWR_EN_IN, 2, 0), 1163 SND_SOC_DAPM_MICBIAS("MICBIAS2", M98095_090_PWR_EN_IN, 3, 0), 1164 1165 SND_SOC_DAPM_OUTPUT("HPL"), 1166 SND_SOC_DAPM_OUTPUT("HPR"), 1167 SND_SOC_DAPM_OUTPUT("SPKL"), 1168 SND_SOC_DAPM_OUTPUT("SPKR"), 1169 SND_SOC_DAPM_OUTPUT("RCV"), 1170 SND_SOC_DAPM_OUTPUT("OUT1"), 1171 SND_SOC_DAPM_OUTPUT("OUT2"), 1172 SND_SOC_DAPM_OUTPUT("OUT3"), 1173 SND_SOC_DAPM_OUTPUT("OUT4"), 1174 1175 SND_SOC_DAPM_INPUT("MIC1"), 1176 SND_SOC_DAPM_INPUT("MIC2"), 1177 SND_SOC_DAPM_INPUT("INA1"), 1178 SND_SOC_DAPM_INPUT("INA2"), 1179 SND_SOC_DAPM_INPUT("INB1"), 1180 SND_SOC_DAPM_INPUT("INB2"), 1181 }; 1182 1183 static const struct snd_soc_dapm_route max98095_audio_map[] = { 1184 /* Left headphone output mixer */ 1185 {"Left Headphone Mixer", "Left DAC1 Switch", "DACL1"}, 1186 {"Left Headphone Mixer", "Right DAC1 Switch", "DACR1"}, 1187 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1188 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1189 {"Left Headphone Mixer", "IN1 Switch", "IN1 Input"}, 1190 {"Left Headphone Mixer", "IN2 Switch", "IN2 Input"}, 1191 1192 /* Right headphone output mixer */ 1193 {"Right Headphone Mixer", "Left DAC1 Switch", "DACL1"}, 1194 {"Right Headphone Mixer", "Right DAC1 Switch", "DACR1"}, 1195 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1196 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1197 {"Right Headphone Mixer", "IN1 Switch", "IN1 Input"}, 1198 {"Right Headphone Mixer", "IN2 Switch", "IN2 Input"}, 1199 1200 /* Left speaker output mixer */ 1201 {"Left Speaker Mixer", "Left DAC1 Switch", "DACL1"}, 1202 {"Left Speaker Mixer", "Right DAC1 Switch", "DACR1"}, 1203 {"Left Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, 1204 {"Left Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, 1205 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1206 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1207 {"Left Speaker Mixer", "IN1 Switch", "IN1 Input"}, 1208 {"Left Speaker Mixer", "IN2 Switch", "IN2 Input"}, 1209 1210 /* Right speaker output mixer */ 1211 {"Right Speaker Mixer", "Left DAC1 Switch", "DACL1"}, 1212 {"Right Speaker Mixer", "Right DAC1 Switch", "DACR1"}, 1213 {"Right Speaker Mixer", "Mono DAC2 Switch", "DACM2"}, 1214 {"Right Speaker Mixer", "Mono DAC3 Switch", "DACM3"}, 1215 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1216 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1217 {"Right Speaker Mixer", "IN1 Switch", "IN1 Input"}, 1218 {"Right Speaker Mixer", "IN2 Switch", "IN2 Input"}, 1219 1220 /* Earpiece/Receiver output mixer */ 1221 {"Receiver Mixer", "Left DAC1 Switch", "DACL1"}, 1222 {"Receiver Mixer", "Right DAC1 Switch", "DACR1"}, 1223 {"Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1224 {"Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1225 {"Receiver Mixer", "IN1 Switch", "IN1 Input"}, 1226 {"Receiver Mixer", "IN2 Switch", "IN2 Input"}, 1227 1228 /* Left Lineout output mixer */ 1229 {"Left Lineout Mixer", "Left DAC1 Switch", "DACL1"}, 1230 {"Left Lineout Mixer", "Right DAC1 Switch", "DACR1"}, 1231 {"Left Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, 1232 {"Left Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, 1233 {"Left Lineout Mixer", "IN1 Switch", "IN1 Input"}, 1234 {"Left Lineout Mixer", "IN2 Switch", "IN2 Input"}, 1235 1236 /* Right lineout output mixer */ 1237 {"Right Lineout Mixer", "Left DAC1 Switch", "DACL1"}, 1238 {"Right Lineout Mixer", "Right DAC1 Switch", "DACR1"}, 1239 {"Right Lineout Mixer", "MIC1 Switch", "MIC1 Input"}, 1240 {"Right Lineout Mixer", "MIC2 Switch", "MIC2 Input"}, 1241 {"Right Lineout Mixer", "IN1 Switch", "IN1 Input"}, 1242 {"Right Lineout Mixer", "IN2 Switch", "IN2 Input"}, 1243 1244 {"HP Left Out", NULL, "Left Headphone Mixer"}, 1245 {"HP Right Out", NULL, "Right Headphone Mixer"}, 1246 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 1247 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 1248 {"RCV Mono Out", NULL, "Receiver Mixer"}, 1249 {"LINE Left Out", NULL, "Left Lineout Mixer"}, 1250 {"LINE Right Out", NULL, "Right Lineout Mixer"}, 1251 1252 {"HPL", NULL, "HP Left Out"}, 1253 {"HPR", NULL, "HP Right Out"}, 1254 {"SPKL", NULL, "SPK Left Out"}, 1255 {"SPKR", NULL, "SPK Right Out"}, 1256 {"RCV", NULL, "RCV Mono Out"}, 1257 {"OUT1", NULL, "LINE Left Out"}, 1258 {"OUT2", NULL, "LINE Right Out"}, 1259 {"OUT3", NULL, "LINE Left Out"}, 1260 {"OUT4", NULL, "LINE Right Out"}, 1261 1262 /* Left ADC input mixer */ 1263 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1264 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1265 {"Left ADC Mixer", "IN1 Switch", "IN1 Input"}, 1266 {"Left ADC Mixer", "IN2 Switch", "IN2 Input"}, 1267 1268 /* Right ADC input mixer */ 1269 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1270 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1271 {"Right ADC Mixer", "IN1 Switch", "IN1 Input"}, 1272 {"Right ADC Mixer", "IN2 Switch", "IN2 Input"}, 1273 1274 /* Inputs */ 1275 {"ADCL", NULL, "Left ADC Mixer"}, 1276 {"ADCR", NULL, "Right ADC Mixer"}, 1277 1278 {"IN1 Input", NULL, "INA1"}, 1279 {"IN2 Input", NULL, "INA2"}, 1280 1281 {"MIC1 Input", NULL, "MIC1"}, 1282 {"MIC2 Input", NULL, "MIC2"}, 1283 }; 1284 1285 static int max98095_add_widgets(struct snd_soc_codec *codec) 1286 { 1287 snd_soc_add_codec_controls(codec, max98095_snd_controls, 1288 ARRAY_SIZE(max98095_snd_controls)); 1289 1290 return 0; 1291 } 1292 1293 /* codec mclk clock divider coefficients */ 1294 static const struct { 1295 u32 rate; 1296 u8 sr; 1297 } rate_table[] = { 1298 {8000, 0x01}, 1299 {11025, 0x02}, 1300 {16000, 0x03}, 1301 {22050, 0x04}, 1302 {24000, 0x05}, 1303 {32000, 0x06}, 1304 {44100, 0x07}, 1305 {48000, 0x08}, 1306 {88200, 0x09}, 1307 {96000, 0x0A}, 1308 }; 1309 1310 static int rate_value(int rate, u8 *value) 1311 { 1312 int i; 1313 1314 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 1315 if (rate_table[i].rate >= rate) { 1316 *value = rate_table[i].sr; 1317 return 0; 1318 } 1319 } 1320 *value = rate_table[0].sr; 1321 return -EINVAL; 1322 } 1323 1324 static int max98095_dai1_hw_params(struct snd_pcm_substream *substream, 1325 struct snd_pcm_hw_params *params, 1326 struct snd_soc_dai *dai) 1327 { 1328 struct snd_soc_codec *codec = dai->codec; 1329 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1330 struct max98095_cdata *cdata; 1331 unsigned long long ni; 1332 unsigned int rate; 1333 u8 regval; 1334 1335 cdata = &max98095->dai[0]; 1336 1337 rate = params_rate(params); 1338 1339 switch (params_format(params)) { 1340 case SNDRV_PCM_FORMAT_S16_LE: 1341 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, 1342 M98095_DAI_WS, 0); 1343 break; 1344 case SNDRV_PCM_FORMAT_S24_LE: 1345 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, 1346 M98095_DAI_WS, M98095_DAI_WS); 1347 break; 1348 default: 1349 return -EINVAL; 1350 } 1351 1352 if (rate_value(rate, ®val)) 1353 return -EINVAL; 1354 1355 snd_soc_update_bits(codec, M98095_027_DAI1_CLKMODE, 1356 M98095_CLKMODE_MASK, regval); 1357 cdata->rate = rate; 1358 1359 /* Configure NI when operating as master */ 1360 if (snd_soc_read(codec, M98095_02A_DAI1_FORMAT) & M98095_DAI_MAS) { 1361 if (max98095->sysclk == 0) { 1362 dev_err(codec->dev, "Invalid system clock frequency\n"); 1363 return -EINVAL; 1364 } 1365 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1366 * (unsigned long long int)rate; 1367 do_div(ni, (unsigned long long int)max98095->sysclk); 1368 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, 1369 (ni >> 8) & 0x7F); 1370 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, 1371 ni & 0xFF); 1372 } 1373 1374 /* Update sample rate mode */ 1375 if (rate < 50000) 1376 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, 1377 M98095_DAI_DHF, 0); 1378 else 1379 snd_soc_update_bits(codec, M98095_02E_DAI1_FILTERS, 1380 M98095_DAI_DHF, M98095_DAI_DHF); 1381 1382 return 0; 1383 } 1384 1385 static int max98095_dai2_hw_params(struct snd_pcm_substream *substream, 1386 struct snd_pcm_hw_params *params, 1387 struct snd_soc_dai *dai) 1388 { 1389 struct snd_soc_codec *codec = dai->codec; 1390 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1391 struct max98095_cdata *cdata; 1392 unsigned long long ni; 1393 unsigned int rate; 1394 u8 regval; 1395 1396 cdata = &max98095->dai[1]; 1397 1398 rate = params_rate(params); 1399 1400 switch (params_format(params)) { 1401 case SNDRV_PCM_FORMAT_S16_LE: 1402 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, 1403 M98095_DAI_WS, 0); 1404 break; 1405 case SNDRV_PCM_FORMAT_S24_LE: 1406 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, 1407 M98095_DAI_WS, M98095_DAI_WS); 1408 break; 1409 default: 1410 return -EINVAL; 1411 } 1412 1413 if (rate_value(rate, ®val)) 1414 return -EINVAL; 1415 1416 snd_soc_update_bits(codec, M98095_031_DAI2_CLKMODE, 1417 M98095_CLKMODE_MASK, regval); 1418 cdata->rate = rate; 1419 1420 /* Configure NI when operating as master */ 1421 if (snd_soc_read(codec, M98095_034_DAI2_FORMAT) & M98095_DAI_MAS) { 1422 if (max98095->sysclk == 0) { 1423 dev_err(codec->dev, "Invalid system clock frequency\n"); 1424 return -EINVAL; 1425 } 1426 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1427 * (unsigned long long int)rate; 1428 do_div(ni, (unsigned long long int)max98095->sysclk); 1429 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, 1430 (ni >> 8) & 0x7F); 1431 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, 1432 ni & 0xFF); 1433 } 1434 1435 /* Update sample rate mode */ 1436 if (rate < 50000) 1437 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, 1438 M98095_DAI_DHF, 0); 1439 else 1440 snd_soc_update_bits(codec, M98095_038_DAI2_FILTERS, 1441 M98095_DAI_DHF, M98095_DAI_DHF); 1442 1443 return 0; 1444 } 1445 1446 static int max98095_dai3_hw_params(struct snd_pcm_substream *substream, 1447 struct snd_pcm_hw_params *params, 1448 struct snd_soc_dai *dai) 1449 { 1450 struct snd_soc_codec *codec = dai->codec; 1451 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1452 struct max98095_cdata *cdata; 1453 unsigned long long ni; 1454 unsigned int rate; 1455 u8 regval; 1456 1457 cdata = &max98095->dai[2]; 1458 1459 rate = params_rate(params); 1460 1461 switch (params_format(params)) { 1462 case SNDRV_PCM_FORMAT_S16_LE: 1463 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, 1464 M98095_DAI_WS, 0); 1465 break; 1466 case SNDRV_PCM_FORMAT_S24_LE: 1467 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, 1468 M98095_DAI_WS, M98095_DAI_WS); 1469 break; 1470 default: 1471 return -EINVAL; 1472 } 1473 1474 if (rate_value(rate, ®val)) 1475 return -EINVAL; 1476 1477 snd_soc_update_bits(codec, M98095_03B_DAI3_CLKMODE, 1478 M98095_CLKMODE_MASK, regval); 1479 cdata->rate = rate; 1480 1481 /* Configure NI when operating as master */ 1482 if (snd_soc_read(codec, M98095_03E_DAI3_FORMAT) & M98095_DAI_MAS) { 1483 if (max98095->sysclk == 0) { 1484 dev_err(codec->dev, "Invalid system clock frequency\n"); 1485 return -EINVAL; 1486 } 1487 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1488 * (unsigned long long int)rate; 1489 do_div(ni, (unsigned long long int)max98095->sysclk); 1490 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, 1491 (ni >> 8) & 0x7F); 1492 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, 1493 ni & 0xFF); 1494 } 1495 1496 /* Update sample rate mode */ 1497 if (rate < 50000) 1498 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, 1499 M98095_DAI_DHF, 0); 1500 else 1501 snd_soc_update_bits(codec, M98095_042_DAI3_FILTERS, 1502 M98095_DAI_DHF, M98095_DAI_DHF); 1503 1504 return 0; 1505 } 1506 1507 static int max98095_dai_set_sysclk(struct snd_soc_dai *dai, 1508 int clk_id, unsigned int freq, int dir) 1509 { 1510 struct snd_soc_codec *codec = dai->codec; 1511 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1512 1513 /* Requested clock frequency is already setup */ 1514 if (freq == max98095->sysclk) 1515 return 0; 1516 1517 /* Setup clocks for slave mode, and using the PLL 1518 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1519 * 0x02 (when master clk is 20MHz to 40MHz).. 1520 * 0x03 (when master clk is 40MHz to 60MHz).. 1521 */ 1522 if ((freq >= 10000000) && (freq < 20000000)) { 1523 snd_soc_write(codec, M98095_026_SYS_CLK, 0x10); 1524 } else if ((freq >= 20000000) && (freq < 40000000)) { 1525 snd_soc_write(codec, M98095_026_SYS_CLK, 0x20); 1526 } else if ((freq >= 40000000) && (freq < 60000000)) { 1527 snd_soc_write(codec, M98095_026_SYS_CLK, 0x30); 1528 } else { 1529 dev_err(codec->dev, "Invalid master clock frequency\n"); 1530 return -EINVAL; 1531 } 1532 1533 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1534 1535 max98095->sysclk = freq; 1536 return 0; 1537 } 1538 1539 static int max98095_dai1_set_fmt(struct snd_soc_dai *codec_dai, 1540 unsigned int fmt) 1541 { 1542 struct snd_soc_codec *codec = codec_dai->codec; 1543 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1544 struct max98095_cdata *cdata; 1545 u8 regval = 0; 1546 1547 cdata = &max98095->dai[0]; 1548 1549 if (fmt != cdata->fmt) { 1550 cdata->fmt = fmt; 1551 1552 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1553 case SND_SOC_DAIFMT_CBS_CFS: 1554 /* Slave mode PLL */ 1555 snd_soc_write(codec, M98095_028_DAI1_CLKCFG_HI, 1556 0x80); 1557 snd_soc_write(codec, M98095_029_DAI1_CLKCFG_LO, 1558 0x00); 1559 break; 1560 case SND_SOC_DAIFMT_CBM_CFM: 1561 /* Set to master mode */ 1562 regval |= M98095_DAI_MAS; 1563 break; 1564 case SND_SOC_DAIFMT_CBS_CFM: 1565 case SND_SOC_DAIFMT_CBM_CFS: 1566 default: 1567 dev_err(codec->dev, "Clock mode unsupported"); 1568 return -EINVAL; 1569 } 1570 1571 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1572 case SND_SOC_DAIFMT_I2S: 1573 regval |= M98095_DAI_DLY; 1574 break; 1575 case SND_SOC_DAIFMT_LEFT_J: 1576 break; 1577 default: 1578 return -EINVAL; 1579 } 1580 1581 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1582 case SND_SOC_DAIFMT_NB_NF: 1583 break; 1584 case SND_SOC_DAIFMT_NB_IF: 1585 regval |= M98095_DAI_WCI; 1586 break; 1587 case SND_SOC_DAIFMT_IB_NF: 1588 regval |= M98095_DAI_BCI; 1589 break; 1590 case SND_SOC_DAIFMT_IB_IF: 1591 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1592 break; 1593 default: 1594 return -EINVAL; 1595 } 1596 1597 snd_soc_update_bits(codec, M98095_02A_DAI1_FORMAT, 1598 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1599 M98095_DAI_WCI, regval); 1600 1601 snd_soc_write(codec, M98095_02B_DAI1_CLOCK, M98095_DAI_BSEL64); 1602 } 1603 1604 return 0; 1605 } 1606 1607 static int max98095_dai2_set_fmt(struct snd_soc_dai *codec_dai, 1608 unsigned int fmt) 1609 { 1610 struct snd_soc_codec *codec = codec_dai->codec; 1611 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1612 struct max98095_cdata *cdata; 1613 u8 regval = 0; 1614 1615 cdata = &max98095->dai[1]; 1616 1617 if (fmt != cdata->fmt) { 1618 cdata->fmt = fmt; 1619 1620 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1621 case SND_SOC_DAIFMT_CBS_CFS: 1622 /* Slave mode PLL */ 1623 snd_soc_write(codec, M98095_032_DAI2_CLKCFG_HI, 1624 0x80); 1625 snd_soc_write(codec, M98095_033_DAI2_CLKCFG_LO, 1626 0x00); 1627 break; 1628 case SND_SOC_DAIFMT_CBM_CFM: 1629 /* Set to master mode */ 1630 regval |= M98095_DAI_MAS; 1631 break; 1632 case SND_SOC_DAIFMT_CBS_CFM: 1633 case SND_SOC_DAIFMT_CBM_CFS: 1634 default: 1635 dev_err(codec->dev, "Clock mode unsupported"); 1636 return -EINVAL; 1637 } 1638 1639 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1640 case SND_SOC_DAIFMT_I2S: 1641 regval |= M98095_DAI_DLY; 1642 break; 1643 case SND_SOC_DAIFMT_LEFT_J: 1644 break; 1645 default: 1646 return -EINVAL; 1647 } 1648 1649 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1650 case SND_SOC_DAIFMT_NB_NF: 1651 break; 1652 case SND_SOC_DAIFMT_NB_IF: 1653 regval |= M98095_DAI_WCI; 1654 break; 1655 case SND_SOC_DAIFMT_IB_NF: 1656 regval |= M98095_DAI_BCI; 1657 break; 1658 case SND_SOC_DAIFMT_IB_IF: 1659 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1660 break; 1661 default: 1662 return -EINVAL; 1663 } 1664 1665 snd_soc_update_bits(codec, M98095_034_DAI2_FORMAT, 1666 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1667 M98095_DAI_WCI, regval); 1668 1669 snd_soc_write(codec, M98095_035_DAI2_CLOCK, 1670 M98095_DAI_BSEL64); 1671 } 1672 1673 return 0; 1674 } 1675 1676 static int max98095_dai3_set_fmt(struct snd_soc_dai *codec_dai, 1677 unsigned int fmt) 1678 { 1679 struct snd_soc_codec *codec = codec_dai->codec; 1680 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1681 struct max98095_cdata *cdata; 1682 u8 regval = 0; 1683 1684 cdata = &max98095->dai[2]; 1685 1686 if (fmt != cdata->fmt) { 1687 cdata->fmt = fmt; 1688 1689 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1690 case SND_SOC_DAIFMT_CBS_CFS: 1691 /* Slave mode PLL */ 1692 snd_soc_write(codec, M98095_03C_DAI3_CLKCFG_HI, 1693 0x80); 1694 snd_soc_write(codec, M98095_03D_DAI3_CLKCFG_LO, 1695 0x00); 1696 break; 1697 case SND_SOC_DAIFMT_CBM_CFM: 1698 /* Set to master mode */ 1699 regval |= M98095_DAI_MAS; 1700 break; 1701 case SND_SOC_DAIFMT_CBS_CFM: 1702 case SND_SOC_DAIFMT_CBM_CFS: 1703 default: 1704 dev_err(codec->dev, "Clock mode unsupported"); 1705 return -EINVAL; 1706 } 1707 1708 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1709 case SND_SOC_DAIFMT_I2S: 1710 regval |= M98095_DAI_DLY; 1711 break; 1712 case SND_SOC_DAIFMT_LEFT_J: 1713 break; 1714 default: 1715 return -EINVAL; 1716 } 1717 1718 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1719 case SND_SOC_DAIFMT_NB_NF: 1720 break; 1721 case SND_SOC_DAIFMT_NB_IF: 1722 regval |= M98095_DAI_WCI; 1723 break; 1724 case SND_SOC_DAIFMT_IB_NF: 1725 regval |= M98095_DAI_BCI; 1726 break; 1727 case SND_SOC_DAIFMT_IB_IF: 1728 regval |= M98095_DAI_BCI|M98095_DAI_WCI; 1729 break; 1730 default: 1731 return -EINVAL; 1732 } 1733 1734 snd_soc_update_bits(codec, M98095_03E_DAI3_FORMAT, 1735 M98095_DAI_MAS | M98095_DAI_DLY | M98095_DAI_BCI | 1736 M98095_DAI_WCI, regval); 1737 1738 snd_soc_write(codec, M98095_03F_DAI3_CLOCK, 1739 M98095_DAI_BSEL64); 1740 } 1741 1742 return 0; 1743 } 1744 1745 static int max98095_set_bias_level(struct snd_soc_codec *codec, 1746 enum snd_soc_bias_level level) 1747 { 1748 int ret; 1749 1750 switch (level) { 1751 case SND_SOC_BIAS_ON: 1752 break; 1753 1754 case SND_SOC_BIAS_PREPARE: 1755 break; 1756 1757 case SND_SOC_BIAS_STANDBY: 1758 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1759 ret = snd_soc_cache_sync(codec); 1760 1761 if (ret != 0) { 1762 dev_err(codec->dev, "Failed to sync cache: %d\n", ret); 1763 return ret; 1764 } 1765 } 1766 1767 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, 1768 M98095_MBEN, M98095_MBEN); 1769 break; 1770 1771 case SND_SOC_BIAS_OFF: 1772 snd_soc_update_bits(codec, M98095_090_PWR_EN_IN, 1773 M98095_MBEN, 0); 1774 codec->cache_sync = 1; 1775 break; 1776 } 1777 codec->dapm.bias_level = level; 1778 return 0; 1779 } 1780 1781 #define MAX98095_RATES SNDRV_PCM_RATE_8000_96000 1782 #define MAX98095_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 1783 1784 static const struct snd_soc_dai_ops max98095_dai1_ops = { 1785 .set_sysclk = max98095_dai_set_sysclk, 1786 .set_fmt = max98095_dai1_set_fmt, 1787 .hw_params = max98095_dai1_hw_params, 1788 }; 1789 1790 static const struct snd_soc_dai_ops max98095_dai2_ops = { 1791 .set_sysclk = max98095_dai_set_sysclk, 1792 .set_fmt = max98095_dai2_set_fmt, 1793 .hw_params = max98095_dai2_hw_params, 1794 }; 1795 1796 static const struct snd_soc_dai_ops max98095_dai3_ops = { 1797 .set_sysclk = max98095_dai_set_sysclk, 1798 .set_fmt = max98095_dai3_set_fmt, 1799 .hw_params = max98095_dai3_hw_params, 1800 }; 1801 1802 static struct snd_soc_dai_driver max98095_dai[] = { 1803 { 1804 .name = "HiFi", 1805 .playback = { 1806 .stream_name = "HiFi Playback", 1807 .channels_min = 1, 1808 .channels_max = 2, 1809 .rates = MAX98095_RATES, 1810 .formats = MAX98095_FORMATS, 1811 }, 1812 .capture = { 1813 .stream_name = "HiFi Capture", 1814 .channels_min = 1, 1815 .channels_max = 2, 1816 .rates = MAX98095_RATES, 1817 .formats = MAX98095_FORMATS, 1818 }, 1819 .ops = &max98095_dai1_ops, 1820 }, 1821 { 1822 .name = "Aux", 1823 .playback = { 1824 .stream_name = "Aux Playback", 1825 .channels_min = 1, 1826 .channels_max = 1, 1827 .rates = MAX98095_RATES, 1828 .formats = MAX98095_FORMATS, 1829 }, 1830 .ops = &max98095_dai2_ops, 1831 }, 1832 { 1833 .name = "Voice", 1834 .playback = { 1835 .stream_name = "Voice Playback", 1836 .channels_min = 1, 1837 .channels_max = 1, 1838 .rates = MAX98095_RATES, 1839 .formats = MAX98095_FORMATS, 1840 }, 1841 .ops = &max98095_dai3_ops, 1842 } 1843 1844 }; 1845 1846 static int max98095_get_eq_channel(const char *name) 1847 { 1848 if (strcmp(name, "EQ1 Mode") == 0) 1849 return 0; 1850 if (strcmp(name, "EQ2 Mode") == 0) 1851 return 1; 1852 return -EINVAL; 1853 } 1854 1855 static int max98095_put_eq_enum(struct snd_kcontrol *kcontrol, 1856 struct snd_ctl_elem_value *ucontrol) 1857 { 1858 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1859 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1860 struct max98095_pdata *pdata = max98095->pdata; 1861 int channel = max98095_get_eq_channel(kcontrol->id.name); 1862 struct max98095_cdata *cdata; 1863 int sel = ucontrol->value.integer.value[0]; 1864 struct max98095_eq_cfg *coef_set; 1865 int fs, best, best_val, i; 1866 int regmask, regsave; 1867 1868 BUG_ON(channel > 1); 1869 1870 if (!pdata || !max98095->eq_textcnt) 1871 return 0; 1872 1873 if (sel >= pdata->eq_cfgcnt) 1874 return -EINVAL; 1875 1876 cdata = &max98095->dai[channel]; 1877 cdata->eq_sel = sel; 1878 fs = cdata->rate; 1879 1880 /* Find the selected configuration with nearest sample rate */ 1881 best = 0; 1882 best_val = INT_MAX; 1883 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1884 if (strcmp(pdata->eq_cfg[i].name, max98095->eq_texts[sel]) == 0 && 1885 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1886 best = i; 1887 best_val = abs(pdata->eq_cfg[i].rate - fs); 1888 } 1889 } 1890 1891 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 1892 pdata->eq_cfg[best].name, 1893 pdata->eq_cfg[best].rate, fs); 1894 1895 coef_set = &pdata->eq_cfg[best]; 1896 1897 regmask = (channel == 0) ? M98095_EQ1EN : M98095_EQ2EN; 1898 1899 /* Disable filter while configuring, and save current on/off state */ 1900 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); 1901 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); 1902 1903 mutex_lock(&codec->mutex); 1904 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); 1905 m98095_eq_band(codec, channel, 0, coef_set->band1); 1906 m98095_eq_band(codec, channel, 1, coef_set->band2); 1907 m98095_eq_band(codec, channel, 2, coef_set->band3); 1908 m98095_eq_band(codec, channel, 3, coef_set->band4); 1909 m98095_eq_band(codec, channel, 4, coef_set->band5); 1910 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); 1911 mutex_unlock(&codec->mutex); 1912 1913 /* Restore the original on/off state */ 1914 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); 1915 return 0; 1916 } 1917 1918 static int max98095_get_eq_enum(struct snd_kcontrol *kcontrol, 1919 struct snd_ctl_elem_value *ucontrol) 1920 { 1921 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1922 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1923 int channel = max98095_get_eq_channel(kcontrol->id.name); 1924 struct max98095_cdata *cdata; 1925 1926 cdata = &max98095->dai[channel]; 1927 ucontrol->value.enumerated.item[0] = cdata->eq_sel; 1928 1929 return 0; 1930 } 1931 1932 static void max98095_handle_eq_pdata(struct snd_soc_codec *codec) 1933 { 1934 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 1935 struct max98095_pdata *pdata = max98095->pdata; 1936 struct max98095_eq_cfg *cfg; 1937 unsigned int cfgcnt; 1938 int i, j; 1939 const char **t; 1940 int ret; 1941 1942 struct snd_kcontrol_new controls[] = { 1943 SOC_ENUM_EXT("EQ1 Mode", 1944 max98095->eq_enum, 1945 max98095_get_eq_enum, 1946 max98095_put_eq_enum), 1947 SOC_ENUM_EXT("EQ2 Mode", 1948 max98095->eq_enum, 1949 max98095_get_eq_enum, 1950 max98095_put_eq_enum), 1951 }; 1952 1953 cfg = pdata->eq_cfg; 1954 cfgcnt = pdata->eq_cfgcnt; 1955 1956 /* Setup an array of texts for the equalizer enum. 1957 * This is based on Mark Brown's equalizer driver code. 1958 */ 1959 max98095->eq_textcnt = 0; 1960 max98095->eq_texts = NULL; 1961 for (i = 0; i < cfgcnt; i++) { 1962 for (j = 0; j < max98095->eq_textcnt; j++) { 1963 if (strcmp(cfg[i].name, max98095->eq_texts[j]) == 0) 1964 break; 1965 } 1966 1967 if (j != max98095->eq_textcnt) 1968 continue; 1969 1970 /* Expand the array */ 1971 t = krealloc(max98095->eq_texts, 1972 sizeof(char *) * (max98095->eq_textcnt + 1), 1973 GFP_KERNEL); 1974 if (t == NULL) 1975 continue; 1976 1977 /* Store the new entry */ 1978 t[max98095->eq_textcnt] = cfg[i].name; 1979 max98095->eq_textcnt++; 1980 max98095->eq_texts = t; 1981 } 1982 1983 /* Now point the soc_enum to .texts array items */ 1984 max98095->eq_enum.texts = max98095->eq_texts; 1985 max98095->eq_enum.max = max98095->eq_textcnt; 1986 1987 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 1988 if (ret != 0) 1989 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret); 1990 } 1991 1992 static const char *bq_mode_name[] = {"Biquad1 Mode", "Biquad2 Mode"}; 1993 1994 static int max98095_get_bq_channel(struct snd_soc_codec *codec, 1995 const char *name) 1996 { 1997 int i; 1998 1999 for (i = 0; i < ARRAY_SIZE(bq_mode_name); i++) 2000 if (strcmp(name, bq_mode_name[i]) == 0) 2001 return i; 2002 2003 /* Shouldn't happen */ 2004 dev_err(codec->dev, "Bad biquad channel name '%s'\n", name); 2005 return -EINVAL; 2006 } 2007 2008 static int max98095_put_bq_enum(struct snd_kcontrol *kcontrol, 2009 struct snd_ctl_elem_value *ucontrol) 2010 { 2011 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 2012 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2013 struct max98095_pdata *pdata = max98095->pdata; 2014 int channel = max98095_get_bq_channel(codec, kcontrol->id.name); 2015 struct max98095_cdata *cdata; 2016 int sel = ucontrol->value.integer.value[0]; 2017 struct max98095_biquad_cfg *coef_set; 2018 int fs, best, best_val, i; 2019 int regmask, regsave; 2020 2021 if (channel < 0) 2022 return channel; 2023 2024 if (!pdata || !max98095->bq_textcnt) 2025 return 0; 2026 2027 if (sel >= pdata->bq_cfgcnt) 2028 return -EINVAL; 2029 2030 cdata = &max98095->dai[channel]; 2031 cdata->bq_sel = sel; 2032 fs = cdata->rate; 2033 2034 /* Find the selected configuration with nearest sample rate */ 2035 best = 0; 2036 best_val = INT_MAX; 2037 for (i = 0; i < pdata->bq_cfgcnt; i++) { 2038 if (strcmp(pdata->bq_cfg[i].name, max98095->bq_texts[sel]) == 0 && 2039 abs(pdata->bq_cfg[i].rate - fs) < best_val) { 2040 best = i; 2041 best_val = abs(pdata->bq_cfg[i].rate - fs); 2042 } 2043 } 2044 2045 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 2046 pdata->bq_cfg[best].name, 2047 pdata->bq_cfg[best].rate, fs); 2048 2049 coef_set = &pdata->bq_cfg[best]; 2050 2051 regmask = (channel == 0) ? M98095_BQ1EN : M98095_BQ2EN; 2052 2053 /* Disable filter while configuring, and save current on/off state */ 2054 regsave = snd_soc_read(codec, M98095_088_CFG_LEVEL); 2055 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, 0); 2056 2057 mutex_lock(&codec->mutex); 2058 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, M98095_SEG); 2059 m98095_biquad_band(codec, channel, 0, coef_set->band1); 2060 m98095_biquad_band(codec, channel, 1, coef_set->band2); 2061 snd_soc_update_bits(codec, M98095_00F_HOST_CFG, M98095_SEG, 0); 2062 mutex_unlock(&codec->mutex); 2063 2064 /* Restore the original on/off state */ 2065 snd_soc_update_bits(codec, M98095_088_CFG_LEVEL, regmask, regsave); 2066 return 0; 2067 } 2068 2069 static int max98095_get_bq_enum(struct snd_kcontrol *kcontrol, 2070 struct snd_ctl_elem_value *ucontrol) 2071 { 2072 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 2073 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2074 int channel = max98095_get_bq_channel(codec, kcontrol->id.name); 2075 struct max98095_cdata *cdata; 2076 2077 if (channel < 0) 2078 return channel; 2079 2080 cdata = &max98095->dai[channel]; 2081 ucontrol->value.enumerated.item[0] = cdata->bq_sel; 2082 2083 return 0; 2084 } 2085 2086 static void max98095_handle_bq_pdata(struct snd_soc_codec *codec) 2087 { 2088 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2089 struct max98095_pdata *pdata = max98095->pdata; 2090 struct max98095_biquad_cfg *cfg; 2091 unsigned int cfgcnt; 2092 int i, j; 2093 const char **t; 2094 int ret; 2095 2096 struct snd_kcontrol_new controls[] = { 2097 SOC_ENUM_EXT((char *)bq_mode_name[0], 2098 max98095->bq_enum, 2099 max98095_get_bq_enum, 2100 max98095_put_bq_enum), 2101 SOC_ENUM_EXT((char *)bq_mode_name[1], 2102 max98095->bq_enum, 2103 max98095_get_bq_enum, 2104 max98095_put_bq_enum), 2105 }; 2106 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(bq_mode_name)); 2107 2108 cfg = pdata->bq_cfg; 2109 cfgcnt = pdata->bq_cfgcnt; 2110 2111 /* Setup an array of texts for the biquad enum. 2112 * This is based on Mark Brown's equalizer driver code. 2113 */ 2114 max98095->bq_textcnt = 0; 2115 max98095->bq_texts = NULL; 2116 for (i = 0; i < cfgcnt; i++) { 2117 for (j = 0; j < max98095->bq_textcnt; j++) { 2118 if (strcmp(cfg[i].name, max98095->bq_texts[j]) == 0) 2119 break; 2120 } 2121 2122 if (j != max98095->bq_textcnt) 2123 continue; 2124 2125 /* Expand the array */ 2126 t = krealloc(max98095->bq_texts, 2127 sizeof(char *) * (max98095->bq_textcnt + 1), 2128 GFP_KERNEL); 2129 if (t == NULL) 2130 continue; 2131 2132 /* Store the new entry */ 2133 t[max98095->bq_textcnt] = cfg[i].name; 2134 max98095->bq_textcnt++; 2135 max98095->bq_texts = t; 2136 } 2137 2138 /* Now point the soc_enum to .texts array items */ 2139 max98095->bq_enum.texts = max98095->bq_texts; 2140 max98095->bq_enum.max = max98095->bq_textcnt; 2141 2142 ret = snd_soc_add_codec_controls(codec, controls, ARRAY_SIZE(controls)); 2143 if (ret != 0) 2144 dev_err(codec->dev, "Failed to add Biquad control: %d\n", ret); 2145 } 2146 2147 static void max98095_handle_pdata(struct snd_soc_codec *codec) 2148 { 2149 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2150 struct max98095_pdata *pdata = max98095->pdata; 2151 u8 regval = 0; 2152 2153 if (!pdata) { 2154 dev_dbg(codec->dev, "No platform data\n"); 2155 return; 2156 } 2157 2158 /* Configure mic for analog/digital mic mode */ 2159 if (pdata->digmic_left_mode) 2160 regval |= M98095_DIGMIC_L; 2161 2162 if (pdata->digmic_right_mode) 2163 regval |= M98095_DIGMIC_R; 2164 2165 snd_soc_write(codec, M98095_087_CFG_MIC, regval); 2166 2167 /* Configure equalizers */ 2168 if (pdata->eq_cfgcnt) 2169 max98095_handle_eq_pdata(codec); 2170 2171 /* Configure bi-quad filters */ 2172 if (pdata->bq_cfgcnt) 2173 max98095_handle_bq_pdata(codec); 2174 } 2175 2176 #ifdef CONFIG_PM 2177 static int max98095_suspend(struct snd_soc_codec *codec) 2178 { 2179 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); 2180 2181 return 0; 2182 } 2183 2184 static int max98095_resume(struct snd_soc_codec *codec) 2185 { 2186 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2187 2188 return 0; 2189 } 2190 #else 2191 #define max98095_suspend NULL 2192 #define max98095_resume NULL 2193 #endif 2194 2195 static int max98095_reset(struct snd_soc_codec *codec) 2196 { 2197 int i, ret; 2198 2199 /* Gracefully reset the DSP core and the codec hardware 2200 * in a proper sequence */ 2201 ret = snd_soc_write(codec, M98095_00F_HOST_CFG, 0); 2202 if (ret < 0) { 2203 dev_err(codec->dev, "Failed to reset DSP: %d\n", ret); 2204 return ret; 2205 } 2206 2207 ret = snd_soc_write(codec, M98095_097_PWR_SYS, 0); 2208 if (ret < 0) { 2209 dev_err(codec->dev, "Failed to reset codec: %d\n", ret); 2210 return ret; 2211 } 2212 2213 /* Reset to hardware default for registers, as there is not 2214 * a soft reset hardware control register */ 2215 for (i = M98095_010_HOST_INT_CFG; i < M98095_REG_MAX_CACHED; i++) { 2216 ret = snd_soc_write(codec, i, max98095_reg_def[i]); 2217 if (ret < 0) { 2218 dev_err(codec->dev, "Failed to reset: %d\n", ret); 2219 return ret; 2220 } 2221 } 2222 2223 return ret; 2224 } 2225 2226 static int max98095_probe(struct snd_soc_codec *codec) 2227 { 2228 struct max98095_priv *max98095 = snd_soc_codec_get_drvdata(codec); 2229 struct max98095_cdata *cdata; 2230 int ret = 0; 2231 2232 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 2233 if (ret != 0) { 2234 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 2235 return ret; 2236 } 2237 2238 /* reset the codec, the DSP core, and disable all interrupts */ 2239 max98095_reset(codec); 2240 2241 /* initialize private data */ 2242 2243 max98095->sysclk = (unsigned)-1; 2244 max98095->eq_textcnt = 0; 2245 max98095->bq_textcnt = 0; 2246 2247 cdata = &max98095->dai[0]; 2248 cdata->rate = (unsigned)-1; 2249 cdata->fmt = (unsigned)-1; 2250 cdata->eq_sel = 0; 2251 cdata->bq_sel = 0; 2252 2253 cdata = &max98095->dai[1]; 2254 cdata->rate = (unsigned)-1; 2255 cdata->fmt = (unsigned)-1; 2256 cdata->eq_sel = 0; 2257 cdata->bq_sel = 0; 2258 2259 cdata = &max98095->dai[2]; 2260 cdata->rate = (unsigned)-1; 2261 cdata->fmt = (unsigned)-1; 2262 cdata->eq_sel = 0; 2263 cdata->bq_sel = 0; 2264 2265 max98095->lin_state = 0; 2266 max98095->mic1pre = 0; 2267 max98095->mic2pre = 0; 2268 2269 ret = snd_soc_read(codec, M98095_0FF_REV_ID); 2270 if (ret < 0) { 2271 dev_err(codec->dev, "Failure reading hardware revision: %d\n", 2272 ret); 2273 goto err_access; 2274 } 2275 dev_info(codec->dev, "Hardware revision: %c\n", ret - 0x40 + 'A'); 2276 2277 snd_soc_write(codec, M98095_097_PWR_SYS, M98095_PWRSV); 2278 2279 /* initialize registers cache to hardware default */ 2280 max98095_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 2281 2282 snd_soc_write(codec, M98095_048_MIX_DAC_LR, 2283 M98095_DAI1L_TO_DACL|M98095_DAI1R_TO_DACR); 2284 2285 snd_soc_write(codec, M98095_049_MIX_DAC_M, 2286 M98095_DAI2M_TO_DACM|M98095_DAI3M_TO_DACM); 2287 2288 snd_soc_write(codec, M98095_092_PWR_EN_OUT, M98095_SPK_SPREADSPECTRUM); 2289 snd_soc_write(codec, M98095_045_CFG_DSP, M98095_DSPNORMAL); 2290 snd_soc_write(codec, M98095_04E_CFG_HP, M98095_HPNORMAL); 2291 2292 snd_soc_write(codec, M98095_02C_DAI1_IOCFG, 2293 M98095_S1NORMAL|M98095_SDATA); 2294 2295 snd_soc_write(codec, M98095_036_DAI2_IOCFG, 2296 M98095_S2NORMAL|M98095_SDATA); 2297 2298 snd_soc_write(codec, M98095_040_DAI3_IOCFG, 2299 M98095_S3NORMAL|M98095_SDATA); 2300 2301 max98095_handle_pdata(codec); 2302 2303 /* take the codec out of the shut down */ 2304 snd_soc_update_bits(codec, M98095_097_PWR_SYS, M98095_SHDNRUN, 2305 M98095_SHDNRUN); 2306 2307 max98095_add_widgets(codec); 2308 2309 err_access: 2310 return ret; 2311 } 2312 2313 static int max98095_remove(struct snd_soc_codec *codec) 2314 { 2315 max98095_set_bias_level(codec, SND_SOC_BIAS_OFF); 2316 2317 return 0; 2318 } 2319 2320 static struct snd_soc_codec_driver soc_codec_dev_max98095 = { 2321 .probe = max98095_probe, 2322 .remove = max98095_remove, 2323 .suspend = max98095_suspend, 2324 .resume = max98095_resume, 2325 .set_bias_level = max98095_set_bias_level, 2326 .reg_cache_size = ARRAY_SIZE(max98095_reg_def), 2327 .reg_word_size = sizeof(u8), 2328 .reg_cache_default = max98095_reg_def, 2329 .readable_register = max98095_readable, 2330 .volatile_register = max98095_volatile, 2331 .dapm_widgets = max98095_dapm_widgets, 2332 .num_dapm_widgets = ARRAY_SIZE(max98095_dapm_widgets), 2333 .dapm_routes = max98095_audio_map, 2334 .num_dapm_routes = ARRAY_SIZE(max98095_audio_map), 2335 }; 2336 2337 static int max98095_i2c_probe(struct i2c_client *i2c, 2338 const struct i2c_device_id *id) 2339 { 2340 struct max98095_priv *max98095; 2341 int ret; 2342 2343 max98095 = devm_kzalloc(&i2c->dev, sizeof(struct max98095_priv), 2344 GFP_KERNEL); 2345 if (max98095 == NULL) 2346 return -ENOMEM; 2347 2348 max98095->devtype = id->driver_data; 2349 i2c_set_clientdata(i2c, max98095); 2350 max98095->pdata = i2c->dev.platform_data; 2351 2352 ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98095, 2353 max98095_dai, ARRAY_SIZE(max98095_dai)); 2354 return ret; 2355 } 2356 2357 static int __devexit max98095_i2c_remove(struct i2c_client *client) 2358 { 2359 snd_soc_unregister_codec(&client->dev); 2360 return 0; 2361 } 2362 2363 static const struct i2c_device_id max98095_i2c_id[] = { 2364 { "max98095", MAX98095 }, 2365 { } 2366 }; 2367 MODULE_DEVICE_TABLE(i2c, max98095_i2c_id); 2368 2369 static struct i2c_driver max98095_i2c_driver = { 2370 .driver = { 2371 .name = "max98095", 2372 .owner = THIS_MODULE, 2373 }, 2374 .probe = max98095_i2c_probe, 2375 .remove = __devexit_p(max98095_i2c_remove), 2376 .id_table = max98095_i2c_id, 2377 }; 2378 2379 static int __init max98095_init(void) 2380 { 2381 int ret; 2382 2383 ret = i2c_add_driver(&max98095_i2c_driver); 2384 if (ret) 2385 pr_err("Failed to register max98095 I2C driver: %d\n", ret); 2386 2387 return ret; 2388 } 2389 module_init(max98095_init); 2390 2391 static void __exit max98095_exit(void) 2392 { 2393 i2c_del_driver(&max98095_i2c_driver); 2394 } 2395 module_exit(max98095_exit); 2396 2397 MODULE_DESCRIPTION("ALSA SoC MAX98095 driver"); 2398 MODULE_AUTHOR("Peter Hsiang"); 2399 MODULE_LICENSE("GPL"); 2400