1 /* 2 * max98090.c -- MAX98090 ALSA SoC Audio driver 3 * 4 * Copyright 2011-2012 Maxim Integrated Products 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/i2c.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/pm.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 #include <linux/acpi.h> 20 #include <linux/clk.h> 21 #include <sound/jack.h> 22 #include <sound/pcm.h> 23 #include <sound/pcm_params.h> 24 #include <sound/soc.h> 25 #include <sound/tlv.h> 26 #include <sound/max98090.h> 27 #include "max98090.h" 28 29 #define DEBUG 30 #define EXTMIC_METHOD 31 #define EXTMIC_METHOD_TEST 32 33 /* Allows for sparsely populated register maps */ 34 static struct reg_default max98090_reg[] = { 35 { 0x00, 0x00 }, /* 00 Software Reset */ 36 { 0x03, 0x04 }, /* 03 Interrupt Masks */ 37 { 0x04, 0x00 }, /* 04 System Clock Quick */ 38 { 0x05, 0x00 }, /* 05 Sample Rate Quick */ 39 { 0x06, 0x00 }, /* 06 DAI Interface Quick */ 40 { 0x07, 0x00 }, /* 07 DAC Path Quick */ 41 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */ 42 { 0x09, 0x00 }, /* 09 Line to ADC Quick */ 43 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */ 44 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */ 45 { 0x0C, 0x00 }, /* 0C Reserved */ 46 { 0x0D, 0x00 }, /* 0D Input Config */ 47 { 0x0E, 0x1B }, /* 0E Line Input Level */ 48 { 0x0F, 0x00 }, /* 0F Line Config */ 49 50 { 0x10, 0x14 }, /* 10 Mic1 Input Level */ 51 { 0x11, 0x14 }, /* 11 Mic2 Input Level */ 52 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */ 53 { 0x13, 0x00 }, /* 13 Digital Mic Config */ 54 { 0x14, 0x00 }, /* 14 Digital Mic Mode */ 55 { 0x15, 0x00 }, /* 15 Left ADC Mixer */ 56 { 0x16, 0x00 }, /* 16 Right ADC Mixer */ 57 { 0x17, 0x03 }, /* 17 Left ADC Level */ 58 { 0x18, 0x03 }, /* 18 Right ADC Level */ 59 { 0x19, 0x00 }, /* 19 ADC Biquad Level */ 60 { 0x1A, 0x00 }, /* 1A ADC Sidetone */ 61 { 0x1B, 0x00 }, /* 1B System Clock */ 62 { 0x1C, 0x00 }, /* 1C Clock Mode */ 63 { 0x1D, 0x00 }, /* 1D Any Clock 1 */ 64 { 0x1E, 0x00 }, /* 1E Any Clock 2 */ 65 { 0x1F, 0x00 }, /* 1F Any Clock 3 */ 66 67 { 0x20, 0x00 }, /* 20 Any Clock 4 */ 68 { 0x21, 0x00 }, /* 21 Master Mode */ 69 { 0x22, 0x00 }, /* 22 Interface Format */ 70 { 0x23, 0x00 }, /* 23 TDM Format 1*/ 71 { 0x24, 0x00 }, /* 24 TDM Format 2*/ 72 { 0x25, 0x00 }, /* 25 I/O Configuration */ 73 { 0x26, 0x80 }, /* 26 Filter Config */ 74 { 0x27, 0x00 }, /* 27 DAI Playback Level */ 75 { 0x28, 0x00 }, /* 28 EQ Playback Level */ 76 { 0x29, 0x00 }, /* 29 Left HP Mixer */ 77 { 0x2A, 0x00 }, /* 2A Right HP Mixer */ 78 { 0x2B, 0x00 }, /* 2B HP Control */ 79 { 0x2C, 0x1A }, /* 2C Left HP Volume */ 80 { 0x2D, 0x1A }, /* 2D Right HP Volume */ 81 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */ 82 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */ 83 84 { 0x30, 0x00 }, /* 30 Spk Control */ 85 { 0x31, 0x2C }, /* 31 Left Spk Volume */ 86 { 0x32, 0x2C }, /* 32 Right Spk Volume */ 87 { 0x33, 0x00 }, /* 33 ALC Timing */ 88 { 0x34, 0x00 }, /* 34 ALC Compressor */ 89 { 0x35, 0x00 }, /* 35 ALC Expander */ 90 { 0x36, 0x00 }, /* 36 ALC Gain */ 91 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */ 92 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */ 93 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */ 94 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */ 95 { 0x3B, 0x00 }, /* 3B Line OutR Control */ 96 { 0x3C, 0x15 }, /* 3C Line OutR Volume */ 97 { 0x3D, 0x00 }, /* 3D Jack Detect */ 98 { 0x3E, 0x00 }, /* 3E Input Enable */ 99 { 0x3F, 0x00 }, /* 3F Output Enable */ 100 101 { 0x40, 0x00 }, /* 40 Level Control */ 102 { 0x41, 0x00 }, /* 41 DSP Filter Enable */ 103 { 0x42, 0x00 }, /* 42 Bias Control */ 104 { 0x43, 0x00 }, /* 43 DAC Control */ 105 { 0x44, 0x06 }, /* 44 ADC Control */ 106 { 0x45, 0x00 }, /* 45 Device Shutdown */ 107 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */ 108 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */ 109 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */ 110 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */ 111 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */ 112 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */ 113 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */ 114 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */ 115 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */ 116 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */ 117 118 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */ 119 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */ 120 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */ 121 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */ 122 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */ 123 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */ 124 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */ 125 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */ 126 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */ 127 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */ 128 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */ 129 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */ 130 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */ 131 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */ 132 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */ 133 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */ 134 135 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */ 136 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */ 137 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */ 138 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */ 139 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */ 140 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */ 141 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */ 142 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */ 143 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */ 144 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */ 145 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */ 146 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */ 147 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */ 148 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */ 149 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */ 150 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */ 151 152 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */ 153 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */ 154 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */ 155 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */ 156 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */ 157 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */ 158 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */ 159 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */ 160 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */ 161 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */ 162 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */ 163 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */ 164 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */ 165 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */ 166 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */ 167 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */ 168 169 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */ 170 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */ 171 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */ 172 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */ 173 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */ 174 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */ 175 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */ 176 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */ 177 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */ 178 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */ 179 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */ 180 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */ 181 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */ 182 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */ 183 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */ 184 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */ 185 186 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */ 187 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */ 188 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */ 189 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */ 190 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */ 191 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */ 192 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */ 193 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */ 194 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */ 195 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */ 196 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */ 197 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */ 198 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */ 199 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */ 200 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */ 201 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */ 202 203 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */ 204 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */ 205 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */ 206 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */ 207 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */ 208 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */ 209 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */ 210 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */ 211 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */ 212 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */ 213 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */ 214 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */ 215 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */ 216 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */ 217 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */ 218 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */ 219 220 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */ 221 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */ 222 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */ 223 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */ 224 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */ 225 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */ 226 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */ 227 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */ 228 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */ 229 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */ 230 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */ 231 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */ 232 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */ 233 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */ 234 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */ 235 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */ 236 237 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */ 238 { 0xC1, 0x00 }, /* C1 Record TDM Slot */ 239 { 0xC2, 0x00 }, /* C2 Sample Rate */ 240 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */ 241 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */ 242 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */ 243 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */ 244 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */ 245 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */ 246 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */ 247 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */ 248 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */ 249 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */ 250 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */ 251 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */ 252 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */ 253 254 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */ 255 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */ 256 }; 257 258 static bool max98090_volatile_register(struct device *dev, unsigned int reg) 259 { 260 switch (reg) { 261 case M98090_REG_SOFTWARE_RESET: 262 case M98090_REG_DEVICE_STATUS: 263 case M98090_REG_JACK_STATUS: 264 case M98090_REG_REVISION_ID: 265 return true; 266 default: 267 return false; 268 } 269 } 270 271 static bool max98090_readable_register(struct device *dev, unsigned int reg) 272 { 273 switch (reg) { 274 case M98090_REG_DEVICE_STATUS: 275 case M98090_REG_JACK_STATUS: 276 case M98090_REG_INTERRUPT_S: 277 case M98090_REG_RESERVED: 278 case M98090_REG_LINE_INPUT_CONFIG: 279 case M98090_REG_LINE_INPUT_LEVEL: 280 case M98090_REG_INPUT_MODE: 281 case M98090_REG_MIC1_INPUT_LEVEL: 282 case M98090_REG_MIC2_INPUT_LEVEL: 283 case M98090_REG_MIC_BIAS_VOLTAGE: 284 case M98090_REG_DIGITAL_MIC_ENABLE: 285 case M98090_REG_DIGITAL_MIC_CONFIG: 286 case M98090_REG_LEFT_ADC_MIXER: 287 case M98090_REG_RIGHT_ADC_MIXER: 288 case M98090_REG_LEFT_ADC_LEVEL: 289 case M98090_REG_RIGHT_ADC_LEVEL: 290 case M98090_REG_ADC_BIQUAD_LEVEL: 291 case M98090_REG_ADC_SIDETONE: 292 case M98090_REG_SYSTEM_CLOCK: 293 case M98090_REG_CLOCK_MODE: 294 case M98090_REG_CLOCK_RATIO_NI_MSB: 295 case M98090_REG_CLOCK_RATIO_NI_LSB: 296 case M98090_REG_CLOCK_RATIO_MI_MSB: 297 case M98090_REG_CLOCK_RATIO_MI_LSB: 298 case M98090_REG_MASTER_MODE: 299 case M98090_REG_INTERFACE_FORMAT: 300 case M98090_REG_TDM_CONTROL: 301 case M98090_REG_TDM_FORMAT: 302 case M98090_REG_IO_CONFIGURATION: 303 case M98090_REG_FILTER_CONFIG: 304 case M98090_REG_DAI_PLAYBACK_LEVEL: 305 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ: 306 case M98090_REG_LEFT_HP_MIXER: 307 case M98090_REG_RIGHT_HP_MIXER: 308 case M98090_REG_HP_CONTROL: 309 case M98090_REG_LEFT_HP_VOLUME: 310 case M98090_REG_RIGHT_HP_VOLUME: 311 case M98090_REG_LEFT_SPK_MIXER: 312 case M98090_REG_RIGHT_SPK_MIXER: 313 case M98090_REG_SPK_CONTROL: 314 case M98090_REG_LEFT_SPK_VOLUME: 315 case M98090_REG_RIGHT_SPK_VOLUME: 316 case M98090_REG_DRC_TIMING: 317 case M98090_REG_DRC_COMPRESSOR: 318 case M98090_REG_DRC_EXPANDER: 319 case M98090_REG_DRC_GAIN: 320 case M98090_REG_RCV_LOUTL_MIXER: 321 case M98090_REG_RCV_LOUTL_CONTROL: 322 case M98090_REG_RCV_LOUTL_VOLUME: 323 case M98090_REG_LOUTR_MIXER: 324 case M98090_REG_LOUTR_CONTROL: 325 case M98090_REG_LOUTR_VOLUME: 326 case M98090_REG_JACK_DETECT: 327 case M98090_REG_INPUT_ENABLE: 328 case M98090_REG_OUTPUT_ENABLE: 329 case M98090_REG_LEVEL_CONTROL: 330 case M98090_REG_DSP_FILTER_ENABLE: 331 case M98090_REG_BIAS_CONTROL: 332 case M98090_REG_DAC_CONTROL: 333 case M98090_REG_ADC_CONTROL: 334 case M98090_REG_DEVICE_SHUTDOWN: 335 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68: 336 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E: 337 case M98090_REG_DMIC3_VOLUME: 338 case M98090_REG_DMIC4_VOLUME: 339 case M98090_REG_DMIC34_BQ_PREATTEN: 340 case M98090_REG_RECORD_TDM_SLOT: 341 case M98090_REG_SAMPLE_RATE: 342 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E: 343 case M98090_REG_REVISION_ID: 344 return true; 345 default: 346 return false; 347 } 348 } 349 350 static int max98090_reset(struct max98090_priv *max98090) 351 { 352 int ret; 353 354 /* Reset the codec by writing to this write-only reset register */ 355 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, 356 M98090_SWRESET_MASK); 357 if (ret < 0) { 358 dev_err(max98090->codec->dev, 359 "Failed to reset codec: %d\n", ret); 360 return ret; 361 } 362 363 msleep(20); 364 return ret; 365 } 366 367 static const unsigned int max98090_micboost_tlv[] = { 368 TLV_DB_RANGE_HEAD(2), 369 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 370 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), 371 }; 372 373 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0); 374 375 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv, 376 -600, 600, 0); 377 378 static const unsigned int max98090_line_tlv[] = { 379 TLV_DB_RANGE_HEAD(2), 380 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0), 381 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), 382 }; 383 384 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0); 385 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0); 386 387 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0); 388 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0); 389 390 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0); 391 392 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0); 393 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0); 394 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0); 395 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0); 396 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0); 397 398 static const unsigned int max98090_mixout_tlv[] = { 399 TLV_DB_RANGE_HEAD(2), 400 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0), 401 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0), 402 }; 403 404 static const unsigned int max98090_hp_tlv[] = { 405 TLV_DB_RANGE_HEAD(5), 406 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 407 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 408 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 409 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 410 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), 411 }; 412 413 static const unsigned int max98090_spk_tlv[] = { 414 TLV_DB_RANGE_HEAD(5), 415 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0), 416 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0), 417 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0), 418 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0), 419 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0), 420 }; 421 422 static const unsigned int max98090_rcv_lout_tlv[] = { 423 TLV_DB_RANGE_HEAD(5), 424 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 425 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 426 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 427 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 428 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), 429 }; 430 431 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol, 432 struct snd_ctl_elem_value *ucontrol) 433 { 434 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 435 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 436 struct soc_mixer_control *mc = 437 (struct soc_mixer_control *)kcontrol->private_value; 438 unsigned int mask = (1 << fls(mc->max)) - 1; 439 unsigned int val = snd_soc_read(codec, mc->reg); 440 unsigned int *select; 441 442 switch (mc->reg) { 443 case M98090_REG_MIC1_INPUT_LEVEL: 444 select = &(max98090->pa1en); 445 break; 446 case M98090_REG_MIC2_INPUT_LEVEL: 447 select = &(max98090->pa2en); 448 break; 449 case M98090_REG_ADC_SIDETONE: 450 select = &(max98090->sidetone); 451 break; 452 default: 453 return -EINVAL; 454 } 455 456 val = (val >> mc->shift) & mask; 457 458 if (val >= 1) { 459 /* If on, return the volume */ 460 val = val - 1; 461 *select = val; 462 } else { 463 /* If off, return last stored value */ 464 val = *select; 465 } 466 467 ucontrol->value.integer.value[0] = val; 468 return 0; 469 } 470 471 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol, 472 struct snd_ctl_elem_value *ucontrol) 473 { 474 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 475 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 476 struct soc_mixer_control *mc = 477 (struct soc_mixer_control *)kcontrol->private_value; 478 unsigned int mask = (1 << fls(mc->max)) - 1; 479 unsigned int sel = ucontrol->value.integer.value[0]; 480 unsigned int val = snd_soc_read(codec, mc->reg); 481 unsigned int *select; 482 483 switch (mc->reg) { 484 case M98090_REG_MIC1_INPUT_LEVEL: 485 select = &(max98090->pa1en); 486 break; 487 case M98090_REG_MIC2_INPUT_LEVEL: 488 select = &(max98090->pa2en); 489 break; 490 case M98090_REG_ADC_SIDETONE: 491 select = &(max98090->sidetone); 492 break; 493 default: 494 return -EINVAL; 495 } 496 497 val = (val >> mc->shift) & mask; 498 499 *select = sel; 500 501 /* Setting a volume is only valid if it is already On */ 502 if (val >= 1) { 503 sel = sel + 1; 504 } else { 505 /* Write what was already there */ 506 sel = val; 507 } 508 509 snd_soc_update_bits(codec, mc->reg, 510 mask << mc->shift, 511 sel << mc->shift); 512 513 return 0; 514 } 515 516 static const char *max98090_perf_pwr_text[] = 517 { "High Performance", "Low Power" }; 518 static const char *max98090_pwr_perf_text[] = 519 { "Low Power", "High Performance" }; 520 521 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum, 522 M98090_REG_BIAS_CONTROL, 523 M98090_VCM_MODE_SHIFT, 524 max98090_pwr_perf_text); 525 526 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" }; 527 528 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum, 529 M98090_REG_ADC_CONTROL, 530 M98090_OSR128_SHIFT, 531 max98090_osr128_text); 532 533 static const char *max98090_mode_text[] = { "Voice", "Music" }; 534 535 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum, 536 M98090_REG_FILTER_CONFIG, 537 M98090_MODE_SHIFT, 538 max98090_mode_text); 539 540 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum, 541 M98090_REG_FILTER_CONFIG, 542 M98090_FLT_DMIC34MODE_SHIFT, 543 max98090_mode_text); 544 545 static const char *max98090_drcatk_text[] = 546 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" }; 547 548 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum, 549 M98090_REG_DRC_TIMING, 550 M98090_DRCATK_SHIFT, 551 max98090_drcatk_text); 552 553 static const char *max98090_drcrls_text[] = 554 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" }; 555 556 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum, 557 M98090_REG_DRC_TIMING, 558 M98090_DRCRLS_SHIFT, 559 max98090_drcrls_text); 560 561 static const char *max98090_alccmp_text[] = 562 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" }; 563 564 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum, 565 M98090_REG_DRC_COMPRESSOR, 566 M98090_DRCCMP_SHIFT, 567 max98090_alccmp_text); 568 569 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" }; 570 571 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum, 572 M98090_REG_DRC_EXPANDER, 573 M98090_DRCEXP_SHIFT, 574 max98090_drcexp_text); 575 576 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum, 577 M98090_REG_DAC_CONTROL, 578 M98090_PERFMODE_SHIFT, 579 max98090_perf_pwr_text); 580 581 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum, 582 M98090_REG_DAC_CONTROL, 583 M98090_DACHP_SHIFT, 584 max98090_pwr_perf_text); 585 586 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum, 587 M98090_REG_ADC_CONTROL, 588 M98090_ADCHP_SHIFT, 589 max98090_pwr_perf_text); 590 591 static const struct snd_kcontrol_new max98090_snd_controls[] = { 592 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum), 593 594 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG, 595 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0), 596 597 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 598 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, 599 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv, 600 max98090_put_enab_tlv, max98090_micboost_tlv), 601 602 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 603 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, 604 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv, 605 max98090_put_enab_tlv, max98090_micboost_tlv), 606 607 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL, 608 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1, 609 max98090_mic_tlv), 610 611 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL, 612 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1, 613 max98090_mic_tlv), 614 615 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume", 616 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0, 617 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv), 618 619 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume", 620 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0, 621 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv), 622 623 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL, 624 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1, 625 max98090_line_tlv), 626 627 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL, 628 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1, 629 max98090_line_tlv), 630 631 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 632 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0), 633 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 634 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0), 635 636 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL, 637 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0, 638 max98090_avg_tlv), 639 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL, 640 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0, 641 max98090_avg_tlv), 642 643 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL, 644 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1, 645 max98090_av_tlv), 646 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL, 647 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1, 648 max98090_av_tlv), 649 650 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum), 651 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, 652 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0), 653 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum), 654 655 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, 656 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0), 657 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION, 658 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0), 659 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION, 660 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0), 661 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, 662 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1), 663 SOC_ENUM("Filter Mode", max98090_mode_enum), 664 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, 665 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0), 666 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, 667 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0), 668 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL, 669 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv), 670 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", 671 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT, 672 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv, 673 max98090_put_enab_tlv, max98090_sdg_tlv), 674 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 675 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0, 676 max98090_dvg_tlv), 677 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 678 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1, 679 max98090_dv_tlv), 680 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105), 681 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 682 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0), 683 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 684 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0), 685 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 686 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0), 687 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 688 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1, 689 1), 690 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 691 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1, 692 max98090_dv_tlv), 693 694 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING, 695 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0), 696 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum), 697 SOC_ENUM("ALC Release Time", max98090_drcrls_enum), 698 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN, 699 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0, 700 max98090_alcmakeup_tlv), 701 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum), 702 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum), 703 SOC_SINGLE_TLV("ALC Compression Threshold Volume", 704 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT, 705 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv), 706 SOC_SINGLE_TLV("ALC Expansion Threshold Volume", 707 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT, 708 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv), 709 710 SOC_ENUM("DAC HP Playback Performance Mode", 711 max98090_dac_perfmode_enum), 712 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum), 713 714 SOC_SINGLE_TLV("Headphone Left Mixer Volume", 715 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT, 716 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv), 717 SOC_SINGLE_TLV("Headphone Right Mixer Volume", 718 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT, 719 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv), 720 721 SOC_SINGLE_TLV("Speaker Left Mixer Volume", 722 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT, 723 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv), 724 SOC_SINGLE_TLV("Speaker Right Mixer Volume", 725 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT, 726 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv), 727 728 SOC_SINGLE_TLV("Receiver Left Mixer Volume", 729 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT, 730 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv), 731 SOC_SINGLE_TLV("Receiver Right Mixer Volume", 732 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT, 733 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv), 734 735 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME, 736 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT, 737 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv), 738 739 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume", 740 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME, 741 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24, 742 0, max98090_spk_tlv), 743 744 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME, 745 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT, 746 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv), 747 748 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME, 749 M98090_HPLM_SHIFT, 1, 1), 750 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME, 751 M98090_HPRM_SHIFT, 1, 1), 752 753 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME, 754 M98090_SPLM_SHIFT, 1, 1), 755 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME, 756 M98090_SPRM_SHIFT, 1, 1), 757 758 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME, 759 M98090_RCVLM_SHIFT, 1, 1), 760 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME, 761 M98090_RCVRM_SHIFT, 1, 1), 762 763 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL, 764 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1), 765 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL, 766 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1), 767 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL, 768 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1), 769 770 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15), 771 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 772 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0), 773 }; 774 775 static const struct snd_kcontrol_new max98091_snd_controls[] = { 776 777 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE, 778 M98090_DMIC34_ZEROPAD_SHIFT, 779 M98090_DMIC34_ZEROPAD_NUM - 1, 0), 780 781 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum), 782 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, 783 M98090_FLT_DMIC34HPF_SHIFT, 784 M98090_FLT_DMIC34HPF_NUM - 1, 0), 785 786 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME, 787 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0, 788 max98090_avg_tlv), 789 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME, 790 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0, 791 max98090_avg_tlv), 792 793 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME, 794 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1, 795 max98090_av_tlv), 796 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME, 797 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1, 798 max98090_av_tlv), 799 800 SND_SOC_BYTES("DMIC34 Biquad Coefficients", 801 M98090_REG_DMIC34_BIQUAD_BASE, 15), 802 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 803 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0), 804 805 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume", 806 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT, 807 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv), 808 }; 809 810 static int max98090_micinput_event(struct snd_soc_dapm_widget *w, 811 struct snd_kcontrol *kcontrol, int event) 812 { 813 struct snd_soc_codec *codec = w->codec; 814 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 815 816 unsigned int val = snd_soc_read(codec, w->reg); 817 818 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 819 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT; 820 else 821 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT; 822 823 824 if (val >= 1) { 825 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { 826 max98090->pa1en = val - 1; /* Update for volatile */ 827 } else { 828 max98090->pa2en = val - 1; /* Update for volatile */ 829 } 830 } 831 832 switch (event) { 833 case SND_SOC_DAPM_POST_PMU: 834 /* If turning on, set to most recently selected volume */ 835 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 836 val = max98090->pa1en + 1; 837 else 838 val = max98090->pa2en + 1; 839 break; 840 case SND_SOC_DAPM_POST_PMD: 841 /* If turning off, turn off */ 842 val = 0; 843 break; 844 default: 845 return -EINVAL; 846 } 847 848 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 849 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK, 850 val << M98090_MIC_PA1EN_SHIFT); 851 else 852 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK, 853 val << M98090_MIC_PA2EN_SHIFT); 854 855 return 0; 856 } 857 858 static const char *mic1_mux_text[] = { "IN12", "IN56" }; 859 860 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum, 861 M98090_REG_INPUT_MODE, 862 M98090_EXTMIC1_SHIFT, 863 mic1_mux_text); 864 865 static const struct snd_kcontrol_new max98090_mic1_mux = 866 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum); 867 868 static const char *mic2_mux_text[] = { "IN34", "IN56" }; 869 870 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum, 871 M98090_REG_INPUT_MODE, 872 M98090_EXTMIC2_SHIFT, 873 mic2_mux_text); 874 875 static const struct snd_kcontrol_new max98090_mic2_mux = 876 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum); 877 878 static const char *dmic_mux_text[] = { "ADC", "DMIC" }; 879 880 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text); 881 882 static const struct snd_kcontrol_new max98090_dmic_mux = 883 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum); 884 885 static const char *max98090_micpre_text[] = { "Off", "On" }; 886 887 static SOC_ENUM_SINGLE_DECL(max98090_pa1en_enum, 888 M98090_REG_MIC1_INPUT_LEVEL, 889 M98090_MIC_PA1EN_SHIFT, 890 max98090_micpre_text); 891 892 static SOC_ENUM_SINGLE_DECL(max98090_pa2en_enum, 893 M98090_REG_MIC2_INPUT_LEVEL, 894 M98090_MIC_PA2EN_SHIFT, 895 max98090_micpre_text); 896 897 /* LINEA mixer switch */ 898 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = { 899 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG, 900 M98090_IN1SEEN_SHIFT, 1, 0), 901 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG, 902 M98090_IN3SEEN_SHIFT, 1, 0), 903 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG, 904 M98090_IN5SEEN_SHIFT, 1, 0), 905 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG, 906 M98090_IN34DIFF_SHIFT, 1, 0), 907 }; 908 909 /* LINEB mixer switch */ 910 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = { 911 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG, 912 M98090_IN2SEEN_SHIFT, 1, 0), 913 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG, 914 M98090_IN4SEEN_SHIFT, 1, 0), 915 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG, 916 M98090_IN6SEEN_SHIFT, 1, 0), 917 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG, 918 M98090_IN56DIFF_SHIFT, 1, 0), 919 }; 920 921 /* Left ADC mixer switch */ 922 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = { 923 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER, 924 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0), 925 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER, 926 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0), 927 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER, 928 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0), 929 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER, 930 M98090_MIXADL_LINEA_SHIFT, 1, 0), 931 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER, 932 M98090_MIXADL_LINEB_SHIFT, 1, 0), 933 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER, 934 M98090_MIXADL_MIC1_SHIFT, 1, 0), 935 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER, 936 M98090_MIXADL_MIC2_SHIFT, 1, 0), 937 }; 938 939 /* Right ADC mixer switch */ 940 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = { 941 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER, 942 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0), 943 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER, 944 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0), 945 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER, 946 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0), 947 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER, 948 M98090_MIXADR_LINEA_SHIFT, 1, 0), 949 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER, 950 M98090_MIXADR_LINEB_SHIFT, 1, 0), 951 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER, 952 M98090_MIXADR_MIC1_SHIFT, 1, 0), 953 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER, 954 M98090_MIXADR_MIC2_SHIFT, 1, 0), 955 }; 956 957 static const char *lten_mux_text[] = { "Normal", "Loopthrough" }; 958 959 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum, 960 M98090_REG_IO_CONFIGURATION, 961 M98090_LTEN_SHIFT, 962 lten_mux_text); 963 964 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum, 965 M98090_REG_IO_CONFIGURATION, 966 M98090_LTEN_SHIFT, 967 lten_mux_text); 968 969 static const struct snd_kcontrol_new max98090_ltenl_mux = 970 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum); 971 972 static const struct snd_kcontrol_new max98090_ltenr_mux = 973 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum); 974 975 static const char *lben_mux_text[] = { "Normal", "Loopback" }; 976 977 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum, 978 M98090_REG_IO_CONFIGURATION, 979 M98090_LBEN_SHIFT, 980 lben_mux_text); 981 982 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum, 983 M98090_REG_IO_CONFIGURATION, 984 M98090_LBEN_SHIFT, 985 lben_mux_text); 986 987 static const struct snd_kcontrol_new max98090_lbenl_mux = 988 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum); 989 990 static const struct snd_kcontrol_new max98090_lbenr_mux = 991 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum); 992 993 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" }; 994 995 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" }; 996 997 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum, 998 M98090_REG_ADC_SIDETONE, 999 M98090_DSTSL_SHIFT, 1000 stenl_mux_text); 1001 1002 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum, 1003 M98090_REG_ADC_SIDETONE, 1004 M98090_DSTSR_SHIFT, 1005 stenr_mux_text); 1006 1007 static const struct snd_kcontrol_new max98090_stenl_mux = 1008 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum); 1009 1010 static const struct snd_kcontrol_new max98090_stenr_mux = 1011 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum); 1012 1013 /* Left speaker mixer switch */ 1014 static const struct 1015 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = { 1016 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER, 1017 M98090_MIXSPL_DACL_SHIFT, 1, 0), 1018 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER, 1019 M98090_MIXSPL_DACR_SHIFT, 1, 0), 1020 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER, 1021 M98090_MIXSPL_LINEA_SHIFT, 1, 0), 1022 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER, 1023 M98090_MIXSPL_LINEB_SHIFT, 1, 0), 1024 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER, 1025 M98090_MIXSPL_MIC1_SHIFT, 1, 0), 1026 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER, 1027 M98090_MIXSPL_MIC2_SHIFT, 1, 0), 1028 }; 1029 1030 /* Right speaker mixer switch */ 1031 static const struct 1032 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = { 1033 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 1034 M98090_MIXSPR_DACL_SHIFT, 1, 0), 1035 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 1036 M98090_MIXSPR_DACR_SHIFT, 1, 0), 1037 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER, 1038 M98090_MIXSPR_LINEA_SHIFT, 1, 0), 1039 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER, 1040 M98090_MIXSPR_LINEB_SHIFT, 1, 0), 1041 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER, 1042 M98090_MIXSPR_MIC1_SHIFT, 1, 0), 1043 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER, 1044 M98090_MIXSPR_MIC2_SHIFT, 1, 0), 1045 }; 1046 1047 /* Left headphone mixer switch */ 1048 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { 1049 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER, 1050 M98090_MIXHPL_DACL_SHIFT, 1, 0), 1051 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER, 1052 M98090_MIXHPL_DACR_SHIFT, 1, 0), 1053 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER, 1054 M98090_MIXHPL_LINEA_SHIFT, 1, 0), 1055 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER, 1056 M98090_MIXHPL_LINEB_SHIFT, 1, 0), 1057 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER, 1058 M98090_MIXHPL_MIC1_SHIFT, 1, 0), 1059 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER, 1060 M98090_MIXHPL_MIC2_SHIFT, 1, 0), 1061 }; 1062 1063 /* Right headphone mixer switch */ 1064 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { 1065 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER, 1066 M98090_MIXHPR_DACL_SHIFT, 1, 0), 1067 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER, 1068 M98090_MIXHPR_DACR_SHIFT, 1, 0), 1069 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER, 1070 M98090_MIXHPR_LINEA_SHIFT, 1, 0), 1071 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER, 1072 M98090_MIXHPR_LINEB_SHIFT, 1, 0), 1073 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER, 1074 M98090_MIXHPR_MIC1_SHIFT, 1, 0), 1075 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER, 1076 M98090_MIXHPR_MIC2_SHIFT, 1, 0), 1077 }; 1078 1079 /* Left receiver mixer switch */ 1080 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = { 1081 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1082 M98090_MIXRCVL_DACL_SHIFT, 1, 0), 1083 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1084 M98090_MIXRCVL_DACR_SHIFT, 1, 0), 1085 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER, 1086 M98090_MIXRCVL_LINEA_SHIFT, 1, 0), 1087 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER, 1088 M98090_MIXRCVL_LINEB_SHIFT, 1, 0), 1089 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER, 1090 M98090_MIXRCVL_MIC1_SHIFT, 1, 0), 1091 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER, 1092 M98090_MIXRCVL_MIC2_SHIFT, 1, 0), 1093 }; 1094 1095 /* Right receiver mixer switch */ 1096 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = { 1097 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER, 1098 M98090_MIXRCVR_DACL_SHIFT, 1, 0), 1099 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER, 1100 M98090_MIXRCVR_DACR_SHIFT, 1, 0), 1101 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER, 1102 M98090_MIXRCVR_LINEA_SHIFT, 1, 0), 1103 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER, 1104 M98090_MIXRCVR_LINEB_SHIFT, 1, 0), 1105 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER, 1106 M98090_MIXRCVR_MIC1_SHIFT, 1, 0), 1107 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER, 1108 M98090_MIXRCVR_MIC2_SHIFT, 1, 0), 1109 }; 1110 1111 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" }; 1112 1113 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum, 1114 M98090_REG_LOUTR_MIXER, 1115 M98090_LINMOD_SHIFT, 1116 linmod_mux_text); 1117 1118 static const struct snd_kcontrol_new max98090_linmod_mux = 1119 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum); 1120 1121 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" }; 1122 1123 /* 1124 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable 1125 */ 1126 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum, 1127 M98090_REG_HP_CONTROL, 1128 M98090_MIXHPLSEL_SHIFT, 1129 mixhpsel_mux_text); 1130 1131 static const struct snd_kcontrol_new max98090_mixhplsel_mux = 1132 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum); 1133 1134 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum, 1135 M98090_REG_HP_CONTROL, 1136 M98090_MIXHPRSEL_SHIFT, 1137 mixhpsel_mux_text); 1138 1139 static const struct snd_kcontrol_new max98090_mixhprsel_mux = 1140 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum); 1141 1142 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { 1143 1144 SND_SOC_DAPM_INPUT("MIC1"), 1145 SND_SOC_DAPM_INPUT("MIC2"), 1146 SND_SOC_DAPM_INPUT("DMICL"), 1147 SND_SOC_DAPM_INPUT("DMICR"), 1148 SND_SOC_DAPM_INPUT("IN1"), 1149 SND_SOC_DAPM_INPUT("IN2"), 1150 SND_SOC_DAPM_INPUT("IN3"), 1151 SND_SOC_DAPM_INPUT("IN4"), 1152 SND_SOC_DAPM_INPUT("IN5"), 1153 SND_SOC_DAPM_INPUT("IN6"), 1154 SND_SOC_DAPM_INPUT("IN12"), 1155 SND_SOC_DAPM_INPUT("IN34"), 1156 SND_SOC_DAPM_INPUT("IN56"), 1157 1158 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE, 1159 M98090_MBEN_SHIFT, 0, NULL, 0), 1160 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN, 1161 M98090_SHDNN_SHIFT, 0, NULL, 0), 1162 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION, 1163 M98090_SDIEN_SHIFT, 0, NULL, 0), 1164 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION, 1165 M98090_SDOEN_SHIFT, 0, NULL, 0), 1166 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1167 M98090_DIGMICL_SHIFT, 0, NULL, 0), 1168 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1169 M98090_DIGMICR_SHIFT, 0, NULL, 0), 1170 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG, 1171 M98090_AHPF_SHIFT, 0, NULL, 0), 1172 1173 /* 1174 * Note: Sysclk and misc power supplies are taken care of by SHDN 1175 */ 1176 1177 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM, 1178 0, 0, &max98090_mic1_mux), 1179 1180 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM, 1181 0, 0, &max98090_mic2_mux), 1182 1183 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux), 1184 1185 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL, 1186 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1187 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1188 1189 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL, 1190 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1191 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1192 1193 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0, 1194 &max98090_linea_mixer_controls[0], 1195 ARRAY_SIZE(max98090_linea_mixer_controls)), 1196 1197 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0, 1198 &max98090_lineb_mixer_controls[0], 1199 ARRAY_SIZE(max98090_lineb_mixer_controls)), 1200 1201 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE, 1202 M98090_LINEAEN_SHIFT, 0, NULL, 0), 1203 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE, 1204 M98090_LINEBEN_SHIFT, 0, NULL, 0), 1205 1206 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1207 &max98090_left_adc_mixer_controls[0], 1208 ARRAY_SIZE(max98090_left_adc_mixer_controls)), 1209 1210 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1211 &max98090_right_adc_mixer_controls[0], 1212 ARRAY_SIZE(max98090_right_adc_mixer_controls)), 1213 1214 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE, 1215 M98090_ADLEN_SHIFT, 0), 1216 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE, 1217 M98090_ADREN_SHIFT, 0), 1218 1219 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0, 1220 SND_SOC_NOPM, 0, 0), 1221 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1, 1222 SND_SOC_NOPM, 0, 0), 1223 1224 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM, 1225 0, 0, &max98090_lbenl_mux), 1226 1227 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM, 1228 0, 0, &max98090_lbenr_mux), 1229 1230 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM, 1231 0, 0, &max98090_ltenl_mux), 1232 1233 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM, 1234 0, 0, &max98090_ltenr_mux), 1235 1236 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM, 1237 0, 0, &max98090_stenl_mux), 1238 1239 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM, 1240 0, 0, &max98090_stenr_mux), 1241 1242 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 1243 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0), 1244 1245 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE, 1246 M98090_DALEN_SHIFT, 0), 1247 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE, 1248 M98090_DAREN_SHIFT, 0), 1249 1250 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 1251 &max98090_left_hp_mixer_controls[0], 1252 ARRAY_SIZE(max98090_left_hp_mixer_controls)), 1253 1254 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 1255 &max98090_right_hp_mixer_controls[0], 1256 ARRAY_SIZE(max98090_right_hp_mixer_controls)), 1257 1258 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 1259 &max98090_left_speaker_mixer_controls[0], 1260 ARRAY_SIZE(max98090_left_speaker_mixer_controls)), 1261 1262 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 1263 &max98090_right_speaker_mixer_controls[0], 1264 ARRAY_SIZE(max98090_right_speaker_mixer_controls)), 1265 1266 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0, 1267 &max98090_left_rcv_mixer_controls[0], 1268 ARRAY_SIZE(max98090_left_rcv_mixer_controls)), 1269 1270 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0, 1271 &max98090_right_rcv_mixer_controls[0], 1272 ARRAY_SIZE(max98090_right_rcv_mixer_controls)), 1273 1274 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER, 1275 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux), 1276 1277 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL, 1278 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux), 1279 1280 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL, 1281 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux), 1282 1283 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE, 1284 M98090_HPLEN_SHIFT, 0, NULL, 0), 1285 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE, 1286 M98090_HPREN_SHIFT, 0, NULL, 0), 1287 1288 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE, 1289 M98090_SPLEN_SHIFT, 0, NULL, 0), 1290 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE, 1291 M98090_SPREN_SHIFT, 0, NULL, 0), 1292 1293 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE, 1294 M98090_RCVLEN_SHIFT, 0, NULL, 0), 1295 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE, 1296 M98090_RCVREN_SHIFT, 0, NULL, 0), 1297 1298 SND_SOC_DAPM_OUTPUT("HPL"), 1299 SND_SOC_DAPM_OUTPUT("HPR"), 1300 SND_SOC_DAPM_OUTPUT("SPKL"), 1301 SND_SOC_DAPM_OUTPUT("SPKR"), 1302 SND_SOC_DAPM_OUTPUT("RCVL"), 1303 SND_SOC_DAPM_OUTPUT("RCVR"), 1304 }; 1305 1306 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = { 1307 1308 SND_SOC_DAPM_INPUT("DMIC3"), 1309 SND_SOC_DAPM_INPUT("DMIC4"), 1310 1311 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1312 M98090_DIGMIC3_SHIFT, 0, NULL, 0), 1313 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1314 M98090_DIGMIC4_SHIFT, 0, NULL, 0), 1315 }; 1316 1317 static const struct snd_soc_dapm_route max98090_dapm_routes[] = { 1318 1319 {"MIC1 Input", NULL, "MIC1"}, 1320 {"MIC2 Input", NULL, "MIC2"}, 1321 1322 {"DMICL", NULL, "DMICL_ENA"}, 1323 {"DMICR", NULL, "DMICR_ENA"}, 1324 {"DMICL", NULL, "AHPF"}, 1325 {"DMICR", NULL, "AHPF"}, 1326 1327 /* MIC1 input mux */ 1328 {"MIC1 Mux", "IN12", "IN12"}, 1329 {"MIC1 Mux", "IN56", "IN56"}, 1330 1331 /* MIC2 input mux */ 1332 {"MIC2 Mux", "IN34", "IN34"}, 1333 {"MIC2 Mux", "IN56", "IN56"}, 1334 1335 {"MIC1 Input", NULL, "MIC1 Mux"}, 1336 {"MIC2 Input", NULL, "MIC2 Mux"}, 1337 1338 /* Left ADC input mixer */ 1339 {"Left ADC Mixer", "IN12 Switch", "IN12"}, 1340 {"Left ADC Mixer", "IN34 Switch", "IN34"}, 1341 {"Left ADC Mixer", "IN56 Switch", "IN56"}, 1342 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"}, 1343 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"}, 1344 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1345 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1346 1347 /* Right ADC input mixer */ 1348 {"Right ADC Mixer", "IN12 Switch", "IN12"}, 1349 {"Right ADC Mixer", "IN34 Switch", "IN34"}, 1350 {"Right ADC Mixer", "IN56 Switch", "IN56"}, 1351 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"}, 1352 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"}, 1353 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1354 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1355 1356 /* Line A input mixer */ 1357 {"LINEA Mixer", "IN1 Switch", "IN1"}, 1358 {"LINEA Mixer", "IN3 Switch", "IN3"}, 1359 {"LINEA Mixer", "IN5 Switch", "IN5"}, 1360 {"LINEA Mixer", "IN34 Switch", "IN34"}, 1361 1362 /* Line B input mixer */ 1363 {"LINEB Mixer", "IN2 Switch", "IN2"}, 1364 {"LINEB Mixer", "IN4 Switch", "IN4"}, 1365 {"LINEB Mixer", "IN6 Switch", "IN6"}, 1366 {"LINEB Mixer", "IN56 Switch", "IN56"}, 1367 1368 {"LINEA Input", NULL, "LINEA Mixer"}, 1369 {"LINEB Input", NULL, "LINEB Mixer"}, 1370 1371 /* Inputs */ 1372 {"ADCL", NULL, "Left ADC Mixer"}, 1373 {"ADCR", NULL, "Right ADC Mixer"}, 1374 {"ADCL", NULL, "SHDN"}, 1375 {"ADCR", NULL, "SHDN"}, 1376 1377 {"DMIC Mux", "ADC", "ADCL"}, 1378 {"DMIC Mux", "ADC", "ADCR"}, 1379 {"DMIC Mux", "DMIC", "DMICL"}, 1380 {"DMIC Mux", "DMIC", "DMICR"}, 1381 1382 {"LBENL Mux", "Normal", "DMIC Mux"}, 1383 {"LBENL Mux", "Loopback", "LTENL Mux"}, 1384 {"LBENR Mux", "Normal", "DMIC Mux"}, 1385 {"LBENR Mux", "Loopback", "LTENR Mux"}, 1386 1387 {"AIFOUTL", NULL, "LBENL Mux"}, 1388 {"AIFOUTR", NULL, "LBENR Mux"}, 1389 {"AIFOUTL", NULL, "SHDN"}, 1390 {"AIFOUTR", NULL, "SHDN"}, 1391 {"AIFOUTL", NULL, "SDOEN"}, 1392 {"AIFOUTR", NULL, "SDOEN"}, 1393 1394 {"LTENL Mux", "Normal", "AIFINL"}, 1395 {"LTENL Mux", "Loopthrough", "LBENL Mux"}, 1396 {"LTENR Mux", "Normal", "AIFINR"}, 1397 {"LTENR Mux", "Loopthrough", "LBENR Mux"}, 1398 1399 {"DACL", NULL, "LTENL Mux"}, 1400 {"DACR", NULL, "LTENR Mux"}, 1401 1402 {"STENL Mux", "Sidetone Left", "ADCL"}, 1403 {"STENL Mux", "Sidetone Left", "DMICL"}, 1404 {"STENR Mux", "Sidetone Right", "ADCR"}, 1405 {"STENR Mux", "Sidetone Right", "DMICR"}, 1406 {"DACL", "NULL", "STENL Mux"}, 1407 {"DACR", "NULL", "STENL Mux"}, 1408 1409 {"AIFINL", NULL, "SHDN"}, 1410 {"AIFINR", NULL, "SHDN"}, 1411 {"AIFINL", NULL, "SDIEN"}, 1412 {"AIFINR", NULL, "SDIEN"}, 1413 {"DACL", NULL, "SHDN"}, 1414 {"DACR", NULL, "SHDN"}, 1415 1416 /* Left headphone output mixer */ 1417 {"Left Headphone Mixer", "Left DAC Switch", "DACL"}, 1418 {"Left Headphone Mixer", "Right DAC Switch", "DACR"}, 1419 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1420 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1421 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1422 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1423 1424 /* Right headphone output mixer */ 1425 {"Right Headphone Mixer", "Left DAC Switch", "DACL"}, 1426 {"Right Headphone Mixer", "Right DAC Switch", "DACR"}, 1427 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1428 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1429 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1430 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1431 1432 /* Left speaker output mixer */ 1433 {"Left Speaker Mixer", "Left DAC Switch", "DACL"}, 1434 {"Left Speaker Mixer", "Right DAC Switch", "DACR"}, 1435 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1436 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1437 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1438 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1439 1440 /* Right speaker output mixer */ 1441 {"Right Speaker Mixer", "Left DAC Switch", "DACL"}, 1442 {"Right Speaker Mixer", "Right DAC Switch", "DACR"}, 1443 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1444 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1445 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1446 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1447 1448 /* Left Receiver output mixer */ 1449 {"Left Receiver Mixer", "Left DAC Switch", "DACL"}, 1450 {"Left Receiver Mixer", "Right DAC Switch", "DACR"}, 1451 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1452 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1453 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1454 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1455 1456 /* Right Receiver output mixer */ 1457 {"Right Receiver Mixer", "Left DAC Switch", "DACL"}, 1458 {"Right Receiver Mixer", "Right DAC Switch", "DACR"}, 1459 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1460 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1461 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1462 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1463 1464 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"}, 1465 1466 /* 1467 * Disable this for lowest power if bypassing 1468 * the DAC with an analog signal 1469 */ 1470 {"HP Left Out", NULL, "DACL"}, 1471 {"HP Left Out", NULL, "MIXHPLSEL Mux"}, 1472 1473 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"}, 1474 1475 /* 1476 * Disable this for lowest power if bypassing 1477 * the DAC with an analog signal 1478 */ 1479 {"HP Right Out", NULL, "DACR"}, 1480 {"HP Right Out", NULL, "MIXHPRSEL Mux"}, 1481 1482 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 1483 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 1484 {"RCV Left Out", NULL, "Left Receiver Mixer"}, 1485 1486 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"}, 1487 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"}, 1488 {"RCV Right Out", NULL, "LINMOD Mux"}, 1489 1490 {"HPL", NULL, "HP Left Out"}, 1491 {"HPR", NULL, "HP Right Out"}, 1492 {"SPKL", NULL, "SPK Left Out"}, 1493 {"SPKR", NULL, "SPK Right Out"}, 1494 {"RCVL", NULL, "RCV Left Out"}, 1495 {"RCVR", NULL, "RCV Right Out"}, 1496 1497 }; 1498 1499 static const struct snd_soc_dapm_route max98091_dapm_routes[] = { 1500 1501 /* DMIC inputs */ 1502 {"DMIC3", NULL, "DMIC3_ENA"}, 1503 {"DMIC4", NULL, "DMIC4_ENA"}, 1504 {"DMIC3", NULL, "AHPF"}, 1505 {"DMIC4", NULL, "AHPF"}, 1506 1507 }; 1508 1509 static int max98090_add_widgets(struct snd_soc_codec *codec) 1510 { 1511 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1512 struct snd_soc_dapm_context *dapm = &codec->dapm; 1513 1514 snd_soc_add_codec_controls(codec, max98090_snd_controls, 1515 ARRAY_SIZE(max98090_snd_controls)); 1516 1517 if (max98090->devtype == MAX98091) { 1518 snd_soc_add_codec_controls(codec, max98091_snd_controls, 1519 ARRAY_SIZE(max98091_snd_controls)); 1520 } 1521 1522 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets, 1523 ARRAY_SIZE(max98090_dapm_widgets)); 1524 1525 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes, 1526 ARRAY_SIZE(max98090_dapm_routes)); 1527 1528 if (max98090->devtype == MAX98091) { 1529 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets, 1530 ARRAY_SIZE(max98091_dapm_widgets)); 1531 1532 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes, 1533 ARRAY_SIZE(max98091_dapm_routes)); 1534 1535 } 1536 1537 return 0; 1538 } 1539 1540 static const int pclk_rates[] = { 1541 12000000, 12000000, 13000000, 13000000, 1542 16000000, 16000000, 19200000, 19200000 1543 }; 1544 1545 static const int lrclk_rates[] = { 1546 8000, 16000, 8000, 16000, 1547 8000, 16000, 8000, 16000 1548 }; 1549 1550 static const int user_pclk_rates[] = { 1551 13000000, 13000000, 19200000, 19200000, 1552 }; 1553 1554 static const int user_lrclk_rates[] = { 1555 44100, 48000, 44100, 48000, 1556 }; 1557 1558 static const unsigned long long ni_value[] = { 1559 3528, 768, 441, 8 1560 }; 1561 1562 static const unsigned long long mi_value[] = { 1563 8125, 1625, 1500, 25 1564 }; 1565 1566 static void max98090_configure_bclk(struct snd_soc_codec *codec) 1567 { 1568 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1569 unsigned long long ni; 1570 int i; 1571 1572 if (!max98090->sysclk) { 1573 dev_err(codec->dev, "No SYSCLK configured\n"); 1574 return; 1575 } 1576 1577 if (!max98090->bclk || !max98090->lrclk) { 1578 dev_err(codec->dev, "No audio clocks configured\n"); 1579 return; 1580 } 1581 1582 /* Skip configuration when operating as slave */ 1583 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) & 1584 M98090_MAS_MASK)) { 1585 return; 1586 } 1587 1588 /* Check for supported PCLK to LRCLK ratios */ 1589 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) { 1590 if ((pclk_rates[i] == max98090->sysclk) && 1591 (lrclk_rates[i] == max98090->lrclk)) { 1592 dev_dbg(codec->dev, 1593 "Found supported PCLK to LRCLK rates 0x%x\n", 1594 i + 0x8); 1595 1596 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1597 M98090_FREQ_MASK, 1598 (i + 0x8) << M98090_FREQ_SHIFT); 1599 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1600 M98090_USE_M1_MASK, 0); 1601 return; 1602 } 1603 } 1604 1605 /* Check for user calculated MI and NI ratios */ 1606 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) { 1607 if ((user_pclk_rates[i] == max98090->sysclk) && 1608 (user_lrclk_rates[i] == max98090->lrclk)) { 1609 dev_dbg(codec->dev, 1610 "Found user supported PCLK to LRCLK rates\n"); 1611 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n", 1612 i, ni_value[i], mi_value[i]); 1613 1614 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1615 M98090_FREQ_MASK, 0); 1616 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1617 M98090_USE_M1_MASK, 1618 1 << M98090_USE_M1_SHIFT); 1619 1620 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, 1621 (ni_value[i] >> 8) & 0x7F); 1622 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, 1623 ni_value[i] & 0xFF); 1624 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB, 1625 (mi_value[i] >> 8) & 0x7F); 1626 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB, 1627 mi_value[i] & 0xFF); 1628 1629 return; 1630 } 1631 } 1632 1633 /* 1634 * Calculate based on MI = 65536 (not as good as either method above) 1635 */ 1636 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1637 M98090_FREQ_MASK, 0); 1638 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1639 M98090_USE_M1_MASK, 0); 1640 1641 /* 1642 * Configure NI when operating as master 1643 * Note: There is a small, but significant audio quality improvement 1644 * by calculating ni and mi. 1645 */ 1646 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) 1647 * (unsigned long long int)max98090->lrclk; 1648 do_div(ni, (unsigned long long int)max98090->sysclk); 1649 dev_info(codec->dev, "No better method found\n"); 1650 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni); 1651 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, 1652 (ni >> 8) & 0x7F); 1653 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF); 1654 } 1655 1656 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai, 1657 unsigned int fmt) 1658 { 1659 struct snd_soc_codec *codec = codec_dai->codec; 1660 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1661 struct max98090_cdata *cdata; 1662 u8 regval; 1663 1664 max98090->dai_fmt = fmt; 1665 cdata = &max98090->dai[0]; 1666 1667 if (fmt != cdata->fmt) { 1668 cdata->fmt = fmt; 1669 1670 regval = 0; 1671 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1672 case SND_SOC_DAIFMT_CBS_CFS: 1673 /* Set to slave mode PLL - MAS mode off */ 1674 snd_soc_write(codec, 1675 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00); 1676 snd_soc_write(codec, 1677 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); 1678 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1679 M98090_USE_M1_MASK, 0); 1680 max98090->master = false; 1681 break; 1682 case SND_SOC_DAIFMT_CBM_CFM: 1683 /* Set to master mode */ 1684 if (max98090->tdm_slots == 4) { 1685 /* TDM */ 1686 regval |= M98090_MAS_MASK | 1687 M98090_BSEL_64; 1688 } else if (max98090->tdm_slots == 3) { 1689 /* TDM */ 1690 regval |= M98090_MAS_MASK | 1691 M98090_BSEL_48; 1692 } else { 1693 /* Few TDM slots, or No TDM */ 1694 regval |= M98090_MAS_MASK | 1695 M98090_BSEL_32; 1696 } 1697 max98090->master = true; 1698 break; 1699 case SND_SOC_DAIFMT_CBS_CFM: 1700 case SND_SOC_DAIFMT_CBM_CFS: 1701 default: 1702 dev_err(codec->dev, "DAI clock mode unsupported"); 1703 return -EINVAL; 1704 } 1705 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval); 1706 1707 regval = 0; 1708 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1709 case SND_SOC_DAIFMT_I2S: 1710 regval |= M98090_DLY_MASK; 1711 break; 1712 case SND_SOC_DAIFMT_LEFT_J: 1713 break; 1714 case SND_SOC_DAIFMT_RIGHT_J: 1715 regval |= M98090_RJ_MASK; 1716 break; 1717 case SND_SOC_DAIFMT_DSP_A: 1718 /* Not supported mode */ 1719 default: 1720 dev_err(codec->dev, "DAI format unsupported"); 1721 return -EINVAL; 1722 } 1723 1724 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1725 case SND_SOC_DAIFMT_NB_NF: 1726 break; 1727 case SND_SOC_DAIFMT_NB_IF: 1728 regval |= M98090_WCI_MASK; 1729 break; 1730 case SND_SOC_DAIFMT_IB_NF: 1731 regval |= M98090_BCI_MASK; 1732 break; 1733 case SND_SOC_DAIFMT_IB_IF: 1734 regval |= M98090_BCI_MASK|M98090_WCI_MASK; 1735 break; 1736 default: 1737 dev_err(codec->dev, "DAI invert mode unsupported"); 1738 return -EINVAL; 1739 } 1740 1741 /* 1742 * This accommodates an inverted logic in the MAX98090 chip 1743 * for Bit Clock Invert (BCI). The inverted logic is only 1744 * seen for the case of TDM mode. The remaining cases have 1745 * normal logic. 1746 */ 1747 if (max98090->tdm_slots > 1) 1748 regval ^= M98090_BCI_MASK; 1749 1750 snd_soc_write(codec, 1751 M98090_REG_INTERFACE_FORMAT, regval); 1752 } 1753 1754 return 0; 1755 } 1756 1757 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai, 1758 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1759 { 1760 struct snd_soc_codec *codec = codec_dai->codec; 1761 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1762 struct max98090_cdata *cdata; 1763 cdata = &max98090->dai[0]; 1764 1765 if (slots < 0 || slots > 4) 1766 return -EINVAL; 1767 1768 max98090->tdm_slots = slots; 1769 max98090->tdm_width = slot_width; 1770 1771 if (max98090->tdm_slots > 1) { 1772 /* SLOTL SLOTR SLOTDLY */ 1773 snd_soc_write(codec, M98090_REG_TDM_FORMAT, 1774 0 << M98090_TDM_SLOTL_SHIFT | 1775 1 << M98090_TDM_SLOTR_SHIFT | 1776 0 << M98090_TDM_SLOTDLY_SHIFT); 1777 1778 /* FSW TDM */ 1779 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL, 1780 M98090_TDM_MASK, 1781 M98090_TDM_MASK); 1782 } 1783 1784 /* 1785 * Normally advisable to set TDM first, but this permits either order 1786 */ 1787 cdata->fmt = 0; 1788 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt); 1789 1790 return 0; 1791 } 1792 1793 static int max98090_set_bias_level(struct snd_soc_codec *codec, 1794 enum snd_soc_bias_level level) 1795 { 1796 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1797 int ret; 1798 1799 switch (level) { 1800 case SND_SOC_BIAS_ON: 1801 break; 1802 1803 case SND_SOC_BIAS_PREPARE: 1804 /* 1805 * SND_SOC_BIAS_PREPARE is called while preparing for a 1806 * transition to ON or away from ON. If current bias_level 1807 * is SND_SOC_BIAS_ON, then it is preparing for a transition 1808 * away from ON. Disable the clock in that case, otherwise 1809 * enable it. 1810 */ 1811 if (!IS_ERR(max98090->mclk)) { 1812 if (codec->dapm.bias_level == SND_SOC_BIAS_ON) 1813 clk_disable_unprepare(max98090->mclk); 1814 else 1815 clk_prepare_enable(max98090->mclk); 1816 } 1817 break; 1818 1819 case SND_SOC_BIAS_STANDBY: 1820 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1821 ret = regcache_sync(max98090->regmap); 1822 if (ret != 0) { 1823 dev_err(codec->dev, 1824 "Failed to sync cache: %d\n", ret); 1825 return ret; 1826 } 1827 } 1828 break; 1829 1830 case SND_SOC_BIAS_OFF: 1831 /* Set internal pull-up to lowest power mode */ 1832 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, 1833 M98090_JDWK_MASK, M98090_JDWK_MASK); 1834 regcache_mark_dirty(max98090->regmap); 1835 break; 1836 } 1837 codec->dapm.bias_level = level; 1838 return 0; 1839 } 1840 1841 static const int comp_pclk_rates[] = { 1842 11289600, 12288000, 12000000, 13000000, 19200000 1843 }; 1844 1845 static const int dmic_micclk[] = { 1846 2, 2, 2, 2, 4, 2 1847 }; 1848 1849 static const int comp_lrclk_rates[] = { 1850 8000, 16000, 32000, 44100, 48000, 96000 1851 }; 1852 1853 static const int dmic_comp[6][6] = { 1854 {7, 8, 3, 3, 3, 3}, 1855 {7, 8, 3, 3, 3, 3}, 1856 {7, 8, 3, 3, 3, 3}, 1857 {7, 8, 3, 1, 1, 1}, 1858 {7, 8, 3, 1, 2, 2}, 1859 {7, 8, 3, 3, 3, 3} 1860 }; 1861 1862 static int max98090_dai_hw_params(struct snd_pcm_substream *substream, 1863 struct snd_pcm_hw_params *params, 1864 struct snd_soc_dai *dai) 1865 { 1866 struct snd_soc_codec *codec = dai->codec; 1867 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1868 struct max98090_cdata *cdata; 1869 int i, j; 1870 1871 cdata = &max98090->dai[0]; 1872 max98090->bclk = snd_soc_params_to_bclk(params); 1873 if (params_channels(params) == 1) 1874 max98090->bclk *= 2; 1875 1876 max98090->lrclk = params_rate(params); 1877 1878 switch (params_width(params)) { 1879 case 16: 1880 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT, 1881 M98090_WS_MASK, 0); 1882 break; 1883 default: 1884 return -EINVAL; 1885 } 1886 1887 if (max98090->master) 1888 max98090_configure_bclk(codec); 1889 1890 cdata->rate = max98090->lrclk; 1891 1892 /* Update filter mode */ 1893 if (max98090->lrclk < 24000) 1894 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1895 M98090_MODE_MASK, 0); 1896 else 1897 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1898 M98090_MODE_MASK, M98090_MODE_MASK); 1899 1900 /* Update sample rate mode */ 1901 if (max98090->lrclk < 50000) 1902 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1903 M98090_DHF_MASK, 0); 1904 else 1905 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1906 M98090_DHF_MASK, M98090_DHF_MASK); 1907 1908 /* Check for supported PCLK to LRCLK ratios */ 1909 for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) { 1910 if (comp_pclk_rates[j] == max98090->sysclk) { 1911 break; 1912 } 1913 } 1914 1915 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { 1916 if (max98090->lrclk <= (comp_lrclk_rates[i] + 1917 comp_lrclk_rates[i + 1]) / 2) { 1918 break; 1919 } 1920 } 1921 1922 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE, 1923 M98090_MICCLK_MASK, 1924 dmic_micclk[j] << M98090_MICCLK_SHIFT); 1925 1926 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG, 1927 M98090_DMIC_COMP_MASK, 1928 dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT); 1929 1930 return 0; 1931 } 1932 1933 /* 1934 * PLL / Sysclk 1935 */ 1936 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, 1937 int clk_id, unsigned int freq, int dir) 1938 { 1939 struct snd_soc_codec *codec = dai->codec; 1940 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1941 1942 /* Requested clock frequency is already setup */ 1943 if (freq == max98090->sysclk) 1944 return 0; 1945 1946 if (!IS_ERR(max98090->mclk)) { 1947 freq = clk_round_rate(max98090->mclk, freq); 1948 clk_set_rate(max98090->mclk, freq); 1949 } 1950 1951 /* Setup clocks for slave mode, and using the PLL 1952 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1953 * 0x02 (when master clk is 20MHz to 40MHz).. 1954 * 0x03 (when master clk is 40MHz to 60MHz).. 1955 */ 1956 if ((freq >= 10000000) && (freq < 20000000)) { 1957 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, 1958 M98090_PSCLK_DIV1); 1959 } else if ((freq >= 20000000) && (freq < 40000000)) { 1960 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, 1961 M98090_PSCLK_DIV2); 1962 } else if ((freq >= 40000000) && (freq < 60000000)) { 1963 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, 1964 M98090_PSCLK_DIV4); 1965 } else { 1966 dev_err(codec->dev, "Invalid master clock frequency\n"); 1967 return -EINVAL; 1968 } 1969 1970 max98090->sysclk = freq; 1971 1972 return 0; 1973 } 1974 1975 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1976 { 1977 struct snd_soc_codec *codec = codec_dai->codec; 1978 int regval; 1979 1980 regval = mute ? M98090_DVM_MASK : 0; 1981 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL, 1982 M98090_DVM_MASK, regval); 1983 1984 return 0; 1985 } 1986 1987 static void max98090_jack_work(struct work_struct *work) 1988 { 1989 struct max98090_priv *max98090 = container_of(work, 1990 struct max98090_priv, 1991 jack_work.work); 1992 struct snd_soc_codec *codec = max98090->codec; 1993 struct snd_soc_dapm_context *dapm = &codec->dapm; 1994 int status = 0; 1995 int reg; 1996 1997 /* Read a second time */ 1998 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { 1999 2000 /* Strong pull up allows mic detection */ 2001 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, 2002 M98090_JDWK_MASK, 0); 2003 2004 msleep(50); 2005 2006 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); 2007 2008 /* Weak pull up allows only insertion detection */ 2009 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, 2010 M98090_JDWK_MASK, M98090_JDWK_MASK); 2011 } else { 2012 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); 2013 } 2014 2015 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); 2016 2017 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { 2018 case M98090_LSNS_MASK | M98090_JKSNS_MASK: 2019 dev_dbg(codec->dev, "No Headset Detected\n"); 2020 2021 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2022 2023 status |= 0; 2024 2025 break; 2026 2027 case 0: 2028 if (max98090->jack_state == 2029 M98090_JACK_STATE_HEADSET) { 2030 2031 dev_dbg(codec->dev, 2032 "Headset Button Down Detected\n"); 2033 2034 /* 2035 * max98090_headset_button_event(codec) 2036 * could be defined, then called here. 2037 */ 2038 2039 status |= SND_JACK_HEADSET; 2040 status |= SND_JACK_BTN_0; 2041 2042 break; 2043 } 2044 2045 /* Line is reported as Headphone */ 2046 /* Nokia Headset is reported as Headphone */ 2047 /* Mono Headphone is reported as Headphone */ 2048 dev_dbg(codec->dev, "Headphone Detected\n"); 2049 2050 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; 2051 2052 status |= SND_JACK_HEADPHONE; 2053 2054 break; 2055 2056 case M98090_JKSNS_MASK: 2057 dev_dbg(codec->dev, "Headset Detected\n"); 2058 2059 max98090->jack_state = M98090_JACK_STATE_HEADSET; 2060 2061 status |= SND_JACK_HEADSET; 2062 2063 break; 2064 2065 default: 2066 dev_dbg(codec->dev, "Unrecognized Jack Status\n"); 2067 break; 2068 } 2069 2070 snd_soc_jack_report(max98090->jack, status, 2071 SND_JACK_HEADSET | SND_JACK_BTN_0); 2072 2073 snd_soc_dapm_sync(dapm); 2074 } 2075 2076 static irqreturn_t max98090_interrupt(int irq, void *data) 2077 { 2078 struct snd_soc_codec *codec = data; 2079 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2080 int ret; 2081 unsigned int mask; 2082 unsigned int active; 2083 2084 dev_dbg(codec->dev, "***** max98090_interrupt *****\n"); 2085 2086 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); 2087 2088 if (ret != 0) { 2089 dev_err(codec->dev, 2090 "failed to read M98090_REG_INTERRUPT_S: %d\n", 2091 ret); 2092 return IRQ_NONE; 2093 } 2094 2095 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); 2096 2097 if (ret != 0) { 2098 dev_err(codec->dev, 2099 "failed to read M98090_REG_DEVICE_STATUS: %d\n", 2100 ret); 2101 return IRQ_NONE; 2102 } 2103 2104 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", 2105 active, mask, active & mask); 2106 2107 active &= mask; 2108 2109 if (!active) 2110 return IRQ_NONE; 2111 2112 if (active & M98090_CLD_MASK) 2113 dev_err(codec->dev, "M98090_CLD_MASK\n"); 2114 2115 if (active & M98090_SLD_MASK) 2116 dev_dbg(codec->dev, "M98090_SLD_MASK\n"); 2117 2118 if (active & M98090_ULK_MASK) 2119 dev_err(codec->dev, "M98090_ULK_MASK\n"); 2120 2121 if (active & M98090_JDET_MASK) { 2122 dev_dbg(codec->dev, "M98090_JDET_MASK\n"); 2123 2124 pm_wakeup_event(codec->dev, 100); 2125 2126 queue_delayed_work(system_power_efficient_wq, 2127 &max98090->jack_work, 2128 msecs_to_jiffies(100)); 2129 } 2130 2131 if (active & M98090_DRCACT_MASK) 2132 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n"); 2133 2134 if (active & M98090_DRCCLP_MASK) 2135 dev_err(codec->dev, "M98090_DRCCLP_MASK\n"); 2136 2137 return IRQ_HANDLED; 2138 } 2139 2140 /** 2141 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ 2142 * 2143 * @codec: MAX98090 codec 2144 * @jack: jack to report detection events on 2145 * 2146 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are 2147 * being used to bring out signals to the processor then only platform 2148 * data configuration is needed for MAX98090 and processor GPIOs should 2149 * be configured using snd_soc_jack_add_gpios() instead. 2150 * 2151 * If no jack is supplied detection will be disabled. 2152 */ 2153 int max98090_mic_detect(struct snd_soc_codec *codec, 2154 struct snd_soc_jack *jack) 2155 { 2156 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2157 2158 dev_dbg(codec->dev, "max98090_mic_detect\n"); 2159 2160 max98090->jack = jack; 2161 if (jack) { 2162 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, 2163 M98090_IJDET_MASK, 2164 1 << M98090_IJDET_SHIFT); 2165 } else { 2166 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, 2167 M98090_IJDET_MASK, 2168 0); 2169 } 2170 2171 /* Send an initial empty report */ 2172 snd_soc_jack_report(max98090->jack, 0, 2173 SND_JACK_HEADSET | SND_JACK_BTN_0); 2174 2175 queue_delayed_work(system_power_efficient_wq, 2176 &max98090->jack_work, 2177 msecs_to_jiffies(100)); 2178 2179 return 0; 2180 } 2181 EXPORT_SYMBOL_GPL(max98090_mic_detect); 2182 2183 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 2184 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 2185 2186 static struct snd_soc_dai_ops max98090_dai_ops = { 2187 .set_sysclk = max98090_dai_set_sysclk, 2188 .set_fmt = max98090_dai_set_fmt, 2189 .set_tdm_slot = max98090_set_tdm_slot, 2190 .hw_params = max98090_dai_hw_params, 2191 .digital_mute = max98090_dai_digital_mute, 2192 }; 2193 2194 static struct snd_soc_dai_driver max98090_dai[] = { 2195 { 2196 .name = "HiFi", 2197 .playback = { 2198 .stream_name = "HiFi Playback", 2199 .channels_min = 2, 2200 .channels_max = 2, 2201 .rates = MAX98090_RATES, 2202 .formats = MAX98090_FORMATS, 2203 }, 2204 .capture = { 2205 .stream_name = "HiFi Capture", 2206 .channels_min = 1, 2207 .channels_max = 2, 2208 .rates = MAX98090_RATES, 2209 .formats = MAX98090_FORMATS, 2210 }, 2211 .ops = &max98090_dai_ops, 2212 } 2213 }; 2214 2215 static void max98090_handle_pdata(struct snd_soc_codec *codec) 2216 { 2217 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2218 struct max98090_pdata *pdata = max98090->pdata; 2219 2220 if (!pdata) { 2221 dev_err(codec->dev, "No platform data\n"); 2222 return; 2223 } 2224 2225 } 2226 2227 static int max98090_probe(struct snd_soc_codec *codec) 2228 { 2229 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2230 struct max98090_cdata *cdata; 2231 int ret = 0; 2232 2233 dev_dbg(codec->dev, "max98090_probe\n"); 2234 2235 max98090->mclk = devm_clk_get(codec->dev, "mclk"); 2236 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER) 2237 return -EPROBE_DEFER; 2238 2239 max98090->codec = codec; 2240 2241 /* Reset the codec, the DSP core, and disable all interrupts */ 2242 max98090_reset(max98090); 2243 2244 /* Initialize private data */ 2245 2246 max98090->sysclk = (unsigned)-1; 2247 max98090->master = false; 2248 2249 cdata = &max98090->dai[0]; 2250 cdata->rate = (unsigned)-1; 2251 cdata->fmt = (unsigned)-1; 2252 2253 max98090->lin_state = 0; 2254 max98090->pa1en = 0; 2255 max98090->pa2en = 0; 2256 max98090->extmic_mux = 0; 2257 2258 ret = snd_soc_read(codec, M98090_REG_REVISION_ID); 2259 if (ret < 0) { 2260 dev_err(codec->dev, "Failed to read device revision: %d\n", 2261 ret); 2262 goto err_access; 2263 } 2264 2265 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) { 2266 max98090->devtype = MAX98090; 2267 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret); 2268 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) { 2269 max98090->devtype = MAX98091; 2270 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret); 2271 } else { 2272 max98090->devtype = MAX98090; 2273 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret); 2274 } 2275 2276 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2277 2278 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); 2279 2280 /* Enable jack detection */ 2281 snd_soc_write(codec, M98090_REG_JACK_DETECT, 2282 M98090_JDETEN_MASK | M98090_JDEB_25MS); 2283 2284 /* Register for interrupts */ 2285 dev_dbg(codec->dev, "irq = %d\n", max98090->irq); 2286 2287 ret = request_threaded_irq(max98090->irq, NULL, 2288 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2289 "max98090_interrupt", codec); 2290 if (ret < 0) { 2291 dev_err(codec->dev, "request_irq failed: %d\n", 2292 ret); 2293 } 2294 2295 /* 2296 * Clear any old interrupts. 2297 * An old interrupt ocurring prior to installing the ISR 2298 * can keep a new interrupt from generating a trigger. 2299 */ 2300 snd_soc_read(codec, M98090_REG_DEVICE_STATUS); 2301 2302 /* High Performance is default */ 2303 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL, 2304 M98090_DACHP_MASK, 2305 1 << M98090_DACHP_SHIFT); 2306 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL, 2307 M98090_PERFMODE_MASK, 2308 0 << M98090_PERFMODE_SHIFT); 2309 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL, 2310 M98090_ADCHP_MASK, 2311 1 << M98090_ADCHP_SHIFT); 2312 2313 /* Turn on VCM bandgap reference */ 2314 snd_soc_write(codec, M98090_REG_BIAS_CONTROL, 2315 M98090_VCM_MODE_MASK); 2316 2317 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE, 2318 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8); 2319 2320 max98090_handle_pdata(codec); 2321 2322 max98090_add_widgets(codec); 2323 2324 err_access: 2325 return ret; 2326 } 2327 2328 static int max98090_remove(struct snd_soc_codec *codec) 2329 { 2330 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2331 2332 cancel_delayed_work_sync(&max98090->jack_work); 2333 2334 return 0; 2335 } 2336 2337 static struct snd_soc_codec_driver soc_codec_dev_max98090 = { 2338 .probe = max98090_probe, 2339 .remove = max98090_remove, 2340 .set_bias_level = max98090_set_bias_level, 2341 }; 2342 2343 static const struct regmap_config max98090_regmap = { 2344 .reg_bits = 8, 2345 .val_bits = 8, 2346 2347 .max_register = MAX98090_MAX_REGISTER, 2348 .reg_defaults = max98090_reg, 2349 .num_reg_defaults = ARRAY_SIZE(max98090_reg), 2350 .volatile_reg = max98090_volatile_register, 2351 .readable_reg = max98090_readable_register, 2352 .cache_type = REGCACHE_RBTREE, 2353 }; 2354 2355 static int max98090_i2c_probe(struct i2c_client *i2c, 2356 const struct i2c_device_id *i2c_id) 2357 { 2358 struct max98090_priv *max98090; 2359 const struct acpi_device_id *acpi_id; 2360 kernel_ulong_t driver_data = 0; 2361 int ret; 2362 2363 pr_debug("max98090_i2c_probe\n"); 2364 2365 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), 2366 GFP_KERNEL); 2367 if (max98090 == NULL) 2368 return -ENOMEM; 2369 2370 if (ACPI_HANDLE(&i2c->dev)) { 2371 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table, 2372 &i2c->dev); 2373 if (!acpi_id) { 2374 dev_err(&i2c->dev, "No driver data\n"); 2375 return -EINVAL; 2376 } 2377 driver_data = acpi_id->driver_data; 2378 } else if (i2c_id) { 2379 driver_data = i2c_id->driver_data; 2380 } 2381 2382 max98090->devtype = driver_data; 2383 i2c_set_clientdata(i2c, max98090); 2384 max98090->pdata = i2c->dev.platform_data; 2385 max98090->irq = i2c->irq; 2386 2387 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); 2388 if (IS_ERR(max98090->regmap)) { 2389 ret = PTR_ERR(max98090->regmap); 2390 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 2391 goto err_enable; 2392 } 2393 2394 ret = snd_soc_register_codec(&i2c->dev, 2395 &soc_codec_dev_max98090, max98090_dai, 2396 ARRAY_SIZE(max98090_dai)); 2397 err_enable: 2398 return ret; 2399 } 2400 2401 static int max98090_i2c_remove(struct i2c_client *client) 2402 { 2403 snd_soc_unregister_codec(&client->dev); 2404 return 0; 2405 } 2406 2407 #ifdef CONFIG_PM_RUNTIME 2408 static int max98090_runtime_resume(struct device *dev) 2409 { 2410 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2411 2412 regcache_cache_only(max98090->regmap, false); 2413 2414 max98090_reset(max98090); 2415 2416 regcache_sync(max98090->regmap); 2417 2418 return 0; 2419 } 2420 2421 static int max98090_runtime_suspend(struct device *dev) 2422 { 2423 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2424 2425 regcache_cache_only(max98090->regmap, true); 2426 2427 return 0; 2428 } 2429 #endif 2430 2431 #ifdef CONFIG_PM 2432 static int max98090_resume(struct device *dev) 2433 { 2434 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2435 unsigned int status; 2436 2437 regcache_mark_dirty(max98090->regmap); 2438 2439 max98090_reset(max98090); 2440 2441 /* clear IRQ status */ 2442 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); 2443 2444 regcache_sync(max98090->regmap); 2445 2446 return 0; 2447 } 2448 2449 static int max98090_suspend(struct device *dev) 2450 { 2451 return 0; 2452 } 2453 #endif 2454 2455 static const struct dev_pm_ops max98090_pm = { 2456 SET_RUNTIME_PM_OPS(max98090_runtime_suspend, 2457 max98090_runtime_resume, NULL) 2458 SET_SYSTEM_SLEEP_PM_OPS(max98090_suspend, max98090_resume) 2459 }; 2460 2461 static const struct i2c_device_id max98090_i2c_id[] = { 2462 { "max98090", MAX98090 }, 2463 { } 2464 }; 2465 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); 2466 2467 static const struct of_device_id max98090_of_match[] = { 2468 { .compatible = "maxim,max98090", }, 2469 { } 2470 }; 2471 MODULE_DEVICE_TABLE(of, max98090_of_match); 2472 2473 #ifdef CONFIG_ACPI 2474 static struct acpi_device_id max98090_acpi_match[] = { 2475 { "193C9890", MAX98090 }, 2476 { } 2477 }; 2478 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match); 2479 #endif 2480 2481 static struct i2c_driver max98090_i2c_driver = { 2482 .driver = { 2483 .name = "max98090", 2484 .owner = THIS_MODULE, 2485 .pm = &max98090_pm, 2486 .of_match_table = of_match_ptr(max98090_of_match), 2487 .acpi_match_table = ACPI_PTR(max98090_acpi_match), 2488 }, 2489 .probe = max98090_i2c_probe, 2490 .remove = max98090_i2c_remove, 2491 .id_table = max98090_i2c_id, 2492 }; 2493 2494 module_i2c_driver(max98090_i2c_driver); 2495 2496 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); 2497 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong"); 2498 MODULE_LICENSE("GPL"); 2499