xref: /openbmc/linux/sound/soc/codecs/max98090.c (revision c819e2cf)
1 /*
2  * max98090.c -- MAX98090 ALSA SoC Audio driver
3  *
4  * Copyright 2011-2012 Maxim Integrated Products
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #include <linux/delay.h>
12 #include <linux/i2c.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/pm.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19 #include <linux/acpi.h>
20 #include <linux/clk.h>
21 #include <sound/jack.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/soc.h>
25 #include <sound/tlv.h>
26 #include <sound/max98090.h>
27 #include "max98090.h"
28 
29 /* Allows for sparsely populated register maps */
30 static struct reg_default max98090_reg[] = {
31 	{ 0x00, 0x00 }, /* 00 Software Reset */
32 	{ 0x03, 0x04 }, /* 03 Interrupt Masks */
33 	{ 0x04, 0x00 }, /* 04 System Clock Quick */
34 	{ 0x05, 0x00 }, /* 05 Sample Rate Quick */
35 	{ 0x06, 0x00 }, /* 06 DAI Interface Quick */
36 	{ 0x07, 0x00 }, /* 07 DAC Path Quick */
37 	{ 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */
38 	{ 0x09, 0x00 }, /* 09 Line to ADC Quick */
39 	{ 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */
40 	{ 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */
41 	{ 0x0C, 0x00 }, /* 0C Reserved */
42 	{ 0x0D, 0x00 }, /* 0D Input Config */
43 	{ 0x0E, 0x1B }, /* 0E Line Input Level */
44 	{ 0x0F, 0x00 }, /* 0F Line Config */
45 
46 	{ 0x10, 0x14 }, /* 10 Mic1 Input Level */
47 	{ 0x11, 0x14 }, /* 11 Mic2 Input Level */
48 	{ 0x12, 0x00 }, /* 12 Mic Bias Voltage */
49 	{ 0x13, 0x00 }, /* 13 Digital Mic Config */
50 	{ 0x14, 0x00 }, /* 14 Digital Mic Mode */
51 	{ 0x15, 0x00 }, /* 15 Left ADC Mixer */
52 	{ 0x16, 0x00 }, /* 16 Right ADC Mixer */
53 	{ 0x17, 0x03 }, /* 17 Left ADC Level */
54 	{ 0x18, 0x03 }, /* 18 Right ADC Level */
55 	{ 0x19, 0x00 }, /* 19 ADC Biquad Level */
56 	{ 0x1A, 0x00 }, /* 1A ADC Sidetone */
57 	{ 0x1B, 0x00 }, /* 1B System Clock */
58 	{ 0x1C, 0x00 }, /* 1C Clock Mode */
59 	{ 0x1D, 0x00 }, /* 1D Any Clock 1 */
60 	{ 0x1E, 0x00 }, /* 1E Any Clock 2 */
61 	{ 0x1F, 0x00 }, /* 1F Any Clock 3 */
62 
63 	{ 0x20, 0x00 }, /* 20 Any Clock 4 */
64 	{ 0x21, 0x00 }, /* 21 Master Mode */
65 	{ 0x22, 0x00 }, /* 22 Interface Format */
66 	{ 0x23, 0x00 }, /* 23 TDM Format 1*/
67 	{ 0x24, 0x00 }, /* 24 TDM Format 2*/
68 	{ 0x25, 0x00 }, /* 25 I/O Configuration */
69 	{ 0x26, 0x80 }, /* 26 Filter Config */
70 	{ 0x27, 0x00 }, /* 27 DAI Playback Level */
71 	{ 0x28, 0x00 }, /* 28 EQ Playback Level */
72 	{ 0x29, 0x00 }, /* 29 Left HP Mixer */
73 	{ 0x2A, 0x00 }, /* 2A Right HP Mixer */
74 	{ 0x2B, 0x00 }, /* 2B HP Control */
75 	{ 0x2C, 0x1A }, /* 2C Left HP Volume */
76 	{ 0x2D, 0x1A }, /* 2D Right HP Volume */
77 	{ 0x2E, 0x00 }, /* 2E Left Spk Mixer */
78 	{ 0x2F, 0x00 }, /* 2F Right Spk Mixer */
79 
80 	{ 0x30, 0x00 }, /* 30 Spk Control */
81 	{ 0x31, 0x2C }, /* 31 Left Spk Volume */
82 	{ 0x32, 0x2C }, /* 32 Right Spk Volume */
83 	{ 0x33, 0x00 }, /* 33 ALC Timing */
84 	{ 0x34, 0x00 }, /* 34 ALC Compressor */
85 	{ 0x35, 0x00 }, /* 35 ALC Expander */
86 	{ 0x36, 0x00 }, /* 36 ALC Gain */
87 	{ 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */
88 	{ 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */
89 	{ 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */
90 	{ 0x3A, 0x00 }, /* 3A Line OutR Mixer */
91 	{ 0x3B, 0x00 }, /* 3B Line OutR Control */
92 	{ 0x3C, 0x15 }, /* 3C Line OutR Volume */
93 	{ 0x3D, 0x00 }, /* 3D Jack Detect */
94 	{ 0x3E, 0x00 }, /* 3E Input Enable */
95 	{ 0x3F, 0x00 }, /* 3F Output Enable */
96 
97 	{ 0x40, 0x00 }, /* 40 Level Control */
98 	{ 0x41, 0x00 }, /* 41 DSP Filter Enable */
99 	{ 0x42, 0x00 }, /* 42 Bias Control */
100 	{ 0x43, 0x00 }, /* 43 DAC Control */
101 	{ 0x44, 0x06 }, /* 44 ADC Control */
102 	{ 0x45, 0x00 }, /* 45 Device Shutdown */
103 	{ 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
104 	{ 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
105 	{ 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
106 	{ 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
107 	{ 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
108 	{ 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
109 	{ 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
110 	{ 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
111 	{ 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
112 	{ 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
113 
114 	{ 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
115 	{ 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
116 	{ 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
117 	{ 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
118 	{ 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
119 	{ 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
120 	{ 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
121 	{ 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
122 	{ 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
123 	{ 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
124 	{ 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
125 	{ 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
126 	{ 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
127 	{ 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
128 	{ 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
129 	{ 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
130 
131 	{ 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
132 	{ 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
133 	{ 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
134 	{ 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
135 	{ 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
136 	{ 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
137 	{ 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
138 	{ 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
139 	{ 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
140 	{ 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
141 	{ 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
142 	{ 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
143 	{ 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
144 	{ 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
145 	{ 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
146 	{ 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
147 
148 	{ 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
149 	{ 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
150 	{ 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
151 	{ 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
152 	{ 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
153 	{ 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
154 	{ 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
155 	{ 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
156 	{ 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
157 	{ 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
158 	{ 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
159 	{ 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
160 	{ 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
161 	{ 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
162 	{ 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
163 	{ 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
164 
165 	{ 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
166 	{ 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
167 	{ 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
168 	{ 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
169 	{ 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
170 	{ 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
171 	{ 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
172 	{ 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
173 	{ 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
174 	{ 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
175 	{ 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
176 	{ 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
177 	{ 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
178 	{ 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
179 	{ 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
180 	{ 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
181 
182 	{ 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
183 	{ 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
184 	{ 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
185 	{ 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
186 	{ 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
187 	{ 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
188 	{ 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
189 	{ 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
190 	{ 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
191 	{ 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
192 	{ 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
193 	{ 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
194 	{ 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
195 	{ 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
196 	{ 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
197 	{ 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
198 
199 	{ 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
200 	{ 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
201 	{ 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
202 	{ 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
203 	{ 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
204 	{ 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
205 	{ 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
206 	{ 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
207 	{ 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
208 	{ 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
209 	{ 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
210 	{ 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
211 	{ 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
212 	{ 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
213 	{ 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
214 	{ 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */
215 
216 	{ 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */
217 	{ 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */
218 	{ 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */
219 	{ 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */
220 	{ 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */
221 	{ 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */
222 	{ 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */
223 	{ 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */
224 	{ 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */
225 	{ 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */
226 	{ 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */
227 	{ 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */
228 	{ 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */
229 	{ 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */
230 	{ 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */
231 	{ 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */
232 
233 	{ 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */
234 	{ 0xC1, 0x00 }, /* C1 Record TDM Slot */
235 	{ 0xC2, 0x00 }, /* C2 Sample Rate */
236 	{ 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */
237 	{ 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */
238 	{ 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */
239 	{ 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */
240 	{ 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */
241 	{ 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */
242 	{ 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */
243 	{ 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */
244 	{ 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */
245 	{ 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */
246 	{ 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */
247 	{ 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */
248 	{ 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */
249 
250 	{ 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */
251 	{ 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */
252 };
253 
254 static bool max98090_volatile_register(struct device *dev, unsigned int reg)
255 {
256 	switch (reg) {
257 	case M98090_REG_SOFTWARE_RESET:
258 	case M98090_REG_DEVICE_STATUS:
259 	case M98090_REG_JACK_STATUS:
260 	case M98090_REG_REVISION_ID:
261 		return true;
262 	default:
263 		return false;
264 	}
265 }
266 
267 static bool max98090_readable_register(struct device *dev, unsigned int reg)
268 {
269 	switch (reg) {
270 	case M98090_REG_DEVICE_STATUS:
271 	case M98090_REG_JACK_STATUS:
272 	case M98090_REG_INTERRUPT_S:
273 	case M98090_REG_RESERVED:
274 	case M98090_REG_LINE_INPUT_CONFIG:
275 	case M98090_REG_LINE_INPUT_LEVEL:
276 	case M98090_REG_INPUT_MODE:
277 	case M98090_REG_MIC1_INPUT_LEVEL:
278 	case M98090_REG_MIC2_INPUT_LEVEL:
279 	case M98090_REG_MIC_BIAS_VOLTAGE:
280 	case M98090_REG_DIGITAL_MIC_ENABLE:
281 	case M98090_REG_DIGITAL_MIC_CONFIG:
282 	case M98090_REG_LEFT_ADC_MIXER:
283 	case M98090_REG_RIGHT_ADC_MIXER:
284 	case M98090_REG_LEFT_ADC_LEVEL:
285 	case M98090_REG_RIGHT_ADC_LEVEL:
286 	case M98090_REG_ADC_BIQUAD_LEVEL:
287 	case M98090_REG_ADC_SIDETONE:
288 	case M98090_REG_SYSTEM_CLOCK:
289 	case M98090_REG_CLOCK_MODE:
290 	case M98090_REG_CLOCK_RATIO_NI_MSB:
291 	case M98090_REG_CLOCK_RATIO_NI_LSB:
292 	case M98090_REG_CLOCK_RATIO_MI_MSB:
293 	case M98090_REG_CLOCK_RATIO_MI_LSB:
294 	case M98090_REG_MASTER_MODE:
295 	case M98090_REG_INTERFACE_FORMAT:
296 	case M98090_REG_TDM_CONTROL:
297 	case M98090_REG_TDM_FORMAT:
298 	case M98090_REG_IO_CONFIGURATION:
299 	case M98090_REG_FILTER_CONFIG:
300 	case M98090_REG_DAI_PLAYBACK_LEVEL:
301 	case M98090_REG_DAI_PLAYBACK_LEVEL_EQ:
302 	case M98090_REG_LEFT_HP_MIXER:
303 	case M98090_REG_RIGHT_HP_MIXER:
304 	case M98090_REG_HP_CONTROL:
305 	case M98090_REG_LEFT_HP_VOLUME:
306 	case M98090_REG_RIGHT_HP_VOLUME:
307 	case M98090_REG_LEFT_SPK_MIXER:
308 	case M98090_REG_RIGHT_SPK_MIXER:
309 	case M98090_REG_SPK_CONTROL:
310 	case M98090_REG_LEFT_SPK_VOLUME:
311 	case M98090_REG_RIGHT_SPK_VOLUME:
312 	case M98090_REG_DRC_TIMING:
313 	case M98090_REG_DRC_COMPRESSOR:
314 	case M98090_REG_DRC_EXPANDER:
315 	case M98090_REG_DRC_GAIN:
316 	case M98090_REG_RCV_LOUTL_MIXER:
317 	case M98090_REG_RCV_LOUTL_CONTROL:
318 	case M98090_REG_RCV_LOUTL_VOLUME:
319 	case M98090_REG_LOUTR_MIXER:
320 	case M98090_REG_LOUTR_CONTROL:
321 	case M98090_REG_LOUTR_VOLUME:
322 	case M98090_REG_JACK_DETECT:
323 	case M98090_REG_INPUT_ENABLE:
324 	case M98090_REG_OUTPUT_ENABLE:
325 	case M98090_REG_LEVEL_CONTROL:
326 	case M98090_REG_DSP_FILTER_ENABLE:
327 	case M98090_REG_BIAS_CONTROL:
328 	case M98090_REG_DAC_CONTROL:
329 	case M98090_REG_ADC_CONTROL:
330 	case M98090_REG_DEVICE_SHUTDOWN:
331 	case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68:
332 	case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E:
333 	case M98090_REG_DMIC3_VOLUME:
334 	case M98090_REG_DMIC4_VOLUME:
335 	case M98090_REG_DMIC34_BQ_PREATTEN:
336 	case M98090_REG_RECORD_TDM_SLOT:
337 	case M98090_REG_SAMPLE_RATE:
338 	case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E:
339 	case M98090_REG_REVISION_ID:
340 		return true;
341 	default:
342 		return false;
343 	}
344 }
345 
346 static int max98090_reset(struct max98090_priv *max98090)
347 {
348 	int ret;
349 
350 	/* Reset the codec by writing to this write-only reset register */
351 	ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
352 		M98090_SWRESET_MASK);
353 	if (ret < 0) {
354 		dev_err(max98090->codec->dev,
355 			"Failed to reset codec: %d\n", ret);
356 		return ret;
357 	}
358 
359 	msleep(20);
360 	return ret;
361 }
362 
363 static const unsigned int max98090_micboost_tlv[] = {
364 	TLV_DB_RANGE_HEAD(2),
365 	0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0),
366 	2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0),
367 };
368 
369 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0);
370 
371 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv,
372 	-600, 600, 0);
373 
374 static const unsigned int max98090_line_tlv[] = {
375 	TLV_DB_RANGE_HEAD(2),
376 	0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
377 	4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0),
378 };
379 
380 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0);
381 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
382 
383 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0);
384 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
385 
386 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0);
387 
388 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0);
389 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0);
390 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
391 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
392 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0);
393 
394 static const unsigned int max98090_mixout_tlv[] = {
395 	TLV_DB_RANGE_HEAD(2),
396 	0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
397 	2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0),
398 };
399 
400 static const unsigned int max98090_hp_tlv[] = {
401 	TLV_DB_RANGE_HEAD(5),
402 	0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
403 	7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
404 	15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
405 	22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
406 	28, 31, TLV_DB_SCALE_ITEM(150, 50, 0),
407 };
408 
409 static const unsigned int max98090_spk_tlv[] = {
410 	TLV_DB_RANGE_HEAD(5),
411 	0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
412 	5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
413 	11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
414 	15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
415 	30, 39, TLV_DB_SCALE_ITEM(950, 50, 0),
416 };
417 
418 static const unsigned int max98090_rcv_lout_tlv[] = {
419 	TLV_DB_RANGE_HEAD(5),
420 	0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
421 	7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
422 	15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
423 	22, 27, TLV_DB_SCALE_ITEM(100, 100, 0),
424 	28, 31, TLV_DB_SCALE_ITEM(650, 50, 0),
425 };
426 
427 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol,
428 				struct snd_ctl_elem_value *ucontrol)
429 {
430 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
431 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
432 	struct soc_mixer_control *mc =
433 		(struct soc_mixer_control *)kcontrol->private_value;
434 	unsigned int mask = (1 << fls(mc->max)) - 1;
435 	unsigned int val = snd_soc_read(codec, mc->reg);
436 	unsigned int *select;
437 
438 	switch (mc->reg) {
439 	case M98090_REG_MIC1_INPUT_LEVEL:
440 		select = &(max98090->pa1en);
441 		break;
442 	case M98090_REG_MIC2_INPUT_LEVEL:
443 		select = &(max98090->pa2en);
444 		break;
445 	case M98090_REG_ADC_SIDETONE:
446 		select = &(max98090->sidetone);
447 		break;
448 	default:
449 		return -EINVAL;
450 	}
451 
452 	val = (val >> mc->shift) & mask;
453 
454 	if (val >= 1) {
455 		/* If on, return the volume */
456 		val = val - 1;
457 		*select = val;
458 	} else {
459 		/* If off, return last stored value */
460 		val = *select;
461 	}
462 
463 	ucontrol->value.integer.value[0] = val;
464 	return 0;
465 }
466 
467 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol,
468 				struct snd_ctl_elem_value *ucontrol)
469 {
470 	struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
471 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
472 	struct soc_mixer_control *mc =
473 		(struct soc_mixer_control *)kcontrol->private_value;
474 	unsigned int mask = (1 << fls(mc->max)) - 1;
475 	unsigned int sel = ucontrol->value.integer.value[0];
476 	unsigned int val = snd_soc_read(codec, mc->reg);
477 	unsigned int *select;
478 
479 	switch (mc->reg) {
480 	case M98090_REG_MIC1_INPUT_LEVEL:
481 		select = &(max98090->pa1en);
482 		break;
483 	case M98090_REG_MIC2_INPUT_LEVEL:
484 		select = &(max98090->pa2en);
485 		break;
486 	case M98090_REG_ADC_SIDETONE:
487 		select = &(max98090->sidetone);
488 		break;
489 	default:
490 		return -EINVAL;
491 	}
492 
493 	val = (val >> mc->shift) & mask;
494 
495 	*select = sel;
496 
497 	/* Setting a volume is only valid if it is already On */
498 	if (val >= 1) {
499 		sel = sel + 1;
500 	} else {
501 		/* Write what was already there */
502 		sel = val;
503 	}
504 
505 	snd_soc_update_bits(codec, mc->reg,
506 		mask << mc->shift,
507 		sel << mc->shift);
508 
509 	return 0;
510 }
511 
512 static const char *max98090_perf_pwr_text[] =
513 	{ "High Performance", "Low Power" };
514 static const char *max98090_pwr_perf_text[] =
515 	{ "Low Power", "High Performance" };
516 
517 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum,
518 			    M98090_REG_BIAS_CONTROL,
519 			    M98090_VCM_MODE_SHIFT,
520 			    max98090_pwr_perf_text);
521 
522 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" };
523 
524 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum,
525 			    M98090_REG_ADC_CONTROL,
526 			    M98090_OSR128_SHIFT,
527 			    max98090_osr128_text);
528 
529 static const char *max98090_mode_text[] = { "Voice", "Music" };
530 
531 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum,
532 			    M98090_REG_FILTER_CONFIG,
533 			    M98090_MODE_SHIFT,
534 			    max98090_mode_text);
535 
536 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum,
537 			    M98090_REG_FILTER_CONFIG,
538 			    M98090_FLT_DMIC34MODE_SHIFT,
539 			    max98090_mode_text);
540 
541 static const char *max98090_drcatk_text[] =
542 	{ "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" };
543 
544 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum,
545 			    M98090_REG_DRC_TIMING,
546 			    M98090_DRCATK_SHIFT,
547 			    max98090_drcatk_text);
548 
549 static const char *max98090_drcrls_text[] =
550 	{ "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" };
551 
552 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum,
553 			    M98090_REG_DRC_TIMING,
554 			    M98090_DRCRLS_SHIFT,
555 			    max98090_drcrls_text);
556 
557 static const char *max98090_alccmp_text[] =
558 	{ "1:1", "1:1.5", "1:2", "1:4", "1:INF" };
559 
560 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum,
561 			    M98090_REG_DRC_COMPRESSOR,
562 			    M98090_DRCCMP_SHIFT,
563 			    max98090_alccmp_text);
564 
565 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" };
566 
567 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum,
568 			    M98090_REG_DRC_EXPANDER,
569 			    M98090_DRCEXP_SHIFT,
570 			    max98090_drcexp_text);
571 
572 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum,
573 			    M98090_REG_DAC_CONTROL,
574 			    M98090_PERFMODE_SHIFT,
575 			    max98090_perf_pwr_text);
576 
577 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum,
578 			    M98090_REG_DAC_CONTROL,
579 			    M98090_DACHP_SHIFT,
580 			    max98090_pwr_perf_text);
581 
582 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum,
583 			    M98090_REG_ADC_CONTROL,
584 			    M98090_ADCHP_SHIFT,
585 			    max98090_pwr_perf_text);
586 
587 static const struct snd_kcontrol_new max98090_snd_controls[] = {
588 	SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum),
589 
590 	SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG,
591 		M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
592 
593 	SOC_SINGLE_EXT_TLV("MIC1 Boost Volume",
594 		M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT,
595 		M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
596 		max98090_put_enab_tlv, max98090_micboost_tlv),
597 
598 	SOC_SINGLE_EXT_TLV("MIC2 Boost Volume",
599 		M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT,
600 		M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
601 		max98090_put_enab_tlv, max98090_micboost_tlv),
602 
603 	SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL,
604 		M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
605 		max98090_mic_tlv),
606 
607 	SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL,
608 		M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
609 		max98090_mic_tlv),
610 
611 	SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume",
612 		M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0,
613 		M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
614 
615 	SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume",
616 		M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0,
617 		M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
618 
619 	SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL,
620 		M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
621 		max98090_line_tlv),
622 
623 	SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL,
624 		M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
625 		max98090_line_tlv),
626 
627 	SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
628 		M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
629 	SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE,
630 		M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
631 
632 	SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL,
633 		M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
634 		max98090_avg_tlv),
635 	SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
636 		M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
637 		max98090_avg_tlv),
638 
639 	SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL,
640 		M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
641 		max98090_av_tlv),
642 	SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
643 		M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
644 		max98090_av_tlv),
645 
646 	SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
647 	SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL,
648 		M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
649 	SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum),
650 
651 	SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION,
652 		M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
653 	SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION,
654 		M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
655 	SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION,
656 		M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
657 	SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
658 		M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
659 	SOC_ENUM("Filter Mode", max98090_mode_enum),
660 	SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG,
661 		M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
662 	SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG,
663 		M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
664 	SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL,
665 		M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
666 	SOC_SINGLE_EXT_TLV("Digital Sidetone Volume",
667 		M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT,
668 		M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
669 		max98090_put_enab_tlv, max98090_sdg_tlv),
670 	SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
671 		M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
672 		max98090_dvg_tlv),
673 	SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL,
674 		M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
675 		max98090_dv_tlv),
676 	SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105),
677 	SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
678 		M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
679 	SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
680 		M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
681 	SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
682 		M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
683 	SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
684 		M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
685 		1),
686 	SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ,
687 		M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
688 		max98090_dv_tlv),
689 
690 	SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING,
691 		M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
692 	SOC_ENUM("ALC Attack Time", max98090_drcatk_enum),
693 	SOC_ENUM("ALC Release Time", max98090_drcrls_enum),
694 	SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN,
695 		M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
696 		max98090_alcmakeup_tlv),
697 	SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
698 	SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
699 	SOC_SINGLE_TLV("ALC Compression Threshold Volume",
700 		M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT,
701 		M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
702 	SOC_SINGLE_TLV("ALC Expansion Threshold Volume",
703 		M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT,
704 		M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
705 
706 	SOC_ENUM("DAC HP Playback Performance Mode",
707 		max98090_dac_perfmode_enum),
708 	SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum),
709 
710 	SOC_SINGLE_TLV("Headphone Left Mixer Volume",
711 		M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT,
712 		M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
713 	SOC_SINGLE_TLV("Headphone Right Mixer Volume",
714 		M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT,
715 		M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
716 
717 	SOC_SINGLE_TLV("Speaker Left Mixer Volume",
718 		M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT,
719 		M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
720 	SOC_SINGLE_TLV("Speaker Right Mixer Volume",
721 		M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT,
722 		M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
723 
724 	SOC_SINGLE_TLV("Receiver Left Mixer Volume",
725 		M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT,
726 		M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
727 	SOC_SINGLE_TLV("Receiver Right Mixer Volume",
728 		M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT,
729 		M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
730 
731 	SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME,
732 		M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT,
733 		M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
734 
735 	SOC_DOUBLE_R_RANGE_TLV("Speaker Volume",
736 		M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME,
737 		M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
738 		0, max98090_spk_tlv),
739 
740 	SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME,
741 		M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT,
742 		M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
743 
744 	SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
745 		M98090_HPLM_SHIFT, 1, 1),
746 	SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
747 		M98090_HPRM_SHIFT, 1, 1),
748 
749 	SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
750 		M98090_SPLM_SHIFT, 1, 1),
751 	SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
752 		M98090_SPRM_SHIFT, 1, 1),
753 
754 	SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
755 		M98090_RCVLM_SHIFT, 1, 1),
756 	SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
757 		M98090_RCVRM_SHIFT, 1, 1),
758 
759 	SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
760 		M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
761 	SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL,
762 		M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
763 	SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL,
764 		M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
765 
766 	SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15),
767 	SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
768 		M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
769 };
770 
771 static const struct snd_kcontrol_new max98091_snd_controls[] = {
772 
773 	SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE,
774 		M98090_DMIC34_ZEROPAD_SHIFT,
775 		M98090_DMIC34_ZEROPAD_NUM - 1, 0),
776 
777 	SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum),
778 	SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG,
779 		M98090_FLT_DMIC34HPF_SHIFT,
780 		M98090_FLT_DMIC34HPF_NUM - 1, 0),
781 
782 	SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME,
783 		M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
784 		max98090_avg_tlv),
785 	SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME,
786 		M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
787 		max98090_avg_tlv),
788 
789 	SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME,
790 		M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
791 		max98090_av_tlv),
792 	SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME,
793 		M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
794 		max98090_av_tlv),
795 
796 	SND_SOC_BYTES("DMIC34 Biquad Coefficients",
797 		M98090_REG_DMIC34_BIQUAD_BASE, 15),
798 	SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
799 		M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
800 
801 	SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume",
802 		M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT,
803 		M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
804 };
805 
806 static int max98090_micinput_event(struct snd_soc_dapm_widget *w,
807 				 struct snd_kcontrol *kcontrol, int event)
808 {
809 	struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
810 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
811 
812 	unsigned int val = snd_soc_read(codec, w->reg);
813 
814 	if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
815 		val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT;
816 	else
817 		val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT;
818 
819 	if (val >= 1) {
820 		if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
821 			max98090->pa1en = val - 1; /* Update for volatile */
822 		} else {
823 			max98090->pa2en = val - 1; /* Update for volatile */
824 		}
825 	}
826 
827 	switch (event) {
828 	case SND_SOC_DAPM_POST_PMU:
829 		/* If turning on, set to most recently selected volume */
830 		if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
831 			val = max98090->pa1en + 1;
832 		else
833 			val = max98090->pa2en + 1;
834 		break;
835 	case SND_SOC_DAPM_POST_PMD:
836 		/* If turning off, turn off */
837 		val = 0;
838 		break;
839 	default:
840 		return -EINVAL;
841 	}
842 
843 	if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
844 		snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK,
845 			val << M98090_MIC_PA1EN_SHIFT);
846 	else
847 		snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK,
848 			val << M98090_MIC_PA2EN_SHIFT);
849 
850 	return 0;
851 }
852 
853 static const char *mic1_mux_text[] = { "IN12", "IN56" };
854 
855 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum,
856 			    M98090_REG_INPUT_MODE,
857 			    M98090_EXTMIC1_SHIFT,
858 			    mic1_mux_text);
859 
860 static const struct snd_kcontrol_new max98090_mic1_mux =
861 	SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum);
862 
863 static const char *mic2_mux_text[] = { "IN34", "IN56" };
864 
865 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum,
866 			    M98090_REG_INPUT_MODE,
867 			    M98090_EXTMIC2_SHIFT,
868 			    mic2_mux_text);
869 
870 static const struct snd_kcontrol_new max98090_mic2_mux =
871 	SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum);
872 
873 static const char *dmic_mux_text[] = { "ADC", "DMIC" };
874 
875 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text);
876 
877 static const struct snd_kcontrol_new max98090_dmic_mux =
878 	SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum);
879 
880 static const char *max98090_micpre_text[] = { "Off", "On" };
881 
882 static SOC_ENUM_SINGLE_DECL(max98090_pa1en_enum,
883 			    M98090_REG_MIC1_INPUT_LEVEL,
884 			    M98090_MIC_PA1EN_SHIFT,
885 			    max98090_micpre_text);
886 
887 static SOC_ENUM_SINGLE_DECL(max98090_pa2en_enum,
888 			    M98090_REG_MIC2_INPUT_LEVEL,
889 			    M98090_MIC_PA2EN_SHIFT,
890 			    max98090_micpre_text);
891 
892 /* LINEA mixer switch */
893 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = {
894 	SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
895 		M98090_IN1SEEN_SHIFT, 1, 0),
896 	SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
897 		M98090_IN3SEEN_SHIFT, 1, 0),
898 	SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
899 		M98090_IN5SEEN_SHIFT, 1, 0),
900 	SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
901 		M98090_IN34DIFF_SHIFT, 1, 0),
902 };
903 
904 /* LINEB mixer switch */
905 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = {
906 	SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
907 		M98090_IN2SEEN_SHIFT, 1, 0),
908 	SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
909 		M98090_IN4SEEN_SHIFT, 1, 0),
910 	SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
911 		M98090_IN6SEEN_SHIFT, 1, 0),
912 	SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
913 		M98090_IN56DIFF_SHIFT, 1, 0),
914 };
915 
916 /* Left ADC mixer switch */
917 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = {
918 	SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
919 		M98090_MIXADL_IN12DIFF_SHIFT, 1, 0),
920 	SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
921 		M98090_MIXADL_IN34DIFF_SHIFT, 1, 0),
922 	SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
923 		M98090_MIXADL_IN65DIFF_SHIFT, 1, 0),
924 	SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
925 		M98090_MIXADL_LINEA_SHIFT, 1, 0),
926 	SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
927 		M98090_MIXADL_LINEB_SHIFT, 1, 0),
928 	SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
929 		M98090_MIXADL_MIC1_SHIFT, 1, 0),
930 	SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
931 		M98090_MIXADL_MIC2_SHIFT, 1, 0),
932 };
933 
934 /* Right ADC mixer switch */
935 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = {
936 	SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
937 		M98090_MIXADR_IN12DIFF_SHIFT, 1, 0),
938 	SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
939 		M98090_MIXADR_IN34DIFF_SHIFT, 1, 0),
940 	SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
941 		M98090_MIXADR_IN65DIFF_SHIFT, 1, 0),
942 	SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
943 		M98090_MIXADR_LINEA_SHIFT, 1, 0),
944 	SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
945 		M98090_MIXADR_LINEB_SHIFT, 1, 0),
946 	SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
947 		M98090_MIXADR_MIC1_SHIFT, 1, 0),
948 	SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
949 		M98090_MIXADR_MIC2_SHIFT, 1, 0),
950 };
951 
952 static const char *lten_mux_text[] = { "Normal", "Loopthrough" };
953 
954 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum,
955 			    M98090_REG_IO_CONFIGURATION,
956 			    M98090_LTEN_SHIFT,
957 			    lten_mux_text);
958 
959 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum,
960 			    M98090_REG_IO_CONFIGURATION,
961 			    M98090_LTEN_SHIFT,
962 			    lten_mux_text);
963 
964 static const struct snd_kcontrol_new max98090_ltenl_mux =
965 	SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum);
966 
967 static const struct snd_kcontrol_new max98090_ltenr_mux =
968 	SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum);
969 
970 static const char *lben_mux_text[] = { "Normal", "Loopback" };
971 
972 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum,
973 			    M98090_REG_IO_CONFIGURATION,
974 			    M98090_LBEN_SHIFT,
975 			    lben_mux_text);
976 
977 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum,
978 			    M98090_REG_IO_CONFIGURATION,
979 			    M98090_LBEN_SHIFT,
980 			    lben_mux_text);
981 
982 static const struct snd_kcontrol_new max98090_lbenl_mux =
983 	SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum);
984 
985 static const struct snd_kcontrol_new max98090_lbenr_mux =
986 	SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum);
987 
988 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" };
989 
990 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" };
991 
992 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum,
993 			    M98090_REG_ADC_SIDETONE,
994 			    M98090_DSTSL_SHIFT,
995 			    stenl_mux_text);
996 
997 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum,
998 			    M98090_REG_ADC_SIDETONE,
999 			    M98090_DSTSR_SHIFT,
1000 			    stenr_mux_text);
1001 
1002 static const struct snd_kcontrol_new max98090_stenl_mux =
1003 	SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum);
1004 
1005 static const struct snd_kcontrol_new max98090_stenr_mux =
1006 	SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum);
1007 
1008 /* Left speaker mixer switch */
1009 static const struct
1010 	snd_kcontrol_new max98090_left_speaker_mixer_controls[] = {
1011 	SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
1012 		M98090_MIXSPL_DACL_SHIFT, 1, 0),
1013 	SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
1014 		M98090_MIXSPL_DACR_SHIFT, 1, 0),
1015 	SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
1016 		M98090_MIXSPL_LINEA_SHIFT, 1, 0),
1017 	SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
1018 		M98090_MIXSPL_LINEB_SHIFT, 1, 0),
1019 	SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
1020 		M98090_MIXSPL_MIC1_SHIFT, 1, 0),
1021 	SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
1022 		M98090_MIXSPL_MIC2_SHIFT, 1, 0),
1023 };
1024 
1025 /* Right speaker mixer switch */
1026 static const struct
1027 	snd_kcontrol_new max98090_right_speaker_mixer_controls[] = {
1028 	SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1029 		M98090_MIXSPR_DACL_SHIFT, 1, 0),
1030 	SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
1031 		M98090_MIXSPR_DACR_SHIFT, 1, 0),
1032 	SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
1033 		M98090_MIXSPR_LINEA_SHIFT, 1, 0),
1034 	SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
1035 		M98090_MIXSPR_LINEB_SHIFT, 1, 0),
1036 	SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
1037 		M98090_MIXSPR_MIC1_SHIFT, 1, 0),
1038 	SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
1039 		M98090_MIXSPR_MIC2_SHIFT, 1, 0),
1040 };
1041 
1042 /* Left headphone mixer switch */
1043 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = {
1044 	SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
1045 		M98090_MIXHPL_DACL_SHIFT, 1, 0),
1046 	SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
1047 		M98090_MIXHPL_DACR_SHIFT, 1, 0),
1048 	SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
1049 		M98090_MIXHPL_LINEA_SHIFT, 1, 0),
1050 	SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
1051 		M98090_MIXHPL_LINEB_SHIFT, 1, 0),
1052 	SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
1053 		M98090_MIXHPL_MIC1_SHIFT, 1, 0),
1054 	SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
1055 		M98090_MIXHPL_MIC2_SHIFT, 1, 0),
1056 };
1057 
1058 /* Right headphone mixer switch */
1059 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = {
1060 	SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1061 		M98090_MIXHPR_DACL_SHIFT, 1, 0),
1062 	SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
1063 		M98090_MIXHPR_DACR_SHIFT, 1, 0),
1064 	SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
1065 		M98090_MIXHPR_LINEA_SHIFT, 1, 0),
1066 	SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
1067 		M98090_MIXHPR_LINEB_SHIFT, 1, 0),
1068 	SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
1069 		M98090_MIXHPR_MIC1_SHIFT, 1, 0),
1070 	SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1071 		M98090_MIXHPR_MIC2_SHIFT, 1, 0),
1072 };
1073 
1074 /* Left receiver mixer switch */
1075 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = {
1076 	SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1077 		M98090_MIXRCVL_DACL_SHIFT, 1, 0),
1078 	SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1079 		M98090_MIXRCVL_DACR_SHIFT, 1, 0),
1080 	SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1081 		M98090_MIXRCVL_LINEA_SHIFT, 1, 0),
1082 	SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1083 		M98090_MIXRCVL_LINEB_SHIFT, 1, 0),
1084 	SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1085 		M98090_MIXRCVL_MIC1_SHIFT, 1, 0),
1086 	SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1087 		M98090_MIXRCVL_MIC2_SHIFT, 1, 0),
1088 };
1089 
1090 /* Right receiver mixer switch */
1091 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = {
1092 	SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1093 		M98090_MIXRCVR_DACL_SHIFT, 1, 0),
1094 	SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1095 		M98090_MIXRCVR_DACR_SHIFT, 1, 0),
1096 	SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1097 		M98090_MIXRCVR_LINEA_SHIFT, 1, 0),
1098 	SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1099 		M98090_MIXRCVR_LINEB_SHIFT, 1, 0),
1100 	SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1101 		M98090_MIXRCVR_MIC1_SHIFT, 1, 0),
1102 	SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1103 		M98090_MIXRCVR_MIC2_SHIFT, 1, 0),
1104 };
1105 
1106 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" };
1107 
1108 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum,
1109 			    M98090_REG_LOUTR_MIXER,
1110 			    M98090_LINMOD_SHIFT,
1111 			    linmod_mux_text);
1112 
1113 static const struct snd_kcontrol_new max98090_linmod_mux =
1114 	SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum);
1115 
1116 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" };
1117 
1118 /*
1119  * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable
1120  */
1121 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum,
1122 			    M98090_REG_HP_CONTROL,
1123 			    M98090_MIXHPLSEL_SHIFT,
1124 			    mixhpsel_mux_text);
1125 
1126 static const struct snd_kcontrol_new max98090_mixhplsel_mux =
1127 	SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum);
1128 
1129 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum,
1130 			    M98090_REG_HP_CONTROL,
1131 			    M98090_MIXHPRSEL_SHIFT,
1132 			    mixhpsel_mux_text);
1133 
1134 static const struct snd_kcontrol_new max98090_mixhprsel_mux =
1135 	SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum);
1136 
1137 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = {
1138 	SND_SOC_DAPM_INPUT("MIC1"),
1139 	SND_SOC_DAPM_INPUT("MIC2"),
1140 	SND_SOC_DAPM_INPUT("DMICL"),
1141 	SND_SOC_DAPM_INPUT("DMICR"),
1142 	SND_SOC_DAPM_INPUT("IN1"),
1143 	SND_SOC_DAPM_INPUT("IN2"),
1144 	SND_SOC_DAPM_INPUT("IN3"),
1145 	SND_SOC_DAPM_INPUT("IN4"),
1146 	SND_SOC_DAPM_INPUT("IN5"),
1147 	SND_SOC_DAPM_INPUT("IN6"),
1148 	SND_SOC_DAPM_INPUT("IN12"),
1149 	SND_SOC_DAPM_INPUT("IN34"),
1150 	SND_SOC_DAPM_INPUT("IN56"),
1151 
1152 	SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE,
1153 		M98090_MBEN_SHIFT, 0, NULL, 0),
1154 	SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN,
1155 		M98090_SHDNN_SHIFT, 0, NULL, 0),
1156 	SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION,
1157 		M98090_SDIEN_SHIFT, 0, NULL, 0),
1158 	SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION,
1159 		M98090_SDOEN_SHIFT, 0, NULL, 0),
1160 	SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1161 		 M98090_DIGMICL_SHIFT, 0, NULL, 0),
1162 	SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1163 		 M98090_DIGMICR_SHIFT, 0, NULL, 0),
1164 	SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG,
1165 		M98090_AHPF_SHIFT, 0, NULL, 0),
1166 
1167 /*
1168  * Note: Sysclk and misc power supplies are taken care of by SHDN
1169  */
1170 
1171 	SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM,
1172 		0, 0, &max98090_mic1_mux),
1173 
1174 	SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM,
1175 		0, 0, &max98090_mic2_mux),
1176 
1177 	SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux),
1178 
1179 	SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL,
1180 		M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1181 		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1182 
1183 	SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL,
1184 		M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event,
1185 		SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
1186 
1187 	SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0,
1188 		&max98090_linea_mixer_controls[0],
1189 		ARRAY_SIZE(max98090_linea_mixer_controls)),
1190 
1191 	SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0,
1192 		&max98090_lineb_mixer_controls[0],
1193 		ARRAY_SIZE(max98090_lineb_mixer_controls)),
1194 
1195 	SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE,
1196 		M98090_LINEAEN_SHIFT, 0, NULL, 0),
1197 	SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE,
1198 		M98090_LINEBEN_SHIFT, 0, NULL, 0),
1199 
1200 	SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
1201 		&max98090_left_adc_mixer_controls[0],
1202 		ARRAY_SIZE(max98090_left_adc_mixer_controls)),
1203 
1204 	SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
1205 		&max98090_right_adc_mixer_controls[0],
1206 		ARRAY_SIZE(max98090_right_adc_mixer_controls)),
1207 
1208 	SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE,
1209 		M98090_ADLEN_SHIFT, 0),
1210 	SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1211 		M98090_ADREN_SHIFT, 0),
1212 
1213 	SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0,
1214 		SND_SOC_NOPM, 0, 0),
1215 	SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1,
1216 		SND_SOC_NOPM, 0, 0),
1217 
1218 	SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM,
1219 		0, 0, &max98090_lbenl_mux),
1220 
1221 	SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM,
1222 		0, 0, &max98090_lbenr_mux),
1223 
1224 	SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM,
1225 		0, 0, &max98090_ltenl_mux),
1226 
1227 	SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM,
1228 		0, 0, &max98090_ltenr_mux),
1229 
1230 	SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM,
1231 		0, 0, &max98090_stenl_mux),
1232 
1233 	SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM,
1234 		0, 0, &max98090_stenr_mux),
1235 
1236 	SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
1237 	SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0),
1238 
1239 	SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE,
1240 		M98090_DALEN_SHIFT, 0),
1241 	SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE,
1242 		M98090_DAREN_SHIFT, 0),
1243 
1244 	SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
1245 		&max98090_left_hp_mixer_controls[0],
1246 		ARRAY_SIZE(max98090_left_hp_mixer_controls)),
1247 
1248 	SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
1249 		&max98090_right_hp_mixer_controls[0],
1250 		ARRAY_SIZE(max98090_right_hp_mixer_controls)),
1251 
1252 	SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0,
1253 		&max98090_left_speaker_mixer_controls[0],
1254 		ARRAY_SIZE(max98090_left_speaker_mixer_controls)),
1255 
1256 	SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0,
1257 		&max98090_right_speaker_mixer_controls[0],
1258 		ARRAY_SIZE(max98090_right_speaker_mixer_controls)),
1259 
1260 	SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0,
1261 		&max98090_left_rcv_mixer_controls[0],
1262 		ARRAY_SIZE(max98090_left_rcv_mixer_controls)),
1263 
1264 	SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0,
1265 		&max98090_right_rcv_mixer_controls[0],
1266 		ARRAY_SIZE(max98090_right_rcv_mixer_controls)),
1267 
1268 	SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER,
1269 		M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux),
1270 
1271 	SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL,
1272 		M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux),
1273 
1274 	SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL,
1275 		M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux),
1276 
1277 	SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1278 		M98090_HPLEN_SHIFT, 0, NULL, 0),
1279 	SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1280 		M98090_HPREN_SHIFT, 0, NULL, 0),
1281 
1282 	SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1283 		M98090_SPLEN_SHIFT, 0, NULL, 0),
1284 	SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1285 		M98090_SPREN_SHIFT, 0, NULL, 0),
1286 
1287 	SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1288 		M98090_RCVLEN_SHIFT, 0, NULL, 0),
1289 	SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1290 		M98090_RCVREN_SHIFT, 0, NULL, 0),
1291 
1292 	SND_SOC_DAPM_OUTPUT("HPL"),
1293 	SND_SOC_DAPM_OUTPUT("HPR"),
1294 	SND_SOC_DAPM_OUTPUT("SPKL"),
1295 	SND_SOC_DAPM_OUTPUT("SPKR"),
1296 	SND_SOC_DAPM_OUTPUT("RCVL"),
1297 	SND_SOC_DAPM_OUTPUT("RCVR"),
1298 };
1299 
1300 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = {
1301 	SND_SOC_DAPM_INPUT("DMIC3"),
1302 	SND_SOC_DAPM_INPUT("DMIC4"),
1303 
1304 	SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1305 		 M98090_DIGMIC3_SHIFT, 0, NULL, 0),
1306 	SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE,
1307 		 M98090_DIGMIC4_SHIFT, 0, NULL, 0),
1308 };
1309 
1310 static const struct snd_soc_dapm_route max98090_dapm_routes[] = {
1311 	{"MIC1 Input", NULL, "MIC1"},
1312 	{"MIC2 Input", NULL, "MIC2"},
1313 
1314 	{"DMICL", NULL, "DMICL_ENA"},
1315 	{"DMICL", NULL, "DMICR_ENA"},
1316 	{"DMICR", NULL, "DMICL_ENA"},
1317 	{"DMICR", NULL, "DMICR_ENA"},
1318 	{"DMICL", NULL, "AHPF"},
1319 	{"DMICR", NULL, "AHPF"},
1320 
1321 	/* MIC1 input mux */
1322 	{"MIC1 Mux", "IN12", "IN12"},
1323 	{"MIC1 Mux", "IN56", "IN56"},
1324 
1325 	/* MIC2 input mux */
1326 	{"MIC2 Mux", "IN34", "IN34"},
1327 	{"MIC2 Mux", "IN56", "IN56"},
1328 
1329 	{"MIC1 Input", NULL, "MIC1 Mux"},
1330 	{"MIC2 Input", NULL, "MIC2 Mux"},
1331 
1332 	/* Left ADC input mixer */
1333 	{"Left ADC Mixer", "IN12 Switch", "IN12"},
1334 	{"Left ADC Mixer", "IN34 Switch", "IN34"},
1335 	{"Left ADC Mixer", "IN56 Switch", "IN56"},
1336 	{"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1337 	{"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1338 	{"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1339 	{"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1340 
1341 	/* Right ADC input mixer */
1342 	{"Right ADC Mixer", "IN12 Switch", "IN12"},
1343 	{"Right ADC Mixer", "IN34 Switch", "IN34"},
1344 	{"Right ADC Mixer", "IN56 Switch", "IN56"},
1345 	{"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1346 	{"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1347 	{"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1348 	{"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1349 
1350 	/* Line A input mixer */
1351 	{"LINEA Mixer", "IN1 Switch", "IN1"},
1352 	{"LINEA Mixer", "IN3 Switch", "IN3"},
1353 	{"LINEA Mixer", "IN5 Switch", "IN5"},
1354 	{"LINEA Mixer", "IN34 Switch", "IN34"},
1355 
1356 	/* Line B input mixer */
1357 	{"LINEB Mixer", "IN2 Switch", "IN2"},
1358 	{"LINEB Mixer", "IN4 Switch", "IN4"},
1359 	{"LINEB Mixer", "IN6 Switch", "IN6"},
1360 	{"LINEB Mixer", "IN56 Switch", "IN56"},
1361 
1362 	{"LINEA Input", NULL, "LINEA Mixer"},
1363 	{"LINEB Input", NULL, "LINEB Mixer"},
1364 
1365 	/* Inputs */
1366 	{"ADCL", NULL, "Left ADC Mixer"},
1367 	{"ADCR", NULL, "Right ADC Mixer"},
1368 	{"ADCL", NULL, "SHDN"},
1369 	{"ADCR", NULL, "SHDN"},
1370 
1371 	{"DMIC Mux", "ADC", "ADCL"},
1372 	{"DMIC Mux", "ADC", "ADCR"},
1373 	{"DMIC Mux", "DMIC", "DMICL"},
1374 	{"DMIC Mux", "DMIC", "DMICR"},
1375 
1376 	{"LBENL Mux", "Normal", "DMIC Mux"},
1377 	{"LBENL Mux", "Loopback", "LTENL Mux"},
1378 	{"LBENR Mux", "Normal", "DMIC Mux"},
1379 	{"LBENR Mux", "Loopback", "LTENR Mux"},
1380 
1381 	{"AIFOUTL", NULL, "LBENL Mux"},
1382 	{"AIFOUTR", NULL, "LBENR Mux"},
1383 	{"AIFOUTL", NULL, "SHDN"},
1384 	{"AIFOUTR", NULL, "SHDN"},
1385 	{"AIFOUTL", NULL, "SDOEN"},
1386 	{"AIFOUTR", NULL, "SDOEN"},
1387 
1388 	{"LTENL Mux", "Normal", "AIFINL"},
1389 	{"LTENL Mux", "Loopthrough", "LBENL Mux"},
1390 	{"LTENR Mux", "Normal", "AIFINR"},
1391 	{"LTENR Mux", "Loopthrough", "LBENR Mux"},
1392 
1393 	{"DACL", NULL, "LTENL Mux"},
1394 	{"DACR", NULL, "LTENR Mux"},
1395 
1396 	{"STENL Mux", "Sidetone Left", "ADCL"},
1397 	{"STENL Mux", "Sidetone Left", "DMICL"},
1398 	{"STENR Mux", "Sidetone Right", "ADCR"},
1399 	{"STENR Mux", "Sidetone Right", "DMICR"},
1400 	{"DACL", NULL, "STENL Mux"},
1401 	{"DACR", NULL, "STENR Mux"},
1402 
1403 	{"AIFINL", NULL, "SHDN"},
1404 	{"AIFINR", NULL, "SHDN"},
1405 	{"AIFINL", NULL, "SDIEN"},
1406 	{"AIFINR", NULL, "SDIEN"},
1407 	{"DACL", NULL, "SHDN"},
1408 	{"DACR", NULL, "SHDN"},
1409 
1410 	/* Left headphone output mixer */
1411 	{"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1412 	{"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1413 	{"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1414 	{"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1415 	{"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1416 	{"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1417 
1418 	/* Right headphone output mixer */
1419 	{"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1420 	{"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1421 	{"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1422 	{"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1423 	{"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1424 	{"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1425 
1426 	/* Left speaker output mixer */
1427 	{"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1428 	{"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1429 	{"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1430 	{"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1431 	{"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1432 	{"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1433 
1434 	/* Right speaker output mixer */
1435 	{"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1436 	{"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1437 	{"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1438 	{"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1439 	{"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1440 	{"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1441 
1442 	/* Left Receiver output mixer */
1443 	{"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1444 	{"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1445 	{"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1446 	{"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1447 	{"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1448 	{"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1449 
1450 	/* Right Receiver output mixer */
1451 	{"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1452 	{"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1453 	{"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1454 	{"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1455 	{"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1456 	{"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1457 
1458 	{"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"},
1459 
1460 	/*
1461 	 * Disable this for lowest power if bypassing
1462 	 * the DAC with an analog signal
1463 	 */
1464 	{"HP Left Out", NULL, "DACL"},
1465 	{"HP Left Out", NULL, "MIXHPLSEL Mux"},
1466 
1467 	{"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"},
1468 
1469 	/*
1470 	 * Disable this for lowest power if bypassing
1471 	 * the DAC with an analog signal
1472 	 */
1473 	{"HP Right Out", NULL, "DACR"},
1474 	{"HP Right Out", NULL, "MIXHPRSEL Mux"},
1475 
1476 	{"SPK Left Out", NULL, "Left Speaker Mixer"},
1477 	{"SPK Right Out", NULL, "Right Speaker Mixer"},
1478 	{"RCV Left Out", NULL, "Left Receiver Mixer"},
1479 
1480 	{"LINMOD Mux", "Left and Right", "Right Receiver Mixer"},
1481 	{"LINMOD Mux", "Left Only",  "Left Receiver Mixer"},
1482 	{"RCV Right Out", NULL, "LINMOD Mux"},
1483 
1484 	{"HPL", NULL, "HP Left Out"},
1485 	{"HPR", NULL, "HP Right Out"},
1486 	{"SPKL", NULL, "SPK Left Out"},
1487 	{"SPKR", NULL, "SPK Right Out"},
1488 	{"RCVL", NULL, "RCV Left Out"},
1489 	{"RCVR", NULL, "RCV Right Out"},
1490 };
1491 
1492 static const struct snd_soc_dapm_route max98091_dapm_routes[] = {
1493 	/* DMIC inputs */
1494 	{"DMIC3", NULL, "DMIC3_ENA"},
1495 	{"DMIC4", NULL, "DMIC4_ENA"},
1496 	{"DMIC3", NULL, "AHPF"},
1497 	{"DMIC4", NULL, "AHPF"},
1498 };
1499 
1500 static int max98090_add_widgets(struct snd_soc_codec *codec)
1501 {
1502 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1503 	struct snd_soc_dapm_context *dapm = &codec->dapm;
1504 
1505 	snd_soc_add_codec_controls(codec, max98090_snd_controls,
1506 		ARRAY_SIZE(max98090_snd_controls));
1507 
1508 	if (max98090->devtype == MAX98091) {
1509 		snd_soc_add_codec_controls(codec, max98091_snd_controls,
1510 			ARRAY_SIZE(max98091_snd_controls));
1511 	}
1512 
1513 	snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets,
1514 		ARRAY_SIZE(max98090_dapm_widgets));
1515 
1516 	snd_soc_dapm_add_routes(dapm, max98090_dapm_routes,
1517 		ARRAY_SIZE(max98090_dapm_routes));
1518 
1519 	if (max98090->devtype == MAX98091) {
1520 		snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets,
1521 			ARRAY_SIZE(max98091_dapm_widgets));
1522 
1523 		snd_soc_dapm_add_routes(dapm, max98091_dapm_routes,
1524 			ARRAY_SIZE(max98091_dapm_routes));
1525 	}
1526 
1527 	return 0;
1528 }
1529 
1530 static const int pclk_rates[] = {
1531 	12000000, 12000000, 13000000, 13000000,
1532 	16000000, 16000000, 19200000, 19200000
1533 };
1534 
1535 static const int lrclk_rates[] = {
1536 	8000, 16000, 8000, 16000,
1537 	8000, 16000, 8000, 16000
1538 };
1539 
1540 static const int user_pclk_rates[] = {
1541 	13000000, 13000000, 19200000, 19200000,
1542 };
1543 
1544 static const int user_lrclk_rates[] = {
1545 	44100, 48000, 44100, 48000,
1546 };
1547 
1548 static const unsigned long long ni_value[] = {
1549 	3528, 768, 441, 8
1550 };
1551 
1552 static const unsigned long long mi_value[] = {
1553 	8125, 1625, 1500, 25
1554 };
1555 
1556 static void max98090_configure_bclk(struct snd_soc_codec *codec)
1557 {
1558 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1559 	unsigned long long ni;
1560 	int i;
1561 
1562 	if (!max98090->sysclk) {
1563 		dev_err(codec->dev, "No SYSCLK configured\n");
1564 		return;
1565 	}
1566 
1567 	if (!max98090->bclk || !max98090->lrclk) {
1568 		dev_err(codec->dev, "No audio clocks configured\n");
1569 		return;
1570 	}
1571 
1572 	/* Skip configuration when operating as slave */
1573 	if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) &
1574 		M98090_MAS_MASK)) {
1575 		return;
1576 	}
1577 
1578 	/* Check for supported PCLK to LRCLK ratios */
1579 	for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) {
1580 		if ((pclk_rates[i] == max98090->sysclk) &&
1581 			(lrclk_rates[i] == max98090->lrclk)) {
1582 			dev_dbg(codec->dev,
1583 				"Found supported PCLK to LRCLK rates 0x%x\n",
1584 				i + 0x8);
1585 
1586 			snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1587 				M98090_FREQ_MASK,
1588 				(i + 0x8) << M98090_FREQ_SHIFT);
1589 			snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1590 				M98090_USE_M1_MASK, 0);
1591 			return;
1592 		}
1593 	}
1594 
1595 	/* Check for user calculated MI and NI ratios */
1596 	for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) {
1597 		if ((user_pclk_rates[i] == max98090->sysclk) &&
1598 			(user_lrclk_rates[i] == max98090->lrclk)) {
1599 			dev_dbg(codec->dev,
1600 				"Found user supported PCLK to LRCLK rates\n");
1601 			dev_dbg(codec->dev, "i %d ni %lld mi %lld\n",
1602 				i, ni_value[i], mi_value[i]);
1603 
1604 			snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1605 				M98090_FREQ_MASK, 0);
1606 			snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1607 				M98090_USE_M1_MASK,
1608 					1 << M98090_USE_M1_SHIFT);
1609 
1610 			snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1611 				(ni_value[i] >> 8) & 0x7F);
1612 			snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB,
1613 				ni_value[i] & 0xFF);
1614 			snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB,
1615 				(mi_value[i] >> 8) & 0x7F);
1616 			snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB,
1617 				mi_value[i] & 0xFF);
1618 
1619 			return;
1620 		}
1621 	}
1622 
1623 	/*
1624 	 * Calculate based on MI = 65536 (not as good as either method above)
1625 	 */
1626 	snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1627 		M98090_FREQ_MASK, 0);
1628 	snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1629 		M98090_USE_M1_MASK, 0);
1630 
1631 	/*
1632 	 * Configure NI when operating as master
1633 	 * Note: There is a small, but significant audio quality improvement
1634 	 * by calculating ni and mi.
1635 	 */
1636 	ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1637 			* (unsigned long long int)max98090->lrclk;
1638 	do_div(ni, (unsigned long long int)max98090->sysclk);
1639 	dev_info(codec->dev, "No better method found\n");
1640 	dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni);
1641 	snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB,
1642 		(ni >> 8) & 0x7F);
1643 	snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF);
1644 }
1645 
1646 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai,
1647 				 unsigned int fmt)
1648 {
1649 	struct snd_soc_codec *codec = codec_dai->codec;
1650 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1651 	struct max98090_cdata *cdata;
1652 	u8 regval;
1653 
1654 	max98090->dai_fmt = fmt;
1655 	cdata = &max98090->dai[0];
1656 
1657 	if (fmt != cdata->fmt) {
1658 		cdata->fmt = fmt;
1659 
1660 		regval = 0;
1661 		switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1662 		case SND_SOC_DAIFMT_CBS_CFS:
1663 			/* Set to slave mode PLL - MAS mode off */
1664 			snd_soc_write(codec,
1665 				M98090_REG_CLOCK_RATIO_NI_MSB, 0x00);
1666 			snd_soc_write(codec,
1667 				M98090_REG_CLOCK_RATIO_NI_LSB, 0x00);
1668 			snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE,
1669 				M98090_USE_M1_MASK, 0);
1670 			max98090->master = false;
1671 			break;
1672 		case SND_SOC_DAIFMT_CBM_CFM:
1673 			/* Set to master mode */
1674 			if (max98090->tdm_slots == 4) {
1675 				/* TDM */
1676 				regval |= M98090_MAS_MASK |
1677 					M98090_BSEL_64;
1678 			} else if (max98090->tdm_slots == 3) {
1679 				/* TDM */
1680 				regval |= M98090_MAS_MASK |
1681 					M98090_BSEL_48;
1682 			} else {
1683 				/* Few TDM slots, or No TDM */
1684 				regval |= M98090_MAS_MASK |
1685 					M98090_BSEL_32;
1686 			}
1687 			max98090->master = true;
1688 			break;
1689 		case SND_SOC_DAIFMT_CBS_CFM:
1690 		case SND_SOC_DAIFMT_CBM_CFS:
1691 		default:
1692 			dev_err(codec->dev, "DAI clock mode unsupported");
1693 			return -EINVAL;
1694 		}
1695 		snd_soc_write(codec, M98090_REG_MASTER_MODE, regval);
1696 
1697 		regval = 0;
1698 		switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1699 		case SND_SOC_DAIFMT_I2S:
1700 			regval |= M98090_DLY_MASK;
1701 			break;
1702 		case SND_SOC_DAIFMT_LEFT_J:
1703 			break;
1704 		case SND_SOC_DAIFMT_RIGHT_J:
1705 			regval |= M98090_RJ_MASK;
1706 			break;
1707 		case SND_SOC_DAIFMT_DSP_A:
1708 			/* Not supported mode */
1709 		default:
1710 			dev_err(codec->dev, "DAI format unsupported");
1711 			return -EINVAL;
1712 		}
1713 
1714 		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1715 		case SND_SOC_DAIFMT_NB_NF:
1716 			break;
1717 		case SND_SOC_DAIFMT_NB_IF:
1718 			regval |= M98090_WCI_MASK;
1719 			break;
1720 		case SND_SOC_DAIFMT_IB_NF:
1721 			regval |= M98090_BCI_MASK;
1722 			break;
1723 		case SND_SOC_DAIFMT_IB_IF:
1724 			regval |= M98090_BCI_MASK|M98090_WCI_MASK;
1725 			break;
1726 		default:
1727 			dev_err(codec->dev, "DAI invert mode unsupported");
1728 			return -EINVAL;
1729 		}
1730 
1731 		/*
1732 		 * This accommodates an inverted logic in the MAX98090 chip
1733 		 * for Bit Clock Invert (BCI). The inverted logic is only
1734 		 * seen for the case of TDM mode. The remaining cases have
1735 		 * normal logic.
1736 		 */
1737 		if (max98090->tdm_slots > 1)
1738 			regval ^= M98090_BCI_MASK;
1739 
1740 		snd_soc_write(codec,
1741 			M98090_REG_INTERFACE_FORMAT, regval);
1742 	}
1743 
1744 	return 0;
1745 }
1746 
1747 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai,
1748 	unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1749 {
1750 	struct snd_soc_codec *codec = codec_dai->codec;
1751 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1752 	struct max98090_cdata *cdata;
1753 	cdata = &max98090->dai[0];
1754 
1755 	if (slots < 0 || slots > 4)
1756 		return -EINVAL;
1757 
1758 	max98090->tdm_slots = slots;
1759 	max98090->tdm_width = slot_width;
1760 
1761 	if (max98090->tdm_slots > 1) {
1762 		/* SLOTL SLOTR SLOTDLY */
1763 		snd_soc_write(codec, M98090_REG_TDM_FORMAT,
1764 			0 << M98090_TDM_SLOTL_SHIFT |
1765 			1 << M98090_TDM_SLOTR_SHIFT |
1766 			0 << M98090_TDM_SLOTDLY_SHIFT);
1767 
1768 		/* FSW TDM */
1769 		snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL,
1770 			M98090_TDM_MASK,
1771 			M98090_TDM_MASK);
1772 	}
1773 
1774 	/*
1775 	 * Normally advisable to set TDM first, but this permits either order
1776 	 */
1777 	cdata->fmt = 0;
1778 	max98090_dai_set_fmt(codec_dai, max98090->dai_fmt);
1779 
1780 	return 0;
1781 }
1782 
1783 static int max98090_set_bias_level(struct snd_soc_codec *codec,
1784 				   enum snd_soc_bias_level level)
1785 {
1786 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1787 	int ret;
1788 
1789 	switch (level) {
1790 	case SND_SOC_BIAS_ON:
1791 		break;
1792 
1793 	case SND_SOC_BIAS_PREPARE:
1794 		/*
1795 		 * SND_SOC_BIAS_PREPARE is called while preparing for a
1796 		 * transition to ON or away from ON. If current bias_level
1797 		 * is SND_SOC_BIAS_ON, then it is preparing for a transition
1798 		 * away from ON. Disable the clock in that case, otherwise
1799 		 * enable it.
1800 		 */
1801 		if (!IS_ERR(max98090->mclk)) {
1802 			if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
1803 				clk_disable_unprepare(max98090->mclk);
1804 			else
1805 				clk_prepare_enable(max98090->mclk);
1806 		}
1807 		break;
1808 
1809 	case SND_SOC_BIAS_STANDBY:
1810 		if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1811 			ret = regcache_sync(max98090->regmap);
1812 			if (ret != 0) {
1813 				dev_err(codec->dev,
1814 					"Failed to sync cache: %d\n", ret);
1815 				return ret;
1816 			}
1817 		}
1818 		break;
1819 
1820 	case SND_SOC_BIAS_OFF:
1821 		/* Set internal pull-up to lowest power mode */
1822 		snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
1823 			M98090_JDWK_MASK, M98090_JDWK_MASK);
1824 		regcache_mark_dirty(max98090->regmap);
1825 		break;
1826 	}
1827 	codec->dapm.bias_level = level;
1828 	return 0;
1829 }
1830 
1831 static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 };
1832 
1833 static const int comp_lrclk_rates[] = {
1834 	8000, 16000, 32000, 44100, 48000, 96000
1835 };
1836 
1837 struct dmic_table {
1838 	int pclk;
1839 	struct {
1840 		int freq;
1841 		int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */
1842 	} settings[6]; /* One for each dmic divisor. */
1843 };
1844 
1845 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1846 	{
1847 		.pclk = 11289600,
1848 		.settings = {
1849 			{ .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1850 			{ .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1851 			{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1852 			{ .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1853 			{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1854 			{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1855 		},
1856 	},
1857 	{
1858 		.pclk = 12000000,
1859 		.settings = {
1860 			{ .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1861 			{ .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1862 			{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1863 			{ .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1864 			{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1865 			{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1866 		}
1867 	},
1868 	{
1869 		.pclk = 12288000,
1870 		.settings = {
1871 			{ .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1872 			{ .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1873 			{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1874 			{ .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1875 			{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1876 			{ .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1877 		}
1878 	},
1879 	{
1880 		.pclk = 13000000,
1881 		.settings = {
1882 			{ .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1883 			{ .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1884 			{ .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1885 			{ .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1886 			{ .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1887 			{ .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1888 		}
1889 	},
1890 	{
1891 		.pclk = 19200000,
1892 		.settings = {
1893 			{ .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
1894 			{ .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
1895 			{ .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1896 			{ .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
1897 			{ .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
1898 			{ .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1899 		}
1900 	},
1901 };
1902 
1903 static int max98090_find_divisor(int target_freq, int pclk)
1904 {
1905 	int current_diff = INT_MAX;
1906 	int test_diff = INT_MAX;
1907 	int divisor_index = 0;
1908 	int i;
1909 
1910 	for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) {
1911 		test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
1912 		if (test_diff < current_diff) {
1913 			current_diff = test_diff;
1914 			divisor_index = i;
1915 		}
1916 	}
1917 
1918 	return divisor_index;
1919 }
1920 
1921 static int max98090_find_closest_pclk(int pclk)
1922 {
1923 	int m1;
1924 	int m2;
1925 	int i;
1926 
1927 	for (i = 0; i < ARRAY_SIZE(dmic_table); i++) {
1928 		if (pclk == dmic_table[i].pclk)
1929 			return i;
1930 		if (pclk < dmic_table[i].pclk) {
1931 			if (i == 0)
1932 				return i;
1933 			m1 = pclk - dmic_table[i-1].pclk;
1934 			m2 = dmic_table[i].pclk - pclk;
1935 			if (m1 < m2)
1936 				return i - 1;
1937 			else
1938 				return i;
1939 		}
1940 	}
1941 
1942 	return -EINVAL;
1943 }
1944 
1945 static int max98090_configure_dmic(struct max98090_priv *max98090,
1946 				   int target_dmic_clk, int pclk, int fs)
1947 {
1948 	int micclk_index;
1949 	int pclk_index;
1950 	int dmic_freq;
1951 	int dmic_comp;
1952 	int i;
1953 
1954 	pclk_index = max98090_find_closest_pclk(pclk);
1955 	if (pclk_index < 0)
1956 		return pclk_index;
1957 
1958 	micclk_index = max98090_find_divisor(target_dmic_clk, pclk);
1959 
1960 	for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1961 		if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2)
1962 			break;
1963 	}
1964 
1965 	dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq;
1966 	dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i];
1967 
1968 	regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
1969 			   M98090_MICCLK_MASK,
1970 			   micclk_index << M98090_MICCLK_SHIFT);
1971 
1972 	regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
1973 			   M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK,
1974 			   dmic_comp << M98090_DMIC_COMP_SHIFT |
1975 			   dmic_freq << M98090_DMIC_FREQ_SHIFT);
1976 
1977 	return 0;
1978 }
1979 
1980 static int max98090_dai_hw_params(struct snd_pcm_substream *substream,
1981 				   struct snd_pcm_hw_params *params,
1982 				   struct snd_soc_dai *dai)
1983 {
1984 	struct snd_soc_codec *codec = dai->codec;
1985 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
1986 	struct max98090_cdata *cdata;
1987 
1988 	cdata = &max98090->dai[0];
1989 	max98090->bclk = snd_soc_params_to_bclk(params);
1990 	if (params_channels(params) == 1)
1991 		max98090->bclk *= 2;
1992 
1993 	max98090->lrclk = params_rate(params);
1994 
1995 	switch (params_width(params)) {
1996 	case 16:
1997 		snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT,
1998 			M98090_WS_MASK, 0);
1999 		break;
2000 	default:
2001 		return -EINVAL;
2002 	}
2003 
2004 	if (max98090->master)
2005 		max98090_configure_bclk(codec);
2006 
2007 	cdata->rate = max98090->lrclk;
2008 
2009 	/* Update filter mode */
2010 	if (max98090->lrclk < 24000)
2011 		snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
2012 			M98090_MODE_MASK, 0);
2013 	else
2014 		snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
2015 			M98090_MODE_MASK, M98090_MODE_MASK);
2016 
2017 	/* Update sample rate mode */
2018 	if (max98090->lrclk < 50000)
2019 		snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
2020 			M98090_DHF_MASK, 0);
2021 	else
2022 		snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG,
2023 			M98090_DHF_MASK, M98090_DHF_MASK);
2024 
2025 	max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
2026 				max98090->lrclk);
2027 
2028 	return 0;
2029 }
2030 
2031 /*
2032  * PLL / Sysclk
2033  */
2034 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai,
2035 				   int clk_id, unsigned int freq, int dir)
2036 {
2037 	struct snd_soc_codec *codec = dai->codec;
2038 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2039 
2040 	/* Requested clock frequency is already setup */
2041 	if (freq == max98090->sysclk)
2042 		return 0;
2043 
2044 	if (!IS_ERR(max98090->mclk)) {
2045 		freq = clk_round_rate(max98090->mclk, freq);
2046 		clk_set_rate(max98090->mclk, freq);
2047 	}
2048 
2049 	/* Setup clocks for slave mode, and using the PLL
2050 	 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz)
2051 	 *		 0x02 (when master clk is 20MHz to 40MHz)..
2052 	 *		 0x03 (when master clk is 40MHz to 60MHz)..
2053 	 */
2054 	if ((freq >= 10000000) && (freq <= 20000000)) {
2055 		snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2056 			M98090_PSCLK_DIV1);
2057 		max98090->pclk = freq;
2058 	} else if ((freq > 20000000) && (freq <= 40000000)) {
2059 		snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2060 			M98090_PSCLK_DIV2);
2061 		max98090->pclk = freq >> 1;
2062 	} else if ((freq > 40000000) && (freq <= 60000000)) {
2063 		snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK,
2064 			M98090_PSCLK_DIV4);
2065 		max98090->pclk = freq >> 2;
2066 	} else {
2067 		dev_err(codec->dev, "Invalid master clock frequency\n");
2068 		return -EINVAL;
2069 	}
2070 
2071 	max98090->sysclk = freq;
2072 
2073 	return 0;
2074 }
2075 
2076 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute)
2077 {
2078 	struct snd_soc_codec *codec = codec_dai->codec;
2079 	int regval;
2080 
2081 	regval = mute ? M98090_DVM_MASK : 0;
2082 	snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL,
2083 		M98090_DVM_MASK, regval);
2084 
2085 	return 0;
2086 }
2087 
2088 static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd,
2089 				struct snd_soc_dai *dai)
2090 {
2091 	struct snd_soc_codec *codec = dai->codec;
2092 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2093 
2094 	switch (cmd) {
2095 	case SNDRV_PCM_TRIGGER_START:
2096 	case SNDRV_PCM_TRIGGER_RESUME:
2097 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2098 		if (!max98090->master && dai->active == 1)
2099 			queue_delayed_work(system_power_efficient_wq,
2100 					   &max98090->pll_det_enable_work,
2101 					   msecs_to_jiffies(10));
2102 		break;
2103 	case SNDRV_PCM_TRIGGER_STOP:
2104 	case SNDRV_PCM_TRIGGER_SUSPEND:
2105 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2106 		if (!max98090->master && dai->active == 1)
2107 			schedule_work(&max98090->pll_det_disable_work);
2108 		break;
2109 	default:
2110 		break;
2111 	}
2112 
2113 	return 0;
2114 }
2115 
2116 static void max98090_pll_det_enable_work(struct work_struct *work)
2117 {
2118 	struct max98090_priv *max98090 =
2119 		container_of(work, struct max98090_priv,
2120 			     pll_det_enable_work.work);
2121 	struct snd_soc_codec *codec = max98090->codec;
2122 	unsigned int status, mask;
2123 
2124 	/*
2125 	 * Clear status register in order to clear possibly already occurred
2126 	 * PLL unlock. If PLL hasn't still locked, the status will be set
2127 	 * again and PLL unlock interrupt will occur.
2128 	 * Note this will clear all status bits
2129 	 */
2130 	regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2131 
2132 	/*
2133 	 * Queue jack work in case jack state has just changed but handler
2134 	 * hasn't run yet
2135 	 */
2136 	regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2137 	status &= mask;
2138 	if (status & M98090_JDET_MASK)
2139 		queue_delayed_work(system_power_efficient_wq,
2140 				   &max98090->jack_work,
2141 				   msecs_to_jiffies(100));
2142 
2143 	/* Enable PLL unlock interrupt */
2144 	snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2145 			    M98090_IULK_MASK,
2146 			    1 << M98090_IULK_SHIFT);
2147 }
2148 
2149 static void max98090_pll_det_disable_work(struct work_struct *work)
2150 {
2151 	struct max98090_priv *max98090 =
2152 		container_of(work, struct max98090_priv, pll_det_disable_work);
2153 	struct snd_soc_codec *codec = max98090->codec;
2154 
2155 	cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2156 
2157 	/* Disable PLL unlock interrupt */
2158 	snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2159 			    M98090_IULK_MASK, 0);
2160 }
2161 
2162 static void max98090_pll_work(struct work_struct *work)
2163 {
2164 	struct max98090_priv *max98090 =
2165 		container_of(work, struct max98090_priv, pll_work);
2166 	struct snd_soc_codec *codec = max98090->codec;
2167 
2168 	if (!snd_soc_codec_is_active(codec))
2169 		return;
2170 
2171 	dev_info(codec->dev, "PLL unlocked\n");
2172 
2173 	/* Toggle shutdown OFF then ON */
2174 	snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2175 			    M98090_SHDNN_MASK, 0);
2176 	msleep(10);
2177 	snd_soc_update_bits(codec, M98090_REG_DEVICE_SHUTDOWN,
2178 			    M98090_SHDNN_MASK, M98090_SHDNN_MASK);
2179 
2180 	/* Give PLL time to lock */
2181 	msleep(10);
2182 }
2183 
2184 static void max98090_jack_work(struct work_struct *work)
2185 {
2186 	struct max98090_priv *max98090 = container_of(work,
2187 		struct max98090_priv,
2188 		jack_work.work);
2189 	struct snd_soc_codec *codec = max98090->codec;
2190 	struct snd_soc_dapm_context *dapm = &codec->dapm;
2191 	int status = 0;
2192 	int reg;
2193 
2194 	/* Read a second time */
2195 	if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
2196 
2197 		/* Strong pull up allows mic detection */
2198 		snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
2199 			M98090_JDWK_MASK, 0);
2200 
2201 		msleep(50);
2202 
2203 		reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2204 
2205 		/* Weak pull up allows only insertion detection */
2206 		snd_soc_update_bits(codec, M98090_REG_JACK_DETECT,
2207 			M98090_JDWK_MASK, M98090_JDWK_MASK);
2208 	} else {
2209 		reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2210 	}
2211 
2212 	reg = snd_soc_read(codec, M98090_REG_JACK_STATUS);
2213 
2214 	switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) {
2215 		case M98090_LSNS_MASK | M98090_JKSNS_MASK:
2216 			dev_dbg(codec->dev, "No Headset Detected\n");
2217 
2218 			max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2219 
2220 			status |= 0;
2221 
2222 			break;
2223 
2224 		case 0:
2225 			if (max98090->jack_state ==
2226 				M98090_JACK_STATE_HEADSET) {
2227 
2228 				dev_dbg(codec->dev,
2229 					"Headset Button Down Detected\n");
2230 
2231 				/*
2232 				 * max98090_headset_button_event(codec)
2233 				 * could be defined, then called here.
2234 				 */
2235 
2236 				status |= SND_JACK_HEADSET;
2237 				status |= SND_JACK_BTN_0;
2238 
2239 				break;
2240 			}
2241 
2242 			/* Line is reported as Headphone */
2243 			/* Nokia Headset is reported as Headphone */
2244 			/* Mono Headphone is reported as Headphone */
2245 			dev_dbg(codec->dev, "Headphone Detected\n");
2246 
2247 			max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2248 
2249 			status |= SND_JACK_HEADPHONE;
2250 
2251 			break;
2252 
2253 		case M98090_JKSNS_MASK:
2254 			dev_dbg(codec->dev, "Headset Detected\n");
2255 
2256 			max98090->jack_state = M98090_JACK_STATE_HEADSET;
2257 
2258 			status |= SND_JACK_HEADSET;
2259 
2260 			break;
2261 
2262 		default:
2263 			dev_dbg(codec->dev, "Unrecognized Jack Status\n");
2264 			break;
2265 	}
2266 
2267 	snd_soc_jack_report(max98090->jack, status,
2268 			    SND_JACK_HEADSET | SND_JACK_BTN_0);
2269 
2270 	snd_soc_dapm_sync(dapm);
2271 }
2272 
2273 static irqreturn_t max98090_interrupt(int irq, void *data)
2274 {
2275 	struct max98090_priv *max98090 = data;
2276 	struct snd_soc_codec *codec = max98090->codec;
2277 	int ret;
2278 	unsigned int mask;
2279 	unsigned int active;
2280 
2281 	/* Treat interrupt before codec is initialized as spurious */
2282 	if (codec == NULL)
2283 		return IRQ_NONE;
2284 
2285 	dev_dbg(codec->dev, "***** max98090_interrupt *****\n");
2286 
2287 	ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2288 
2289 	if (ret != 0) {
2290 		dev_err(codec->dev,
2291 			"failed to read M98090_REG_INTERRUPT_S: %d\n",
2292 			ret);
2293 		return IRQ_NONE;
2294 	}
2295 
2296 	ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2297 
2298 	if (ret != 0) {
2299 		dev_err(codec->dev,
2300 			"failed to read M98090_REG_DEVICE_STATUS: %d\n",
2301 			ret);
2302 		return IRQ_NONE;
2303 	}
2304 
2305 	dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2306 		active, mask, active & mask);
2307 
2308 	active &= mask;
2309 
2310 	if (!active)
2311 		return IRQ_NONE;
2312 
2313 	if (active & M98090_CLD_MASK)
2314 		dev_err(codec->dev, "M98090_CLD_MASK\n");
2315 
2316 	if (active & M98090_SLD_MASK)
2317 		dev_dbg(codec->dev, "M98090_SLD_MASK\n");
2318 
2319 	if (active & M98090_ULK_MASK) {
2320 		dev_dbg(codec->dev, "M98090_ULK_MASK\n");
2321 		schedule_work(&max98090->pll_work);
2322 	}
2323 
2324 	if (active & M98090_JDET_MASK) {
2325 		dev_dbg(codec->dev, "M98090_JDET_MASK\n");
2326 
2327 		pm_wakeup_event(codec->dev, 100);
2328 
2329 		queue_delayed_work(system_power_efficient_wq,
2330 				   &max98090->jack_work,
2331 				   msecs_to_jiffies(100));
2332 	}
2333 
2334 	if (active & M98090_DRCACT_MASK)
2335 		dev_dbg(codec->dev, "M98090_DRCACT_MASK\n");
2336 
2337 	if (active & M98090_DRCCLP_MASK)
2338 		dev_err(codec->dev, "M98090_DRCCLP_MASK\n");
2339 
2340 	return IRQ_HANDLED;
2341 }
2342 
2343 /**
2344  * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2345  *
2346  * @codec:  MAX98090 codec
2347  * @jack:   jack to report detection events on
2348  *
2349  * Enable microphone detection via IRQ on the MAX98090.  If GPIOs are
2350  * being used to bring out signals to the processor then only platform
2351  * data configuration is needed for MAX98090 and processor GPIOs should
2352  * be configured using snd_soc_jack_add_gpios() instead.
2353  *
2354  * If no jack is supplied detection will be disabled.
2355  */
2356 int max98090_mic_detect(struct snd_soc_codec *codec,
2357 	struct snd_soc_jack *jack)
2358 {
2359 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2360 
2361 	dev_dbg(codec->dev, "max98090_mic_detect\n");
2362 
2363 	max98090->jack = jack;
2364 	if (jack) {
2365 		snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2366 			M98090_IJDET_MASK,
2367 			1 << M98090_IJDET_SHIFT);
2368 	} else {
2369 		snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S,
2370 			M98090_IJDET_MASK,
2371 			0);
2372 	}
2373 
2374 	/* Send an initial empty report */
2375 	snd_soc_jack_report(max98090->jack, 0,
2376 			    SND_JACK_HEADSET | SND_JACK_BTN_0);
2377 
2378 	queue_delayed_work(system_power_efficient_wq,
2379 			   &max98090->jack_work,
2380 			   msecs_to_jiffies(100));
2381 
2382 	return 0;
2383 }
2384 EXPORT_SYMBOL_GPL(max98090_mic_detect);
2385 
2386 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000
2387 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
2388 
2389 static struct snd_soc_dai_ops max98090_dai_ops = {
2390 	.set_sysclk = max98090_dai_set_sysclk,
2391 	.set_fmt = max98090_dai_set_fmt,
2392 	.set_tdm_slot = max98090_set_tdm_slot,
2393 	.hw_params = max98090_dai_hw_params,
2394 	.digital_mute = max98090_dai_digital_mute,
2395 	.trigger = max98090_dai_trigger,
2396 };
2397 
2398 static struct snd_soc_dai_driver max98090_dai[] = {
2399 {
2400 	.name = "HiFi",
2401 	.playback = {
2402 		.stream_name = "HiFi Playback",
2403 		.channels_min = 2,
2404 		.channels_max = 2,
2405 		.rates = MAX98090_RATES,
2406 		.formats = MAX98090_FORMATS,
2407 	},
2408 	.capture = {
2409 		.stream_name = "HiFi Capture",
2410 		.channels_min = 1,
2411 		.channels_max = 2,
2412 		.rates = MAX98090_RATES,
2413 		.formats = MAX98090_FORMATS,
2414 	},
2415 	 .ops = &max98090_dai_ops,
2416 }
2417 };
2418 
2419 static int max98090_probe(struct snd_soc_codec *codec)
2420 {
2421 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2422 	struct max98090_cdata *cdata;
2423 	enum max98090_type devtype;
2424 	int ret = 0;
2425 
2426 	dev_dbg(codec->dev, "max98090_probe\n");
2427 
2428 	max98090->mclk = devm_clk_get(codec->dev, "mclk");
2429 	if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
2430 		return -EPROBE_DEFER;
2431 
2432 	max98090->codec = codec;
2433 
2434 	/* Reset the codec, the DSP core, and disable all interrupts */
2435 	max98090_reset(max98090);
2436 
2437 	/* Initialize private data */
2438 
2439 	max98090->sysclk = (unsigned)-1;
2440 	max98090->pclk = (unsigned)-1;
2441 	max98090->master = false;
2442 
2443 	cdata = &max98090->dai[0];
2444 	cdata->rate = (unsigned)-1;
2445 	cdata->fmt  = (unsigned)-1;
2446 
2447 	max98090->lin_state = 0;
2448 	max98090->pa1en = 0;
2449 	max98090->pa2en = 0;
2450 
2451 	ret = snd_soc_read(codec, M98090_REG_REVISION_ID);
2452 	if (ret < 0) {
2453 		dev_err(codec->dev, "Failed to read device revision: %d\n",
2454 			ret);
2455 		goto err_access;
2456 	}
2457 
2458 	if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) {
2459 		devtype = MAX98090;
2460 		dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret);
2461 	} else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) {
2462 		devtype = MAX98091;
2463 		dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret);
2464 	} else {
2465 		devtype = MAX98090;
2466 		dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret);
2467 	}
2468 
2469 	if (max98090->devtype != devtype) {
2470 		dev_warn(codec->dev, "Mismatch in DT specified CODEC type.\n");
2471 		max98090->devtype = devtype;
2472 	}
2473 
2474 	max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2475 
2476 	INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2477 	INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
2478 			  max98090_pll_det_enable_work);
2479 	INIT_WORK(&max98090->pll_det_disable_work,
2480 		  max98090_pll_det_disable_work);
2481 	INIT_WORK(&max98090->pll_work, max98090_pll_work);
2482 
2483 	/* Enable jack detection */
2484 	snd_soc_write(codec, M98090_REG_JACK_DETECT,
2485 		M98090_JDETEN_MASK | M98090_JDEB_25MS);
2486 
2487 	/*
2488 	 * Clear any old interrupts.
2489 	 * An old interrupt ocurring prior to installing the ISR
2490 	 * can keep a new interrupt from generating a trigger.
2491 	 */
2492 	snd_soc_read(codec, M98090_REG_DEVICE_STATUS);
2493 
2494 	/* High Performance is default */
2495 	snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2496 		M98090_DACHP_MASK,
2497 		1 << M98090_DACHP_SHIFT);
2498 	snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL,
2499 		M98090_PERFMODE_MASK,
2500 		0 << M98090_PERFMODE_SHIFT);
2501 	snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL,
2502 		M98090_ADCHP_MASK,
2503 		1 << M98090_ADCHP_SHIFT);
2504 
2505 	/* Turn on VCM bandgap reference */
2506 	snd_soc_write(codec, M98090_REG_BIAS_CONTROL,
2507 		M98090_VCM_MODE_MASK);
2508 
2509 	snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE,
2510 		M98090_MBVSEL_MASK, M98090_MBVSEL_2V8);
2511 
2512 	max98090_add_widgets(codec);
2513 
2514 err_access:
2515 	return ret;
2516 }
2517 
2518 static int max98090_remove(struct snd_soc_codec *codec)
2519 {
2520 	struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec);
2521 
2522 	cancel_delayed_work_sync(&max98090->jack_work);
2523 	cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2524 	cancel_work_sync(&max98090->pll_det_disable_work);
2525 	cancel_work_sync(&max98090->pll_work);
2526 	max98090->codec = NULL;
2527 
2528 	return 0;
2529 }
2530 
2531 static struct snd_soc_codec_driver soc_codec_dev_max98090 = {
2532 	.probe   = max98090_probe,
2533 	.remove  = max98090_remove,
2534 	.set_bias_level = max98090_set_bias_level,
2535 };
2536 
2537 static const struct regmap_config max98090_regmap = {
2538 	.reg_bits = 8,
2539 	.val_bits = 8,
2540 
2541 	.max_register = MAX98090_MAX_REGISTER,
2542 	.reg_defaults = max98090_reg,
2543 	.num_reg_defaults = ARRAY_SIZE(max98090_reg),
2544 	.volatile_reg = max98090_volatile_register,
2545 	.readable_reg = max98090_readable_register,
2546 	.cache_type = REGCACHE_RBTREE,
2547 };
2548 
2549 static int max98090_i2c_probe(struct i2c_client *i2c,
2550 				 const struct i2c_device_id *i2c_id)
2551 {
2552 	struct max98090_priv *max98090;
2553 	const struct acpi_device_id *acpi_id;
2554 	kernel_ulong_t driver_data = 0;
2555 	int ret;
2556 
2557 	pr_debug("max98090_i2c_probe\n");
2558 
2559 	max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2560 		GFP_KERNEL);
2561 	if (max98090 == NULL)
2562 		return -ENOMEM;
2563 
2564 	if (ACPI_HANDLE(&i2c->dev)) {
2565 		acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table,
2566 					    &i2c->dev);
2567 		if (!acpi_id) {
2568 			dev_err(&i2c->dev, "No driver data\n");
2569 			return -EINVAL;
2570 		}
2571 		driver_data = acpi_id->driver_data;
2572 	} else if (i2c_id) {
2573 		driver_data = i2c_id->driver_data;
2574 	}
2575 
2576 	max98090->devtype = driver_data;
2577 	i2c_set_clientdata(i2c, max98090);
2578 	max98090->pdata = i2c->dev.platform_data;
2579 
2580 	ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
2581 				   &max98090->dmic_freq);
2582 	if (ret < 0)
2583 		max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
2584 
2585 	max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2586 	if (IS_ERR(max98090->regmap)) {
2587 		ret = PTR_ERR(max98090->regmap);
2588 		dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2589 		goto err_enable;
2590 	}
2591 
2592 	ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2593 		max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2594 		"max98090_interrupt", max98090);
2595 	if (ret < 0) {
2596 		dev_err(&i2c->dev, "request_irq failed: %d\n",
2597 			ret);
2598 		return ret;
2599 	}
2600 
2601 	ret = snd_soc_register_codec(&i2c->dev,
2602 			&soc_codec_dev_max98090, max98090_dai,
2603 			ARRAY_SIZE(max98090_dai));
2604 err_enable:
2605 	return ret;
2606 }
2607 
2608 static int max98090_i2c_remove(struct i2c_client *client)
2609 {
2610 	snd_soc_unregister_codec(&client->dev);
2611 	return 0;
2612 }
2613 
2614 #ifdef CONFIG_PM
2615 static int max98090_runtime_resume(struct device *dev)
2616 {
2617 	struct max98090_priv *max98090 = dev_get_drvdata(dev);
2618 
2619 	regcache_cache_only(max98090->regmap, false);
2620 
2621 	max98090_reset(max98090);
2622 
2623 	regcache_sync(max98090->regmap);
2624 
2625 	return 0;
2626 }
2627 
2628 static int max98090_runtime_suspend(struct device *dev)
2629 {
2630 	struct max98090_priv *max98090 = dev_get_drvdata(dev);
2631 
2632 	regcache_cache_only(max98090->regmap, true);
2633 
2634 	return 0;
2635 }
2636 #endif
2637 
2638 #ifdef CONFIG_PM_SLEEP
2639 static int max98090_resume(struct device *dev)
2640 {
2641 	struct max98090_priv *max98090 = dev_get_drvdata(dev);
2642 	unsigned int status;
2643 
2644 	regcache_mark_dirty(max98090->regmap);
2645 
2646 	max98090_reset(max98090);
2647 
2648 	/* clear IRQ status */
2649 	regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2650 
2651 	regcache_sync(max98090->regmap);
2652 
2653 	return 0;
2654 }
2655 
2656 static int max98090_suspend(struct device *dev)
2657 {
2658 	return 0;
2659 }
2660 #endif
2661 
2662 static const struct dev_pm_ops max98090_pm = {
2663 	SET_RUNTIME_PM_OPS(max98090_runtime_suspend,
2664 		max98090_runtime_resume, NULL)
2665 	SET_SYSTEM_SLEEP_PM_OPS(max98090_suspend, max98090_resume)
2666 };
2667 
2668 static const struct i2c_device_id max98090_i2c_id[] = {
2669 	{ "max98090", MAX98090 },
2670 	{ "max98091", MAX98091 },
2671 	{ }
2672 };
2673 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id);
2674 
2675 static const struct of_device_id max98090_of_match[] = {
2676 	{ .compatible = "maxim,max98090", },
2677 	{ .compatible = "maxim,max98091", },
2678 	{ }
2679 };
2680 MODULE_DEVICE_TABLE(of, max98090_of_match);
2681 
2682 #ifdef CONFIG_ACPI
2683 static struct acpi_device_id max98090_acpi_match[] = {
2684 	{ "193C9890", MAX98090 },
2685 	{ }
2686 };
2687 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match);
2688 #endif
2689 
2690 static struct i2c_driver max98090_i2c_driver = {
2691 	.driver = {
2692 		.name = "max98090",
2693 		.owner = THIS_MODULE,
2694 		.pm = &max98090_pm,
2695 		.of_match_table = of_match_ptr(max98090_of_match),
2696 		.acpi_match_table = ACPI_PTR(max98090_acpi_match),
2697 	},
2698 	.probe  = max98090_i2c_probe,
2699 	.remove = max98090_i2c_remove,
2700 	.id_table = max98090_i2c_id,
2701 };
2702 
2703 module_i2c_driver(max98090_i2c_driver);
2704 
2705 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver");
2706 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong");
2707 MODULE_LICENSE("GPL");
2708