1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * max98090.c -- MAX98090 ALSA SoC Audio driver 4 * 5 * Copyright 2011-2012 Maxim Integrated Products 6 */ 7 8 #include <linux/acpi.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/i2c.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/pm.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/slab.h> 19 #include <sound/jack.h> 20 #include <sound/max98090.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include <sound/soc.h> 24 #include <sound/tlv.h> 25 #include "max98090.h" 26 27 static void max98090_shdn_save_locked(struct max98090_priv *max98090) 28 { 29 int shdn = 0; 30 31 /* saved_shdn, saved_count, SHDN are protected by card->dapm_mutex */ 32 regmap_read(max98090->regmap, M98090_REG_DEVICE_SHUTDOWN, &shdn); 33 max98090->saved_shdn |= shdn; 34 ++max98090->saved_count; 35 36 if (shdn) 37 regmap_write(max98090->regmap, M98090_REG_DEVICE_SHUTDOWN, 0x0); 38 } 39 40 static void max98090_shdn_restore_locked(struct max98090_priv *max98090) 41 { 42 /* saved_shdn, saved_count, SHDN are protected by card->dapm_mutex */ 43 if (--max98090->saved_count == 0) { 44 if (max98090->saved_shdn) { 45 regmap_write(max98090->regmap, 46 M98090_REG_DEVICE_SHUTDOWN, 47 M98090_SHDNN_MASK); 48 max98090->saved_shdn = 0; 49 } 50 } 51 } 52 53 static void max98090_shdn_save(struct max98090_priv *max98090) 54 { 55 mutex_lock(&max98090->component->card->dapm_mutex); 56 max98090_shdn_save_locked(max98090); 57 } 58 59 static void max98090_shdn_restore(struct max98090_priv *max98090) 60 { 61 max98090_shdn_restore_locked(max98090); 62 mutex_unlock(&max98090->component->card->dapm_mutex); 63 } 64 65 static int max98090_put_volsw(struct snd_kcontrol *kcontrol, 66 struct snd_ctl_elem_value *ucontrol) 67 { 68 struct snd_soc_component *component = 69 snd_soc_kcontrol_component(kcontrol); 70 struct max98090_priv *max98090 = 71 snd_soc_component_get_drvdata(component); 72 int ret; 73 74 max98090_shdn_save(max98090); 75 ret = snd_soc_put_volsw(kcontrol, ucontrol); 76 max98090_shdn_restore(max98090); 77 78 return ret; 79 } 80 81 static int max98090_dapm_put_enum_double(struct snd_kcontrol *kcontrol, 82 struct snd_ctl_elem_value *ucontrol) 83 { 84 struct snd_soc_component *component = 85 snd_soc_dapm_kcontrol_component(kcontrol); 86 struct max98090_priv *max98090 = 87 snd_soc_component_get_drvdata(component); 88 int ret; 89 90 max98090_shdn_save(max98090); 91 ret = snd_soc_dapm_put_enum_double_locked(kcontrol, ucontrol); 92 max98090_shdn_restore(max98090); 93 94 return ret; 95 } 96 97 static int max98090_put_enum_double(struct snd_kcontrol *kcontrol, 98 struct snd_ctl_elem_value *ucontrol) 99 { 100 struct snd_soc_component *component = 101 snd_soc_kcontrol_component(kcontrol); 102 struct max98090_priv *max98090 = 103 snd_soc_component_get_drvdata(component); 104 int ret; 105 106 max98090_shdn_save(max98090); 107 ret = snd_soc_put_enum_double(kcontrol, ucontrol); 108 max98090_shdn_restore(max98090); 109 110 return ret; 111 } 112 113 static int max98090_bytes_put(struct snd_kcontrol *kcontrol, 114 struct snd_ctl_elem_value *ucontrol) 115 { 116 struct snd_soc_component *component = 117 snd_soc_kcontrol_component(kcontrol); 118 struct max98090_priv *max98090 = 119 snd_soc_component_get_drvdata(component); 120 int ret; 121 122 max98090_shdn_save(max98090); 123 ret = snd_soc_bytes_put(kcontrol, ucontrol); 124 max98090_shdn_restore(max98090); 125 126 return ret; 127 } 128 129 static int max98090_dapm_event(struct snd_soc_dapm_widget *w, 130 struct snd_kcontrol *kcontrol, int event) 131 { 132 struct snd_soc_component *component = 133 snd_soc_dapm_to_component(w->dapm); 134 struct max98090_priv *max98090 = 135 snd_soc_component_get_drvdata(component); 136 137 switch (event) { 138 case SND_SOC_DAPM_PRE_PMU: 139 case SND_SOC_DAPM_PRE_PMD: 140 max98090_shdn_save_locked(max98090); 141 break; 142 case SND_SOC_DAPM_POST_PMU: 143 case SND_SOC_DAPM_POST_PMD: 144 max98090_shdn_restore_locked(max98090); 145 break; 146 } 147 148 return 0; 149 } 150 151 /* Allows for sparsely populated register maps */ 152 static const struct reg_default max98090_reg[] = { 153 { 0x00, 0x00 }, /* 00 Software Reset */ 154 { 0x03, 0x04 }, /* 03 Interrupt Masks */ 155 { 0x04, 0x00 }, /* 04 System Clock Quick */ 156 { 0x05, 0x00 }, /* 05 Sample Rate Quick */ 157 { 0x06, 0x00 }, /* 06 DAI Interface Quick */ 158 { 0x07, 0x00 }, /* 07 DAC Path Quick */ 159 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */ 160 { 0x09, 0x00 }, /* 09 Line to ADC Quick */ 161 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */ 162 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */ 163 { 0x0C, 0x00 }, /* 0C Reserved */ 164 { 0x0D, 0x00 }, /* 0D Input Config */ 165 { 0x0E, 0x1B }, /* 0E Line Input Level */ 166 { 0x0F, 0x00 }, /* 0F Line Config */ 167 168 { 0x10, 0x14 }, /* 10 Mic1 Input Level */ 169 { 0x11, 0x14 }, /* 11 Mic2 Input Level */ 170 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */ 171 { 0x13, 0x00 }, /* 13 Digital Mic Config */ 172 { 0x14, 0x00 }, /* 14 Digital Mic Mode */ 173 { 0x15, 0x00 }, /* 15 Left ADC Mixer */ 174 { 0x16, 0x00 }, /* 16 Right ADC Mixer */ 175 { 0x17, 0x03 }, /* 17 Left ADC Level */ 176 { 0x18, 0x03 }, /* 18 Right ADC Level */ 177 { 0x19, 0x00 }, /* 19 ADC Biquad Level */ 178 { 0x1A, 0x00 }, /* 1A ADC Sidetone */ 179 { 0x1B, 0x00 }, /* 1B System Clock */ 180 { 0x1C, 0x00 }, /* 1C Clock Mode */ 181 { 0x1D, 0x00 }, /* 1D Any Clock 1 */ 182 { 0x1E, 0x00 }, /* 1E Any Clock 2 */ 183 { 0x1F, 0x00 }, /* 1F Any Clock 3 */ 184 185 { 0x20, 0x00 }, /* 20 Any Clock 4 */ 186 { 0x21, 0x00 }, /* 21 Master Mode */ 187 { 0x22, 0x00 }, /* 22 Interface Format */ 188 { 0x23, 0x00 }, /* 23 TDM Format 1*/ 189 { 0x24, 0x00 }, /* 24 TDM Format 2*/ 190 { 0x25, 0x00 }, /* 25 I/O Configuration */ 191 { 0x26, 0x80 }, /* 26 Filter Config */ 192 { 0x27, 0x00 }, /* 27 DAI Playback Level */ 193 { 0x28, 0x00 }, /* 28 EQ Playback Level */ 194 { 0x29, 0x00 }, /* 29 Left HP Mixer */ 195 { 0x2A, 0x00 }, /* 2A Right HP Mixer */ 196 { 0x2B, 0x00 }, /* 2B HP Control */ 197 { 0x2C, 0x1A }, /* 2C Left HP Volume */ 198 { 0x2D, 0x1A }, /* 2D Right HP Volume */ 199 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */ 200 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */ 201 202 { 0x30, 0x00 }, /* 30 Spk Control */ 203 { 0x31, 0x2C }, /* 31 Left Spk Volume */ 204 { 0x32, 0x2C }, /* 32 Right Spk Volume */ 205 { 0x33, 0x00 }, /* 33 ALC Timing */ 206 { 0x34, 0x00 }, /* 34 ALC Compressor */ 207 { 0x35, 0x00 }, /* 35 ALC Expander */ 208 { 0x36, 0x00 }, /* 36 ALC Gain */ 209 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */ 210 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */ 211 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */ 212 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */ 213 { 0x3B, 0x00 }, /* 3B Line OutR Control */ 214 { 0x3C, 0x15 }, /* 3C Line OutR Volume */ 215 { 0x3D, 0x00 }, /* 3D Jack Detect */ 216 { 0x3E, 0x00 }, /* 3E Input Enable */ 217 { 0x3F, 0x00 }, /* 3F Output Enable */ 218 219 { 0x40, 0x00 }, /* 40 Level Control */ 220 { 0x41, 0x00 }, /* 41 DSP Filter Enable */ 221 { 0x42, 0x00 }, /* 42 Bias Control */ 222 { 0x43, 0x00 }, /* 43 DAC Control */ 223 { 0x44, 0x06 }, /* 44 ADC Control */ 224 { 0x45, 0x00 }, /* 45 Device Shutdown */ 225 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */ 226 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */ 227 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */ 228 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */ 229 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */ 230 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */ 231 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */ 232 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */ 233 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */ 234 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */ 235 236 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */ 237 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */ 238 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */ 239 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */ 240 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */ 241 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */ 242 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */ 243 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */ 244 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */ 245 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */ 246 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */ 247 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */ 248 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */ 249 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */ 250 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */ 251 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */ 252 253 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */ 254 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */ 255 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */ 256 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */ 257 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */ 258 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */ 259 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */ 260 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */ 261 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */ 262 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */ 263 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */ 264 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */ 265 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */ 266 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */ 267 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */ 268 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */ 269 270 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */ 271 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */ 272 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */ 273 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */ 274 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */ 275 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */ 276 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */ 277 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */ 278 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */ 279 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */ 280 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */ 281 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */ 282 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */ 283 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */ 284 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */ 285 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */ 286 287 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */ 288 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */ 289 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */ 290 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */ 291 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */ 292 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */ 293 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */ 294 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */ 295 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */ 296 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */ 297 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */ 298 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */ 299 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */ 300 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */ 301 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */ 302 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */ 303 304 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */ 305 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */ 306 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */ 307 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */ 308 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */ 309 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */ 310 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */ 311 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */ 312 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */ 313 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */ 314 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */ 315 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */ 316 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */ 317 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */ 318 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */ 319 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */ 320 321 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */ 322 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */ 323 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */ 324 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */ 325 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */ 326 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */ 327 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */ 328 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */ 329 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */ 330 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */ 331 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */ 332 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */ 333 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */ 334 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */ 335 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */ 336 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */ 337 338 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */ 339 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */ 340 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */ 341 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */ 342 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */ 343 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */ 344 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */ 345 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */ 346 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */ 347 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */ 348 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */ 349 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */ 350 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */ 351 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */ 352 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */ 353 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */ 354 355 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */ 356 { 0xC1, 0x00 }, /* C1 Record TDM Slot */ 357 { 0xC2, 0x00 }, /* C2 Sample Rate */ 358 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */ 359 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */ 360 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */ 361 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */ 362 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */ 363 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */ 364 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */ 365 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */ 366 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */ 367 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */ 368 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */ 369 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */ 370 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */ 371 372 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */ 373 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */ 374 }; 375 376 static bool max98090_volatile_register(struct device *dev, unsigned int reg) 377 { 378 switch (reg) { 379 case M98090_REG_SOFTWARE_RESET: 380 case M98090_REG_DEVICE_STATUS: 381 case M98090_REG_JACK_STATUS: 382 case M98090_REG_REVISION_ID: 383 return true; 384 default: 385 return false; 386 } 387 } 388 389 static bool max98090_readable_register(struct device *dev, unsigned int reg) 390 { 391 switch (reg) { 392 case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S: 393 case M98090_REG_LINE_INPUT_CONFIG ... 0xD1: 394 case M98090_REG_REVISION_ID: 395 return true; 396 default: 397 return false; 398 } 399 } 400 401 static int max98090_reset(struct max98090_priv *max98090) 402 { 403 int ret; 404 405 /* Reset the codec by writing to this write-only reset register */ 406 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, 407 M98090_SWRESET_MASK); 408 if (ret < 0) { 409 dev_err(max98090->component->dev, 410 "Failed to reset codec: %d\n", ret); 411 return ret; 412 } 413 414 msleep(20); 415 return ret; 416 } 417 418 static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv, 419 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 420 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0) 421 ); 422 423 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0); 424 425 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv, 426 -600, 600, 0); 427 428 static const DECLARE_TLV_DB_RANGE(max98090_line_tlv, 429 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0), 430 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0) 431 ); 432 433 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0); 434 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0); 435 436 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0); 437 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0); 438 439 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0); 440 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0); 441 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0); 442 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0); 443 444 static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv, 445 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0), 446 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0) 447 ); 448 449 static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv, 450 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 451 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 452 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 453 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 454 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0) 455 ); 456 457 static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv, 458 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0), 459 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0), 460 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0), 461 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0), 462 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0) 463 ); 464 465 static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv, 466 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 467 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 468 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 469 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 470 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0) 471 ); 472 473 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol, 474 struct snd_ctl_elem_value *ucontrol) 475 { 476 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 477 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 478 struct soc_mixer_control *mc = 479 (struct soc_mixer_control *)kcontrol->private_value; 480 unsigned int mask = (1 << fls(mc->max)) - 1; 481 unsigned int val = snd_soc_component_read32(component, mc->reg); 482 unsigned int *select; 483 484 switch (mc->reg) { 485 case M98090_REG_MIC1_INPUT_LEVEL: 486 select = &(max98090->pa1en); 487 break; 488 case M98090_REG_MIC2_INPUT_LEVEL: 489 select = &(max98090->pa2en); 490 break; 491 case M98090_REG_ADC_SIDETONE: 492 select = &(max98090->sidetone); 493 break; 494 default: 495 return -EINVAL; 496 } 497 498 val = (val >> mc->shift) & mask; 499 500 if (val >= 1) { 501 /* If on, return the volume */ 502 val = val - 1; 503 *select = val; 504 } else { 505 /* If off, return last stored value */ 506 val = *select; 507 } 508 509 ucontrol->value.integer.value[0] = val; 510 return 0; 511 } 512 513 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol, 514 struct snd_ctl_elem_value *ucontrol) 515 { 516 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 517 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 518 struct soc_mixer_control *mc = 519 (struct soc_mixer_control *)kcontrol->private_value; 520 unsigned int mask = (1 << fls(mc->max)) - 1; 521 unsigned int sel = ucontrol->value.integer.value[0]; 522 unsigned int val = snd_soc_component_read32(component, mc->reg); 523 unsigned int *select; 524 525 switch (mc->reg) { 526 case M98090_REG_MIC1_INPUT_LEVEL: 527 select = &(max98090->pa1en); 528 break; 529 case M98090_REG_MIC2_INPUT_LEVEL: 530 select = &(max98090->pa2en); 531 break; 532 case M98090_REG_ADC_SIDETONE: 533 select = &(max98090->sidetone); 534 break; 535 default: 536 return -EINVAL; 537 } 538 539 val = (val >> mc->shift) & mask; 540 541 *select = sel; 542 543 /* Setting a volume is only valid if it is already On */ 544 if (val >= 1) { 545 sel = sel + 1; 546 } else { 547 /* Write what was already there */ 548 sel = val; 549 } 550 551 snd_soc_component_update_bits(component, mc->reg, 552 mask << mc->shift, 553 sel << mc->shift); 554 555 return 0; 556 } 557 558 static const char *max98090_perf_pwr_text[] = 559 { "High Performance", "Low Power" }; 560 static const char *max98090_pwr_perf_text[] = 561 { "Low Power", "High Performance" }; 562 563 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum, 564 M98090_REG_BIAS_CONTROL, 565 M98090_VCM_MODE_SHIFT, 566 max98090_pwr_perf_text); 567 568 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" }; 569 570 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum, 571 M98090_REG_ADC_CONTROL, 572 M98090_OSR128_SHIFT, 573 max98090_osr128_text); 574 575 static const char *max98090_mode_text[] = { "Voice", "Music" }; 576 577 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum, 578 M98090_REG_FILTER_CONFIG, 579 M98090_MODE_SHIFT, 580 max98090_mode_text); 581 582 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum, 583 M98090_REG_FILTER_CONFIG, 584 M98090_FLT_DMIC34MODE_SHIFT, 585 max98090_mode_text); 586 587 static const char *max98090_drcatk_text[] = 588 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" }; 589 590 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum, 591 M98090_REG_DRC_TIMING, 592 M98090_DRCATK_SHIFT, 593 max98090_drcatk_text); 594 595 static const char *max98090_drcrls_text[] = 596 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" }; 597 598 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum, 599 M98090_REG_DRC_TIMING, 600 M98090_DRCRLS_SHIFT, 601 max98090_drcrls_text); 602 603 static const char *max98090_alccmp_text[] = 604 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" }; 605 606 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum, 607 M98090_REG_DRC_COMPRESSOR, 608 M98090_DRCCMP_SHIFT, 609 max98090_alccmp_text); 610 611 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" }; 612 613 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum, 614 M98090_REG_DRC_EXPANDER, 615 M98090_DRCEXP_SHIFT, 616 max98090_drcexp_text); 617 618 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum, 619 M98090_REG_DAC_CONTROL, 620 M98090_PERFMODE_SHIFT, 621 max98090_perf_pwr_text); 622 623 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum, 624 M98090_REG_DAC_CONTROL, 625 M98090_DACHP_SHIFT, 626 max98090_pwr_perf_text); 627 628 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum, 629 M98090_REG_ADC_CONTROL, 630 M98090_ADCHP_SHIFT, 631 max98090_pwr_perf_text); 632 633 static const struct snd_kcontrol_new max98090_snd_controls[] = { 634 SOC_ENUM_EXT("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum, 635 snd_soc_get_enum_double, max98090_put_enum_double), 636 637 SOC_SINGLE_EXT("DMIC MIC Comp Filter Config", 638 M98090_REG_DIGITAL_MIC_CONFIG, 639 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0, 640 snd_soc_get_volsw, max98090_put_volsw), 641 642 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 643 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, 644 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv, 645 max98090_put_enab_tlv, max98090_micboost_tlv), 646 647 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 648 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, 649 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv, 650 max98090_put_enab_tlv, max98090_micboost_tlv), 651 652 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL, 653 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1, 654 max98090_mic_tlv), 655 656 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL, 657 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1, 658 max98090_mic_tlv), 659 660 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume", 661 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0, 662 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv), 663 664 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume", 665 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0, 666 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv), 667 668 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL, 669 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1, 670 max98090_line_tlv), 671 672 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL, 673 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1, 674 max98090_line_tlv), 675 676 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 677 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0), 678 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 679 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0), 680 681 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL, 682 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0, 683 max98090_avg_tlv), 684 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL, 685 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0, 686 max98090_avg_tlv), 687 688 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL, 689 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1, 690 max98090_av_tlv), 691 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL, 692 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1, 693 max98090_av_tlv), 694 695 SOC_ENUM_EXT("ADC Oversampling Rate", max98090_osr128_enum, 696 snd_soc_get_enum_double, max98090_put_enum_double), 697 SOC_SINGLE_EXT("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, 698 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0, 699 snd_soc_get_volsw, max98090_put_volsw), 700 SOC_ENUM_EXT("ADC High Performance Mode", max98090_adchp_enum, 701 snd_soc_get_enum_double, max98090_put_enum_double), 702 703 SOC_SINGLE_EXT("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, 704 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0, 705 snd_soc_get_volsw, max98090_put_volsw), 706 SOC_SINGLE_EXT("SDIN Mode", M98090_REG_IO_CONFIGURATION, 707 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0, 708 snd_soc_get_volsw, max98090_put_volsw), 709 SOC_SINGLE_EXT("SDOUT Mode", M98090_REG_IO_CONFIGURATION, 710 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0, 711 snd_soc_get_volsw, max98090_put_volsw), 712 SOC_SINGLE_EXT("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, 713 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1, 714 snd_soc_get_volsw, max98090_put_volsw), 715 SOC_ENUM_EXT("Filter Mode", max98090_mode_enum, 716 snd_soc_get_enum_double, max98090_put_enum_double), 717 SOC_SINGLE_EXT("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, 718 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0, 719 snd_soc_get_volsw, max98090_put_volsw), 720 SOC_SINGLE_EXT("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, 721 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0, 722 snd_soc_get_volsw, max98090_put_volsw), 723 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL, 724 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv), 725 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", 726 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT, 727 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv, 728 max98090_put_enab_tlv, max98090_sdg_tlv), 729 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 730 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0, 731 max98090_dvg_tlv), 732 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 733 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1, 734 max98090_dv_tlv), 735 SND_SOC_BYTES_E("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105, 736 snd_soc_bytes_get, max98090_bytes_put), 737 SOC_SINGLE_EXT("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 738 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0, 739 snd_soc_get_volsw, max98090_put_volsw), 740 SOC_SINGLE_EXT("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 741 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0, 742 snd_soc_get_volsw, max98090_put_volsw), 743 SOC_SINGLE_EXT("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 744 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0, 745 snd_soc_get_volsw, max98090_put_volsw), 746 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 747 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1, 748 1), 749 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 750 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1, 751 max98090_dv_tlv), 752 753 SOC_SINGLE_EXT("ALC Enable", M98090_REG_DRC_TIMING, 754 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0, 755 snd_soc_get_volsw, max98090_put_volsw), 756 SOC_ENUM_EXT("ALC Attack Time", max98090_drcatk_enum, 757 snd_soc_get_enum_double, max98090_put_enum_double), 758 SOC_ENUM_EXT("ALC Release Time", max98090_drcrls_enum, 759 snd_soc_get_enum_double, max98090_put_enum_double), 760 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN, 761 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0, 762 max98090_alcmakeup_tlv), 763 SOC_ENUM_EXT("ALC Compression Ratio", max98090_alccmp_enum, 764 snd_soc_get_enum_double, max98090_put_enum_double), 765 SOC_ENUM_EXT("ALC Expansion Ratio", max98090_drcexp_enum, 766 snd_soc_get_enum_double, max98090_put_enum_double), 767 SOC_SINGLE_EXT_TLV("ALC Compression Threshold Volume", 768 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT, 769 M98090_DRCTHC_NUM - 1, 1, 770 snd_soc_get_volsw, max98090_put_volsw, max98090_alccomp_tlv), 771 SOC_SINGLE_EXT_TLV("ALC Expansion Threshold Volume", 772 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT, 773 M98090_DRCTHE_NUM - 1, 1, 774 snd_soc_get_volsw, max98090_put_volsw, max98090_drcexp_tlv), 775 776 SOC_ENUM_EXT("DAC HP Playback Performance Mode", 777 max98090_dac_perfmode_enum, 778 snd_soc_get_enum_double, max98090_put_enum_double), 779 SOC_ENUM_EXT("DAC High Performance Mode", max98090_dachp_enum, 780 snd_soc_get_enum_double, max98090_put_enum_double), 781 782 SOC_SINGLE_TLV("Headphone Left Mixer Volume", 783 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT, 784 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv), 785 SOC_SINGLE_TLV("Headphone Right Mixer Volume", 786 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT, 787 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv), 788 789 SOC_SINGLE_TLV("Speaker Left Mixer Volume", 790 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT, 791 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv), 792 SOC_SINGLE_TLV("Speaker Right Mixer Volume", 793 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT, 794 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv), 795 796 SOC_SINGLE_TLV("Receiver Left Mixer Volume", 797 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT, 798 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv), 799 SOC_SINGLE_TLV("Receiver Right Mixer Volume", 800 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT, 801 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv), 802 803 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME, 804 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT, 805 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv), 806 807 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume", 808 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME, 809 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24, 810 0, max98090_spk_tlv), 811 812 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME, 813 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT, 814 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv), 815 816 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME, 817 M98090_HPLM_SHIFT, 1, 1), 818 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME, 819 M98090_HPRM_SHIFT, 1, 1), 820 821 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME, 822 M98090_SPLM_SHIFT, 1, 1), 823 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME, 824 M98090_SPRM_SHIFT, 1, 1), 825 826 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME, 827 M98090_RCVLM_SHIFT, 1, 1), 828 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME, 829 M98090_RCVRM_SHIFT, 1, 1), 830 831 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL, 832 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1), 833 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL, 834 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1), 835 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL, 836 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1), 837 838 SND_SOC_BYTES_E("Biquad Coefficients", 839 M98090_REG_RECORD_BIQUAD_BASE, 15, 840 snd_soc_bytes_get, max98090_bytes_put), 841 SOC_SINGLE_EXT("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 842 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0, 843 snd_soc_get_volsw, max98090_put_volsw), 844 }; 845 846 static const struct snd_kcontrol_new max98091_snd_controls[] = { 847 848 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE, 849 M98090_DMIC34_ZEROPAD_SHIFT, 850 M98090_DMIC34_ZEROPAD_NUM - 1, 0), 851 852 SOC_ENUM_EXT("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum, 853 snd_soc_get_enum_double, max98090_put_enum_double), 854 SOC_SINGLE_EXT("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, 855 M98090_FLT_DMIC34HPF_SHIFT, 856 M98090_FLT_DMIC34HPF_NUM - 1, 0, 857 snd_soc_get_volsw, max98090_put_volsw), 858 859 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME, 860 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0, 861 max98090_avg_tlv), 862 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME, 863 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0, 864 max98090_avg_tlv), 865 866 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME, 867 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1, 868 max98090_av_tlv), 869 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME, 870 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1, 871 max98090_av_tlv), 872 873 SND_SOC_BYTES("DMIC34 Biquad Coefficients", 874 M98090_REG_DMIC34_BIQUAD_BASE, 15), 875 SOC_SINGLE_EXT("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 876 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0, 877 snd_soc_get_volsw, max98090_put_volsw), 878 879 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume", 880 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT, 881 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv), 882 }; 883 884 static int max98090_micinput_event(struct snd_soc_dapm_widget *w, 885 struct snd_kcontrol *kcontrol, int event) 886 { 887 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 888 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 889 890 unsigned int val = snd_soc_component_read32(component, w->reg); 891 892 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 893 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT; 894 else 895 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT; 896 897 if (val >= 1) { 898 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { 899 max98090->pa1en = val - 1; /* Update for volatile */ 900 } else { 901 max98090->pa2en = val - 1; /* Update for volatile */ 902 } 903 } 904 905 switch (event) { 906 case SND_SOC_DAPM_POST_PMU: 907 /* If turning on, set to most recently selected volume */ 908 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 909 val = max98090->pa1en + 1; 910 else 911 val = max98090->pa2en + 1; 912 break; 913 case SND_SOC_DAPM_POST_PMD: 914 /* If turning off, turn off */ 915 val = 0; 916 break; 917 default: 918 return -EINVAL; 919 } 920 921 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 922 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK, 923 val << M98090_MIC_PA1EN_SHIFT); 924 else 925 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK, 926 val << M98090_MIC_PA2EN_SHIFT); 927 928 return 0; 929 } 930 931 static const char *mic1_mux_text[] = { "IN12", "IN56" }; 932 933 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum, 934 M98090_REG_INPUT_MODE, 935 M98090_EXTMIC1_SHIFT, 936 mic1_mux_text); 937 938 static const struct snd_kcontrol_new max98090_mic1_mux = 939 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum); 940 941 static const char *mic2_mux_text[] = { "IN34", "IN56" }; 942 943 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum, 944 M98090_REG_INPUT_MODE, 945 M98090_EXTMIC2_SHIFT, 946 mic2_mux_text); 947 948 static const struct snd_kcontrol_new max98090_mic2_mux = 949 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum); 950 951 static const char *dmic_mux_text[] = { "ADC", "DMIC" }; 952 953 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text); 954 955 static const struct snd_kcontrol_new max98090_dmic_mux = 956 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum); 957 958 /* LINEA mixer switch */ 959 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = { 960 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG, 961 M98090_IN1SEEN_SHIFT, 1, 0), 962 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG, 963 M98090_IN3SEEN_SHIFT, 1, 0), 964 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG, 965 M98090_IN5SEEN_SHIFT, 1, 0), 966 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG, 967 M98090_IN34DIFF_SHIFT, 1, 0), 968 }; 969 970 /* LINEB mixer switch */ 971 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = { 972 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG, 973 M98090_IN2SEEN_SHIFT, 1, 0), 974 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG, 975 M98090_IN4SEEN_SHIFT, 1, 0), 976 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG, 977 M98090_IN6SEEN_SHIFT, 1, 0), 978 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG, 979 M98090_IN56DIFF_SHIFT, 1, 0), 980 }; 981 982 /* Left ADC mixer switch */ 983 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = { 984 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER, 985 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0), 986 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER, 987 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0), 988 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER, 989 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0), 990 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER, 991 M98090_MIXADL_LINEA_SHIFT, 1, 0), 992 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER, 993 M98090_MIXADL_LINEB_SHIFT, 1, 0), 994 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER, 995 M98090_MIXADL_MIC1_SHIFT, 1, 0), 996 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER, 997 M98090_MIXADL_MIC2_SHIFT, 1, 0), 998 }; 999 1000 /* Right ADC mixer switch */ 1001 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = { 1002 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER, 1003 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0), 1004 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER, 1005 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0), 1006 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER, 1007 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0), 1008 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER, 1009 M98090_MIXADR_LINEA_SHIFT, 1, 0), 1010 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER, 1011 M98090_MIXADR_LINEB_SHIFT, 1, 0), 1012 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER, 1013 M98090_MIXADR_MIC1_SHIFT, 1, 0), 1014 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER, 1015 M98090_MIXADR_MIC2_SHIFT, 1, 0), 1016 }; 1017 1018 static const char *lten_mux_text[] = { "Normal", "Loopthrough" }; 1019 1020 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum, 1021 M98090_REG_IO_CONFIGURATION, 1022 M98090_LTEN_SHIFT, 1023 lten_mux_text); 1024 1025 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum, 1026 M98090_REG_IO_CONFIGURATION, 1027 M98090_LTEN_SHIFT, 1028 lten_mux_text); 1029 1030 static const struct snd_kcontrol_new max98090_ltenl_mux = 1031 SOC_DAPM_ENUM_EXT("LTENL Mux", ltenl_mux_enum, 1032 snd_soc_dapm_get_enum_double, 1033 max98090_dapm_put_enum_double); 1034 1035 static const struct snd_kcontrol_new max98090_ltenr_mux = 1036 SOC_DAPM_ENUM_EXT("LTENR Mux", ltenr_mux_enum, 1037 snd_soc_dapm_get_enum_double, 1038 max98090_dapm_put_enum_double); 1039 1040 static const char *lben_mux_text[] = { "Normal", "Loopback" }; 1041 1042 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum, 1043 M98090_REG_IO_CONFIGURATION, 1044 M98090_LBEN_SHIFT, 1045 lben_mux_text); 1046 1047 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum, 1048 M98090_REG_IO_CONFIGURATION, 1049 M98090_LBEN_SHIFT, 1050 lben_mux_text); 1051 1052 static const struct snd_kcontrol_new max98090_lbenl_mux = 1053 SOC_DAPM_ENUM_EXT("LBENL Mux", lbenl_mux_enum, 1054 snd_soc_dapm_get_enum_double, 1055 max98090_dapm_put_enum_double); 1056 1057 static const struct snd_kcontrol_new max98090_lbenr_mux = 1058 SOC_DAPM_ENUM_EXT("LBENR Mux", lbenr_mux_enum, 1059 snd_soc_dapm_get_enum_double, 1060 max98090_dapm_put_enum_double); 1061 1062 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" }; 1063 1064 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" }; 1065 1066 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum, 1067 M98090_REG_ADC_SIDETONE, 1068 M98090_DSTSL_SHIFT, 1069 stenl_mux_text); 1070 1071 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum, 1072 M98090_REG_ADC_SIDETONE, 1073 M98090_DSTSR_SHIFT, 1074 stenr_mux_text); 1075 1076 static const struct snd_kcontrol_new max98090_stenl_mux = 1077 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum); 1078 1079 static const struct snd_kcontrol_new max98090_stenr_mux = 1080 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum); 1081 1082 /* Left speaker mixer switch */ 1083 static const struct 1084 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = { 1085 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER, 1086 M98090_MIXSPL_DACL_SHIFT, 1, 0), 1087 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER, 1088 M98090_MIXSPL_DACR_SHIFT, 1, 0), 1089 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER, 1090 M98090_MIXSPL_LINEA_SHIFT, 1, 0), 1091 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER, 1092 M98090_MIXSPL_LINEB_SHIFT, 1, 0), 1093 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER, 1094 M98090_MIXSPL_MIC1_SHIFT, 1, 0), 1095 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER, 1096 M98090_MIXSPL_MIC2_SHIFT, 1, 0), 1097 }; 1098 1099 /* Right speaker mixer switch */ 1100 static const struct 1101 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = { 1102 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 1103 M98090_MIXSPR_DACL_SHIFT, 1, 0), 1104 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 1105 M98090_MIXSPR_DACR_SHIFT, 1, 0), 1106 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER, 1107 M98090_MIXSPR_LINEA_SHIFT, 1, 0), 1108 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER, 1109 M98090_MIXSPR_LINEB_SHIFT, 1, 0), 1110 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER, 1111 M98090_MIXSPR_MIC1_SHIFT, 1, 0), 1112 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER, 1113 M98090_MIXSPR_MIC2_SHIFT, 1, 0), 1114 }; 1115 1116 /* Left headphone mixer switch */ 1117 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { 1118 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER, 1119 M98090_MIXHPL_DACL_SHIFT, 1, 0), 1120 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER, 1121 M98090_MIXHPL_DACR_SHIFT, 1, 0), 1122 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER, 1123 M98090_MIXHPL_LINEA_SHIFT, 1, 0), 1124 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER, 1125 M98090_MIXHPL_LINEB_SHIFT, 1, 0), 1126 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER, 1127 M98090_MIXHPL_MIC1_SHIFT, 1, 0), 1128 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER, 1129 M98090_MIXHPL_MIC2_SHIFT, 1, 0), 1130 }; 1131 1132 /* Right headphone mixer switch */ 1133 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { 1134 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER, 1135 M98090_MIXHPR_DACL_SHIFT, 1, 0), 1136 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER, 1137 M98090_MIXHPR_DACR_SHIFT, 1, 0), 1138 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER, 1139 M98090_MIXHPR_LINEA_SHIFT, 1, 0), 1140 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER, 1141 M98090_MIXHPR_LINEB_SHIFT, 1, 0), 1142 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER, 1143 M98090_MIXHPR_MIC1_SHIFT, 1, 0), 1144 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER, 1145 M98090_MIXHPR_MIC2_SHIFT, 1, 0), 1146 }; 1147 1148 /* Left receiver mixer switch */ 1149 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = { 1150 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1151 M98090_MIXRCVL_DACL_SHIFT, 1, 0), 1152 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1153 M98090_MIXRCVL_DACR_SHIFT, 1, 0), 1154 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER, 1155 M98090_MIXRCVL_LINEA_SHIFT, 1, 0), 1156 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER, 1157 M98090_MIXRCVL_LINEB_SHIFT, 1, 0), 1158 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER, 1159 M98090_MIXRCVL_MIC1_SHIFT, 1, 0), 1160 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER, 1161 M98090_MIXRCVL_MIC2_SHIFT, 1, 0), 1162 }; 1163 1164 /* Right receiver mixer switch */ 1165 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = { 1166 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER, 1167 M98090_MIXRCVR_DACL_SHIFT, 1, 0), 1168 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER, 1169 M98090_MIXRCVR_DACR_SHIFT, 1, 0), 1170 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER, 1171 M98090_MIXRCVR_LINEA_SHIFT, 1, 0), 1172 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER, 1173 M98090_MIXRCVR_LINEB_SHIFT, 1, 0), 1174 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER, 1175 M98090_MIXRCVR_MIC1_SHIFT, 1, 0), 1176 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER, 1177 M98090_MIXRCVR_MIC2_SHIFT, 1, 0), 1178 }; 1179 1180 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" }; 1181 1182 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum, 1183 M98090_REG_LOUTR_MIXER, 1184 M98090_LINMOD_SHIFT, 1185 linmod_mux_text); 1186 1187 static const struct snd_kcontrol_new max98090_linmod_mux = 1188 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum); 1189 1190 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" }; 1191 1192 /* 1193 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable 1194 */ 1195 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum, 1196 M98090_REG_HP_CONTROL, 1197 M98090_MIXHPLSEL_SHIFT, 1198 mixhpsel_mux_text); 1199 1200 static const struct snd_kcontrol_new max98090_mixhplsel_mux = 1201 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum); 1202 1203 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum, 1204 M98090_REG_HP_CONTROL, 1205 M98090_MIXHPRSEL_SHIFT, 1206 mixhpsel_mux_text); 1207 1208 static const struct snd_kcontrol_new max98090_mixhprsel_mux = 1209 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum); 1210 1211 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { 1212 SND_SOC_DAPM_INPUT("MIC1"), 1213 SND_SOC_DAPM_INPUT("MIC2"), 1214 SND_SOC_DAPM_INPUT("DMICL"), 1215 SND_SOC_DAPM_INPUT("DMICR"), 1216 SND_SOC_DAPM_INPUT("IN1"), 1217 SND_SOC_DAPM_INPUT("IN2"), 1218 SND_SOC_DAPM_INPUT("IN3"), 1219 SND_SOC_DAPM_INPUT("IN4"), 1220 SND_SOC_DAPM_INPUT("IN5"), 1221 SND_SOC_DAPM_INPUT("IN6"), 1222 SND_SOC_DAPM_INPUT("IN12"), 1223 SND_SOC_DAPM_INPUT("IN34"), 1224 SND_SOC_DAPM_INPUT("IN56"), 1225 1226 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE, 1227 M98090_MBEN_SHIFT, 0, max98090_dapm_event, 1228 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1229 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN, 1230 M98090_SHDNN_SHIFT, 0, NULL, 0), 1231 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION, 1232 M98090_SDIEN_SHIFT, 0, max98090_dapm_event, 1233 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1234 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION, 1235 M98090_SDOEN_SHIFT, 0, max98090_dapm_event, 1236 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1237 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1238 M98090_DIGMICL_SHIFT, 0, max98090_dapm_event, 1239 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1240 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1241 M98090_DIGMICR_SHIFT, 0, max98090_dapm_event, 1242 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1243 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG, 1244 M98090_AHPF_SHIFT, 0, max98090_dapm_event, 1245 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1246 1247 /* 1248 * Note: Sysclk and misc power supplies are taken care of by SHDN 1249 */ 1250 1251 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM, 1252 0, 0, &max98090_mic1_mux), 1253 1254 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM, 1255 0, 0, &max98090_mic2_mux), 1256 1257 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux), 1258 1259 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL, 1260 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1261 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1262 1263 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL, 1264 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1265 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1266 1267 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0, 1268 &max98090_linea_mixer_controls[0], 1269 ARRAY_SIZE(max98090_linea_mixer_controls)), 1270 1271 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0, 1272 &max98090_lineb_mixer_controls[0], 1273 ARRAY_SIZE(max98090_lineb_mixer_controls)), 1274 1275 SND_SOC_DAPM_PGA_E("LINEA Input", M98090_REG_INPUT_ENABLE, 1276 M98090_LINEAEN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1277 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1278 SND_SOC_DAPM_PGA_E("LINEB Input", M98090_REG_INPUT_ENABLE, 1279 M98090_LINEBEN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1280 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1281 1282 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1283 &max98090_left_adc_mixer_controls[0], 1284 ARRAY_SIZE(max98090_left_adc_mixer_controls)), 1285 1286 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1287 &max98090_right_adc_mixer_controls[0], 1288 ARRAY_SIZE(max98090_right_adc_mixer_controls)), 1289 1290 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE, 1291 M98090_ADLEN_SHIFT, 0, max98090_dapm_event, 1292 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1293 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE, 1294 M98090_ADREN_SHIFT, 0, max98090_dapm_event, 1295 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1296 1297 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0, 1298 SND_SOC_NOPM, 0, 0), 1299 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1, 1300 SND_SOC_NOPM, 0, 0), 1301 1302 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM, 1303 0, 0, &max98090_lbenl_mux), 1304 1305 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM, 1306 0, 0, &max98090_lbenr_mux), 1307 1308 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM, 1309 0, 0, &max98090_ltenl_mux), 1310 1311 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM, 1312 0, 0, &max98090_ltenr_mux), 1313 1314 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM, 1315 0, 0, &max98090_stenl_mux), 1316 1317 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM, 1318 0, 0, &max98090_stenr_mux), 1319 1320 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 1321 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0), 1322 1323 SND_SOC_DAPM_DAC_E("DACL", NULL, M98090_REG_OUTPUT_ENABLE, 1324 M98090_DALEN_SHIFT, 0, max98090_dapm_event, 1325 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1326 SND_SOC_DAPM_DAC_E("DACR", NULL, M98090_REG_OUTPUT_ENABLE, 1327 M98090_DAREN_SHIFT, 0, max98090_dapm_event, 1328 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1329 1330 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 1331 &max98090_left_hp_mixer_controls[0], 1332 ARRAY_SIZE(max98090_left_hp_mixer_controls)), 1333 1334 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 1335 &max98090_right_hp_mixer_controls[0], 1336 ARRAY_SIZE(max98090_right_hp_mixer_controls)), 1337 1338 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 1339 &max98090_left_speaker_mixer_controls[0], 1340 ARRAY_SIZE(max98090_left_speaker_mixer_controls)), 1341 1342 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 1343 &max98090_right_speaker_mixer_controls[0], 1344 ARRAY_SIZE(max98090_right_speaker_mixer_controls)), 1345 1346 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0, 1347 &max98090_left_rcv_mixer_controls[0], 1348 ARRAY_SIZE(max98090_left_rcv_mixer_controls)), 1349 1350 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0, 1351 &max98090_right_rcv_mixer_controls[0], 1352 ARRAY_SIZE(max98090_right_rcv_mixer_controls)), 1353 1354 SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0, 1355 &max98090_linmod_mux), 1356 1357 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0, 1358 &max98090_mixhplsel_mux), 1359 1360 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0, 1361 &max98090_mixhprsel_mux), 1362 1363 SND_SOC_DAPM_PGA_E("HP Left Out", M98090_REG_OUTPUT_ENABLE, 1364 M98090_HPLEN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1365 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1366 SND_SOC_DAPM_PGA_E("HP Right Out", M98090_REG_OUTPUT_ENABLE, 1367 M98090_HPREN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1368 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1369 1370 SND_SOC_DAPM_PGA_E("SPK Left Out", M98090_REG_OUTPUT_ENABLE, 1371 M98090_SPLEN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1372 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1373 SND_SOC_DAPM_PGA_E("SPK Right Out", M98090_REG_OUTPUT_ENABLE, 1374 M98090_SPREN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1375 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1376 1377 SND_SOC_DAPM_PGA_E("RCV Left Out", M98090_REG_OUTPUT_ENABLE, 1378 M98090_RCVLEN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1379 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1380 SND_SOC_DAPM_PGA_E("RCV Right Out", M98090_REG_OUTPUT_ENABLE, 1381 M98090_RCVREN_SHIFT, 0, NULL, 0, max98090_dapm_event, 1382 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1383 1384 SND_SOC_DAPM_OUTPUT("HPL"), 1385 SND_SOC_DAPM_OUTPUT("HPR"), 1386 SND_SOC_DAPM_OUTPUT("SPKL"), 1387 SND_SOC_DAPM_OUTPUT("SPKR"), 1388 SND_SOC_DAPM_OUTPUT("RCVL"), 1389 SND_SOC_DAPM_OUTPUT("RCVR"), 1390 }; 1391 1392 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = { 1393 SND_SOC_DAPM_INPUT("DMIC3"), 1394 SND_SOC_DAPM_INPUT("DMIC4"), 1395 1396 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1397 M98090_DIGMIC3_SHIFT, 0, max98090_dapm_event, 1398 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1399 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1400 M98090_DIGMIC4_SHIFT, 0, max98090_dapm_event, 1401 SND_SOC_DAPM_PRE_POST_PMU | SND_SOC_DAPM_PRE_POST_PMD), 1402 }; 1403 1404 static const struct snd_soc_dapm_route max98090_dapm_routes[] = { 1405 {"MIC1 Input", NULL, "MIC1"}, 1406 {"MIC2 Input", NULL, "MIC2"}, 1407 1408 {"DMICL", NULL, "DMICL_ENA"}, 1409 {"DMICL", NULL, "DMICR_ENA"}, 1410 {"DMICR", NULL, "DMICL_ENA"}, 1411 {"DMICR", NULL, "DMICR_ENA"}, 1412 {"DMICL", NULL, "AHPF"}, 1413 {"DMICR", NULL, "AHPF"}, 1414 1415 /* MIC1 input mux */ 1416 {"MIC1 Mux", "IN12", "IN12"}, 1417 {"MIC1 Mux", "IN56", "IN56"}, 1418 1419 /* MIC2 input mux */ 1420 {"MIC2 Mux", "IN34", "IN34"}, 1421 {"MIC2 Mux", "IN56", "IN56"}, 1422 1423 {"MIC1 Input", NULL, "MIC1 Mux"}, 1424 {"MIC2 Input", NULL, "MIC2 Mux"}, 1425 1426 /* Left ADC input mixer */ 1427 {"Left ADC Mixer", "IN12 Switch", "IN12"}, 1428 {"Left ADC Mixer", "IN34 Switch", "IN34"}, 1429 {"Left ADC Mixer", "IN56 Switch", "IN56"}, 1430 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"}, 1431 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"}, 1432 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1433 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1434 1435 /* Right ADC input mixer */ 1436 {"Right ADC Mixer", "IN12 Switch", "IN12"}, 1437 {"Right ADC Mixer", "IN34 Switch", "IN34"}, 1438 {"Right ADC Mixer", "IN56 Switch", "IN56"}, 1439 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"}, 1440 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"}, 1441 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1442 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1443 1444 /* Line A input mixer */ 1445 {"LINEA Mixer", "IN1 Switch", "IN1"}, 1446 {"LINEA Mixer", "IN3 Switch", "IN3"}, 1447 {"LINEA Mixer", "IN5 Switch", "IN5"}, 1448 {"LINEA Mixer", "IN34 Switch", "IN34"}, 1449 1450 /* Line B input mixer */ 1451 {"LINEB Mixer", "IN2 Switch", "IN2"}, 1452 {"LINEB Mixer", "IN4 Switch", "IN4"}, 1453 {"LINEB Mixer", "IN6 Switch", "IN6"}, 1454 {"LINEB Mixer", "IN56 Switch", "IN56"}, 1455 1456 {"LINEA Input", NULL, "LINEA Mixer"}, 1457 {"LINEB Input", NULL, "LINEB Mixer"}, 1458 1459 /* Inputs */ 1460 {"ADCL", NULL, "Left ADC Mixer"}, 1461 {"ADCR", NULL, "Right ADC Mixer"}, 1462 {"ADCL", NULL, "SHDN"}, 1463 {"ADCR", NULL, "SHDN"}, 1464 1465 {"DMIC Mux", "ADC", "ADCL"}, 1466 {"DMIC Mux", "ADC", "ADCR"}, 1467 {"DMIC Mux", "DMIC", "DMICL"}, 1468 {"DMIC Mux", "DMIC", "DMICR"}, 1469 1470 {"LBENL Mux", "Normal", "DMIC Mux"}, 1471 {"LBENL Mux", "Loopback", "LTENL Mux"}, 1472 {"LBENR Mux", "Normal", "DMIC Mux"}, 1473 {"LBENR Mux", "Loopback", "LTENR Mux"}, 1474 1475 {"AIFOUTL", NULL, "LBENL Mux"}, 1476 {"AIFOUTR", NULL, "LBENR Mux"}, 1477 {"AIFOUTL", NULL, "SHDN"}, 1478 {"AIFOUTR", NULL, "SHDN"}, 1479 {"AIFOUTL", NULL, "SDOEN"}, 1480 {"AIFOUTR", NULL, "SDOEN"}, 1481 1482 {"LTENL Mux", "Normal", "AIFINL"}, 1483 {"LTENL Mux", "Loopthrough", "LBENL Mux"}, 1484 {"LTENR Mux", "Normal", "AIFINR"}, 1485 {"LTENR Mux", "Loopthrough", "LBENR Mux"}, 1486 1487 {"DACL", NULL, "LTENL Mux"}, 1488 {"DACR", NULL, "LTENR Mux"}, 1489 1490 {"STENL Mux", "Sidetone Left", "ADCL"}, 1491 {"STENL Mux", "Sidetone Left", "DMICL"}, 1492 {"STENR Mux", "Sidetone Right", "ADCR"}, 1493 {"STENR Mux", "Sidetone Right", "DMICR"}, 1494 {"DACL", NULL, "STENL Mux"}, 1495 {"DACR", NULL, "STENR Mux"}, 1496 1497 {"AIFINL", NULL, "SHDN"}, 1498 {"AIFINR", NULL, "SHDN"}, 1499 {"AIFINL", NULL, "SDIEN"}, 1500 {"AIFINR", NULL, "SDIEN"}, 1501 {"DACL", NULL, "SHDN"}, 1502 {"DACR", NULL, "SHDN"}, 1503 1504 /* Left headphone output mixer */ 1505 {"Left Headphone Mixer", "Left DAC Switch", "DACL"}, 1506 {"Left Headphone Mixer", "Right DAC Switch", "DACR"}, 1507 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1508 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1509 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1510 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1511 1512 /* Right headphone output mixer */ 1513 {"Right Headphone Mixer", "Left DAC Switch", "DACL"}, 1514 {"Right Headphone Mixer", "Right DAC Switch", "DACR"}, 1515 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1516 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1517 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1518 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1519 1520 /* Left speaker output mixer */ 1521 {"Left Speaker Mixer", "Left DAC Switch", "DACL"}, 1522 {"Left Speaker Mixer", "Right DAC Switch", "DACR"}, 1523 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1524 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1525 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1526 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1527 1528 /* Right speaker output mixer */ 1529 {"Right Speaker Mixer", "Left DAC Switch", "DACL"}, 1530 {"Right Speaker Mixer", "Right DAC Switch", "DACR"}, 1531 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1532 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1533 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1534 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1535 1536 /* Left Receiver output mixer */ 1537 {"Left Receiver Mixer", "Left DAC Switch", "DACL"}, 1538 {"Left Receiver Mixer", "Right DAC Switch", "DACR"}, 1539 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1540 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1541 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1542 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1543 1544 /* Right Receiver output mixer */ 1545 {"Right Receiver Mixer", "Left DAC Switch", "DACL"}, 1546 {"Right Receiver Mixer", "Right DAC Switch", "DACR"}, 1547 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1548 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1549 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1550 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1551 1552 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"}, 1553 1554 /* 1555 * Disable this for lowest power if bypassing 1556 * the DAC with an analog signal 1557 */ 1558 {"HP Left Out", NULL, "DACL"}, 1559 {"HP Left Out", NULL, "MIXHPLSEL Mux"}, 1560 1561 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"}, 1562 1563 /* 1564 * Disable this for lowest power if bypassing 1565 * the DAC with an analog signal 1566 */ 1567 {"HP Right Out", NULL, "DACR"}, 1568 {"HP Right Out", NULL, "MIXHPRSEL Mux"}, 1569 1570 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 1571 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 1572 {"RCV Left Out", NULL, "Left Receiver Mixer"}, 1573 1574 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"}, 1575 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"}, 1576 {"RCV Right Out", NULL, "LINMOD Mux"}, 1577 1578 {"HPL", NULL, "HP Left Out"}, 1579 {"HPR", NULL, "HP Right Out"}, 1580 {"SPKL", NULL, "SPK Left Out"}, 1581 {"SPKR", NULL, "SPK Right Out"}, 1582 {"RCVL", NULL, "RCV Left Out"}, 1583 {"RCVR", NULL, "RCV Right Out"}, 1584 }; 1585 1586 static const struct snd_soc_dapm_route max98091_dapm_routes[] = { 1587 /* DMIC inputs */ 1588 {"DMIC3", NULL, "DMIC3_ENA"}, 1589 {"DMIC4", NULL, "DMIC4_ENA"}, 1590 {"DMIC3", NULL, "AHPF"}, 1591 {"DMIC4", NULL, "AHPF"}, 1592 }; 1593 1594 static int max98090_add_widgets(struct snd_soc_component *component) 1595 { 1596 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1597 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1598 1599 snd_soc_add_component_controls(component, max98090_snd_controls, 1600 ARRAY_SIZE(max98090_snd_controls)); 1601 1602 if (max98090->devtype == MAX98091) { 1603 snd_soc_add_component_controls(component, max98091_snd_controls, 1604 ARRAY_SIZE(max98091_snd_controls)); 1605 } 1606 1607 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets, 1608 ARRAY_SIZE(max98090_dapm_widgets)); 1609 1610 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes, 1611 ARRAY_SIZE(max98090_dapm_routes)); 1612 1613 if (max98090->devtype == MAX98091) { 1614 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets, 1615 ARRAY_SIZE(max98091_dapm_widgets)); 1616 1617 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes, 1618 ARRAY_SIZE(max98091_dapm_routes)); 1619 } 1620 1621 return 0; 1622 } 1623 1624 static const int pclk_rates[] = { 1625 12000000, 12000000, 13000000, 13000000, 1626 16000000, 16000000, 19200000, 19200000 1627 }; 1628 1629 static const int lrclk_rates[] = { 1630 8000, 16000, 8000, 16000, 1631 8000, 16000, 8000, 16000 1632 }; 1633 1634 static const int user_pclk_rates[] = { 1635 13000000, 13000000, 19200000, 19200000, 1636 }; 1637 1638 static const int user_lrclk_rates[] = { 1639 44100, 48000, 44100, 48000, 1640 }; 1641 1642 static const unsigned long long ni_value[] = { 1643 3528, 768, 441, 8 1644 }; 1645 1646 static const unsigned long long mi_value[] = { 1647 8125, 1625, 1500, 25 1648 }; 1649 1650 static void max98090_configure_bclk(struct snd_soc_component *component) 1651 { 1652 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1653 unsigned long long ni; 1654 int i; 1655 1656 if (!max98090->sysclk) { 1657 dev_err(component->dev, "No SYSCLK configured\n"); 1658 return; 1659 } 1660 1661 if (!max98090->bclk || !max98090->lrclk) { 1662 dev_err(component->dev, "No audio clocks configured\n"); 1663 return; 1664 } 1665 1666 /* Skip configuration when operating as slave */ 1667 if (!(snd_soc_component_read32(component, M98090_REG_MASTER_MODE) & 1668 M98090_MAS_MASK)) { 1669 return; 1670 } 1671 1672 /* 1673 * Master mode: no need to save and restore SHDN for the following 1674 * sensitive registers. 1675 */ 1676 1677 /* Check for supported PCLK to LRCLK ratios */ 1678 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) { 1679 if ((pclk_rates[i] == max98090->sysclk) && 1680 (lrclk_rates[i] == max98090->lrclk)) { 1681 dev_dbg(component->dev, 1682 "Found supported PCLK to LRCLK rates 0x%x\n", 1683 i + 0x8); 1684 1685 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1686 M98090_FREQ_MASK, 1687 (i + 0x8) << M98090_FREQ_SHIFT); 1688 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1689 M98090_USE_M1_MASK, 0); 1690 return; 1691 } 1692 } 1693 1694 /* Check for user calculated MI and NI ratios */ 1695 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) { 1696 if ((user_pclk_rates[i] == max98090->sysclk) && 1697 (user_lrclk_rates[i] == max98090->lrclk)) { 1698 dev_dbg(component->dev, 1699 "Found user supported PCLK to LRCLK rates\n"); 1700 dev_dbg(component->dev, "i %d ni %lld mi %lld\n", 1701 i, ni_value[i], mi_value[i]); 1702 1703 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1704 M98090_FREQ_MASK, 0); 1705 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1706 M98090_USE_M1_MASK, 1707 1 << M98090_USE_M1_SHIFT); 1708 1709 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB, 1710 (ni_value[i] >> 8) & 0x7F); 1711 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, 1712 ni_value[i] & 0xFF); 1713 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_MSB, 1714 (mi_value[i] >> 8) & 0x7F); 1715 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_LSB, 1716 mi_value[i] & 0xFF); 1717 1718 return; 1719 } 1720 } 1721 1722 /* 1723 * Calculate based on MI = 65536 (not as good as either method above) 1724 */ 1725 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1726 M98090_FREQ_MASK, 0); 1727 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1728 M98090_USE_M1_MASK, 0); 1729 1730 /* 1731 * Configure NI when operating as master 1732 * Note: There is a small, but significant audio quality improvement 1733 * by calculating ni and mi. 1734 */ 1735 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) 1736 * (unsigned long long int)max98090->lrclk; 1737 do_div(ni, (unsigned long long int)max98090->sysclk); 1738 dev_info(component->dev, "No better method found\n"); 1739 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni); 1740 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB, 1741 (ni >> 8) & 0x7F); 1742 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF); 1743 } 1744 1745 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai, 1746 unsigned int fmt) 1747 { 1748 struct snd_soc_component *component = codec_dai->component; 1749 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1750 struct max98090_cdata *cdata; 1751 u8 regval; 1752 1753 max98090->dai_fmt = fmt; 1754 cdata = &max98090->dai[0]; 1755 1756 if (fmt != cdata->fmt) { 1757 cdata->fmt = fmt; 1758 1759 regval = 0; 1760 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1761 case SND_SOC_DAIFMT_CBS_CFS: 1762 /* Set to slave mode PLL - MAS mode off */ 1763 max98090_shdn_save(max98090); 1764 snd_soc_component_write(component, 1765 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00); 1766 snd_soc_component_write(component, 1767 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); 1768 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1769 M98090_USE_M1_MASK, 0); 1770 max98090_shdn_restore(max98090); 1771 max98090->master = false; 1772 break; 1773 case SND_SOC_DAIFMT_CBM_CFM: 1774 /* Set to master mode */ 1775 if (max98090->tdm_slots == 4) { 1776 /* TDM */ 1777 regval |= M98090_MAS_MASK | 1778 M98090_BSEL_64; 1779 } else if (max98090->tdm_slots == 3) { 1780 /* TDM */ 1781 regval |= M98090_MAS_MASK | 1782 M98090_BSEL_48; 1783 } else { 1784 /* Few TDM slots, or No TDM */ 1785 regval |= M98090_MAS_MASK | 1786 M98090_BSEL_32; 1787 } 1788 max98090->master = true; 1789 break; 1790 case SND_SOC_DAIFMT_CBS_CFM: 1791 case SND_SOC_DAIFMT_CBM_CFS: 1792 default: 1793 dev_err(component->dev, "DAI clock mode unsupported"); 1794 return -EINVAL; 1795 } 1796 max98090_shdn_save(max98090); 1797 snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval); 1798 max98090_shdn_restore(max98090); 1799 1800 regval = 0; 1801 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1802 case SND_SOC_DAIFMT_I2S: 1803 regval |= M98090_DLY_MASK; 1804 break; 1805 case SND_SOC_DAIFMT_LEFT_J: 1806 break; 1807 case SND_SOC_DAIFMT_RIGHT_J: 1808 regval |= M98090_RJ_MASK; 1809 break; 1810 case SND_SOC_DAIFMT_DSP_A: 1811 /* Not supported mode */ 1812 default: 1813 dev_err(component->dev, "DAI format unsupported"); 1814 return -EINVAL; 1815 } 1816 1817 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1818 case SND_SOC_DAIFMT_NB_NF: 1819 break; 1820 case SND_SOC_DAIFMT_NB_IF: 1821 regval |= M98090_WCI_MASK; 1822 break; 1823 case SND_SOC_DAIFMT_IB_NF: 1824 regval |= M98090_BCI_MASK; 1825 break; 1826 case SND_SOC_DAIFMT_IB_IF: 1827 regval |= M98090_BCI_MASK|M98090_WCI_MASK; 1828 break; 1829 default: 1830 dev_err(component->dev, "DAI invert mode unsupported"); 1831 return -EINVAL; 1832 } 1833 1834 /* 1835 * This accommodates an inverted logic in the MAX98090 chip 1836 * for Bit Clock Invert (BCI). The inverted logic is only 1837 * seen for the case of TDM mode. The remaining cases have 1838 * normal logic. 1839 */ 1840 if (max98090->tdm_slots > 1) 1841 regval ^= M98090_BCI_MASK; 1842 1843 max98090_shdn_save(max98090); 1844 snd_soc_component_write(component, 1845 M98090_REG_INTERFACE_FORMAT, regval); 1846 max98090_shdn_restore(max98090); 1847 } 1848 1849 return 0; 1850 } 1851 1852 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai, 1853 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1854 { 1855 struct snd_soc_component *component = codec_dai->component; 1856 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1857 struct max98090_cdata *cdata; 1858 1859 cdata = &max98090->dai[0]; 1860 1861 if (slots < 0 || slots > 4) 1862 return -EINVAL; 1863 1864 max98090->tdm_slots = slots; 1865 max98090->tdm_width = slot_width; 1866 1867 if (max98090->tdm_slots > 1) { 1868 max98090_shdn_save(max98090); 1869 /* SLOTL SLOTR SLOTDLY */ 1870 snd_soc_component_write(component, M98090_REG_TDM_FORMAT, 1871 0 << M98090_TDM_SLOTL_SHIFT | 1872 1 << M98090_TDM_SLOTR_SHIFT | 1873 0 << M98090_TDM_SLOTDLY_SHIFT); 1874 1875 /* FSW TDM */ 1876 snd_soc_component_update_bits(component, M98090_REG_TDM_CONTROL, 1877 M98090_TDM_MASK, 1878 M98090_TDM_MASK); 1879 max98090_shdn_restore(max98090); 1880 } 1881 1882 /* 1883 * Normally advisable to set TDM first, but this permits either order 1884 */ 1885 cdata->fmt = 0; 1886 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt); 1887 1888 return 0; 1889 } 1890 1891 static int max98090_set_bias_level(struct snd_soc_component *component, 1892 enum snd_soc_bias_level level) 1893 { 1894 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1895 int ret; 1896 1897 switch (level) { 1898 case SND_SOC_BIAS_ON: 1899 break; 1900 1901 case SND_SOC_BIAS_PREPARE: 1902 /* 1903 * SND_SOC_BIAS_PREPARE is called while preparing for a 1904 * transition to ON or away from ON. If current bias_level 1905 * is SND_SOC_BIAS_ON, then it is preparing for a transition 1906 * away from ON. Disable the clock in that case, otherwise 1907 * enable it. 1908 */ 1909 if (IS_ERR(max98090->mclk)) 1910 break; 1911 1912 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) { 1913 clk_disable_unprepare(max98090->mclk); 1914 } else { 1915 ret = clk_prepare_enable(max98090->mclk); 1916 if (ret) 1917 return ret; 1918 } 1919 break; 1920 1921 case SND_SOC_BIAS_STANDBY: 1922 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1923 ret = regcache_sync(max98090->regmap); 1924 if (ret != 0) { 1925 dev_err(component->dev, 1926 "Failed to sync cache: %d\n", ret); 1927 return ret; 1928 } 1929 } 1930 break; 1931 1932 case SND_SOC_BIAS_OFF: 1933 /* Set internal pull-up to lowest power mode */ 1934 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, 1935 M98090_JDWK_MASK, M98090_JDWK_MASK); 1936 regcache_mark_dirty(max98090->regmap); 1937 break; 1938 } 1939 return 0; 1940 } 1941 1942 static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 }; 1943 1944 static const int comp_lrclk_rates[] = { 1945 8000, 16000, 32000, 44100, 48000, 96000 1946 }; 1947 1948 struct dmic_table { 1949 int pclk; 1950 struct { 1951 int freq; 1952 int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */ 1953 } settings[6]; /* One for each dmic divisor. */ 1954 }; 1955 1956 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */ 1957 { 1958 .pclk = 11289600, 1959 .settings = { 1960 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, 1961 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, 1962 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1963 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } }, 1964 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1965 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1966 }, 1967 }, 1968 { 1969 .pclk = 12000000, 1970 .settings = { 1971 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, 1972 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, 1973 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1974 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, 1975 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1976 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1977 } 1978 }, 1979 { 1980 .pclk = 12288000, 1981 .settings = { 1982 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, 1983 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, 1984 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1985 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } }, 1986 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1987 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1988 } 1989 }, 1990 { 1991 .pclk = 13000000, 1992 .settings = { 1993 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } }, 1994 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } }, 1995 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, 1996 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } }, 1997 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, 1998 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, 1999 } 2000 }, 2001 { 2002 .pclk = 19200000, 2003 .settings = { 2004 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } }, 2005 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } }, 2006 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, 2007 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } }, 2008 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } }, 2009 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, 2010 } 2011 }, 2012 }; 2013 2014 static int max98090_find_divisor(int target_freq, int pclk) 2015 { 2016 int current_diff = INT_MAX; 2017 int test_diff = INT_MAX; 2018 int divisor_index = 0; 2019 int i; 2020 2021 for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) { 2022 test_diff = abs(target_freq - (pclk / dmic_divisors[i])); 2023 if (test_diff < current_diff) { 2024 current_diff = test_diff; 2025 divisor_index = i; 2026 } 2027 } 2028 2029 return divisor_index; 2030 } 2031 2032 static int max98090_find_closest_pclk(int pclk) 2033 { 2034 int m1; 2035 int m2; 2036 int i; 2037 2038 for (i = 0; i < ARRAY_SIZE(dmic_table); i++) { 2039 if (pclk == dmic_table[i].pclk) 2040 return i; 2041 if (pclk < dmic_table[i].pclk) { 2042 if (i == 0) 2043 return i; 2044 m1 = pclk - dmic_table[i-1].pclk; 2045 m2 = dmic_table[i].pclk - pclk; 2046 if (m1 < m2) 2047 return i - 1; 2048 else 2049 return i; 2050 } 2051 } 2052 2053 return -EINVAL; 2054 } 2055 2056 static int max98090_configure_dmic(struct max98090_priv *max98090, 2057 int target_dmic_clk, int pclk, int fs) 2058 { 2059 int micclk_index; 2060 int pclk_index; 2061 int dmic_freq; 2062 int dmic_comp; 2063 int i; 2064 2065 pclk_index = max98090_find_closest_pclk(pclk); 2066 if (pclk_index < 0) 2067 return pclk_index; 2068 2069 micclk_index = max98090_find_divisor(target_dmic_clk, pclk); 2070 2071 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { 2072 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2) 2073 break; 2074 } 2075 2076 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq; 2077 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i]; 2078 2079 max98090_shdn_save(max98090); 2080 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE, 2081 M98090_MICCLK_MASK, 2082 micclk_index << M98090_MICCLK_SHIFT); 2083 2084 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG, 2085 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK, 2086 dmic_comp << M98090_DMIC_COMP_SHIFT | 2087 dmic_freq << M98090_DMIC_FREQ_SHIFT); 2088 max98090_shdn_restore(max98090); 2089 2090 return 0; 2091 } 2092 2093 static int max98090_dai_startup(struct snd_pcm_substream *substream, 2094 struct snd_soc_dai *dai) 2095 { 2096 struct snd_soc_component *component = dai->component; 2097 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2098 unsigned int fmt = max98090->dai_fmt; 2099 2100 /* Remove 24-bit format support if it is not in right justified mode. */ 2101 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) { 2102 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; 2103 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16); 2104 } 2105 return 0; 2106 } 2107 2108 static int max98090_dai_hw_params(struct snd_pcm_substream *substream, 2109 struct snd_pcm_hw_params *params, 2110 struct snd_soc_dai *dai) 2111 { 2112 struct snd_soc_component *component = dai->component; 2113 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2114 struct max98090_cdata *cdata; 2115 2116 cdata = &max98090->dai[0]; 2117 max98090->bclk = snd_soc_params_to_bclk(params); 2118 if (params_channels(params) == 1) 2119 max98090->bclk *= 2; 2120 2121 max98090->lrclk = params_rate(params); 2122 2123 switch (params_width(params)) { 2124 case 16: 2125 max98090_shdn_save(max98090); 2126 snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT, 2127 M98090_WS_MASK, 0); 2128 max98090_shdn_restore(max98090); 2129 break; 2130 default: 2131 return -EINVAL; 2132 } 2133 2134 if (max98090->master) 2135 max98090_configure_bclk(component); 2136 2137 cdata->rate = max98090->lrclk; 2138 2139 max98090_shdn_save(max98090); 2140 /* Update filter mode */ 2141 if (max98090->lrclk < 24000) 2142 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 2143 M98090_MODE_MASK, 0); 2144 else 2145 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 2146 M98090_MODE_MASK, M98090_MODE_MASK); 2147 2148 /* Update sample rate mode */ 2149 if (max98090->lrclk < 50000) 2150 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 2151 M98090_DHF_MASK, 0); 2152 else 2153 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 2154 M98090_DHF_MASK, M98090_DHF_MASK); 2155 max98090_shdn_restore(max98090); 2156 2157 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk, 2158 max98090->lrclk); 2159 2160 return 0; 2161 } 2162 2163 /* 2164 * PLL / Sysclk 2165 */ 2166 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, 2167 int clk_id, unsigned int freq, int dir) 2168 { 2169 struct snd_soc_component *component = dai->component; 2170 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2171 2172 /* Requested clock frequency is already setup */ 2173 if (freq == max98090->sysclk) 2174 return 0; 2175 2176 if (!IS_ERR(max98090->mclk)) { 2177 freq = clk_round_rate(max98090->mclk, freq); 2178 clk_set_rate(max98090->mclk, freq); 2179 } 2180 2181 /* Setup clocks for slave mode, and using the PLL 2182 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 2183 * 0x02 (when master clk is 20MHz to 40MHz).. 2184 * 0x03 (when master clk is 40MHz to 60MHz).. 2185 */ 2186 max98090_shdn_save(max98090); 2187 if ((freq >= 10000000) && (freq <= 20000000)) { 2188 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2189 M98090_PSCLK_DIV1); 2190 max98090->pclk = freq; 2191 } else if ((freq > 20000000) && (freq <= 40000000)) { 2192 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2193 M98090_PSCLK_DIV2); 2194 max98090->pclk = freq >> 1; 2195 } else if ((freq > 40000000) && (freq <= 60000000)) { 2196 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2197 M98090_PSCLK_DIV4); 2198 max98090->pclk = freq >> 2; 2199 } else { 2200 dev_err(component->dev, "Invalid master clock frequency\n"); 2201 max98090_shdn_restore(max98090); 2202 return -EINVAL; 2203 } 2204 max98090_shdn_restore(max98090); 2205 2206 max98090->sysclk = freq; 2207 2208 return 0; 2209 } 2210 2211 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute) 2212 { 2213 struct snd_soc_component *component = codec_dai->component; 2214 int regval; 2215 2216 regval = mute ? M98090_DVM_MASK : 0; 2217 snd_soc_component_update_bits(component, M98090_REG_DAI_PLAYBACK_LEVEL, 2218 M98090_DVM_MASK, regval); 2219 2220 return 0; 2221 } 2222 2223 static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd, 2224 struct snd_soc_dai *dai) 2225 { 2226 struct snd_soc_component *component = dai->component; 2227 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2228 2229 switch (cmd) { 2230 case SNDRV_PCM_TRIGGER_START: 2231 case SNDRV_PCM_TRIGGER_RESUME: 2232 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 2233 if (!max98090->master && dai->active == 1) 2234 queue_delayed_work(system_power_efficient_wq, 2235 &max98090->pll_det_enable_work, 2236 msecs_to_jiffies(10)); 2237 break; 2238 case SNDRV_PCM_TRIGGER_STOP: 2239 case SNDRV_PCM_TRIGGER_SUSPEND: 2240 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 2241 if (!max98090->master && dai->active == 1) 2242 schedule_work(&max98090->pll_det_disable_work); 2243 break; 2244 default: 2245 break; 2246 } 2247 2248 return 0; 2249 } 2250 2251 static void max98090_pll_det_enable_work(struct work_struct *work) 2252 { 2253 struct max98090_priv *max98090 = 2254 container_of(work, struct max98090_priv, 2255 pll_det_enable_work.work); 2256 struct snd_soc_component *component = max98090->component; 2257 unsigned int status, mask; 2258 2259 /* 2260 * Clear status register in order to clear possibly already occurred 2261 * PLL unlock. If PLL hasn't still locked, the status will be set 2262 * again and PLL unlock interrupt will occur. 2263 * Note this will clear all status bits 2264 */ 2265 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); 2266 2267 /* 2268 * Queue jack work in case jack state has just changed but handler 2269 * hasn't run yet 2270 */ 2271 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); 2272 status &= mask; 2273 if (status & M98090_JDET_MASK) 2274 queue_delayed_work(system_power_efficient_wq, 2275 &max98090->jack_work, 2276 msecs_to_jiffies(100)); 2277 2278 /* Enable PLL unlock interrupt */ 2279 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2280 M98090_IULK_MASK, 2281 1 << M98090_IULK_SHIFT); 2282 } 2283 2284 static void max98090_pll_det_disable_work(struct work_struct *work) 2285 { 2286 struct max98090_priv *max98090 = 2287 container_of(work, struct max98090_priv, pll_det_disable_work); 2288 struct snd_soc_component *component = max98090->component; 2289 2290 cancel_delayed_work_sync(&max98090->pll_det_enable_work); 2291 2292 /* Disable PLL unlock interrupt */ 2293 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2294 M98090_IULK_MASK, 0); 2295 } 2296 2297 static void max98090_pll_work(struct max98090_priv *max98090) 2298 { 2299 struct snd_soc_component *component = max98090->component; 2300 unsigned int pll; 2301 int i; 2302 2303 if (!snd_soc_component_is_active(component)) 2304 return; 2305 2306 dev_info_ratelimited(component->dev, "PLL unlocked\n"); 2307 2308 /* 2309 * As the datasheet suggested, the maximum PLL lock time should be 2310 * 7 msec. The workaround resets the codec softly by toggling SHDN 2311 * off and on if PLL failed to lock for 10 msec. Notably, there is 2312 * no suggested hold time for SHDN off. 2313 */ 2314 2315 /* Toggle shutdown OFF then ON */ 2316 mutex_lock(&component->card->dapm_mutex); 2317 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2318 M98090_SHDNN_MASK, 0); 2319 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2320 M98090_SHDNN_MASK, M98090_SHDNN_MASK); 2321 mutex_unlock(&component->card->dapm_mutex); 2322 2323 for (i = 0; i < 10; ++i) { 2324 /* Give PLL time to lock */ 2325 usleep_range(1000, 1200); 2326 2327 /* Check lock status */ 2328 pll = snd_soc_component_read32( 2329 component, M98090_REG_DEVICE_STATUS); 2330 if (!(pll & M98090_ULK_MASK)) 2331 break; 2332 } 2333 } 2334 2335 static void max98090_jack_work(struct work_struct *work) 2336 { 2337 struct max98090_priv *max98090 = container_of(work, 2338 struct max98090_priv, 2339 jack_work.work); 2340 struct snd_soc_component *component = max98090->component; 2341 int status = 0; 2342 int reg; 2343 2344 /* Read a second time */ 2345 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { 2346 2347 /* Strong pull up allows mic detection */ 2348 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, 2349 M98090_JDWK_MASK, 0); 2350 2351 msleep(50); 2352 2353 reg = snd_soc_component_read32(component, M98090_REG_JACK_STATUS); 2354 2355 /* Weak pull up allows only insertion detection */ 2356 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, 2357 M98090_JDWK_MASK, M98090_JDWK_MASK); 2358 } else { 2359 reg = snd_soc_component_read32(component, M98090_REG_JACK_STATUS); 2360 } 2361 2362 reg = snd_soc_component_read32(component, M98090_REG_JACK_STATUS); 2363 2364 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { 2365 case M98090_LSNS_MASK | M98090_JKSNS_MASK: 2366 dev_dbg(component->dev, "No Headset Detected\n"); 2367 2368 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2369 2370 status |= 0; 2371 2372 break; 2373 2374 case 0: 2375 if (max98090->jack_state == 2376 M98090_JACK_STATE_HEADSET) { 2377 2378 dev_dbg(component->dev, 2379 "Headset Button Down Detected\n"); 2380 2381 /* 2382 * max98090_headset_button_event(codec) 2383 * could be defined, then called here. 2384 */ 2385 2386 status |= SND_JACK_HEADSET; 2387 status |= SND_JACK_BTN_0; 2388 2389 break; 2390 } 2391 2392 /* Line is reported as Headphone */ 2393 /* Nokia Headset is reported as Headphone */ 2394 /* Mono Headphone is reported as Headphone */ 2395 dev_dbg(component->dev, "Headphone Detected\n"); 2396 2397 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; 2398 2399 status |= SND_JACK_HEADPHONE; 2400 2401 break; 2402 2403 case M98090_JKSNS_MASK: 2404 dev_dbg(component->dev, "Headset Detected\n"); 2405 2406 max98090->jack_state = M98090_JACK_STATE_HEADSET; 2407 2408 status |= SND_JACK_HEADSET; 2409 2410 break; 2411 2412 default: 2413 dev_dbg(component->dev, "Unrecognized Jack Status\n"); 2414 break; 2415 } 2416 2417 snd_soc_jack_report(max98090->jack, status, 2418 SND_JACK_HEADSET | SND_JACK_BTN_0); 2419 } 2420 2421 static irqreturn_t max98090_interrupt(int irq, void *data) 2422 { 2423 struct max98090_priv *max98090 = data; 2424 struct snd_soc_component *component = max98090->component; 2425 int ret; 2426 unsigned int mask; 2427 unsigned int active; 2428 2429 /* Treat interrupt before codec is initialized as spurious */ 2430 if (component == NULL) 2431 return IRQ_NONE; 2432 2433 dev_dbg(component->dev, "***** max98090_interrupt *****\n"); 2434 2435 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); 2436 2437 if (ret != 0) { 2438 dev_err(component->dev, 2439 "failed to read M98090_REG_INTERRUPT_S: %d\n", 2440 ret); 2441 return IRQ_NONE; 2442 } 2443 2444 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); 2445 2446 if (ret != 0) { 2447 dev_err(component->dev, 2448 "failed to read M98090_REG_DEVICE_STATUS: %d\n", 2449 ret); 2450 return IRQ_NONE; 2451 } 2452 2453 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", 2454 active, mask, active & mask); 2455 2456 active &= mask; 2457 2458 if (!active) 2459 return IRQ_NONE; 2460 2461 if (active & M98090_CLD_MASK) 2462 dev_err(component->dev, "M98090_CLD_MASK\n"); 2463 2464 if (active & M98090_SLD_MASK) 2465 dev_dbg(component->dev, "M98090_SLD_MASK\n"); 2466 2467 if (active & M98090_ULK_MASK) { 2468 dev_dbg(component->dev, "M98090_ULK_MASK\n"); 2469 max98090_pll_work(max98090); 2470 } 2471 2472 if (active & M98090_JDET_MASK) { 2473 dev_dbg(component->dev, "M98090_JDET_MASK\n"); 2474 2475 pm_wakeup_event(component->dev, 100); 2476 2477 queue_delayed_work(system_power_efficient_wq, 2478 &max98090->jack_work, 2479 msecs_to_jiffies(100)); 2480 } 2481 2482 if (active & M98090_DRCACT_MASK) 2483 dev_dbg(component->dev, "M98090_DRCACT_MASK\n"); 2484 2485 if (active & M98090_DRCCLP_MASK) 2486 dev_err(component->dev, "M98090_DRCCLP_MASK\n"); 2487 2488 return IRQ_HANDLED; 2489 } 2490 2491 /** 2492 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ 2493 * 2494 * @component: MAX98090 component 2495 * @jack: jack to report detection events on 2496 * 2497 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are 2498 * being used to bring out signals to the processor then only platform 2499 * data configuration is needed for MAX98090 and processor GPIOs should 2500 * be configured using snd_soc_jack_add_gpios() instead. 2501 * 2502 * If no jack is supplied detection will be disabled. 2503 */ 2504 int max98090_mic_detect(struct snd_soc_component *component, 2505 struct snd_soc_jack *jack) 2506 { 2507 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2508 2509 dev_dbg(component->dev, "max98090_mic_detect\n"); 2510 2511 max98090->jack = jack; 2512 if (jack) { 2513 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2514 M98090_IJDET_MASK, 2515 1 << M98090_IJDET_SHIFT); 2516 } else { 2517 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2518 M98090_IJDET_MASK, 2519 0); 2520 } 2521 2522 /* Send an initial empty report */ 2523 snd_soc_jack_report(max98090->jack, 0, 2524 SND_JACK_HEADSET | SND_JACK_BTN_0); 2525 2526 queue_delayed_work(system_power_efficient_wq, 2527 &max98090->jack_work, 2528 msecs_to_jiffies(100)); 2529 2530 return 0; 2531 } 2532 EXPORT_SYMBOL_GPL(max98090_mic_detect); 2533 2534 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 2535 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 2536 2537 static const struct snd_soc_dai_ops max98090_dai_ops = { 2538 .startup = max98090_dai_startup, 2539 .set_sysclk = max98090_dai_set_sysclk, 2540 .set_fmt = max98090_dai_set_fmt, 2541 .set_tdm_slot = max98090_set_tdm_slot, 2542 .hw_params = max98090_dai_hw_params, 2543 .digital_mute = max98090_dai_digital_mute, 2544 .trigger = max98090_dai_trigger, 2545 }; 2546 2547 static struct snd_soc_dai_driver max98090_dai[] = { 2548 { 2549 .name = "HiFi", 2550 .playback = { 2551 .stream_name = "HiFi Playback", 2552 .channels_min = 2, 2553 .channels_max = 2, 2554 .rates = MAX98090_RATES, 2555 .formats = MAX98090_FORMATS, 2556 }, 2557 .capture = { 2558 .stream_name = "HiFi Capture", 2559 .channels_min = 1, 2560 .channels_max = 2, 2561 .rates = MAX98090_RATES, 2562 .formats = MAX98090_FORMATS, 2563 }, 2564 .ops = &max98090_dai_ops, 2565 } 2566 }; 2567 2568 static int max98090_probe(struct snd_soc_component *component) 2569 { 2570 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2571 struct max98090_cdata *cdata; 2572 enum max98090_type devtype; 2573 int ret = 0; 2574 int err; 2575 unsigned int micbias; 2576 2577 dev_dbg(component->dev, "max98090_probe\n"); 2578 2579 max98090->mclk = devm_clk_get(component->dev, "mclk"); 2580 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER) 2581 return -EPROBE_DEFER; 2582 2583 max98090->component = component; 2584 2585 /* Reset the codec, the DSP core, and disable all interrupts */ 2586 max98090_reset(max98090); 2587 2588 /* Initialize private data */ 2589 2590 max98090->sysclk = (unsigned)-1; 2591 max98090->pclk = (unsigned)-1; 2592 max98090->master = false; 2593 2594 cdata = &max98090->dai[0]; 2595 cdata->rate = (unsigned)-1; 2596 cdata->fmt = (unsigned)-1; 2597 2598 max98090->lin_state = 0; 2599 max98090->pa1en = 0; 2600 max98090->pa2en = 0; 2601 2602 ret = snd_soc_component_read32(component, M98090_REG_REVISION_ID); 2603 if (ret < 0) { 2604 dev_err(component->dev, "Failed to read device revision: %d\n", 2605 ret); 2606 goto err_access; 2607 } 2608 2609 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) { 2610 devtype = MAX98090; 2611 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret); 2612 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) { 2613 devtype = MAX98091; 2614 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret); 2615 } else { 2616 devtype = MAX98090; 2617 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret); 2618 } 2619 2620 if (max98090->devtype != devtype) { 2621 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n"); 2622 max98090->devtype = devtype; 2623 } 2624 2625 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2626 2627 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); 2628 INIT_DELAYED_WORK(&max98090->pll_det_enable_work, 2629 max98090_pll_det_enable_work); 2630 INIT_WORK(&max98090->pll_det_disable_work, 2631 max98090_pll_det_disable_work); 2632 2633 /* Enable jack detection */ 2634 snd_soc_component_write(component, M98090_REG_JACK_DETECT, 2635 M98090_JDETEN_MASK | M98090_JDEB_25MS); 2636 2637 /* 2638 * Clear any old interrupts. 2639 * An old interrupt ocurring prior to installing the ISR 2640 * can keep a new interrupt from generating a trigger. 2641 */ 2642 snd_soc_component_read32(component, M98090_REG_DEVICE_STATUS); 2643 2644 /* 2645 * SHDN should be 0 at the point, no need to save/restore for the 2646 * following registers. 2647 * 2648 * High Performance is default 2649 */ 2650 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL, 2651 M98090_DACHP_MASK, 2652 1 << M98090_DACHP_SHIFT); 2653 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL, 2654 M98090_PERFMODE_MASK, 2655 0 << M98090_PERFMODE_SHIFT); 2656 snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL, 2657 M98090_ADCHP_MASK, 2658 1 << M98090_ADCHP_SHIFT); 2659 2660 /* 2661 * SHDN should be 0 at the point, no need to save/restore for the 2662 * following registers. 2663 * 2664 * Turn on VCM bandgap reference 2665 */ 2666 snd_soc_component_write(component, M98090_REG_BIAS_CONTROL, 2667 M98090_VCM_MODE_MASK); 2668 2669 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias); 2670 if (err) { 2671 micbias = M98090_MBVSEL_2V8; 2672 dev_info(component->dev, "use default 2.8v micbias\n"); 2673 } else if (micbias > M98090_MBVSEL_2V8) { 2674 dev_err(component->dev, "micbias out of range 0x%x\n", micbias); 2675 micbias = M98090_MBVSEL_2V8; 2676 } 2677 2678 snd_soc_component_update_bits(component, M98090_REG_MIC_BIAS_VOLTAGE, 2679 M98090_MBVSEL_MASK, micbias); 2680 2681 max98090_add_widgets(component); 2682 2683 err_access: 2684 return ret; 2685 } 2686 2687 static void max98090_remove(struct snd_soc_component *component) 2688 { 2689 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2690 2691 cancel_delayed_work_sync(&max98090->jack_work); 2692 cancel_delayed_work_sync(&max98090->pll_det_enable_work); 2693 cancel_work_sync(&max98090->pll_det_disable_work); 2694 max98090->component = NULL; 2695 } 2696 2697 static const struct snd_soc_component_driver soc_component_dev_max98090 = { 2698 .probe = max98090_probe, 2699 .remove = max98090_remove, 2700 .set_bias_level = max98090_set_bias_level, 2701 .idle_bias_on = 1, 2702 .use_pmdown_time = 1, 2703 .endianness = 1, 2704 .non_legacy_dai_naming = 1, 2705 }; 2706 2707 static const struct regmap_config max98090_regmap = { 2708 .reg_bits = 8, 2709 .val_bits = 8, 2710 2711 .max_register = MAX98090_MAX_REGISTER, 2712 .reg_defaults = max98090_reg, 2713 .num_reg_defaults = ARRAY_SIZE(max98090_reg), 2714 .volatile_reg = max98090_volatile_register, 2715 .readable_reg = max98090_readable_register, 2716 .cache_type = REGCACHE_RBTREE, 2717 }; 2718 2719 static int max98090_i2c_probe(struct i2c_client *i2c, 2720 const struct i2c_device_id *i2c_id) 2721 { 2722 struct max98090_priv *max98090; 2723 const struct acpi_device_id *acpi_id; 2724 kernel_ulong_t driver_data = 0; 2725 int ret; 2726 2727 pr_debug("max98090_i2c_probe\n"); 2728 2729 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), 2730 GFP_KERNEL); 2731 if (max98090 == NULL) 2732 return -ENOMEM; 2733 2734 if (ACPI_HANDLE(&i2c->dev)) { 2735 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table, 2736 &i2c->dev); 2737 if (!acpi_id) { 2738 dev_err(&i2c->dev, "No driver data\n"); 2739 return -EINVAL; 2740 } 2741 driver_data = acpi_id->driver_data; 2742 } else if (i2c_id) { 2743 driver_data = i2c_id->driver_data; 2744 } 2745 2746 max98090->devtype = driver_data; 2747 i2c_set_clientdata(i2c, max98090); 2748 max98090->pdata = i2c->dev.platform_data; 2749 2750 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq", 2751 &max98090->dmic_freq); 2752 if (ret < 0) 2753 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ; 2754 2755 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); 2756 if (IS_ERR(max98090->regmap)) { 2757 ret = PTR_ERR(max98090->regmap); 2758 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 2759 goto err_enable; 2760 } 2761 2762 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 2763 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2764 "max98090_interrupt", max98090); 2765 if (ret < 0) { 2766 dev_err(&i2c->dev, "request_irq failed: %d\n", 2767 ret); 2768 return ret; 2769 } 2770 2771 ret = devm_snd_soc_register_component(&i2c->dev, 2772 &soc_component_dev_max98090, max98090_dai, 2773 ARRAY_SIZE(max98090_dai)); 2774 err_enable: 2775 return ret; 2776 } 2777 2778 static void max98090_i2c_shutdown(struct i2c_client *i2c) 2779 { 2780 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev); 2781 2782 /* 2783 * Enable volume smoothing, disable zero cross. This will cause 2784 * a quick 40ms ramp to mute on shutdown. 2785 */ 2786 regmap_write(max98090->regmap, 2787 M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK); 2788 regmap_write(max98090->regmap, 2789 M98090_REG_DEVICE_SHUTDOWN, 0x00); 2790 msleep(40); 2791 } 2792 2793 static int max98090_i2c_remove(struct i2c_client *client) 2794 { 2795 max98090_i2c_shutdown(client); 2796 2797 return 0; 2798 } 2799 2800 #ifdef CONFIG_PM 2801 static int max98090_runtime_resume(struct device *dev) 2802 { 2803 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2804 2805 regcache_cache_only(max98090->regmap, false); 2806 2807 max98090_reset(max98090); 2808 2809 regcache_sync(max98090->regmap); 2810 2811 return 0; 2812 } 2813 2814 static int max98090_runtime_suspend(struct device *dev) 2815 { 2816 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2817 2818 regcache_cache_only(max98090->regmap, true); 2819 2820 return 0; 2821 } 2822 #endif 2823 2824 #ifdef CONFIG_PM_SLEEP 2825 static int max98090_resume(struct device *dev) 2826 { 2827 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2828 unsigned int status; 2829 2830 regcache_mark_dirty(max98090->regmap); 2831 2832 max98090_reset(max98090); 2833 2834 /* clear IRQ status */ 2835 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); 2836 2837 regcache_sync(max98090->regmap); 2838 2839 return 0; 2840 } 2841 #endif 2842 2843 static const struct dev_pm_ops max98090_pm = { 2844 SET_RUNTIME_PM_OPS(max98090_runtime_suspend, 2845 max98090_runtime_resume, NULL) 2846 SET_SYSTEM_SLEEP_PM_OPS(NULL, max98090_resume) 2847 }; 2848 2849 static const struct i2c_device_id max98090_i2c_id[] = { 2850 { "max98090", MAX98090 }, 2851 { "max98091", MAX98091 }, 2852 { } 2853 }; 2854 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); 2855 2856 static const struct of_device_id max98090_of_match[] = { 2857 { .compatible = "maxim,max98090", }, 2858 { .compatible = "maxim,max98091", }, 2859 { } 2860 }; 2861 MODULE_DEVICE_TABLE(of, max98090_of_match); 2862 2863 #ifdef CONFIG_ACPI 2864 static const struct acpi_device_id max98090_acpi_match[] = { 2865 { "193C9890", MAX98090 }, 2866 { } 2867 }; 2868 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match); 2869 #endif 2870 2871 static struct i2c_driver max98090_i2c_driver = { 2872 .driver = { 2873 .name = "max98090", 2874 .pm = &max98090_pm, 2875 .of_match_table = of_match_ptr(max98090_of_match), 2876 .acpi_match_table = ACPI_PTR(max98090_acpi_match), 2877 }, 2878 .probe = max98090_i2c_probe, 2879 .shutdown = max98090_i2c_shutdown, 2880 .remove = max98090_i2c_remove, 2881 .id_table = max98090_i2c_id, 2882 }; 2883 2884 module_i2c_driver(max98090_i2c_driver); 2885 2886 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); 2887 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong"); 2888 MODULE_LICENSE("GPL"); 2889