1 /* 2 * max98090.c -- MAX98090 ALSA SoC Audio driver 3 * 4 * Copyright 2011-2012 Maxim Integrated Products 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/i2c.h> 13 #include <linux/module.h> 14 #include <linux/pm.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/slab.h> 18 #include <sound/jack.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/tlv.h> 23 #include <sound/max98090.h> 24 #include "max98090.h" 25 26 #define DEBUG 27 #define EXTMIC_METHOD 28 #define EXTMIC_METHOD_TEST 29 30 /* Allows for sparsely populated register maps */ 31 static struct reg_default max98090_reg[] = { 32 { 0x00, 0x00 }, /* 00 Software Reset */ 33 { 0x03, 0x04 }, /* 03 Interrupt Masks */ 34 { 0x04, 0x00 }, /* 04 System Clock Quick */ 35 { 0x05, 0x00 }, /* 05 Sample Rate Quick */ 36 { 0x06, 0x00 }, /* 06 DAI Interface Quick */ 37 { 0x07, 0x00 }, /* 07 DAC Path Quick */ 38 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */ 39 { 0x09, 0x00 }, /* 09 Line to ADC Quick */ 40 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */ 41 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */ 42 { 0x0C, 0x00 }, /* 0C Reserved */ 43 { 0x0D, 0x00 }, /* 0D Input Config */ 44 { 0x0E, 0x1B }, /* 0E Line Input Level */ 45 { 0x0F, 0x00 }, /* 0F Line Config */ 46 47 { 0x10, 0x14 }, /* 10 Mic1 Input Level */ 48 { 0x11, 0x14 }, /* 11 Mic2 Input Level */ 49 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */ 50 { 0x13, 0x00 }, /* 13 Digital Mic Config */ 51 { 0x14, 0x00 }, /* 14 Digital Mic Mode */ 52 { 0x15, 0x00 }, /* 15 Left ADC Mixer */ 53 { 0x16, 0x00 }, /* 16 Right ADC Mixer */ 54 { 0x17, 0x03 }, /* 17 Left ADC Level */ 55 { 0x18, 0x03 }, /* 18 Right ADC Level */ 56 { 0x19, 0x00 }, /* 19 ADC Biquad Level */ 57 { 0x1A, 0x00 }, /* 1A ADC Sidetone */ 58 { 0x1B, 0x00 }, /* 1B System Clock */ 59 { 0x1C, 0x00 }, /* 1C Clock Mode */ 60 { 0x1D, 0x00 }, /* 1D Any Clock 1 */ 61 { 0x1E, 0x00 }, /* 1E Any Clock 2 */ 62 { 0x1F, 0x00 }, /* 1F Any Clock 3 */ 63 64 { 0x20, 0x00 }, /* 20 Any Clock 4 */ 65 { 0x21, 0x00 }, /* 21 Master Mode */ 66 { 0x22, 0x00 }, /* 22 Interface Format */ 67 { 0x23, 0x00 }, /* 23 TDM Format 1*/ 68 { 0x24, 0x00 }, /* 24 TDM Format 2*/ 69 { 0x25, 0x00 }, /* 25 I/O Configuration */ 70 { 0x26, 0x80 }, /* 26 Filter Config */ 71 { 0x27, 0x00 }, /* 27 DAI Playback Level */ 72 { 0x28, 0x00 }, /* 28 EQ Playback Level */ 73 { 0x29, 0x00 }, /* 29 Left HP Mixer */ 74 { 0x2A, 0x00 }, /* 2A Right HP Mixer */ 75 { 0x2B, 0x00 }, /* 2B HP Control */ 76 { 0x2C, 0x1A }, /* 2C Left HP Volume */ 77 { 0x2D, 0x1A }, /* 2D Right HP Volume */ 78 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */ 79 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */ 80 81 { 0x30, 0x00 }, /* 30 Spk Control */ 82 { 0x31, 0x2C }, /* 31 Left Spk Volume */ 83 { 0x32, 0x2C }, /* 32 Right Spk Volume */ 84 { 0x33, 0x00 }, /* 33 ALC Timing */ 85 { 0x34, 0x00 }, /* 34 ALC Compressor */ 86 { 0x35, 0x00 }, /* 35 ALC Expander */ 87 { 0x36, 0x00 }, /* 36 ALC Gain */ 88 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */ 89 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */ 90 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */ 91 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */ 92 { 0x3B, 0x00 }, /* 3B Line OutR Control */ 93 { 0x3C, 0x15 }, /* 3C Line OutR Volume */ 94 { 0x3D, 0x00 }, /* 3D Jack Detect */ 95 { 0x3E, 0x00 }, /* 3E Input Enable */ 96 { 0x3F, 0x00 }, /* 3F Output Enable */ 97 98 { 0x40, 0x00 }, /* 40 Level Control */ 99 { 0x41, 0x00 }, /* 41 DSP Filter Enable */ 100 { 0x42, 0x00 }, /* 42 Bias Control */ 101 { 0x43, 0x00 }, /* 43 DAC Control */ 102 { 0x44, 0x06 }, /* 44 ADC Control */ 103 { 0x45, 0x00 }, /* 45 Device Shutdown */ 104 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */ 105 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */ 106 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */ 107 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */ 108 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */ 109 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */ 110 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */ 111 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */ 112 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */ 113 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */ 114 115 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */ 116 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */ 117 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */ 118 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */ 119 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */ 120 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */ 121 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */ 122 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */ 123 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */ 124 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */ 125 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */ 126 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */ 127 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */ 128 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */ 129 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */ 130 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */ 131 132 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */ 133 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */ 134 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */ 135 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */ 136 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */ 137 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */ 138 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */ 139 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */ 140 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */ 141 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */ 142 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */ 143 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */ 144 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */ 145 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */ 146 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */ 147 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */ 148 149 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */ 150 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */ 151 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */ 152 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */ 153 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */ 154 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */ 155 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */ 156 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */ 157 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */ 158 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */ 159 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */ 160 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */ 161 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */ 162 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */ 163 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */ 164 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */ 165 166 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */ 167 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */ 168 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */ 169 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */ 170 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */ 171 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */ 172 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */ 173 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */ 174 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */ 175 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */ 176 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */ 177 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */ 178 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */ 179 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */ 180 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */ 181 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */ 182 183 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */ 184 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */ 185 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */ 186 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */ 187 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */ 188 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */ 189 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */ 190 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */ 191 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */ 192 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */ 193 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */ 194 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */ 195 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */ 196 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */ 197 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */ 198 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */ 199 200 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */ 201 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */ 202 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */ 203 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */ 204 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */ 205 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */ 206 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */ 207 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */ 208 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */ 209 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */ 210 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */ 211 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */ 212 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */ 213 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */ 214 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */ 215 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */ 216 217 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */ 218 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */ 219 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */ 220 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */ 221 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */ 222 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */ 223 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */ 224 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */ 225 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */ 226 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */ 227 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */ 228 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */ 229 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */ 230 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */ 231 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */ 232 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */ 233 234 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */ 235 { 0xC1, 0x00 }, /* C1 Record TDM Slot */ 236 { 0xC2, 0x00 }, /* C2 Sample Rate */ 237 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */ 238 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */ 239 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */ 240 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */ 241 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */ 242 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */ 243 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */ 244 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */ 245 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */ 246 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */ 247 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */ 248 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */ 249 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */ 250 251 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */ 252 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */ 253 }; 254 255 static bool max98090_volatile_register(struct device *dev, unsigned int reg) 256 { 257 switch (reg) { 258 case M98090_REG_DEVICE_STATUS: 259 case M98090_REG_JACK_STATUS: 260 case M98090_REG_REVISION_ID: 261 return true; 262 default: 263 return false; 264 } 265 } 266 267 static bool max98090_readable_register(struct device *dev, unsigned int reg) 268 { 269 switch (reg) { 270 case M98090_REG_DEVICE_STATUS: 271 case M98090_REG_JACK_STATUS: 272 case M98090_REG_INTERRUPT_S: 273 case M98090_REG_RESERVED: 274 case M98090_REG_LINE_INPUT_CONFIG: 275 case M98090_REG_LINE_INPUT_LEVEL: 276 case M98090_REG_INPUT_MODE: 277 case M98090_REG_MIC1_INPUT_LEVEL: 278 case M98090_REG_MIC2_INPUT_LEVEL: 279 case M98090_REG_MIC_BIAS_VOLTAGE: 280 case M98090_REG_DIGITAL_MIC_ENABLE: 281 case M98090_REG_DIGITAL_MIC_CONFIG: 282 case M98090_REG_LEFT_ADC_MIXER: 283 case M98090_REG_RIGHT_ADC_MIXER: 284 case M98090_REG_LEFT_ADC_LEVEL: 285 case M98090_REG_RIGHT_ADC_LEVEL: 286 case M98090_REG_ADC_BIQUAD_LEVEL: 287 case M98090_REG_ADC_SIDETONE: 288 case M98090_REG_SYSTEM_CLOCK: 289 case M98090_REG_CLOCK_MODE: 290 case M98090_REG_CLOCK_RATIO_NI_MSB: 291 case M98090_REG_CLOCK_RATIO_NI_LSB: 292 case M98090_REG_CLOCK_RATIO_MI_MSB: 293 case M98090_REG_CLOCK_RATIO_MI_LSB: 294 case M98090_REG_MASTER_MODE: 295 case M98090_REG_INTERFACE_FORMAT: 296 case M98090_REG_TDM_CONTROL: 297 case M98090_REG_TDM_FORMAT: 298 case M98090_REG_IO_CONFIGURATION: 299 case M98090_REG_FILTER_CONFIG: 300 case M98090_REG_DAI_PLAYBACK_LEVEL: 301 case M98090_REG_DAI_PLAYBACK_LEVEL_EQ: 302 case M98090_REG_LEFT_HP_MIXER: 303 case M98090_REG_RIGHT_HP_MIXER: 304 case M98090_REG_HP_CONTROL: 305 case M98090_REG_LEFT_HP_VOLUME: 306 case M98090_REG_RIGHT_HP_VOLUME: 307 case M98090_REG_LEFT_SPK_MIXER: 308 case M98090_REG_RIGHT_SPK_MIXER: 309 case M98090_REG_SPK_CONTROL: 310 case M98090_REG_LEFT_SPK_VOLUME: 311 case M98090_REG_RIGHT_SPK_VOLUME: 312 case M98090_REG_DRC_TIMING: 313 case M98090_REG_DRC_COMPRESSOR: 314 case M98090_REG_DRC_EXPANDER: 315 case M98090_REG_DRC_GAIN: 316 case M98090_REG_RCV_LOUTL_MIXER: 317 case M98090_REG_RCV_LOUTL_CONTROL: 318 case M98090_REG_RCV_LOUTL_VOLUME: 319 case M98090_REG_LOUTR_MIXER: 320 case M98090_REG_LOUTR_CONTROL: 321 case M98090_REG_LOUTR_VOLUME: 322 case M98090_REG_JACK_DETECT: 323 case M98090_REG_INPUT_ENABLE: 324 case M98090_REG_OUTPUT_ENABLE: 325 case M98090_REG_LEVEL_CONTROL: 326 case M98090_REG_DSP_FILTER_ENABLE: 327 case M98090_REG_BIAS_CONTROL: 328 case M98090_REG_DAC_CONTROL: 329 case M98090_REG_ADC_CONTROL: 330 case M98090_REG_DEVICE_SHUTDOWN: 331 case M98090_REG_EQUALIZER_BASE ... M98090_REG_EQUALIZER_BASE + 0x68: 332 case M98090_REG_RECORD_BIQUAD_BASE ... M98090_REG_RECORD_BIQUAD_BASE + 0x0E: 333 case M98090_REG_DMIC3_VOLUME: 334 case M98090_REG_DMIC4_VOLUME: 335 case M98090_REG_DMIC34_BQ_PREATTEN: 336 case M98090_REG_RECORD_TDM_SLOT: 337 case M98090_REG_SAMPLE_RATE: 338 case M98090_REG_DMIC34_BIQUAD_BASE ... M98090_REG_DMIC34_BIQUAD_BASE + 0x0E: 339 case M98090_REG_REVISION_ID: 340 return true; 341 default: 342 return false; 343 } 344 } 345 346 static int max98090_reset(struct max98090_priv *max98090) 347 { 348 int ret; 349 350 /* Reset the codec by writing to this write-only reset register */ 351 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, 352 M98090_SWRESET_MASK); 353 if (ret < 0) { 354 dev_err(max98090->codec->dev, 355 "Failed to reset codec: %d\n", ret); 356 return ret; 357 } 358 359 msleep(20); 360 return ret; 361 } 362 363 static const unsigned int max98090_micboost_tlv[] = { 364 TLV_DB_RANGE_HEAD(2), 365 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 366 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), 367 }; 368 369 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0); 370 371 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv, 372 -600, 600, 0); 373 374 static const unsigned int max98090_line_tlv[] = { 375 TLV_DB_RANGE_HEAD(2), 376 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0), 377 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0), 378 }; 379 380 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0); 381 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0); 382 383 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0); 384 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0); 385 386 static const DECLARE_TLV_DB_SCALE(max98090_sidetone_tlv, -6050, 200, 0); 387 388 static const DECLARE_TLV_DB_SCALE(max98090_alc_tlv, -1500, 100, 0); 389 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0); 390 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0); 391 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0); 392 393 static const unsigned int max98090_mixout_tlv[] = { 394 TLV_DB_RANGE_HEAD(2), 395 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0), 396 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0), 397 }; 398 399 static const unsigned int max98090_hp_tlv[] = { 400 TLV_DB_RANGE_HEAD(5), 401 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 402 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 403 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 404 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 405 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0), 406 }; 407 408 static const unsigned int max98090_spk_tlv[] = { 409 TLV_DB_RANGE_HEAD(5), 410 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0), 411 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0), 412 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0), 413 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0), 414 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0), 415 }; 416 417 static const unsigned int max98090_rcv_lout_tlv[] = { 418 TLV_DB_RANGE_HEAD(5), 419 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 420 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 421 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 422 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 423 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0), 424 }; 425 426 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol, 427 struct snd_ctl_elem_value *ucontrol) 428 { 429 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 430 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 431 struct soc_mixer_control *mc = 432 (struct soc_mixer_control *)kcontrol->private_value; 433 unsigned int mask = (1 << fls(mc->max)) - 1; 434 unsigned int val = snd_soc_read(codec, mc->reg); 435 unsigned int *select; 436 437 switch (mc->reg) { 438 case M98090_REG_MIC1_INPUT_LEVEL: 439 select = &(max98090->pa1en); 440 break; 441 case M98090_REG_MIC2_INPUT_LEVEL: 442 select = &(max98090->pa2en); 443 break; 444 case M98090_REG_ADC_SIDETONE: 445 select = &(max98090->sidetone); 446 break; 447 default: 448 return -EINVAL; 449 } 450 451 val = (val >> mc->shift) & mask; 452 453 if (val >= 1) { 454 /* If on, return the volume */ 455 val = val - 1; 456 *select = val; 457 } else { 458 /* If off, return last stored value */ 459 val = *select; 460 } 461 462 ucontrol->value.integer.value[0] = val; 463 return 0; 464 } 465 466 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol, 467 struct snd_ctl_elem_value *ucontrol) 468 { 469 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 470 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 471 struct soc_mixer_control *mc = 472 (struct soc_mixer_control *)kcontrol->private_value; 473 unsigned int mask = (1 << fls(mc->max)) - 1; 474 unsigned int sel = ucontrol->value.integer.value[0]; 475 unsigned int val = snd_soc_read(codec, mc->reg); 476 unsigned int *select; 477 478 switch (mc->reg) { 479 case M98090_REG_MIC1_INPUT_LEVEL: 480 select = &(max98090->pa1en); 481 break; 482 case M98090_REG_MIC2_INPUT_LEVEL: 483 select = &(max98090->pa2en); 484 break; 485 case M98090_REG_ADC_SIDETONE: 486 select = &(max98090->sidetone); 487 break; 488 default: 489 return -EINVAL; 490 } 491 492 val = (val >> mc->shift) & mask; 493 494 *select = sel; 495 496 /* Setting a volume is only valid if it is already On */ 497 if (val >= 1) { 498 sel = sel + 1; 499 } else { 500 /* Write what was already there */ 501 sel = val; 502 } 503 504 snd_soc_update_bits(codec, mc->reg, 505 mask << mc->shift, 506 sel << mc->shift); 507 508 return 0; 509 } 510 511 static const char *max98090_perf_pwr_text[] = 512 { "High Performance", "Low Power" }; 513 static const char *max98090_pwr_perf_text[] = 514 { "Low Power", "High Performance" }; 515 516 static const struct soc_enum max98090_vcmbandgap_enum = 517 SOC_ENUM_SINGLE(M98090_REG_BIAS_CONTROL, M98090_VCM_MODE_SHIFT, 518 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text); 519 520 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" }; 521 522 static const struct soc_enum max98090_osr128_enum = 523 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_OSR128_SHIFT, 524 ARRAY_SIZE(max98090_osr128_text), max98090_osr128_text); 525 526 static const char *max98090_mode_text[] = { "Voice", "Music" }; 527 528 static const struct soc_enum max98090_mode_enum = 529 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG, M98090_MODE_SHIFT, 530 ARRAY_SIZE(max98090_mode_text), max98090_mode_text); 531 532 static const struct soc_enum max98090_filter_dmic34mode_enum = 533 SOC_ENUM_SINGLE(M98090_REG_FILTER_CONFIG, 534 M98090_FLT_DMIC34MODE_SHIFT, 535 ARRAY_SIZE(max98090_mode_text), max98090_mode_text); 536 537 static const char *max98090_drcatk_text[] = 538 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" }; 539 540 static const struct soc_enum max98090_drcatk_enum = 541 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCATK_SHIFT, 542 ARRAY_SIZE(max98090_drcatk_text), max98090_drcatk_text); 543 544 static const char *max98090_drcrls_text[] = 545 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" }; 546 547 static const struct soc_enum max98090_drcrls_enum = 548 SOC_ENUM_SINGLE(M98090_REG_DRC_TIMING, M98090_DRCRLS_SHIFT, 549 ARRAY_SIZE(max98090_drcrls_text), max98090_drcrls_text); 550 551 static const char *max98090_alccmp_text[] = 552 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" }; 553 554 static const struct soc_enum max98090_alccmp_enum = 555 SOC_ENUM_SINGLE(M98090_REG_DRC_COMPRESSOR, M98090_DRCCMP_SHIFT, 556 ARRAY_SIZE(max98090_alccmp_text), max98090_alccmp_text); 557 558 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" }; 559 560 static const struct soc_enum max98090_drcexp_enum = 561 SOC_ENUM_SINGLE(M98090_REG_DRC_EXPANDER, M98090_DRCEXP_SHIFT, 562 ARRAY_SIZE(max98090_drcexp_text), max98090_drcexp_text); 563 564 static const struct soc_enum max98090_dac_perfmode_enum = 565 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_PERFMODE_SHIFT, 566 ARRAY_SIZE(max98090_perf_pwr_text), max98090_perf_pwr_text); 567 568 static const struct soc_enum max98090_dachp_enum = 569 SOC_ENUM_SINGLE(M98090_REG_DAC_CONTROL, M98090_DACHP_SHIFT, 570 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text); 571 572 static const struct soc_enum max98090_adchp_enum = 573 SOC_ENUM_SINGLE(M98090_REG_ADC_CONTROL, M98090_ADCHP_SHIFT, 574 ARRAY_SIZE(max98090_pwr_perf_text), max98090_pwr_perf_text); 575 576 static const struct snd_kcontrol_new max98090_snd_controls[] = { 577 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum), 578 579 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG, 580 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0), 581 582 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 583 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, 584 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv, 585 max98090_put_enab_tlv, max98090_micboost_tlv), 586 587 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 588 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, 589 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv, 590 max98090_put_enab_tlv, max98090_micboost_tlv), 591 592 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL, 593 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1, 594 max98090_mic_tlv), 595 596 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL, 597 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1, 598 max98090_mic_tlv), 599 600 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume", 601 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0, 602 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv), 603 604 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume", 605 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0, 606 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv), 607 608 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL, 609 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1, 610 max98090_line_tlv), 611 612 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL, 613 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1, 614 max98090_line_tlv), 615 616 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 617 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0), 618 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 619 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0), 620 621 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL, 622 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0, 623 max98090_avg_tlv), 624 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL, 625 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0, 626 max98090_avg_tlv), 627 628 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL, 629 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1, 630 max98090_av_tlv), 631 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL, 632 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1, 633 max98090_av_tlv), 634 635 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum), 636 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, 637 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0), 638 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum), 639 640 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, 641 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0), 642 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION, 643 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0), 644 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION, 645 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0), 646 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, 647 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1), 648 SOC_ENUM("Filter Mode", max98090_mode_enum), 649 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, 650 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0), 651 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, 652 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0), 653 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL, 654 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv), 655 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", 656 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT, 657 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv, 658 max98090_put_enab_tlv, max98090_micboost_tlv), 659 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 660 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0, 661 max98090_dvg_tlv), 662 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 663 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1, 664 max98090_dv_tlv), 665 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105), 666 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 667 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0), 668 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 669 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0), 670 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 671 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0), 672 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 673 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1, 674 1), 675 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 676 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1, 677 max98090_dv_tlv), 678 679 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING, 680 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0), 681 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum), 682 SOC_ENUM("ALC Release Time", max98090_drcrls_enum), 683 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN, 684 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0, 685 max98090_alcmakeup_tlv), 686 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum), 687 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum), 688 SOC_SINGLE_TLV("ALC Compression Threshold Volume", 689 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT, 690 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv), 691 SOC_SINGLE_TLV("ALC Expansion Threshold Volume", 692 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT, 693 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv), 694 695 SOC_ENUM("DAC HP Playback Performance Mode", 696 max98090_dac_perfmode_enum), 697 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum), 698 699 SOC_SINGLE_TLV("Headphone Left Mixer Volume", 700 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT, 701 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv), 702 SOC_SINGLE_TLV("Headphone Right Mixer Volume", 703 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT, 704 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv), 705 706 SOC_SINGLE_TLV("Speaker Left Mixer Volume", 707 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT, 708 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv), 709 SOC_SINGLE_TLV("Speaker Right Mixer Volume", 710 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT, 711 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv), 712 713 SOC_SINGLE_TLV("Receiver Left Mixer Volume", 714 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT, 715 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv), 716 SOC_SINGLE_TLV("Receiver Right Mixer Volume", 717 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT, 718 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv), 719 720 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME, 721 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT, 722 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv), 723 724 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume", 725 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME, 726 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24, 727 0, max98090_spk_tlv), 728 729 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME, 730 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT, 731 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv), 732 733 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME, 734 M98090_HPLM_SHIFT, 1, 1), 735 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME, 736 M98090_HPRM_SHIFT, 1, 1), 737 738 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME, 739 M98090_SPLM_SHIFT, 1, 1), 740 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME, 741 M98090_SPRM_SHIFT, 1, 1), 742 743 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME, 744 M98090_RCVLM_SHIFT, 1, 1), 745 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME, 746 M98090_RCVRM_SHIFT, 1, 1), 747 748 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL, 749 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1), 750 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL, 751 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1), 752 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL, 753 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1), 754 755 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15), 756 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 757 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0), 758 }; 759 760 static const struct snd_kcontrol_new max98091_snd_controls[] = { 761 762 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE, 763 M98090_DMIC34_ZEROPAD_SHIFT, 764 M98090_DMIC34_ZEROPAD_NUM - 1, 0), 765 766 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum), 767 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, 768 M98090_FLT_DMIC34HPF_SHIFT, 769 M98090_FLT_DMIC34HPF_NUM - 1, 0), 770 771 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME, 772 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0, 773 max98090_avg_tlv), 774 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME, 775 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0, 776 max98090_avg_tlv), 777 778 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME, 779 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1, 780 max98090_av_tlv), 781 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME, 782 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1, 783 max98090_av_tlv), 784 785 SND_SOC_BYTES("DMIC34 Biquad Coefficients", 786 M98090_REG_DMIC34_BIQUAD_BASE, 15), 787 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 788 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0), 789 790 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume", 791 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT, 792 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv), 793 }; 794 795 static int max98090_micinput_event(struct snd_soc_dapm_widget *w, 796 struct snd_kcontrol *kcontrol, int event) 797 { 798 struct snd_soc_codec *codec = w->codec; 799 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 800 801 unsigned int val = snd_soc_read(codec, w->reg); 802 803 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 804 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT; 805 else 806 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT; 807 808 809 if (val >= 1) { 810 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { 811 max98090->pa1en = val - 1; /* Update for volatile */ 812 } else { 813 max98090->pa2en = val - 1; /* Update for volatile */ 814 } 815 } 816 817 switch (event) { 818 case SND_SOC_DAPM_POST_PMU: 819 /* If turning on, set to most recently selected volume */ 820 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 821 val = max98090->pa1en + 1; 822 else 823 val = max98090->pa2en + 1; 824 break; 825 case SND_SOC_DAPM_POST_PMD: 826 /* If turning off, turn off */ 827 val = 0; 828 break; 829 default: 830 return -EINVAL; 831 } 832 833 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 834 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA1EN_MASK, 835 val << M98090_MIC_PA1EN_SHIFT); 836 else 837 snd_soc_update_bits(codec, w->reg, M98090_MIC_PA2EN_MASK, 838 val << M98090_MIC_PA2EN_SHIFT); 839 840 return 0; 841 } 842 843 static const char *mic1_mux_text[] = { "IN12", "IN56" }; 844 845 static const struct soc_enum mic1_mux_enum = 846 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC1_SHIFT, 847 ARRAY_SIZE(mic1_mux_text), mic1_mux_text); 848 849 static const struct snd_kcontrol_new max98090_mic1_mux = 850 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum); 851 852 static const char *mic2_mux_text[] = { "IN34", "IN56" }; 853 854 static const struct soc_enum mic2_mux_enum = 855 SOC_ENUM_SINGLE(M98090_REG_INPUT_MODE, M98090_EXTMIC2_SHIFT, 856 ARRAY_SIZE(mic2_mux_text), mic2_mux_text); 857 858 static const struct snd_kcontrol_new max98090_mic2_mux = 859 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum); 860 861 static const char *dmic_mux_text[] = { "ADC", "DMIC" }; 862 863 static const struct soc_enum dmic_mux_enum = 864 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dmic_mux_text), dmic_mux_text); 865 866 static const struct snd_kcontrol_new max98090_dmic_mux = 867 SOC_DAPM_ENUM_VIRT("DMIC Mux", dmic_mux_enum); 868 869 static const char *max98090_micpre_text[] = { "Off", "On" }; 870 871 static const struct soc_enum max98090_pa1en_enum = 872 SOC_ENUM_SINGLE(M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, 873 ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text); 874 875 static const struct soc_enum max98090_pa2en_enum = 876 SOC_ENUM_SINGLE(M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, 877 ARRAY_SIZE(max98090_micpre_text), max98090_micpre_text); 878 879 /* LINEA mixer switch */ 880 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = { 881 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG, 882 M98090_IN1SEEN_SHIFT, 1, 0), 883 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG, 884 M98090_IN3SEEN_SHIFT, 1, 0), 885 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG, 886 M98090_IN5SEEN_SHIFT, 1, 0), 887 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG, 888 M98090_IN34DIFF_SHIFT, 1, 0), 889 }; 890 891 /* LINEB mixer switch */ 892 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = { 893 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG, 894 M98090_IN2SEEN_SHIFT, 1, 0), 895 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG, 896 M98090_IN4SEEN_SHIFT, 1, 0), 897 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG, 898 M98090_IN6SEEN_SHIFT, 1, 0), 899 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG, 900 M98090_IN56DIFF_SHIFT, 1, 0), 901 }; 902 903 /* Left ADC mixer switch */ 904 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = { 905 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER, 906 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0), 907 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER, 908 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0), 909 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER, 910 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0), 911 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER, 912 M98090_MIXADL_LINEA_SHIFT, 1, 0), 913 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER, 914 M98090_MIXADL_LINEB_SHIFT, 1, 0), 915 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER, 916 M98090_MIXADL_MIC1_SHIFT, 1, 0), 917 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER, 918 M98090_MIXADL_MIC2_SHIFT, 1, 0), 919 }; 920 921 /* Right ADC mixer switch */ 922 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = { 923 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER, 924 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0), 925 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER, 926 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0), 927 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER, 928 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0), 929 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER, 930 M98090_MIXADR_LINEA_SHIFT, 1, 0), 931 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER, 932 M98090_MIXADR_LINEB_SHIFT, 1, 0), 933 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER, 934 M98090_MIXADR_MIC1_SHIFT, 1, 0), 935 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER, 936 M98090_MIXADR_MIC2_SHIFT, 1, 0), 937 }; 938 939 static const char *lten_mux_text[] = { "Normal", "Loopthrough" }; 940 941 static const struct soc_enum ltenl_mux_enum = 942 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT, 943 ARRAY_SIZE(lten_mux_text), lten_mux_text); 944 945 static const struct soc_enum ltenr_mux_enum = 946 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LTEN_SHIFT, 947 ARRAY_SIZE(lten_mux_text), lten_mux_text); 948 949 static const struct snd_kcontrol_new max98090_ltenl_mux = 950 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum); 951 952 static const struct snd_kcontrol_new max98090_ltenr_mux = 953 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum); 954 955 static const char *lben_mux_text[] = { "Normal", "Loopback" }; 956 957 static const struct soc_enum lbenl_mux_enum = 958 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT, 959 ARRAY_SIZE(lben_mux_text), lben_mux_text); 960 961 static const struct soc_enum lbenr_mux_enum = 962 SOC_ENUM_SINGLE(M98090_REG_IO_CONFIGURATION, M98090_LBEN_SHIFT, 963 ARRAY_SIZE(lben_mux_text), lben_mux_text); 964 965 static const struct snd_kcontrol_new max98090_lbenl_mux = 966 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum); 967 968 static const struct snd_kcontrol_new max98090_lbenr_mux = 969 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum); 970 971 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" }; 972 973 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" }; 974 975 static const struct soc_enum stenl_mux_enum = 976 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSL_SHIFT, 977 ARRAY_SIZE(stenl_mux_text), stenl_mux_text); 978 979 static const struct soc_enum stenr_mux_enum = 980 SOC_ENUM_SINGLE(M98090_REG_ADC_SIDETONE, M98090_DSTSR_SHIFT, 981 ARRAY_SIZE(stenr_mux_text), stenr_mux_text); 982 983 static const struct snd_kcontrol_new max98090_stenl_mux = 984 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum); 985 986 static const struct snd_kcontrol_new max98090_stenr_mux = 987 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum); 988 989 /* Left speaker mixer switch */ 990 static const struct 991 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = { 992 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER, 993 M98090_MIXSPL_DACL_SHIFT, 1, 0), 994 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER, 995 M98090_MIXSPL_DACR_SHIFT, 1, 0), 996 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER, 997 M98090_MIXSPL_LINEA_SHIFT, 1, 0), 998 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER, 999 M98090_MIXSPL_LINEB_SHIFT, 1, 0), 1000 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER, 1001 M98090_MIXSPL_MIC1_SHIFT, 1, 0), 1002 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER, 1003 M98090_MIXSPL_MIC2_SHIFT, 1, 0), 1004 }; 1005 1006 /* Right speaker mixer switch */ 1007 static const struct 1008 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = { 1009 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 1010 M98090_MIXSPR_DACL_SHIFT, 1, 0), 1011 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 1012 M98090_MIXSPR_DACR_SHIFT, 1, 0), 1013 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER, 1014 M98090_MIXSPR_LINEA_SHIFT, 1, 0), 1015 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER, 1016 M98090_MIXSPR_LINEB_SHIFT, 1, 0), 1017 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER, 1018 M98090_MIXSPR_MIC1_SHIFT, 1, 0), 1019 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER, 1020 M98090_MIXSPR_MIC2_SHIFT, 1, 0), 1021 }; 1022 1023 /* Left headphone mixer switch */ 1024 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { 1025 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER, 1026 M98090_MIXHPL_DACL_SHIFT, 1, 0), 1027 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER, 1028 M98090_MIXHPL_DACR_SHIFT, 1, 0), 1029 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER, 1030 M98090_MIXHPL_LINEA_SHIFT, 1, 0), 1031 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER, 1032 M98090_MIXHPL_LINEB_SHIFT, 1, 0), 1033 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER, 1034 M98090_MIXHPL_MIC1_SHIFT, 1, 0), 1035 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER, 1036 M98090_MIXHPL_MIC2_SHIFT, 1, 0), 1037 }; 1038 1039 /* Right headphone mixer switch */ 1040 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { 1041 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER, 1042 M98090_MIXHPR_DACL_SHIFT, 1, 0), 1043 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER, 1044 M98090_MIXHPR_DACR_SHIFT, 1, 0), 1045 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER, 1046 M98090_MIXHPR_LINEA_SHIFT, 1, 0), 1047 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER, 1048 M98090_MIXHPR_LINEB_SHIFT, 1, 0), 1049 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER, 1050 M98090_MIXHPR_MIC1_SHIFT, 1, 0), 1051 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER, 1052 M98090_MIXHPR_MIC2_SHIFT, 1, 0), 1053 }; 1054 1055 /* Left receiver mixer switch */ 1056 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = { 1057 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1058 M98090_MIXRCVL_DACL_SHIFT, 1, 0), 1059 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1060 M98090_MIXRCVL_DACR_SHIFT, 1, 0), 1061 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER, 1062 M98090_MIXRCVL_LINEA_SHIFT, 1, 0), 1063 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER, 1064 M98090_MIXRCVL_LINEB_SHIFT, 1, 0), 1065 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER, 1066 M98090_MIXRCVL_MIC1_SHIFT, 1, 0), 1067 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER, 1068 M98090_MIXRCVL_MIC2_SHIFT, 1, 0), 1069 }; 1070 1071 /* Right receiver mixer switch */ 1072 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = { 1073 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER, 1074 M98090_MIXRCVR_DACL_SHIFT, 1, 0), 1075 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER, 1076 M98090_MIXRCVR_DACR_SHIFT, 1, 0), 1077 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER, 1078 M98090_MIXRCVR_LINEA_SHIFT, 1, 0), 1079 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER, 1080 M98090_MIXRCVR_LINEB_SHIFT, 1, 0), 1081 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER, 1082 M98090_MIXRCVR_MIC1_SHIFT, 1, 0), 1083 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER, 1084 M98090_MIXRCVR_MIC2_SHIFT, 1, 0), 1085 }; 1086 1087 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" }; 1088 1089 static const struct soc_enum linmod_mux_enum = 1090 SOC_ENUM_SINGLE(M98090_REG_LOUTR_MIXER, M98090_LINMOD_SHIFT, 1091 ARRAY_SIZE(linmod_mux_text), linmod_mux_text); 1092 1093 static const struct snd_kcontrol_new max98090_linmod_mux = 1094 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum); 1095 1096 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" }; 1097 1098 /* 1099 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable 1100 */ 1101 static const struct soc_enum mixhplsel_mux_enum = 1102 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPLSEL_SHIFT, 1103 ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text); 1104 1105 static const struct snd_kcontrol_new max98090_mixhplsel_mux = 1106 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum); 1107 1108 static const struct soc_enum mixhprsel_mux_enum = 1109 SOC_ENUM_SINGLE(M98090_REG_HP_CONTROL, M98090_MIXHPRSEL_SHIFT, 1110 ARRAY_SIZE(mixhpsel_mux_text), mixhpsel_mux_text); 1111 1112 static const struct snd_kcontrol_new max98090_mixhprsel_mux = 1113 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum); 1114 1115 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { 1116 1117 SND_SOC_DAPM_INPUT("MIC1"), 1118 SND_SOC_DAPM_INPUT("MIC2"), 1119 SND_SOC_DAPM_INPUT("DMICL"), 1120 SND_SOC_DAPM_INPUT("DMICR"), 1121 SND_SOC_DAPM_INPUT("IN1"), 1122 SND_SOC_DAPM_INPUT("IN2"), 1123 SND_SOC_DAPM_INPUT("IN3"), 1124 SND_SOC_DAPM_INPUT("IN4"), 1125 SND_SOC_DAPM_INPUT("IN5"), 1126 SND_SOC_DAPM_INPUT("IN6"), 1127 SND_SOC_DAPM_INPUT("IN12"), 1128 SND_SOC_DAPM_INPUT("IN34"), 1129 SND_SOC_DAPM_INPUT("IN56"), 1130 1131 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE, 1132 M98090_MBEN_SHIFT, 0, NULL, 0), 1133 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN, 1134 M98090_SHDNN_SHIFT, 0, NULL, 0), 1135 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION, 1136 M98090_SDIEN_SHIFT, 0, NULL, 0), 1137 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION, 1138 M98090_SDOEN_SHIFT, 0, NULL, 0), 1139 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1140 M98090_DIGMICL_SHIFT, 0, NULL, 0), 1141 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1142 M98090_DIGMICR_SHIFT, 0, NULL, 0), 1143 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG, 1144 M98090_AHPF_SHIFT, 0, NULL, 0), 1145 1146 /* 1147 * Note: Sysclk and misc power supplies are taken care of by SHDN 1148 */ 1149 1150 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM, 1151 0, 0, &max98090_mic1_mux), 1152 1153 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM, 1154 0, 0, &max98090_mic2_mux), 1155 1156 SND_SOC_DAPM_VIRT_MUX("DMIC Mux", SND_SOC_NOPM, 1157 0, 0, &max98090_dmic_mux), 1158 1159 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL, 1160 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1161 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1162 1163 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL, 1164 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1165 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1166 1167 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0, 1168 &max98090_linea_mixer_controls[0], 1169 ARRAY_SIZE(max98090_linea_mixer_controls)), 1170 1171 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0, 1172 &max98090_lineb_mixer_controls[0], 1173 ARRAY_SIZE(max98090_lineb_mixer_controls)), 1174 1175 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE, 1176 M98090_LINEAEN_SHIFT, 0, NULL, 0), 1177 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE, 1178 M98090_LINEBEN_SHIFT, 0, NULL, 0), 1179 1180 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1181 &max98090_left_adc_mixer_controls[0], 1182 ARRAY_SIZE(max98090_left_adc_mixer_controls)), 1183 1184 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1185 &max98090_right_adc_mixer_controls[0], 1186 ARRAY_SIZE(max98090_right_adc_mixer_controls)), 1187 1188 SND_SOC_DAPM_ADC("ADCL", NULL, M98090_REG_INPUT_ENABLE, 1189 M98090_ADLEN_SHIFT, 0), 1190 SND_SOC_DAPM_ADC("ADCR", NULL, M98090_REG_INPUT_ENABLE, 1191 M98090_ADREN_SHIFT, 0), 1192 1193 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0, 1194 SND_SOC_NOPM, 0, 0), 1195 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1, 1196 SND_SOC_NOPM, 0, 0), 1197 1198 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM, 1199 0, 0, &max98090_lbenl_mux), 1200 1201 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM, 1202 0, 0, &max98090_lbenr_mux), 1203 1204 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM, 1205 0, 0, &max98090_ltenl_mux), 1206 1207 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM, 1208 0, 0, &max98090_ltenr_mux), 1209 1210 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM, 1211 0, 0, &max98090_stenl_mux), 1212 1213 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM, 1214 0, 0, &max98090_stenr_mux), 1215 1216 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 1217 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0), 1218 1219 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE, 1220 M98090_DALEN_SHIFT, 0), 1221 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE, 1222 M98090_DAREN_SHIFT, 0), 1223 1224 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 1225 &max98090_left_hp_mixer_controls[0], 1226 ARRAY_SIZE(max98090_left_hp_mixer_controls)), 1227 1228 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 1229 &max98090_right_hp_mixer_controls[0], 1230 ARRAY_SIZE(max98090_right_hp_mixer_controls)), 1231 1232 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 1233 &max98090_left_speaker_mixer_controls[0], 1234 ARRAY_SIZE(max98090_left_speaker_mixer_controls)), 1235 1236 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 1237 &max98090_right_speaker_mixer_controls[0], 1238 ARRAY_SIZE(max98090_right_speaker_mixer_controls)), 1239 1240 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0, 1241 &max98090_left_rcv_mixer_controls[0], 1242 ARRAY_SIZE(max98090_left_rcv_mixer_controls)), 1243 1244 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0, 1245 &max98090_right_rcv_mixer_controls[0], 1246 ARRAY_SIZE(max98090_right_rcv_mixer_controls)), 1247 1248 SND_SOC_DAPM_MUX("LINMOD Mux", M98090_REG_LOUTR_MIXER, 1249 M98090_LINMOD_SHIFT, 0, &max98090_linmod_mux), 1250 1251 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", M98090_REG_HP_CONTROL, 1252 M98090_MIXHPLSEL_SHIFT, 0, &max98090_mixhplsel_mux), 1253 1254 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", M98090_REG_HP_CONTROL, 1255 M98090_MIXHPRSEL_SHIFT, 0, &max98090_mixhprsel_mux), 1256 1257 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE, 1258 M98090_HPLEN_SHIFT, 0, NULL, 0), 1259 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE, 1260 M98090_HPREN_SHIFT, 0, NULL, 0), 1261 1262 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE, 1263 M98090_SPLEN_SHIFT, 0, NULL, 0), 1264 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE, 1265 M98090_SPREN_SHIFT, 0, NULL, 0), 1266 1267 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE, 1268 M98090_RCVLEN_SHIFT, 0, NULL, 0), 1269 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE, 1270 M98090_RCVREN_SHIFT, 0, NULL, 0), 1271 1272 SND_SOC_DAPM_OUTPUT("HPL"), 1273 SND_SOC_DAPM_OUTPUT("HPR"), 1274 SND_SOC_DAPM_OUTPUT("SPKL"), 1275 SND_SOC_DAPM_OUTPUT("SPKR"), 1276 SND_SOC_DAPM_OUTPUT("RCVL"), 1277 SND_SOC_DAPM_OUTPUT("RCVR"), 1278 }; 1279 1280 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = { 1281 1282 SND_SOC_DAPM_INPUT("DMIC3"), 1283 SND_SOC_DAPM_INPUT("DMIC4"), 1284 1285 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1286 M98090_DIGMIC3_SHIFT, 0, NULL, 0), 1287 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1288 M98090_DIGMIC4_SHIFT, 0, NULL, 0), 1289 }; 1290 1291 static const struct snd_soc_dapm_route max98090_dapm_routes[] = { 1292 1293 {"MIC1 Input", NULL, "MIC1"}, 1294 {"MIC2 Input", NULL, "MIC2"}, 1295 1296 {"DMICL", NULL, "DMICL_ENA"}, 1297 {"DMICR", NULL, "DMICR_ENA"}, 1298 {"DMICL", NULL, "AHPF"}, 1299 {"DMICR", NULL, "AHPF"}, 1300 1301 /* MIC1 input mux */ 1302 {"MIC1 Mux", "IN12", "IN12"}, 1303 {"MIC1 Mux", "IN56", "IN56"}, 1304 1305 /* MIC2 input mux */ 1306 {"MIC2 Mux", "IN34", "IN34"}, 1307 {"MIC2 Mux", "IN56", "IN56"}, 1308 1309 {"MIC1 Input", NULL, "MIC1 Mux"}, 1310 {"MIC2 Input", NULL, "MIC2 Mux"}, 1311 1312 /* Left ADC input mixer */ 1313 {"Left ADC Mixer", "IN12 Switch", "IN12"}, 1314 {"Left ADC Mixer", "IN34 Switch", "IN34"}, 1315 {"Left ADC Mixer", "IN56 Switch", "IN56"}, 1316 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"}, 1317 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"}, 1318 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1319 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1320 1321 /* Right ADC input mixer */ 1322 {"Right ADC Mixer", "IN12 Switch", "IN12"}, 1323 {"Right ADC Mixer", "IN34 Switch", "IN34"}, 1324 {"Right ADC Mixer", "IN56 Switch", "IN56"}, 1325 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"}, 1326 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"}, 1327 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1328 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1329 1330 /* Line A input mixer */ 1331 {"LINEA Mixer", "IN1 Switch", "IN1"}, 1332 {"LINEA Mixer", "IN3 Switch", "IN3"}, 1333 {"LINEA Mixer", "IN5 Switch", "IN5"}, 1334 {"LINEA Mixer", "IN34 Switch", "IN34"}, 1335 1336 /* Line B input mixer */ 1337 {"LINEB Mixer", "IN2 Switch", "IN2"}, 1338 {"LINEB Mixer", "IN4 Switch", "IN4"}, 1339 {"LINEB Mixer", "IN6 Switch", "IN6"}, 1340 {"LINEB Mixer", "IN56 Switch", "IN56"}, 1341 1342 {"LINEA Input", NULL, "LINEA Mixer"}, 1343 {"LINEB Input", NULL, "LINEB Mixer"}, 1344 1345 /* Inputs */ 1346 {"ADCL", NULL, "Left ADC Mixer"}, 1347 {"ADCR", NULL, "Right ADC Mixer"}, 1348 {"ADCL", NULL, "SHDN"}, 1349 {"ADCR", NULL, "SHDN"}, 1350 1351 {"DMIC Mux", "ADC", "ADCL"}, 1352 {"DMIC Mux", "ADC", "ADCR"}, 1353 {"DMIC Mux", "DMIC", "DMICL"}, 1354 {"DMIC Mux", "DMIC", "DMICR"}, 1355 1356 {"LBENL Mux", "Normal", "DMIC Mux"}, 1357 {"LBENL Mux", "Loopback", "LTENL Mux"}, 1358 {"LBENR Mux", "Normal", "DMIC Mux"}, 1359 {"LBENR Mux", "Loopback", "LTENR Mux"}, 1360 1361 {"AIFOUTL", NULL, "LBENL Mux"}, 1362 {"AIFOUTR", NULL, "LBENR Mux"}, 1363 {"AIFOUTL", NULL, "SHDN"}, 1364 {"AIFOUTR", NULL, "SHDN"}, 1365 {"AIFOUTL", NULL, "SDOEN"}, 1366 {"AIFOUTR", NULL, "SDOEN"}, 1367 1368 {"LTENL Mux", "Normal", "AIFINL"}, 1369 {"LTENL Mux", "Loopthrough", "LBENL Mux"}, 1370 {"LTENR Mux", "Normal", "AIFINR"}, 1371 {"LTENR Mux", "Loopthrough", "LBENR Mux"}, 1372 1373 {"DACL", NULL, "LTENL Mux"}, 1374 {"DACR", NULL, "LTENR Mux"}, 1375 1376 {"STENL Mux", "Sidetone Left", "ADCL"}, 1377 {"STENL Mux", "Sidetone Left", "DMICL"}, 1378 {"STENR Mux", "Sidetone Right", "ADCR"}, 1379 {"STENR Mux", "Sidetone Right", "DMICR"}, 1380 {"DACL", "NULL", "STENL Mux"}, 1381 {"DACR", "NULL", "STENL Mux"}, 1382 1383 {"AIFINL", NULL, "SHDN"}, 1384 {"AIFINR", NULL, "SHDN"}, 1385 {"AIFINL", NULL, "SDIEN"}, 1386 {"AIFINR", NULL, "SDIEN"}, 1387 {"DACL", NULL, "SHDN"}, 1388 {"DACR", NULL, "SHDN"}, 1389 1390 /* Left headphone output mixer */ 1391 {"Left Headphone Mixer", "Left DAC Switch", "DACL"}, 1392 {"Left Headphone Mixer", "Right DAC Switch", "DACR"}, 1393 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1394 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1395 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1396 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1397 1398 /* Right headphone output mixer */ 1399 {"Right Headphone Mixer", "Left DAC Switch", "DACL"}, 1400 {"Right Headphone Mixer", "Right DAC Switch", "DACR"}, 1401 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1402 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1403 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1404 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1405 1406 /* Left speaker output mixer */ 1407 {"Left Speaker Mixer", "Left DAC Switch", "DACL"}, 1408 {"Left Speaker Mixer", "Right DAC Switch", "DACR"}, 1409 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1410 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1411 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1412 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1413 1414 /* Right speaker output mixer */ 1415 {"Right Speaker Mixer", "Left DAC Switch", "DACL"}, 1416 {"Right Speaker Mixer", "Right DAC Switch", "DACR"}, 1417 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1418 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1419 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1420 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1421 1422 /* Left Receiver output mixer */ 1423 {"Left Receiver Mixer", "Left DAC Switch", "DACL"}, 1424 {"Left Receiver Mixer", "Right DAC Switch", "DACR"}, 1425 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1426 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1427 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1428 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1429 1430 /* Right Receiver output mixer */ 1431 {"Right Receiver Mixer", "Left DAC Switch", "DACL"}, 1432 {"Right Receiver Mixer", "Right DAC Switch", "DACR"}, 1433 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1434 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1435 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1436 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1437 1438 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"}, 1439 1440 /* 1441 * Disable this for lowest power if bypassing 1442 * the DAC with an analog signal 1443 */ 1444 {"HP Left Out", NULL, "DACL"}, 1445 {"HP Left Out", NULL, "MIXHPLSEL Mux"}, 1446 1447 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"}, 1448 1449 /* 1450 * Disable this for lowest power if bypassing 1451 * the DAC with an analog signal 1452 */ 1453 {"HP Right Out", NULL, "DACR"}, 1454 {"HP Right Out", NULL, "MIXHPRSEL Mux"}, 1455 1456 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 1457 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 1458 {"RCV Left Out", NULL, "Left Receiver Mixer"}, 1459 1460 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"}, 1461 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"}, 1462 {"RCV Right Out", NULL, "LINMOD Mux"}, 1463 1464 {"HPL", NULL, "HP Left Out"}, 1465 {"HPR", NULL, "HP Right Out"}, 1466 {"SPKL", NULL, "SPK Left Out"}, 1467 {"SPKR", NULL, "SPK Right Out"}, 1468 {"RCVL", NULL, "RCV Left Out"}, 1469 {"RCVR", NULL, "RCV Right Out"}, 1470 1471 }; 1472 1473 static const struct snd_soc_dapm_route max98091_dapm_routes[] = { 1474 1475 /* DMIC inputs */ 1476 {"DMIC3", NULL, "DMIC3_ENA"}, 1477 {"DMIC4", NULL, "DMIC4_ENA"}, 1478 {"DMIC3", NULL, "AHPF"}, 1479 {"DMIC4", NULL, "AHPF"}, 1480 1481 }; 1482 1483 static int max98090_add_widgets(struct snd_soc_codec *codec) 1484 { 1485 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1486 struct snd_soc_dapm_context *dapm = &codec->dapm; 1487 1488 snd_soc_add_codec_controls(codec, max98090_snd_controls, 1489 ARRAY_SIZE(max98090_snd_controls)); 1490 1491 if (max98090->devtype == MAX98091) { 1492 snd_soc_add_codec_controls(codec, max98091_snd_controls, 1493 ARRAY_SIZE(max98091_snd_controls)); 1494 } 1495 1496 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets, 1497 ARRAY_SIZE(max98090_dapm_widgets)); 1498 1499 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes, 1500 ARRAY_SIZE(max98090_dapm_routes)); 1501 1502 if (max98090->devtype == MAX98091) { 1503 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets, 1504 ARRAY_SIZE(max98091_dapm_widgets)); 1505 1506 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes, 1507 ARRAY_SIZE(max98091_dapm_routes)); 1508 1509 } 1510 1511 return 0; 1512 } 1513 1514 static const int pclk_rates[] = { 1515 12000000, 12000000, 13000000, 13000000, 1516 16000000, 16000000, 19200000, 19200000 1517 }; 1518 1519 static const int lrclk_rates[] = { 1520 8000, 16000, 8000, 16000, 1521 8000, 16000, 8000, 16000 1522 }; 1523 1524 static const int user_pclk_rates[] = { 1525 13000000, 13000000 1526 }; 1527 1528 static const int user_lrclk_rates[] = { 1529 44100, 48000 1530 }; 1531 1532 static const unsigned long long ni_value[] = { 1533 3528, 768 1534 }; 1535 1536 static const unsigned long long mi_value[] = { 1537 8125, 1625 1538 }; 1539 1540 static void max98090_configure_bclk(struct snd_soc_codec *codec) 1541 { 1542 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1543 unsigned long long ni; 1544 int i; 1545 1546 if (!max98090->sysclk) { 1547 dev_err(codec->dev, "No SYSCLK configured\n"); 1548 return; 1549 } 1550 1551 if (!max98090->bclk || !max98090->lrclk) { 1552 dev_err(codec->dev, "No audio clocks configured\n"); 1553 return; 1554 } 1555 1556 /* Skip configuration when operating as slave */ 1557 if (!(snd_soc_read(codec, M98090_REG_MASTER_MODE) & 1558 M98090_MAS_MASK)) { 1559 return; 1560 } 1561 1562 /* Check for supported PCLK to LRCLK ratios */ 1563 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) { 1564 if ((pclk_rates[i] == max98090->sysclk) && 1565 (lrclk_rates[i] == max98090->lrclk)) { 1566 dev_dbg(codec->dev, 1567 "Found supported PCLK to LRCLK rates 0x%x\n", 1568 i + 0x8); 1569 1570 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1571 M98090_FREQ_MASK, 1572 (i + 0x8) << M98090_FREQ_SHIFT); 1573 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1574 M98090_USE_M1_MASK, 0); 1575 return; 1576 } 1577 } 1578 1579 /* Check for user calculated MI and NI ratios */ 1580 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) { 1581 if ((user_pclk_rates[i] == max98090->sysclk) && 1582 (user_lrclk_rates[i] == max98090->lrclk)) { 1583 dev_dbg(codec->dev, 1584 "Found user supported PCLK to LRCLK rates\n"); 1585 dev_dbg(codec->dev, "i %d ni %lld mi %lld\n", 1586 i, ni_value[i], mi_value[i]); 1587 1588 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1589 M98090_FREQ_MASK, 0); 1590 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1591 M98090_USE_M1_MASK, 1592 1 << M98090_USE_M1_SHIFT); 1593 1594 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, 1595 (ni_value[i] >> 8) & 0x7F); 1596 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, 1597 ni_value[i] & 0xFF); 1598 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_MSB, 1599 (mi_value[i] >> 8) & 0x7F); 1600 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_MI_LSB, 1601 mi_value[i] & 0xFF); 1602 1603 return; 1604 } 1605 } 1606 1607 /* 1608 * Calculate based on MI = 65536 (not as good as either method above) 1609 */ 1610 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1611 M98090_FREQ_MASK, 0); 1612 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1613 M98090_USE_M1_MASK, 0); 1614 1615 /* 1616 * Configure NI when operating as master 1617 * Note: There is a small, but significant audio quality improvement 1618 * by calculating ni and mi. 1619 */ 1620 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) 1621 * (unsigned long long int)max98090->lrclk; 1622 do_div(ni, (unsigned long long int)max98090->sysclk); 1623 dev_info(codec->dev, "No better method found\n"); 1624 dev_info(codec->dev, "Calculating ni %lld with mi 65536\n", ni); 1625 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_MSB, 1626 (ni >> 8) & 0x7F); 1627 snd_soc_write(codec, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF); 1628 } 1629 1630 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai, 1631 unsigned int fmt) 1632 { 1633 struct snd_soc_codec *codec = codec_dai->codec; 1634 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1635 struct max98090_cdata *cdata; 1636 u8 regval; 1637 1638 max98090->dai_fmt = fmt; 1639 cdata = &max98090->dai[0]; 1640 1641 if (fmt != cdata->fmt) { 1642 cdata->fmt = fmt; 1643 1644 regval = 0; 1645 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1646 case SND_SOC_DAIFMT_CBS_CFS: 1647 /* Set to slave mode PLL - MAS mode off */ 1648 snd_soc_write(codec, 1649 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00); 1650 snd_soc_write(codec, 1651 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); 1652 snd_soc_update_bits(codec, M98090_REG_CLOCK_MODE, 1653 M98090_USE_M1_MASK, 0); 1654 break; 1655 case SND_SOC_DAIFMT_CBM_CFM: 1656 /* Set to master mode */ 1657 if (max98090->tdm_slots == 4) { 1658 /* TDM */ 1659 regval |= M98090_MAS_MASK | 1660 M98090_BSEL_64; 1661 } else if (max98090->tdm_slots == 3) { 1662 /* TDM */ 1663 regval |= M98090_MAS_MASK | 1664 M98090_BSEL_48; 1665 } else { 1666 /* Few TDM slots, or No TDM */ 1667 regval |= M98090_MAS_MASK | 1668 M98090_BSEL_32; 1669 } 1670 break; 1671 case SND_SOC_DAIFMT_CBS_CFM: 1672 case SND_SOC_DAIFMT_CBM_CFS: 1673 default: 1674 dev_err(codec->dev, "DAI clock mode unsupported"); 1675 return -EINVAL; 1676 } 1677 snd_soc_write(codec, M98090_REG_MASTER_MODE, regval); 1678 1679 regval = 0; 1680 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1681 case SND_SOC_DAIFMT_I2S: 1682 regval |= M98090_DLY_MASK; 1683 break; 1684 case SND_SOC_DAIFMT_LEFT_J: 1685 break; 1686 case SND_SOC_DAIFMT_RIGHT_J: 1687 regval |= M98090_RJ_MASK; 1688 break; 1689 case SND_SOC_DAIFMT_DSP_A: 1690 /* Not supported mode */ 1691 default: 1692 dev_err(codec->dev, "DAI format unsupported"); 1693 return -EINVAL; 1694 } 1695 1696 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1697 case SND_SOC_DAIFMT_NB_NF: 1698 break; 1699 case SND_SOC_DAIFMT_NB_IF: 1700 regval |= M98090_WCI_MASK; 1701 break; 1702 case SND_SOC_DAIFMT_IB_NF: 1703 regval |= M98090_BCI_MASK; 1704 break; 1705 case SND_SOC_DAIFMT_IB_IF: 1706 regval |= M98090_BCI_MASK|M98090_WCI_MASK; 1707 break; 1708 default: 1709 dev_err(codec->dev, "DAI invert mode unsupported"); 1710 return -EINVAL; 1711 } 1712 1713 /* 1714 * This accommodates an inverted logic in the MAX98090 chip 1715 * for Bit Clock Invert (BCI). The inverted logic is only 1716 * seen for the case of TDM mode. The remaining cases have 1717 * normal logic. 1718 */ 1719 if (max98090->tdm_slots > 1) 1720 regval ^= M98090_BCI_MASK; 1721 1722 snd_soc_write(codec, 1723 M98090_REG_INTERFACE_FORMAT, regval); 1724 } 1725 1726 return 0; 1727 } 1728 1729 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai, 1730 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1731 { 1732 struct snd_soc_codec *codec = codec_dai->codec; 1733 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1734 struct max98090_cdata *cdata; 1735 cdata = &max98090->dai[0]; 1736 1737 if (slots < 0 || slots > 4) 1738 return -EINVAL; 1739 1740 max98090->tdm_slots = slots; 1741 max98090->tdm_width = slot_width; 1742 1743 if (max98090->tdm_slots > 1) { 1744 /* SLOTL SLOTR SLOTDLY */ 1745 snd_soc_write(codec, M98090_REG_TDM_FORMAT, 1746 0 << M98090_TDM_SLOTL_SHIFT | 1747 1 << M98090_TDM_SLOTR_SHIFT | 1748 0 << M98090_TDM_SLOTDLY_SHIFT); 1749 1750 /* FSW TDM */ 1751 snd_soc_update_bits(codec, M98090_REG_TDM_CONTROL, 1752 M98090_TDM_MASK, 1753 M98090_TDM_MASK); 1754 } 1755 1756 /* 1757 * Normally advisable to set TDM first, but this permits either order 1758 */ 1759 cdata->fmt = 0; 1760 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt); 1761 1762 return 0; 1763 } 1764 1765 static int max98090_set_bias_level(struct snd_soc_codec *codec, 1766 enum snd_soc_bias_level level) 1767 { 1768 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1769 int ret; 1770 1771 switch (level) { 1772 case SND_SOC_BIAS_ON: 1773 if (max98090->jack_state == M98090_JACK_STATE_HEADSET) { 1774 /* 1775 * Set to normal bias level. 1776 */ 1777 snd_soc_update_bits(codec, M98090_REG_MIC_BIAS_VOLTAGE, 1778 M98090_MBVSEL_MASK, M98090_MBVSEL_2V8); 1779 } 1780 break; 1781 1782 case SND_SOC_BIAS_PREPARE: 1783 break; 1784 1785 case SND_SOC_BIAS_STANDBY: 1786 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1787 ret = regcache_sync(max98090->regmap); 1788 if (ret != 0) { 1789 dev_err(codec->dev, 1790 "Failed to sync cache: %d\n", ret); 1791 return ret; 1792 } 1793 } 1794 break; 1795 1796 case SND_SOC_BIAS_OFF: 1797 /* Set internal pull-up to lowest power mode */ 1798 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, 1799 M98090_JDWK_MASK, M98090_JDWK_MASK); 1800 regcache_mark_dirty(max98090->regmap); 1801 break; 1802 } 1803 codec->dapm.bias_level = level; 1804 return 0; 1805 } 1806 1807 static const int comp_pclk_rates[] = { 1808 11289600, 12288000, 12000000, 13000000, 19200000 1809 }; 1810 1811 static const int dmic_micclk[] = { 1812 2, 2, 2, 2, 4, 2 1813 }; 1814 1815 static const int comp_lrclk_rates[] = { 1816 8000, 16000, 32000, 44100, 48000, 96000 1817 }; 1818 1819 static const int dmic_comp[6][6] = { 1820 {7, 8, 3, 3, 3, 3}, 1821 {7, 8, 3, 3, 3, 3}, 1822 {7, 8, 3, 3, 3, 3}, 1823 {7, 8, 3, 1, 1, 1}, 1824 {7, 8, 3, 1, 2, 2}, 1825 {7, 8, 3, 3, 3, 3} 1826 }; 1827 1828 static int max98090_dai_hw_params(struct snd_pcm_substream *substream, 1829 struct snd_pcm_hw_params *params, 1830 struct snd_soc_dai *dai) 1831 { 1832 struct snd_soc_codec *codec = dai->codec; 1833 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1834 struct max98090_cdata *cdata; 1835 int i, j; 1836 1837 cdata = &max98090->dai[0]; 1838 max98090->bclk = snd_soc_params_to_bclk(params); 1839 if (params_channels(params) == 1) 1840 max98090->bclk *= 2; 1841 1842 max98090->lrclk = params_rate(params); 1843 1844 switch (params_width(params)) { 1845 case 16: 1846 snd_soc_update_bits(codec, M98090_REG_INTERFACE_FORMAT, 1847 M98090_WS_MASK, 0); 1848 break; 1849 default: 1850 return -EINVAL; 1851 } 1852 1853 max98090_configure_bclk(codec); 1854 1855 cdata->rate = max98090->lrclk; 1856 1857 /* Update filter mode */ 1858 if (max98090->lrclk < 24000) 1859 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1860 M98090_MODE_MASK, 0); 1861 else 1862 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1863 M98090_MODE_MASK, M98090_MODE_MASK); 1864 1865 /* Update sample rate mode */ 1866 if (max98090->lrclk < 50000) 1867 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1868 M98090_DHF_MASK, 0); 1869 else 1870 snd_soc_update_bits(codec, M98090_REG_FILTER_CONFIG, 1871 M98090_DHF_MASK, M98090_DHF_MASK); 1872 1873 /* Check for supported PCLK to LRCLK ratios */ 1874 for (j = 0; j < ARRAY_SIZE(comp_pclk_rates); j++) { 1875 if (comp_pclk_rates[j] == max98090->sysclk) { 1876 break; 1877 } 1878 } 1879 1880 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { 1881 if (max98090->lrclk <= (comp_lrclk_rates[i] + 1882 comp_lrclk_rates[i + 1]) / 2) { 1883 break; 1884 } 1885 } 1886 1887 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_ENABLE, 1888 M98090_MICCLK_MASK, 1889 dmic_micclk[j] << M98090_MICCLK_SHIFT); 1890 1891 snd_soc_update_bits(codec, M98090_REG_DIGITAL_MIC_CONFIG, 1892 M98090_DMIC_COMP_MASK, 1893 dmic_comp[j][i] << M98090_DMIC_COMP_SHIFT); 1894 1895 return 0; 1896 } 1897 1898 /* 1899 * PLL / Sysclk 1900 */ 1901 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, 1902 int clk_id, unsigned int freq, int dir) 1903 { 1904 struct snd_soc_codec *codec = dai->codec; 1905 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 1906 1907 /* Requested clock frequency is already setup */ 1908 if (freq == max98090->sysclk) 1909 return 0; 1910 1911 /* Setup clocks for slave mode, and using the PLL 1912 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1913 * 0x02 (when master clk is 20MHz to 40MHz).. 1914 * 0x03 (when master clk is 40MHz to 60MHz).. 1915 */ 1916 if ((freq >= 10000000) && (freq < 20000000)) { 1917 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, 1918 M98090_PSCLK_DIV1); 1919 } else if ((freq >= 20000000) && (freq < 40000000)) { 1920 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, 1921 M98090_PSCLK_DIV2); 1922 } else if ((freq >= 40000000) && (freq < 60000000)) { 1923 snd_soc_write(codec, M98090_REG_SYSTEM_CLOCK, 1924 M98090_PSCLK_DIV4); 1925 } else { 1926 dev_err(codec->dev, "Invalid master clock frequency\n"); 1927 return -EINVAL; 1928 } 1929 1930 max98090->sysclk = freq; 1931 1932 max98090_configure_bclk(codec); 1933 1934 return 0; 1935 } 1936 1937 static int max98090_dai_digital_mute(struct snd_soc_dai *codec_dai, int mute) 1938 { 1939 struct snd_soc_codec *codec = codec_dai->codec; 1940 int regval; 1941 1942 regval = mute ? M98090_DVM_MASK : 0; 1943 snd_soc_update_bits(codec, M98090_REG_DAI_PLAYBACK_LEVEL, 1944 M98090_DVM_MASK, regval); 1945 1946 return 0; 1947 } 1948 1949 static void max98090_jack_work(struct work_struct *work) 1950 { 1951 struct max98090_priv *max98090 = container_of(work, 1952 struct max98090_priv, 1953 jack_work.work); 1954 struct snd_soc_codec *codec = max98090->codec; 1955 struct snd_soc_dapm_context *dapm = &codec->dapm; 1956 int status = 0; 1957 int reg; 1958 1959 /* Read a second time */ 1960 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { 1961 1962 /* Strong pull up allows mic detection */ 1963 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, 1964 M98090_JDWK_MASK, 0); 1965 1966 msleep(50); 1967 1968 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); 1969 1970 /* Weak pull up allows only insertion detection */ 1971 snd_soc_update_bits(codec, M98090_REG_JACK_DETECT, 1972 M98090_JDWK_MASK, M98090_JDWK_MASK); 1973 } else { 1974 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); 1975 } 1976 1977 reg = snd_soc_read(codec, M98090_REG_JACK_STATUS); 1978 1979 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { 1980 case M98090_LSNS_MASK | M98090_JKSNS_MASK: 1981 dev_dbg(codec->dev, "No Headset Detected\n"); 1982 1983 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 1984 1985 status |= 0; 1986 1987 break; 1988 1989 case 0: 1990 if (max98090->jack_state == 1991 M98090_JACK_STATE_HEADSET) { 1992 1993 dev_dbg(codec->dev, 1994 "Headset Button Down Detected\n"); 1995 1996 /* 1997 * max98090_headset_button_event(codec) 1998 * could be defined, then called here. 1999 */ 2000 2001 status |= SND_JACK_HEADSET; 2002 status |= SND_JACK_BTN_0; 2003 2004 break; 2005 } 2006 2007 /* Line is reported as Headphone */ 2008 /* Nokia Headset is reported as Headphone */ 2009 /* Mono Headphone is reported as Headphone */ 2010 dev_dbg(codec->dev, "Headphone Detected\n"); 2011 2012 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; 2013 2014 status |= SND_JACK_HEADPHONE; 2015 2016 break; 2017 2018 case M98090_JKSNS_MASK: 2019 dev_dbg(codec->dev, "Headset Detected\n"); 2020 2021 max98090->jack_state = M98090_JACK_STATE_HEADSET; 2022 2023 status |= SND_JACK_HEADSET; 2024 2025 break; 2026 2027 default: 2028 dev_dbg(codec->dev, "Unrecognized Jack Status\n"); 2029 break; 2030 } 2031 2032 snd_soc_jack_report(max98090->jack, status, 2033 SND_JACK_HEADSET | SND_JACK_BTN_0); 2034 2035 snd_soc_dapm_sync(dapm); 2036 } 2037 2038 static irqreturn_t max98090_interrupt(int irq, void *data) 2039 { 2040 struct snd_soc_codec *codec = data; 2041 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2042 int ret; 2043 unsigned int mask; 2044 unsigned int active; 2045 2046 dev_dbg(codec->dev, "***** max98090_interrupt *****\n"); 2047 2048 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); 2049 2050 if (ret != 0) { 2051 dev_err(codec->dev, 2052 "failed to read M98090_REG_INTERRUPT_S: %d\n", 2053 ret); 2054 return IRQ_NONE; 2055 } 2056 2057 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); 2058 2059 if (ret != 0) { 2060 dev_err(codec->dev, 2061 "failed to read M98090_REG_DEVICE_STATUS: %d\n", 2062 ret); 2063 return IRQ_NONE; 2064 } 2065 2066 dev_dbg(codec->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", 2067 active, mask, active & mask); 2068 2069 active &= mask; 2070 2071 if (!active) 2072 return IRQ_NONE; 2073 2074 if (active & M98090_CLD_MASK) 2075 dev_err(codec->dev, "M98090_CLD_MASK\n"); 2076 2077 if (active & M98090_SLD_MASK) 2078 dev_dbg(codec->dev, "M98090_SLD_MASK\n"); 2079 2080 if (active & M98090_ULK_MASK) 2081 dev_err(codec->dev, "M98090_ULK_MASK\n"); 2082 2083 if (active & M98090_JDET_MASK) { 2084 dev_dbg(codec->dev, "M98090_JDET_MASK\n"); 2085 2086 pm_wakeup_event(codec->dev, 100); 2087 2088 queue_delayed_work(system_power_efficient_wq, 2089 &max98090->jack_work, 2090 msecs_to_jiffies(100)); 2091 } 2092 2093 if (active & M98090_DRCACT_MASK) 2094 dev_dbg(codec->dev, "M98090_DRCACT_MASK\n"); 2095 2096 if (active & M98090_DRCCLP_MASK) 2097 dev_err(codec->dev, "M98090_DRCCLP_MASK\n"); 2098 2099 return IRQ_HANDLED; 2100 } 2101 2102 /** 2103 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ 2104 * 2105 * @codec: MAX98090 codec 2106 * @jack: jack to report detection events on 2107 * 2108 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are 2109 * being used to bring out signals to the processor then only platform 2110 * data configuration is needed for MAX98090 and processor GPIOs should 2111 * be configured using snd_soc_jack_add_gpios() instead. 2112 * 2113 * If no jack is supplied detection will be disabled. 2114 */ 2115 int max98090_mic_detect(struct snd_soc_codec *codec, 2116 struct snd_soc_jack *jack) 2117 { 2118 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2119 2120 dev_dbg(codec->dev, "max98090_mic_detect\n"); 2121 2122 max98090->jack = jack; 2123 if (jack) { 2124 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, 2125 M98090_IJDET_MASK, 2126 1 << M98090_IJDET_SHIFT); 2127 } else { 2128 snd_soc_update_bits(codec, M98090_REG_INTERRUPT_S, 2129 M98090_IJDET_MASK, 2130 0); 2131 } 2132 2133 /* Send an initial empty report */ 2134 snd_soc_jack_report(max98090->jack, 0, 2135 SND_JACK_HEADSET | SND_JACK_BTN_0); 2136 2137 queue_delayed_work(system_power_efficient_wq, 2138 &max98090->jack_work, 2139 msecs_to_jiffies(100)); 2140 2141 return 0; 2142 } 2143 EXPORT_SYMBOL_GPL(max98090_mic_detect); 2144 2145 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 2146 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 2147 2148 static struct snd_soc_dai_ops max98090_dai_ops = { 2149 .set_sysclk = max98090_dai_set_sysclk, 2150 .set_fmt = max98090_dai_set_fmt, 2151 .set_tdm_slot = max98090_set_tdm_slot, 2152 .hw_params = max98090_dai_hw_params, 2153 .digital_mute = max98090_dai_digital_mute, 2154 }; 2155 2156 static struct snd_soc_dai_driver max98090_dai[] = { 2157 { 2158 .name = "HiFi", 2159 .playback = { 2160 .stream_name = "HiFi Playback", 2161 .channels_min = 2, 2162 .channels_max = 2, 2163 .rates = MAX98090_RATES, 2164 .formats = MAX98090_FORMATS, 2165 }, 2166 .capture = { 2167 .stream_name = "HiFi Capture", 2168 .channels_min = 1, 2169 .channels_max = 2, 2170 .rates = MAX98090_RATES, 2171 .formats = MAX98090_FORMATS, 2172 }, 2173 .ops = &max98090_dai_ops, 2174 } 2175 }; 2176 2177 static void max98090_handle_pdata(struct snd_soc_codec *codec) 2178 { 2179 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2180 struct max98090_pdata *pdata = max98090->pdata; 2181 2182 if (!pdata) { 2183 dev_err(codec->dev, "No platform data\n"); 2184 return; 2185 } 2186 2187 } 2188 2189 static int max98090_probe(struct snd_soc_codec *codec) 2190 { 2191 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2192 struct max98090_cdata *cdata; 2193 int ret = 0; 2194 2195 dev_dbg(codec->dev, "max98090_probe\n"); 2196 2197 max98090->codec = codec; 2198 2199 codec->control_data = max98090->regmap; 2200 2201 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP); 2202 if (ret != 0) { 2203 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 2204 return ret; 2205 } 2206 2207 /* Reset the codec, the DSP core, and disable all interrupts */ 2208 max98090_reset(max98090); 2209 2210 /* Initialize private data */ 2211 2212 max98090->sysclk = (unsigned)-1; 2213 2214 cdata = &max98090->dai[0]; 2215 cdata->rate = (unsigned)-1; 2216 cdata->fmt = (unsigned)-1; 2217 2218 max98090->lin_state = 0; 2219 max98090->pa1en = 0; 2220 max98090->pa2en = 0; 2221 max98090->extmic_mux = 0; 2222 2223 ret = snd_soc_read(codec, M98090_REG_REVISION_ID); 2224 if (ret < 0) { 2225 dev_err(codec->dev, "Failed to read device revision: %d\n", 2226 ret); 2227 goto err_access; 2228 } 2229 2230 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) { 2231 max98090->devtype = MAX98090; 2232 dev_info(codec->dev, "MAX98090 REVID=0x%02x\n", ret); 2233 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) { 2234 max98090->devtype = MAX98091; 2235 dev_info(codec->dev, "MAX98091 REVID=0x%02x\n", ret); 2236 } else { 2237 max98090->devtype = MAX98090; 2238 dev_err(codec->dev, "Unrecognized revision 0x%02x\n", ret); 2239 } 2240 2241 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2242 2243 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); 2244 2245 /* Enable jack detection */ 2246 snd_soc_write(codec, M98090_REG_JACK_DETECT, 2247 M98090_JDETEN_MASK | M98090_JDEB_25MS); 2248 2249 /* Register for interrupts */ 2250 dev_dbg(codec->dev, "irq = %d\n", max98090->irq); 2251 2252 ret = request_threaded_irq(max98090->irq, NULL, 2253 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2254 "max98090_interrupt", codec); 2255 if (ret < 0) { 2256 dev_err(codec->dev, "request_irq failed: %d\n", 2257 ret); 2258 } 2259 2260 /* 2261 * Clear any old interrupts. 2262 * An old interrupt ocurring prior to installing the ISR 2263 * can keep a new interrupt from generating a trigger. 2264 */ 2265 snd_soc_read(codec, M98090_REG_DEVICE_STATUS); 2266 2267 /* High Performance is default */ 2268 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL, 2269 M98090_DACHP_MASK, 2270 1 << M98090_DACHP_SHIFT); 2271 snd_soc_update_bits(codec, M98090_REG_DAC_CONTROL, 2272 M98090_PERFMODE_MASK, 2273 0 << M98090_PERFMODE_SHIFT); 2274 snd_soc_update_bits(codec, M98090_REG_ADC_CONTROL, 2275 M98090_ADCHP_MASK, 2276 1 << M98090_ADCHP_SHIFT); 2277 2278 /* Turn on VCM bandgap reference */ 2279 snd_soc_write(codec, M98090_REG_BIAS_CONTROL, 2280 M98090_VCM_MODE_MASK); 2281 2282 max98090_handle_pdata(codec); 2283 2284 max98090_add_widgets(codec); 2285 2286 err_access: 2287 return ret; 2288 } 2289 2290 static int max98090_remove(struct snd_soc_codec *codec) 2291 { 2292 struct max98090_priv *max98090 = snd_soc_codec_get_drvdata(codec); 2293 2294 cancel_delayed_work_sync(&max98090->jack_work); 2295 2296 return 0; 2297 } 2298 2299 static struct snd_soc_codec_driver soc_codec_dev_max98090 = { 2300 .probe = max98090_probe, 2301 .remove = max98090_remove, 2302 .set_bias_level = max98090_set_bias_level, 2303 }; 2304 2305 static const struct regmap_config max98090_regmap = { 2306 .reg_bits = 8, 2307 .val_bits = 8, 2308 2309 .max_register = MAX98090_MAX_REGISTER, 2310 .reg_defaults = max98090_reg, 2311 .num_reg_defaults = ARRAY_SIZE(max98090_reg), 2312 .volatile_reg = max98090_volatile_register, 2313 .readable_reg = max98090_readable_register, 2314 .cache_type = REGCACHE_RBTREE, 2315 }; 2316 2317 static int max98090_i2c_probe(struct i2c_client *i2c, 2318 const struct i2c_device_id *id) 2319 { 2320 struct max98090_priv *max98090; 2321 int ret; 2322 2323 pr_debug("max98090_i2c_probe\n"); 2324 2325 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), 2326 GFP_KERNEL); 2327 if (max98090 == NULL) 2328 return -ENOMEM; 2329 2330 max98090->devtype = id->driver_data; 2331 i2c_set_clientdata(i2c, max98090); 2332 max98090->control_data = i2c; 2333 max98090->pdata = i2c->dev.platform_data; 2334 max98090->irq = i2c->irq; 2335 2336 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); 2337 if (IS_ERR(max98090->regmap)) { 2338 ret = PTR_ERR(max98090->regmap); 2339 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 2340 goto err_enable; 2341 } 2342 2343 ret = snd_soc_register_codec(&i2c->dev, 2344 &soc_codec_dev_max98090, max98090_dai, 2345 ARRAY_SIZE(max98090_dai)); 2346 err_enable: 2347 return ret; 2348 } 2349 2350 static int max98090_i2c_remove(struct i2c_client *client) 2351 { 2352 snd_soc_unregister_codec(&client->dev); 2353 return 0; 2354 } 2355 2356 #ifdef CONFIG_PM_RUNTIME 2357 static int max98090_runtime_resume(struct device *dev) 2358 { 2359 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2360 2361 regcache_cache_only(max98090->regmap, false); 2362 2363 regcache_sync(max98090->regmap); 2364 2365 return 0; 2366 } 2367 2368 static int max98090_runtime_suspend(struct device *dev) 2369 { 2370 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2371 2372 regcache_cache_only(max98090->regmap, true); 2373 2374 return 0; 2375 } 2376 #endif 2377 2378 static const struct dev_pm_ops max98090_pm = { 2379 SET_RUNTIME_PM_OPS(max98090_runtime_suspend, 2380 max98090_runtime_resume, NULL) 2381 }; 2382 2383 static const struct i2c_device_id max98090_i2c_id[] = { 2384 { "max98090", MAX98090 }, 2385 { } 2386 }; 2387 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); 2388 2389 static struct i2c_driver max98090_i2c_driver = { 2390 .driver = { 2391 .name = "max98090", 2392 .owner = THIS_MODULE, 2393 .pm = &max98090_pm, 2394 }, 2395 .probe = max98090_i2c_probe, 2396 .remove = max98090_i2c_remove, 2397 .id_table = max98090_i2c_id, 2398 }; 2399 2400 module_i2c_driver(max98090_i2c_driver); 2401 2402 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); 2403 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong"); 2404 MODULE_LICENSE("GPL"); 2405