1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * max98090.c -- MAX98090 ALSA SoC Audio driver 4 * 5 * Copyright 2011-2012 Maxim Integrated Products 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/pm.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/slab.h> 16 #include <linux/acpi.h> 17 #include <linux/clk.h> 18 #include <sound/jack.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 #include <sound/tlv.h> 23 #include <sound/max98090.h> 24 #include "max98090.h" 25 26 /* Allows for sparsely populated register maps */ 27 static const struct reg_default max98090_reg[] = { 28 { 0x00, 0x00 }, /* 00 Software Reset */ 29 { 0x03, 0x04 }, /* 03 Interrupt Masks */ 30 { 0x04, 0x00 }, /* 04 System Clock Quick */ 31 { 0x05, 0x00 }, /* 05 Sample Rate Quick */ 32 { 0x06, 0x00 }, /* 06 DAI Interface Quick */ 33 { 0x07, 0x00 }, /* 07 DAC Path Quick */ 34 { 0x08, 0x00 }, /* 08 Mic/Direct to ADC Quick */ 35 { 0x09, 0x00 }, /* 09 Line to ADC Quick */ 36 { 0x0A, 0x00 }, /* 0A Analog Mic Loop Quick */ 37 { 0x0B, 0x00 }, /* 0B Analog Line Loop Quick */ 38 { 0x0C, 0x00 }, /* 0C Reserved */ 39 { 0x0D, 0x00 }, /* 0D Input Config */ 40 { 0x0E, 0x1B }, /* 0E Line Input Level */ 41 { 0x0F, 0x00 }, /* 0F Line Config */ 42 43 { 0x10, 0x14 }, /* 10 Mic1 Input Level */ 44 { 0x11, 0x14 }, /* 11 Mic2 Input Level */ 45 { 0x12, 0x00 }, /* 12 Mic Bias Voltage */ 46 { 0x13, 0x00 }, /* 13 Digital Mic Config */ 47 { 0x14, 0x00 }, /* 14 Digital Mic Mode */ 48 { 0x15, 0x00 }, /* 15 Left ADC Mixer */ 49 { 0x16, 0x00 }, /* 16 Right ADC Mixer */ 50 { 0x17, 0x03 }, /* 17 Left ADC Level */ 51 { 0x18, 0x03 }, /* 18 Right ADC Level */ 52 { 0x19, 0x00 }, /* 19 ADC Biquad Level */ 53 { 0x1A, 0x00 }, /* 1A ADC Sidetone */ 54 { 0x1B, 0x00 }, /* 1B System Clock */ 55 { 0x1C, 0x00 }, /* 1C Clock Mode */ 56 { 0x1D, 0x00 }, /* 1D Any Clock 1 */ 57 { 0x1E, 0x00 }, /* 1E Any Clock 2 */ 58 { 0x1F, 0x00 }, /* 1F Any Clock 3 */ 59 60 { 0x20, 0x00 }, /* 20 Any Clock 4 */ 61 { 0x21, 0x00 }, /* 21 Master Mode */ 62 { 0x22, 0x00 }, /* 22 Interface Format */ 63 { 0x23, 0x00 }, /* 23 TDM Format 1*/ 64 { 0x24, 0x00 }, /* 24 TDM Format 2*/ 65 { 0x25, 0x00 }, /* 25 I/O Configuration */ 66 { 0x26, 0x80 }, /* 26 Filter Config */ 67 { 0x27, 0x00 }, /* 27 DAI Playback Level */ 68 { 0x28, 0x00 }, /* 28 EQ Playback Level */ 69 { 0x29, 0x00 }, /* 29 Left HP Mixer */ 70 { 0x2A, 0x00 }, /* 2A Right HP Mixer */ 71 { 0x2B, 0x00 }, /* 2B HP Control */ 72 { 0x2C, 0x1A }, /* 2C Left HP Volume */ 73 { 0x2D, 0x1A }, /* 2D Right HP Volume */ 74 { 0x2E, 0x00 }, /* 2E Left Spk Mixer */ 75 { 0x2F, 0x00 }, /* 2F Right Spk Mixer */ 76 77 { 0x30, 0x00 }, /* 30 Spk Control */ 78 { 0x31, 0x2C }, /* 31 Left Spk Volume */ 79 { 0x32, 0x2C }, /* 32 Right Spk Volume */ 80 { 0x33, 0x00 }, /* 33 ALC Timing */ 81 { 0x34, 0x00 }, /* 34 ALC Compressor */ 82 { 0x35, 0x00 }, /* 35 ALC Expander */ 83 { 0x36, 0x00 }, /* 36 ALC Gain */ 84 { 0x37, 0x00 }, /* 37 Rcv/Line OutL Mixer */ 85 { 0x38, 0x00 }, /* 38 Rcv/Line OutL Control */ 86 { 0x39, 0x15 }, /* 39 Rcv/Line OutL Volume */ 87 { 0x3A, 0x00 }, /* 3A Line OutR Mixer */ 88 { 0x3B, 0x00 }, /* 3B Line OutR Control */ 89 { 0x3C, 0x15 }, /* 3C Line OutR Volume */ 90 { 0x3D, 0x00 }, /* 3D Jack Detect */ 91 { 0x3E, 0x00 }, /* 3E Input Enable */ 92 { 0x3F, 0x00 }, /* 3F Output Enable */ 93 94 { 0x40, 0x00 }, /* 40 Level Control */ 95 { 0x41, 0x00 }, /* 41 DSP Filter Enable */ 96 { 0x42, 0x00 }, /* 42 Bias Control */ 97 { 0x43, 0x00 }, /* 43 DAC Control */ 98 { 0x44, 0x06 }, /* 44 ADC Control */ 99 { 0x45, 0x00 }, /* 45 Device Shutdown */ 100 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */ 101 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */ 102 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */ 103 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */ 104 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */ 105 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */ 106 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */ 107 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */ 108 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */ 109 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */ 110 111 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */ 112 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */ 113 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */ 114 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */ 115 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */ 116 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */ 117 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */ 118 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */ 119 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */ 120 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */ 121 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */ 122 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */ 123 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */ 124 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */ 125 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */ 126 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */ 127 128 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */ 129 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */ 130 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */ 131 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */ 132 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */ 133 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */ 134 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */ 135 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */ 136 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */ 137 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */ 138 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */ 139 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */ 140 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */ 141 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */ 142 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */ 143 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */ 144 145 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */ 146 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */ 147 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */ 148 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */ 149 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */ 150 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */ 151 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */ 152 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */ 153 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */ 154 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */ 155 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */ 156 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */ 157 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */ 158 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */ 159 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */ 160 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */ 161 162 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */ 163 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */ 164 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */ 165 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */ 166 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */ 167 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */ 168 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */ 169 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */ 170 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */ 171 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */ 172 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */ 173 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */ 174 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */ 175 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */ 176 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */ 177 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */ 178 179 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */ 180 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */ 181 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */ 182 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */ 183 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */ 184 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */ 185 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */ 186 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */ 187 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */ 188 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */ 189 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */ 190 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */ 191 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */ 192 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */ 193 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */ 194 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */ 195 196 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */ 197 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */ 198 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */ 199 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */ 200 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */ 201 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */ 202 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */ 203 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */ 204 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */ 205 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */ 206 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */ 207 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */ 208 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */ 209 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */ 210 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */ 211 { 0xAF, 0x00 }, /* AF ADC Biquad Coefficient B0 */ 212 213 { 0xB0, 0x00 }, /* B0 ADC Biquad Coefficient B0 */ 214 { 0xB1, 0x00 }, /* B1 ADC Biquad Coefficient B0 */ 215 { 0xB2, 0x00 }, /* B2 ADC Biquad Coefficient B1 */ 216 { 0xB3, 0x00 }, /* B3 ADC Biquad Coefficient B1 */ 217 { 0xB4, 0x00 }, /* B4 ADC Biquad Coefficient B1 */ 218 { 0xB5, 0x00 }, /* B5 ADC Biquad Coefficient B2 */ 219 { 0xB6, 0x00 }, /* B6 ADC Biquad Coefficient B2 */ 220 { 0xB7, 0x00 }, /* B7 ADC Biquad Coefficient B2 */ 221 { 0xB8, 0x00 }, /* B8 ADC Biquad Coefficient A1 */ 222 { 0xB9, 0x00 }, /* B9 ADC Biquad Coefficient A1 */ 223 { 0xBA, 0x00 }, /* BA ADC Biquad Coefficient A1 */ 224 { 0xBB, 0x00 }, /* BB ADC Biquad Coefficient A2 */ 225 { 0xBC, 0x00 }, /* BC ADC Biquad Coefficient A2 */ 226 { 0xBD, 0x00 }, /* BD ADC Biquad Coefficient A2 */ 227 { 0xBE, 0x00 }, /* BE Digital Mic 3 Volume */ 228 { 0xBF, 0x00 }, /* BF Digital Mic 4 Volume */ 229 230 { 0xC0, 0x00 }, /* C0 Digital Mic 34 Biquad Pre Atten */ 231 { 0xC1, 0x00 }, /* C1 Record TDM Slot */ 232 { 0xC2, 0x00 }, /* C2 Sample Rate */ 233 { 0xC3, 0x00 }, /* C3 Digital Mic 34 Biquad Coefficient C3 */ 234 { 0xC4, 0x00 }, /* C4 Digital Mic 34 Biquad Coefficient C4 */ 235 { 0xC5, 0x00 }, /* C5 Digital Mic 34 Biquad Coefficient C5 */ 236 { 0xC6, 0x00 }, /* C6 Digital Mic 34 Biquad Coefficient C6 */ 237 { 0xC7, 0x00 }, /* C7 Digital Mic 34 Biquad Coefficient C7 */ 238 { 0xC8, 0x00 }, /* C8 Digital Mic 34 Biquad Coefficient C8 */ 239 { 0xC9, 0x00 }, /* C9 Digital Mic 34 Biquad Coefficient C9 */ 240 { 0xCA, 0x00 }, /* CA Digital Mic 34 Biquad Coefficient CA */ 241 { 0xCB, 0x00 }, /* CB Digital Mic 34 Biquad Coefficient CB */ 242 { 0xCC, 0x00 }, /* CC Digital Mic 34 Biquad Coefficient CC */ 243 { 0xCD, 0x00 }, /* CD Digital Mic 34 Biquad Coefficient CD */ 244 { 0xCE, 0x00 }, /* CE Digital Mic 34 Biquad Coefficient CE */ 245 { 0xCF, 0x00 }, /* CF Digital Mic 34 Biquad Coefficient CF */ 246 247 { 0xD0, 0x00 }, /* D0 Digital Mic 34 Biquad Coefficient D0 */ 248 { 0xD1, 0x00 }, /* D1 Digital Mic 34 Biquad Coefficient D1 */ 249 }; 250 251 static bool max98090_volatile_register(struct device *dev, unsigned int reg) 252 { 253 switch (reg) { 254 case M98090_REG_SOFTWARE_RESET: 255 case M98090_REG_DEVICE_STATUS: 256 case M98090_REG_JACK_STATUS: 257 case M98090_REG_REVISION_ID: 258 return true; 259 default: 260 return false; 261 } 262 } 263 264 static bool max98090_readable_register(struct device *dev, unsigned int reg) 265 { 266 switch (reg) { 267 case M98090_REG_DEVICE_STATUS ... M98090_REG_INTERRUPT_S: 268 case M98090_REG_LINE_INPUT_CONFIG ... 0xD1: 269 case M98090_REG_REVISION_ID: 270 return true; 271 default: 272 return false; 273 } 274 } 275 276 static int max98090_reset(struct max98090_priv *max98090) 277 { 278 int ret; 279 280 /* Reset the codec by writing to this write-only reset register */ 281 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, 282 M98090_SWRESET_MASK); 283 if (ret < 0) { 284 dev_err(max98090->component->dev, 285 "Failed to reset codec: %d\n", ret); 286 return ret; 287 } 288 289 msleep(20); 290 return ret; 291 } 292 293 static const DECLARE_TLV_DB_RANGE(max98090_micboost_tlv, 294 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 295 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0) 296 ); 297 298 static const DECLARE_TLV_DB_SCALE(max98090_mic_tlv, 0, 100, 0); 299 300 static const DECLARE_TLV_DB_SCALE(max98090_line_single_ended_tlv, 301 -600, 600, 0); 302 303 static const DECLARE_TLV_DB_RANGE(max98090_line_tlv, 304 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0), 305 4, 5, TLV_DB_SCALE_ITEM(1400, 600, 0) 306 ); 307 308 static const DECLARE_TLV_DB_SCALE(max98090_avg_tlv, 0, 600, 0); 309 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0); 310 311 static const DECLARE_TLV_DB_SCALE(max98090_dvg_tlv, 0, 600, 0); 312 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0); 313 314 static const DECLARE_TLV_DB_SCALE(max98090_alcmakeup_tlv, 0, 100, 0); 315 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0); 316 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0); 317 static const DECLARE_TLV_DB_SCALE(max98090_sdg_tlv, 50, 200, 0); 318 319 static const DECLARE_TLV_DB_RANGE(max98090_mixout_tlv, 320 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0), 321 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0) 322 ); 323 324 static const DECLARE_TLV_DB_RANGE(max98090_hp_tlv, 325 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 326 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 327 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 328 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 329 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0) 330 ); 331 332 static const DECLARE_TLV_DB_RANGE(max98090_spk_tlv, 333 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0), 334 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0), 335 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0), 336 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0), 337 30, 39, TLV_DB_SCALE_ITEM(950, 50, 0) 338 ); 339 340 static const DECLARE_TLV_DB_RANGE(max98090_rcv_lout_tlv, 341 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 342 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 343 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 344 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 345 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0) 346 ); 347 348 static int max98090_get_enab_tlv(struct snd_kcontrol *kcontrol, 349 struct snd_ctl_elem_value *ucontrol) 350 { 351 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 352 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 353 struct soc_mixer_control *mc = 354 (struct soc_mixer_control *)kcontrol->private_value; 355 unsigned int mask = (1 << fls(mc->max)) - 1; 356 unsigned int val = snd_soc_component_read(component, mc->reg); 357 unsigned int *select; 358 359 switch (mc->reg) { 360 case M98090_REG_MIC1_INPUT_LEVEL: 361 select = &(max98090->pa1en); 362 break; 363 case M98090_REG_MIC2_INPUT_LEVEL: 364 select = &(max98090->pa2en); 365 break; 366 case M98090_REG_ADC_SIDETONE: 367 select = &(max98090->sidetone); 368 break; 369 default: 370 return -EINVAL; 371 } 372 373 val = (val >> mc->shift) & mask; 374 375 if (val >= 1) { 376 /* If on, return the volume */ 377 val = val - 1; 378 *select = val; 379 } else { 380 /* If off, return last stored value */ 381 val = *select; 382 } 383 384 ucontrol->value.integer.value[0] = val; 385 return 0; 386 } 387 388 static int max98090_put_enab_tlv(struct snd_kcontrol *kcontrol, 389 struct snd_ctl_elem_value *ucontrol) 390 { 391 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 392 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 393 struct soc_mixer_control *mc = 394 (struct soc_mixer_control *)kcontrol->private_value; 395 unsigned int mask = (1 << fls(mc->max)) - 1; 396 int sel_unchecked = ucontrol->value.integer.value[0]; 397 unsigned int sel; 398 unsigned int val = snd_soc_component_read(component, mc->reg); 399 unsigned int *select; 400 int change; 401 402 switch (mc->reg) { 403 case M98090_REG_MIC1_INPUT_LEVEL: 404 select = &(max98090->pa1en); 405 break; 406 case M98090_REG_MIC2_INPUT_LEVEL: 407 select = &(max98090->pa2en); 408 break; 409 case M98090_REG_ADC_SIDETONE: 410 select = &(max98090->sidetone); 411 break; 412 default: 413 return -EINVAL; 414 } 415 416 val = (val >> mc->shift) & mask; 417 418 if (sel_unchecked < 0 || sel_unchecked > mc->max) 419 return -EINVAL; 420 sel = sel_unchecked; 421 422 change = *select != sel; 423 *select = sel; 424 425 /* Setting a volume is only valid if it is already On */ 426 if (val >= 1) { 427 sel = sel + 1; 428 } else { 429 /* Write what was already there */ 430 sel = val; 431 } 432 433 snd_soc_component_update_bits(component, mc->reg, 434 mask << mc->shift, 435 sel << mc->shift); 436 437 return change; 438 } 439 440 static const char *max98090_perf_pwr_text[] = 441 { "High Performance", "Low Power" }; 442 static const char *max98090_pwr_perf_text[] = 443 { "Low Power", "High Performance" }; 444 445 static SOC_ENUM_SINGLE_DECL(max98090_vcmbandgap_enum, 446 M98090_REG_BIAS_CONTROL, 447 M98090_VCM_MODE_SHIFT, 448 max98090_pwr_perf_text); 449 450 static const char *max98090_osr128_text[] = { "64*fs", "128*fs" }; 451 452 static SOC_ENUM_SINGLE_DECL(max98090_osr128_enum, 453 M98090_REG_ADC_CONTROL, 454 M98090_OSR128_SHIFT, 455 max98090_osr128_text); 456 457 static const char *max98090_mode_text[] = { "Voice", "Music" }; 458 459 static SOC_ENUM_SINGLE_DECL(max98090_mode_enum, 460 M98090_REG_FILTER_CONFIG, 461 M98090_MODE_SHIFT, 462 max98090_mode_text); 463 464 static SOC_ENUM_SINGLE_DECL(max98090_filter_dmic34mode_enum, 465 M98090_REG_FILTER_CONFIG, 466 M98090_FLT_DMIC34MODE_SHIFT, 467 max98090_mode_text); 468 469 static const char *max98090_drcatk_text[] = 470 { "0.5ms", "1ms", "5ms", "10ms", "25ms", "50ms", "100ms", "200ms" }; 471 472 static SOC_ENUM_SINGLE_DECL(max98090_drcatk_enum, 473 M98090_REG_DRC_TIMING, 474 M98090_DRCATK_SHIFT, 475 max98090_drcatk_text); 476 477 static const char *max98090_drcrls_text[] = 478 { "8s", "4s", "2s", "1s", "0.5s", "0.25s", "0.125s", "0.0625s" }; 479 480 static SOC_ENUM_SINGLE_DECL(max98090_drcrls_enum, 481 M98090_REG_DRC_TIMING, 482 M98090_DRCRLS_SHIFT, 483 max98090_drcrls_text); 484 485 static const char *max98090_alccmp_text[] = 486 { "1:1", "1:1.5", "1:2", "1:4", "1:INF" }; 487 488 static SOC_ENUM_SINGLE_DECL(max98090_alccmp_enum, 489 M98090_REG_DRC_COMPRESSOR, 490 M98090_DRCCMP_SHIFT, 491 max98090_alccmp_text); 492 493 static const char *max98090_drcexp_text[] = { "1:1", "2:1", "3:1" }; 494 495 static SOC_ENUM_SINGLE_DECL(max98090_drcexp_enum, 496 M98090_REG_DRC_EXPANDER, 497 M98090_DRCEXP_SHIFT, 498 max98090_drcexp_text); 499 500 static SOC_ENUM_SINGLE_DECL(max98090_dac_perfmode_enum, 501 M98090_REG_DAC_CONTROL, 502 M98090_PERFMODE_SHIFT, 503 max98090_perf_pwr_text); 504 505 static SOC_ENUM_SINGLE_DECL(max98090_dachp_enum, 506 M98090_REG_DAC_CONTROL, 507 M98090_DACHP_SHIFT, 508 max98090_pwr_perf_text); 509 510 static SOC_ENUM_SINGLE_DECL(max98090_adchp_enum, 511 M98090_REG_ADC_CONTROL, 512 M98090_ADCHP_SHIFT, 513 max98090_pwr_perf_text); 514 515 static const struct snd_kcontrol_new max98090_snd_controls[] = { 516 SOC_ENUM("MIC Bias VCM Bandgap", max98090_vcmbandgap_enum), 517 518 SOC_SINGLE("DMIC MIC Comp Filter Config", M98090_REG_DIGITAL_MIC_CONFIG, 519 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0), 520 521 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 522 M98090_REG_MIC1_INPUT_LEVEL, M98090_MIC_PA1EN_SHIFT, 523 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv, 524 max98090_put_enab_tlv, max98090_micboost_tlv), 525 526 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 527 M98090_REG_MIC2_INPUT_LEVEL, M98090_MIC_PA2EN_SHIFT, 528 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv, 529 max98090_put_enab_tlv, max98090_micboost_tlv), 530 531 SOC_SINGLE_TLV("MIC1 Volume", M98090_REG_MIC1_INPUT_LEVEL, 532 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1, 533 max98090_mic_tlv), 534 535 SOC_SINGLE_TLV("MIC2 Volume", M98090_REG_MIC2_INPUT_LEVEL, 536 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1, 537 max98090_mic_tlv), 538 539 SOC_SINGLE_RANGE_TLV("LINEA Single Ended Volume", 540 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG135_SHIFT, 0, 541 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv), 542 543 SOC_SINGLE_RANGE_TLV("LINEB Single Ended Volume", 544 M98090_REG_LINE_INPUT_LEVEL, M98090_MIXG246_SHIFT, 0, 545 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv), 546 547 SOC_SINGLE_RANGE_TLV("LINEA Volume", M98090_REG_LINE_INPUT_LEVEL, 548 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1, 549 max98090_line_tlv), 550 551 SOC_SINGLE_RANGE_TLV("LINEB Volume", M98090_REG_LINE_INPUT_LEVEL, 552 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1, 553 max98090_line_tlv), 554 555 SOC_SINGLE("LINEA Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 556 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0), 557 SOC_SINGLE("LINEB Ext Resistor Gain Mode", M98090_REG_INPUT_MODE, 558 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0), 559 560 SOC_SINGLE_TLV("ADCL Boost Volume", M98090_REG_LEFT_ADC_LEVEL, 561 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0, 562 max98090_avg_tlv), 563 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL, 564 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0, 565 max98090_avg_tlv), 566 567 SOC_SINGLE_TLV("ADCL Volume", M98090_REG_LEFT_ADC_LEVEL, 568 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1, 569 max98090_av_tlv), 570 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL, 571 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1, 572 max98090_av_tlv), 573 574 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum), 575 SOC_SINGLE("ADC Quantizer Dither", M98090_REG_ADC_CONTROL, 576 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0), 577 SOC_ENUM("ADC High Performance Mode", max98090_adchp_enum), 578 579 SOC_SINGLE("DAC Mono Mode", M98090_REG_IO_CONFIGURATION, 580 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0), 581 SOC_SINGLE("SDIN Mode", M98090_REG_IO_CONFIGURATION, 582 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0), 583 SOC_SINGLE("SDOUT Mode", M98090_REG_IO_CONFIGURATION, 584 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0), 585 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION, 586 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1), 587 SOC_ENUM("Filter Mode", max98090_mode_enum), 588 SOC_SINGLE("Record Path DC Blocking", M98090_REG_FILTER_CONFIG, 589 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0), 590 SOC_SINGLE("Playback Path DC Blocking", M98090_REG_FILTER_CONFIG, 591 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0), 592 SOC_SINGLE_TLV("Digital BQ Volume", M98090_REG_ADC_BIQUAD_LEVEL, 593 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv), 594 SOC_SINGLE_EXT_TLV("Digital Sidetone Volume", 595 M98090_REG_ADC_SIDETONE, M98090_DVST_SHIFT, 596 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv, 597 max98090_put_enab_tlv, max98090_sdg_tlv), 598 SOC_SINGLE_TLV("Digital Coarse Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 599 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0, 600 max98090_dvg_tlv), 601 SOC_SINGLE_TLV("Digital Volume", M98090_REG_DAI_PLAYBACK_LEVEL, 602 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1, 603 max98090_dv_tlv), 604 SND_SOC_BYTES("EQ Coefficients", M98090_REG_EQUALIZER_BASE, 105), 605 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 606 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0), 607 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 608 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0), 609 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE, 610 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0), 611 SOC_SINGLE("Digital EQ Clipping Detection", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 612 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1, 613 1), 614 SOC_SINGLE_TLV("Digital EQ Volume", M98090_REG_DAI_PLAYBACK_LEVEL_EQ, 615 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1, 616 max98090_dv_tlv), 617 618 SOC_SINGLE("ALC Enable", M98090_REG_DRC_TIMING, 619 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0), 620 SOC_ENUM("ALC Attack Time", max98090_drcatk_enum), 621 SOC_ENUM("ALC Release Time", max98090_drcrls_enum), 622 SOC_SINGLE_TLV("ALC Make Up Volume", M98090_REG_DRC_GAIN, 623 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0, 624 max98090_alcmakeup_tlv), 625 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum), 626 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum), 627 SOC_SINGLE_TLV("ALC Compression Threshold Volume", 628 M98090_REG_DRC_COMPRESSOR, M98090_DRCTHC_SHIFT, 629 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv), 630 SOC_SINGLE_TLV("ALC Expansion Threshold Volume", 631 M98090_REG_DRC_EXPANDER, M98090_DRCTHE_SHIFT, 632 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv), 633 634 SOC_ENUM("DAC HP Playback Performance Mode", 635 max98090_dac_perfmode_enum), 636 SOC_ENUM("DAC High Performance Mode", max98090_dachp_enum), 637 638 SOC_SINGLE_TLV("Headphone Left Mixer Volume", 639 M98090_REG_HP_CONTROL, M98090_MIXHPLG_SHIFT, 640 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv), 641 SOC_SINGLE_TLV("Headphone Right Mixer Volume", 642 M98090_REG_HP_CONTROL, M98090_MIXHPRG_SHIFT, 643 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv), 644 645 SOC_SINGLE_TLV("Speaker Left Mixer Volume", 646 M98090_REG_SPK_CONTROL, M98090_MIXSPLG_SHIFT, 647 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv), 648 SOC_SINGLE_TLV("Speaker Right Mixer Volume", 649 M98090_REG_SPK_CONTROL, M98090_MIXSPRG_SHIFT, 650 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv), 651 652 SOC_SINGLE_TLV("Receiver Left Mixer Volume", 653 M98090_REG_RCV_LOUTL_CONTROL, M98090_MIXRCVLG_SHIFT, 654 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv), 655 SOC_SINGLE_TLV("Receiver Right Mixer Volume", 656 M98090_REG_LOUTR_CONTROL, M98090_MIXRCVRG_SHIFT, 657 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv), 658 659 SOC_DOUBLE_R_TLV("Headphone Volume", M98090_REG_LEFT_HP_VOLUME, 660 M98090_REG_RIGHT_HP_VOLUME, M98090_HPVOLL_SHIFT, 661 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv), 662 663 SOC_DOUBLE_R_RANGE_TLV("Speaker Volume", 664 M98090_REG_LEFT_SPK_VOLUME, M98090_REG_RIGHT_SPK_VOLUME, 665 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24, 666 0, max98090_spk_tlv), 667 668 SOC_DOUBLE_R_TLV("Receiver Volume", M98090_REG_RCV_LOUTL_VOLUME, 669 M98090_REG_LOUTR_VOLUME, M98090_RCVLVOL_SHIFT, 670 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv), 671 672 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME, 673 M98090_HPLM_SHIFT, 1, 1), 674 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME, 675 M98090_HPRM_SHIFT, 1, 1), 676 677 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME, 678 M98090_SPLM_SHIFT, 1, 1), 679 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME, 680 M98090_SPRM_SHIFT, 1, 1), 681 682 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME, 683 M98090_RCVLM_SHIFT, 1, 1), 684 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME, 685 M98090_RCVRM_SHIFT, 1, 1), 686 687 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL, 688 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1), 689 SOC_SINGLE("Enhanced Vol Smoothing", M98090_REG_LEVEL_CONTROL, 690 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1), 691 SOC_SINGLE("Volume Adjustment Smoothing", M98090_REG_LEVEL_CONTROL, 692 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1), 693 694 SND_SOC_BYTES("Biquad Coefficients", M98090_REG_RECORD_BIQUAD_BASE, 15), 695 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 696 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0), 697 }; 698 699 static const struct snd_kcontrol_new max98091_snd_controls[] = { 700 701 SOC_SINGLE("DMIC34 Zeropad", M98090_REG_SAMPLE_RATE, 702 M98090_DMIC34_ZEROPAD_SHIFT, 703 M98090_DMIC34_ZEROPAD_NUM - 1, 0), 704 705 SOC_ENUM("Filter DMIC34 Mode", max98090_filter_dmic34mode_enum), 706 SOC_SINGLE("DMIC34 DC Blocking", M98090_REG_FILTER_CONFIG, 707 M98090_FLT_DMIC34HPF_SHIFT, 708 M98090_FLT_DMIC34HPF_NUM - 1, 0), 709 710 SOC_SINGLE_TLV("DMIC3 Boost Volume", M98090_REG_DMIC3_VOLUME, 711 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0, 712 max98090_avg_tlv), 713 SOC_SINGLE_TLV("DMIC4 Boost Volume", M98090_REG_DMIC4_VOLUME, 714 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0, 715 max98090_avg_tlv), 716 717 SOC_SINGLE_TLV("DMIC3 Volume", M98090_REG_DMIC3_VOLUME, 718 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1, 719 max98090_av_tlv), 720 SOC_SINGLE_TLV("DMIC4 Volume", M98090_REG_DMIC4_VOLUME, 721 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1, 722 max98090_av_tlv), 723 724 SND_SOC_BYTES("DMIC34 Biquad Coefficients", 725 M98090_REG_DMIC34_BIQUAD_BASE, 15), 726 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE, 727 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0), 728 729 SOC_SINGLE_TLV("DMIC34 BQ PreAttenuation Volume", 730 M98090_REG_DMIC34_BQ_PREATTEN, M98090_AV34BQ_SHIFT, 731 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv), 732 }; 733 734 static int max98090_micinput_event(struct snd_soc_dapm_widget *w, 735 struct snd_kcontrol *kcontrol, int event) 736 { 737 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 738 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 739 740 unsigned int val = snd_soc_component_read(component, w->reg); 741 742 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 743 val = (val & M98090_MIC_PA1EN_MASK) >> M98090_MIC_PA1EN_SHIFT; 744 else 745 val = (val & M98090_MIC_PA2EN_MASK) >> M98090_MIC_PA2EN_SHIFT; 746 747 if (val >= 1) { 748 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { 749 max98090->pa1en = val - 1; /* Update for volatile */ 750 } else { 751 max98090->pa2en = val - 1; /* Update for volatile */ 752 } 753 } 754 755 switch (event) { 756 case SND_SOC_DAPM_POST_PMU: 757 /* If turning on, set to most recently selected volume */ 758 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 759 val = max98090->pa1en + 1; 760 else 761 val = max98090->pa2en + 1; 762 break; 763 case SND_SOC_DAPM_POST_PMD: 764 /* If turning off, turn off */ 765 val = 0; 766 break; 767 default: 768 return -EINVAL; 769 } 770 771 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) 772 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK, 773 val << M98090_MIC_PA1EN_SHIFT); 774 else 775 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK, 776 val << M98090_MIC_PA2EN_SHIFT); 777 778 return 0; 779 } 780 781 static int max98090_shdn_event(struct snd_soc_dapm_widget *w, 782 struct snd_kcontrol *kcontrol, int event) 783 { 784 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 785 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 786 787 if (event & SND_SOC_DAPM_POST_PMU) 788 max98090->shdn_pending = true; 789 790 return 0; 791 792 } 793 794 static const char *mic1_mux_text[] = { "IN12", "IN56" }; 795 796 static SOC_ENUM_SINGLE_DECL(mic1_mux_enum, 797 M98090_REG_INPUT_MODE, 798 M98090_EXTMIC1_SHIFT, 799 mic1_mux_text); 800 801 static const struct snd_kcontrol_new max98090_mic1_mux = 802 SOC_DAPM_ENUM("MIC1 Mux", mic1_mux_enum); 803 804 static const char *mic2_mux_text[] = { "IN34", "IN56" }; 805 806 static SOC_ENUM_SINGLE_DECL(mic2_mux_enum, 807 M98090_REG_INPUT_MODE, 808 M98090_EXTMIC2_SHIFT, 809 mic2_mux_text); 810 811 static const struct snd_kcontrol_new max98090_mic2_mux = 812 SOC_DAPM_ENUM("MIC2 Mux", mic2_mux_enum); 813 814 static const char *dmic_mux_text[] = { "ADC", "DMIC" }; 815 816 static SOC_ENUM_SINGLE_VIRT_DECL(dmic_mux_enum, dmic_mux_text); 817 818 static const struct snd_kcontrol_new max98090_dmic_mux = 819 SOC_DAPM_ENUM("DMIC Mux", dmic_mux_enum); 820 821 /* LINEA mixer switch */ 822 static const struct snd_kcontrol_new max98090_linea_mixer_controls[] = { 823 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG, 824 M98090_IN1SEEN_SHIFT, 1, 0), 825 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG, 826 M98090_IN3SEEN_SHIFT, 1, 0), 827 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG, 828 M98090_IN5SEEN_SHIFT, 1, 0), 829 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG, 830 M98090_IN34DIFF_SHIFT, 1, 0), 831 }; 832 833 /* LINEB mixer switch */ 834 static const struct snd_kcontrol_new max98090_lineb_mixer_controls[] = { 835 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG, 836 M98090_IN2SEEN_SHIFT, 1, 0), 837 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG, 838 M98090_IN4SEEN_SHIFT, 1, 0), 839 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG, 840 M98090_IN6SEEN_SHIFT, 1, 0), 841 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG, 842 M98090_IN56DIFF_SHIFT, 1, 0), 843 }; 844 845 /* Left ADC mixer switch */ 846 static const struct snd_kcontrol_new max98090_left_adc_mixer_controls[] = { 847 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER, 848 M98090_MIXADL_IN12DIFF_SHIFT, 1, 0), 849 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER, 850 M98090_MIXADL_IN34DIFF_SHIFT, 1, 0), 851 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER, 852 M98090_MIXADL_IN65DIFF_SHIFT, 1, 0), 853 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER, 854 M98090_MIXADL_LINEA_SHIFT, 1, 0), 855 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER, 856 M98090_MIXADL_LINEB_SHIFT, 1, 0), 857 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER, 858 M98090_MIXADL_MIC1_SHIFT, 1, 0), 859 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER, 860 M98090_MIXADL_MIC2_SHIFT, 1, 0), 861 }; 862 863 /* Right ADC mixer switch */ 864 static const struct snd_kcontrol_new max98090_right_adc_mixer_controls[] = { 865 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER, 866 M98090_MIXADR_IN12DIFF_SHIFT, 1, 0), 867 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER, 868 M98090_MIXADR_IN34DIFF_SHIFT, 1, 0), 869 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER, 870 M98090_MIXADR_IN65DIFF_SHIFT, 1, 0), 871 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER, 872 M98090_MIXADR_LINEA_SHIFT, 1, 0), 873 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER, 874 M98090_MIXADR_LINEB_SHIFT, 1, 0), 875 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER, 876 M98090_MIXADR_MIC1_SHIFT, 1, 0), 877 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER, 878 M98090_MIXADR_MIC2_SHIFT, 1, 0), 879 }; 880 881 static const char *lten_mux_text[] = { "Normal", "Loopthrough" }; 882 883 static SOC_ENUM_SINGLE_DECL(ltenl_mux_enum, 884 M98090_REG_IO_CONFIGURATION, 885 M98090_LTEN_SHIFT, 886 lten_mux_text); 887 888 static SOC_ENUM_SINGLE_DECL(ltenr_mux_enum, 889 M98090_REG_IO_CONFIGURATION, 890 M98090_LTEN_SHIFT, 891 lten_mux_text); 892 893 static const struct snd_kcontrol_new max98090_ltenl_mux = 894 SOC_DAPM_ENUM("LTENL Mux", ltenl_mux_enum); 895 896 static const struct snd_kcontrol_new max98090_ltenr_mux = 897 SOC_DAPM_ENUM("LTENR Mux", ltenr_mux_enum); 898 899 static const char *lben_mux_text[] = { "Normal", "Loopback" }; 900 901 static SOC_ENUM_SINGLE_DECL(lbenl_mux_enum, 902 M98090_REG_IO_CONFIGURATION, 903 M98090_LBEN_SHIFT, 904 lben_mux_text); 905 906 static SOC_ENUM_SINGLE_DECL(lbenr_mux_enum, 907 M98090_REG_IO_CONFIGURATION, 908 M98090_LBEN_SHIFT, 909 lben_mux_text); 910 911 static const struct snd_kcontrol_new max98090_lbenl_mux = 912 SOC_DAPM_ENUM("LBENL Mux", lbenl_mux_enum); 913 914 static const struct snd_kcontrol_new max98090_lbenr_mux = 915 SOC_DAPM_ENUM("LBENR Mux", lbenr_mux_enum); 916 917 static const char *stenl_mux_text[] = { "Normal", "Sidetone Left" }; 918 919 static const char *stenr_mux_text[] = { "Normal", "Sidetone Right" }; 920 921 static SOC_ENUM_SINGLE_DECL(stenl_mux_enum, 922 M98090_REG_ADC_SIDETONE, 923 M98090_DSTSL_SHIFT, 924 stenl_mux_text); 925 926 static SOC_ENUM_SINGLE_DECL(stenr_mux_enum, 927 M98090_REG_ADC_SIDETONE, 928 M98090_DSTSR_SHIFT, 929 stenr_mux_text); 930 931 static const struct snd_kcontrol_new max98090_stenl_mux = 932 SOC_DAPM_ENUM("STENL Mux", stenl_mux_enum); 933 934 static const struct snd_kcontrol_new max98090_stenr_mux = 935 SOC_DAPM_ENUM("STENR Mux", stenr_mux_enum); 936 937 /* Left speaker mixer switch */ 938 static const struct 939 snd_kcontrol_new max98090_left_speaker_mixer_controls[] = { 940 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER, 941 M98090_MIXSPL_DACL_SHIFT, 1, 0), 942 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER, 943 M98090_MIXSPL_DACR_SHIFT, 1, 0), 944 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER, 945 M98090_MIXSPL_LINEA_SHIFT, 1, 0), 946 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER, 947 M98090_MIXSPL_LINEB_SHIFT, 1, 0), 948 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER, 949 M98090_MIXSPL_MIC1_SHIFT, 1, 0), 950 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER, 951 M98090_MIXSPL_MIC2_SHIFT, 1, 0), 952 }; 953 954 /* Right speaker mixer switch */ 955 static const struct 956 snd_kcontrol_new max98090_right_speaker_mixer_controls[] = { 957 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 958 M98090_MIXSPR_DACL_SHIFT, 1, 0), 959 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER, 960 M98090_MIXSPR_DACR_SHIFT, 1, 0), 961 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER, 962 M98090_MIXSPR_LINEA_SHIFT, 1, 0), 963 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER, 964 M98090_MIXSPR_LINEB_SHIFT, 1, 0), 965 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER, 966 M98090_MIXSPR_MIC1_SHIFT, 1, 0), 967 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER, 968 M98090_MIXSPR_MIC2_SHIFT, 1, 0), 969 }; 970 971 /* Left headphone mixer switch */ 972 static const struct snd_kcontrol_new max98090_left_hp_mixer_controls[] = { 973 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER, 974 M98090_MIXHPL_DACL_SHIFT, 1, 0), 975 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER, 976 M98090_MIXHPL_DACR_SHIFT, 1, 0), 977 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER, 978 M98090_MIXHPL_LINEA_SHIFT, 1, 0), 979 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER, 980 M98090_MIXHPL_LINEB_SHIFT, 1, 0), 981 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER, 982 M98090_MIXHPL_MIC1_SHIFT, 1, 0), 983 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER, 984 M98090_MIXHPL_MIC2_SHIFT, 1, 0), 985 }; 986 987 /* Right headphone mixer switch */ 988 static const struct snd_kcontrol_new max98090_right_hp_mixer_controls[] = { 989 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER, 990 M98090_MIXHPR_DACL_SHIFT, 1, 0), 991 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER, 992 M98090_MIXHPR_DACR_SHIFT, 1, 0), 993 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER, 994 M98090_MIXHPR_LINEA_SHIFT, 1, 0), 995 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER, 996 M98090_MIXHPR_LINEB_SHIFT, 1, 0), 997 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER, 998 M98090_MIXHPR_MIC1_SHIFT, 1, 0), 999 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER, 1000 M98090_MIXHPR_MIC2_SHIFT, 1, 0), 1001 }; 1002 1003 /* Left receiver mixer switch */ 1004 static const struct snd_kcontrol_new max98090_left_rcv_mixer_controls[] = { 1005 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1006 M98090_MIXRCVL_DACL_SHIFT, 1, 0), 1007 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER, 1008 M98090_MIXRCVL_DACR_SHIFT, 1, 0), 1009 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER, 1010 M98090_MIXRCVL_LINEA_SHIFT, 1, 0), 1011 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER, 1012 M98090_MIXRCVL_LINEB_SHIFT, 1, 0), 1013 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER, 1014 M98090_MIXRCVL_MIC1_SHIFT, 1, 0), 1015 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER, 1016 M98090_MIXRCVL_MIC2_SHIFT, 1, 0), 1017 }; 1018 1019 /* Right receiver mixer switch */ 1020 static const struct snd_kcontrol_new max98090_right_rcv_mixer_controls[] = { 1021 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER, 1022 M98090_MIXRCVR_DACL_SHIFT, 1, 0), 1023 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER, 1024 M98090_MIXRCVR_DACR_SHIFT, 1, 0), 1025 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER, 1026 M98090_MIXRCVR_LINEA_SHIFT, 1, 0), 1027 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER, 1028 M98090_MIXRCVR_LINEB_SHIFT, 1, 0), 1029 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER, 1030 M98090_MIXRCVR_MIC1_SHIFT, 1, 0), 1031 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER, 1032 M98090_MIXRCVR_MIC2_SHIFT, 1, 0), 1033 }; 1034 1035 static const char *linmod_mux_text[] = { "Left Only", "Left and Right" }; 1036 1037 static SOC_ENUM_SINGLE_DECL(linmod_mux_enum, 1038 M98090_REG_LOUTR_MIXER, 1039 M98090_LINMOD_SHIFT, 1040 linmod_mux_text); 1041 1042 static const struct snd_kcontrol_new max98090_linmod_mux = 1043 SOC_DAPM_ENUM("LINMOD Mux", linmod_mux_enum); 1044 1045 static const char *mixhpsel_mux_text[] = { "DAC Only", "HP Mixer" }; 1046 1047 /* 1048 * This is a mux as it selects the HP output, but to DAPM it is a Mixer enable 1049 */ 1050 static SOC_ENUM_SINGLE_DECL(mixhplsel_mux_enum, 1051 M98090_REG_HP_CONTROL, 1052 M98090_MIXHPLSEL_SHIFT, 1053 mixhpsel_mux_text); 1054 1055 static const struct snd_kcontrol_new max98090_mixhplsel_mux = 1056 SOC_DAPM_ENUM("MIXHPLSEL Mux", mixhplsel_mux_enum); 1057 1058 static SOC_ENUM_SINGLE_DECL(mixhprsel_mux_enum, 1059 M98090_REG_HP_CONTROL, 1060 M98090_MIXHPRSEL_SHIFT, 1061 mixhpsel_mux_text); 1062 1063 static const struct snd_kcontrol_new max98090_mixhprsel_mux = 1064 SOC_DAPM_ENUM("MIXHPRSEL Mux", mixhprsel_mux_enum); 1065 1066 static const struct snd_soc_dapm_widget max98090_dapm_widgets[] = { 1067 SND_SOC_DAPM_INPUT("MIC1"), 1068 SND_SOC_DAPM_INPUT("MIC2"), 1069 SND_SOC_DAPM_INPUT("DMICL"), 1070 SND_SOC_DAPM_INPUT("DMICR"), 1071 SND_SOC_DAPM_INPUT("IN1"), 1072 SND_SOC_DAPM_INPUT("IN2"), 1073 SND_SOC_DAPM_INPUT("IN3"), 1074 SND_SOC_DAPM_INPUT("IN4"), 1075 SND_SOC_DAPM_INPUT("IN5"), 1076 SND_SOC_DAPM_INPUT("IN6"), 1077 SND_SOC_DAPM_INPUT("IN12"), 1078 SND_SOC_DAPM_INPUT("IN34"), 1079 SND_SOC_DAPM_INPUT("IN56"), 1080 1081 SND_SOC_DAPM_SUPPLY("MICBIAS", M98090_REG_INPUT_ENABLE, 1082 M98090_MBEN_SHIFT, 0, NULL, 0), 1083 SND_SOC_DAPM_SUPPLY("SHDN", M98090_REG_DEVICE_SHUTDOWN, 1084 M98090_SHDNN_SHIFT, 0, NULL, 0), 1085 SND_SOC_DAPM_SUPPLY("SDIEN", M98090_REG_IO_CONFIGURATION, 1086 M98090_SDIEN_SHIFT, 0, NULL, 0), 1087 SND_SOC_DAPM_SUPPLY("SDOEN", M98090_REG_IO_CONFIGURATION, 1088 M98090_SDOEN_SHIFT, 0, NULL, 0), 1089 SND_SOC_DAPM_SUPPLY("DMICL_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1090 M98090_DIGMICL_SHIFT, 0, max98090_shdn_event, 1091 SND_SOC_DAPM_POST_PMU), 1092 SND_SOC_DAPM_SUPPLY("DMICR_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1093 M98090_DIGMICR_SHIFT, 0, max98090_shdn_event, 1094 SND_SOC_DAPM_POST_PMU), 1095 SND_SOC_DAPM_SUPPLY("AHPF", M98090_REG_FILTER_CONFIG, 1096 M98090_AHPF_SHIFT, 0, NULL, 0), 1097 1098 /* 1099 * Note: Sysclk and misc power supplies are taken care of by SHDN 1100 */ 1101 1102 SND_SOC_DAPM_MUX("MIC1 Mux", SND_SOC_NOPM, 1103 0, 0, &max98090_mic1_mux), 1104 1105 SND_SOC_DAPM_MUX("MIC2 Mux", SND_SOC_NOPM, 1106 0, 0, &max98090_mic2_mux), 1107 1108 SND_SOC_DAPM_MUX("DMIC Mux", SND_SOC_NOPM, 0, 0, &max98090_dmic_mux), 1109 1110 SND_SOC_DAPM_PGA_E("MIC1 Input", M98090_REG_MIC1_INPUT_LEVEL, 1111 M98090_MIC_PA1EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1112 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1113 1114 SND_SOC_DAPM_PGA_E("MIC2 Input", M98090_REG_MIC2_INPUT_LEVEL, 1115 M98090_MIC_PA2EN_SHIFT, 0, NULL, 0, max98090_micinput_event, 1116 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1117 1118 SND_SOC_DAPM_MIXER("LINEA Mixer", SND_SOC_NOPM, 0, 0, 1119 &max98090_linea_mixer_controls[0], 1120 ARRAY_SIZE(max98090_linea_mixer_controls)), 1121 1122 SND_SOC_DAPM_MIXER("LINEB Mixer", SND_SOC_NOPM, 0, 0, 1123 &max98090_lineb_mixer_controls[0], 1124 ARRAY_SIZE(max98090_lineb_mixer_controls)), 1125 1126 SND_SOC_DAPM_PGA("LINEA Input", M98090_REG_INPUT_ENABLE, 1127 M98090_LINEAEN_SHIFT, 0, NULL, 0), 1128 SND_SOC_DAPM_PGA("LINEB Input", M98090_REG_INPUT_ENABLE, 1129 M98090_LINEBEN_SHIFT, 0, NULL, 0), 1130 1131 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1132 &max98090_left_adc_mixer_controls[0], 1133 ARRAY_SIZE(max98090_left_adc_mixer_controls)), 1134 1135 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1136 &max98090_right_adc_mixer_controls[0], 1137 ARRAY_SIZE(max98090_right_adc_mixer_controls)), 1138 1139 SND_SOC_DAPM_ADC_E("ADCL", NULL, M98090_REG_INPUT_ENABLE, 1140 M98090_ADLEN_SHIFT, 0, max98090_shdn_event, 1141 SND_SOC_DAPM_POST_PMU), 1142 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE, 1143 M98090_ADREN_SHIFT, 0, max98090_shdn_event, 1144 SND_SOC_DAPM_POST_PMU), 1145 1146 SND_SOC_DAPM_AIF_OUT("AIFOUTL", "HiFi Capture", 0, 1147 SND_SOC_NOPM, 0, 0), 1148 SND_SOC_DAPM_AIF_OUT("AIFOUTR", "HiFi Capture", 1, 1149 SND_SOC_NOPM, 0, 0), 1150 1151 SND_SOC_DAPM_MUX("LBENL Mux", SND_SOC_NOPM, 1152 0, 0, &max98090_lbenl_mux), 1153 1154 SND_SOC_DAPM_MUX("LBENR Mux", SND_SOC_NOPM, 1155 0, 0, &max98090_lbenr_mux), 1156 1157 SND_SOC_DAPM_MUX("LTENL Mux", SND_SOC_NOPM, 1158 0, 0, &max98090_ltenl_mux), 1159 1160 SND_SOC_DAPM_MUX("LTENR Mux", SND_SOC_NOPM, 1161 0, 0, &max98090_ltenr_mux), 1162 1163 SND_SOC_DAPM_MUX("STENL Mux", SND_SOC_NOPM, 1164 0, 0, &max98090_stenl_mux), 1165 1166 SND_SOC_DAPM_MUX("STENR Mux", SND_SOC_NOPM, 1167 0, 0, &max98090_stenr_mux), 1168 1169 SND_SOC_DAPM_AIF_IN("AIFINL", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0), 1170 SND_SOC_DAPM_AIF_IN("AIFINR", "HiFi Playback", 1, SND_SOC_NOPM, 0, 0), 1171 1172 SND_SOC_DAPM_DAC("DACL", NULL, M98090_REG_OUTPUT_ENABLE, 1173 M98090_DALEN_SHIFT, 0), 1174 SND_SOC_DAPM_DAC("DACR", NULL, M98090_REG_OUTPUT_ENABLE, 1175 M98090_DAREN_SHIFT, 0), 1176 1177 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 1178 &max98090_left_hp_mixer_controls[0], 1179 ARRAY_SIZE(max98090_left_hp_mixer_controls)), 1180 1181 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 1182 &max98090_right_hp_mixer_controls[0], 1183 ARRAY_SIZE(max98090_right_hp_mixer_controls)), 1184 1185 SND_SOC_DAPM_MIXER("Left Speaker Mixer", SND_SOC_NOPM, 0, 0, 1186 &max98090_left_speaker_mixer_controls[0], 1187 ARRAY_SIZE(max98090_left_speaker_mixer_controls)), 1188 1189 SND_SOC_DAPM_MIXER("Right Speaker Mixer", SND_SOC_NOPM, 0, 0, 1190 &max98090_right_speaker_mixer_controls[0], 1191 ARRAY_SIZE(max98090_right_speaker_mixer_controls)), 1192 1193 SND_SOC_DAPM_MIXER("Left Receiver Mixer", SND_SOC_NOPM, 0, 0, 1194 &max98090_left_rcv_mixer_controls[0], 1195 ARRAY_SIZE(max98090_left_rcv_mixer_controls)), 1196 1197 SND_SOC_DAPM_MIXER("Right Receiver Mixer", SND_SOC_NOPM, 0, 0, 1198 &max98090_right_rcv_mixer_controls[0], 1199 ARRAY_SIZE(max98090_right_rcv_mixer_controls)), 1200 1201 SND_SOC_DAPM_MUX("LINMOD Mux", SND_SOC_NOPM, 0, 0, 1202 &max98090_linmod_mux), 1203 1204 SND_SOC_DAPM_MUX("MIXHPLSEL Mux", SND_SOC_NOPM, 0, 0, 1205 &max98090_mixhplsel_mux), 1206 1207 SND_SOC_DAPM_MUX("MIXHPRSEL Mux", SND_SOC_NOPM, 0, 0, 1208 &max98090_mixhprsel_mux), 1209 1210 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE, 1211 M98090_HPLEN_SHIFT, 0, NULL, 0), 1212 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE, 1213 M98090_HPREN_SHIFT, 0, NULL, 0), 1214 1215 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE, 1216 M98090_SPLEN_SHIFT, 0, NULL, 0), 1217 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE, 1218 M98090_SPREN_SHIFT, 0, NULL, 0), 1219 1220 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE, 1221 M98090_RCVLEN_SHIFT, 0, NULL, 0), 1222 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE, 1223 M98090_RCVREN_SHIFT, 0, NULL, 0), 1224 1225 SND_SOC_DAPM_OUTPUT("HPL"), 1226 SND_SOC_DAPM_OUTPUT("HPR"), 1227 SND_SOC_DAPM_OUTPUT("SPKL"), 1228 SND_SOC_DAPM_OUTPUT("SPKR"), 1229 SND_SOC_DAPM_OUTPUT("RCVL"), 1230 SND_SOC_DAPM_OUTPUT("RCVR"), 1231 }; 1232 1233 static const struct snd_soc_dapm_widget max98091_dapm_widgets[] = { 1234 SND_SOC_DAPM_INPUT("DMIC3"), 1235 SND_SOC_DAPM_INPUT("DMIC4"), 1236 1237 SND_SOC_DAPM_SUPPLY("DMIC3_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1238 M98090_DIGMIC3_SHIFT, 0, NULL, 0), 1239 SND_SOC_DAPM_SUPPLY("DMIC4_ENA", M98090_REG_DIGITAL_MIC_ENABLE, 1240 M98090_DIGMIC4_SHIFT, 0, NULL, 0), 1241 }; 1242 1243 static const struct snd_soc_dapm_route max98090_dapm_routes[] = { 1244 {"MIC1 Input", NULL, "MIC1"}, 1245 {"MIC2 Input", NULL, "MIC2"}, 1246 1247 {"DMICL", NULL, "DMICL_ENA"}, 1248 {"DMICL", NULL, "DMICR_ENA"}, 1249 {"DMICR", NULL, "DMICL_ENA"}, 1250 {"DMICR", NULL, "DMICR_ENA"}, 1251 {"DMICL", NULL, "AHPF"}, 1252 {"DMICR", NULL, "AHPF"}, 1253 1254 /* MIC1 input mux */ 1255 {"MIC1 Mux", "IN12", "IN12"}, 1256 {"MIC1 Mux", "IN56", "IN56"}, 1257 1258 /* MIC2 input mux */ 1259 {"MIC2 Mux", "IN34", "IN34"}, 1260 {"MIC2 Mux", "IN56", "IN56"}, 1261 1262 {"MIC1 Input", NULL, "MIC1 Mux"}, 1263 {"MIC2 Input", NULL, "MIC2 Mux"}, 1264 1265 /* Left ADC input mixer */ 1266 {"Left ADC Mixer", "IN12 Switch", "IN12"}, 1267 {"Left ADC Mixer", "IN34 Switch", "IN34"}, 1268 {"Left ADC Mixer", "IN56 Switch", "IN56"}, 1269 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"}, 1270 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"}, 1271 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1272 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1273 1274 /* Right ADC input mixer */ 1275 {"Right ADC Mixer", "IN12 Switch", "IN12"}, 1276 {"Right ADC Mixer", "IN34 Switch", "IN34"}, 1277 {"Right ADC Mixer", "IN56 Switch", "IN56"}, 1278 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"}, 1279 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"}, 1280 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1281 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1282 1283 /* Line A input mixer */ 1284 {"LINEA Mixer", "IN1 Switch", "IN1"}, 1285 {"LINEA Mixer", "IN3 Switch", "IN3"}, 1286 {"LINEA Mixer", "IN5 Switch", "IN5"}, 1287 {"LINEA Mixer", "IN34 Switch", "IN34"}, 1288 1289 /* Line B input mixer */ 1290 {"LINEB Mixer", "IN2 Switch", "IN2"}, 1291 {"LINEB Mixer", "IN4 Switch", "IN4"}, 1292 {"LINEB Mixer", "IN6 Switch", "IN6"}, 1293 {"LINEB Mixer", "IN56 Switch", "IN56"}, 1294 1295 {"LINEA Input", NULL, "LINEA Mixer"}, 1296 {"LINEB Input", NULL, "LINEB Mixer"}, 1297 1298 /* Inputs */ 1299 {"ADCL", NULL, "Left ADC Mixer"}, 1300 {"ADCR", NULL, "Right ADC Mixer"}, 1301 {"ADCL", NULL, "SHDN"}, 1302 {"ADCR", NULL, "SHDN"}, 1303 1304 {"DMIC Mux", "ADC", "ADCL"}, 1305 {"DMIC Mux", "ADC", "ADCR"}, 1306 {"DMIC Mux", "DMIC", "DMICL"}, 1307 {"DMIC Mux", "DMIC", "DMICR"}, 1308 1309 {"LBENL Mux", "Normal", "DMIC Mux"}, 1310 {"LBENL Mux", "Loopback", "LTENL Mux"}, 1311 {"LBENR Mux", "Normal", "DMIC Mux"}, 1312 {"LBENR Mux", "Loopback", "LTENR Mux"}, 1313 1314 {"AIFOUTL", NULL, "LBENL Mux"}, 1315 {"AIFOUTR", NULL, "LBENR Mux"}, 1316 {"AIFOUTL", NULL, "SHDN"}, 1317 {"AIFOUTR", NULL, "SHDN"}, 1318 {"AIFOUTL", NULL, "SDOEN"}, 1319 {"AIFOUTR", NULL, "SDOEN"}, 1320 1321 {"LTENL Mux", "Normal", "AIFINL"}, 1322 {"LTENL Mux", "Loopthrough", "LBENL Mux"}, 1323 {"LTENR Mux", "Normal", "AIFINR"}, 1324 {"LTENR Mux", "Loopthrough", "LBENR Mux"}, 1325 1326 {"DACL", NULL, "LTENL Mux"}, 1327 {"DACR", NULL, "LTENR Mux"}, 1328 1329 {"STENL Mux", "Sidetone Left", "ADCL"}, 1330 {"STENL Mux", "Sidetone Left", "DMICL"}, 1331 {"STENR Mux", "Sidetone Right", "ADCR"}, 1332 {"STENR Mux", "Sidetone Right", "DMICR"}, 1333 {"DACL", NULL, "STENL Mux"}, 1334 {"DACR", NULL, "STENR Mux"}, 1335 1336 {"AIFINL", NULL, "SHDN"}, 1337 {"AIFINR", NULL, "SHDN"}, 1338 {"AIFINL", NULL, "SDIEN"}, 1339 {"AIFINR", NULL, "SDIEN"}, 1340 {"DACL", NULL, "SHDN"}, 1341 {"DACR", NULL, "SHDN"}, 1342 1343 /* Left headphone output mixer */ 1344 {"Left Headphone Mixer", "Left DAC Switch", "DACL"}, 1345 {"Left Headphone Mixer", "Right DAC Switch", "DACR"}, 1346 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1347 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1348 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1349 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1350 1351 /* Right headphone output mixer */ 1352 {"Right Headphone Mixer", "Left DAC Switch", "DACL"}, 1353 {"Right Headphone Mixer", "Right DAC Switch", "DACR"}, 1354 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"}, 1355 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"}, 1356 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"}, 1357 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"}, 1358 1359 /* Left speaker output mixer */ 1360 {"Left Speaker Mixer", "Left DAC Switch", "DACL"}, 1361 {"Left Speaker Mixer", "Right DAC Switch", "DACR"}, 1362 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1363 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1364 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1365 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1366 1367 /* Right speaker output mixer */ 1368 {"Right Speaker Mixer", "Left DAC Switch", "DACL"}, 1369 {"Right Speaker Mixer", "Right DAC Switch", "DACR"}, 1370 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"}, 1371 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"}, 1372 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"}, 1373 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"}, 1374 1375 /* Left Receiver output mixer */ 1376 {"Left Receiver Mixer", "Left DAC Switch", "DACL"}, 1377 {"Left Receiver Mixer", "Right DAC Switch", "DACR"}, 1378 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1379 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1380 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1381 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1382 1383 /* Right Receiver output mixer */ 1384 {"Right Receiver Mixer", "Left DAC Switch", "DACL"}, 1385 {"Right Receiver Mixer", "Right DAC Switch", "DACR"}, 1386 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"}, 1387 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"}, 1388 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"}, 1389 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"}, 1390 1391 {"MIXHPLSEL Mux", "HP Mixer", "Left Headphone Mixer"}, 1392 1393 /* 1394 * Disable this for lowest power if bypassing 1395 * the DAC with an analog signal 1396 */ 1397 {"HP Left Out", NULL, "DACL"}, 1398 {"HP Left Out", NULL, "MIXHPLSEL Mux"}, 1399 1400 {"MIXHPRSEL Mux", "HP Mixer", "Right Headphone Mixer"}, 1401 1402 /* 1403 * Disable this for lowest power if bypassing 1404 * the DAC with an analog signal 1405 */ 1406 {"HP Right Out", NULL, "DACR"}, 1407 {"HP Right Out", NULL, "MIXHPRSEL Mux"}, 1408 1409 {"SPK Left Out", NULL, "Left Speaker Mixer"}, 1410 {"SPK Right Out", NULL, "Right Speaker Mixer"}, 1411 {"RCV Left Out", NULL, "Left Receiver Mixer"}, 1412 1413 {"LINMOD Mux", "Left and Right", "Right Receiver Mixer"}, 1414 {"LINMOD Mux", "Left Only", "Left Receiver Mixer"}, 1415 {"RCV Right Out", NULL, "LINMOD Mux"}, 1416 1417 {"HPL", NULL, "HP Left Out"}, 1418 {"HPR", NULL, "HP Right Out"}, 1419 {"SPKL", NULL, "SPK Left Out"}, 1420 {"SPKR", NULL, "SPK Right Out"}, 1421 {"RCVL", NULL, "RCV Left Out"}, 1422 {"RCVR", NULL, "RCV Right Out"}, 1423 }; 1424 1425 static const struct snd_soc_dapm_route max98091_dapm_routes[] = { 1426 /* DMIC inputs */ 1427 {"DMIC3", NULL, "DMIC3_ENA"}, 1428 {"DMIC4", NULL, "DMIC4_ENA"}, 1429 {"DMIC3", NULL, "AHPF"}, 1430 {"DMIC4", NULL, "AHPF"}, 1431 }; 1432 1433 static int max98090_add_widgets(struct snd_soc_component *component) 1434 { 1435 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1436 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component); 1437 1438 snd_soc_add_component_controls(component, max98090_snd_controls, 1439 ARRAY_SIZE(max98090_snd_controls)); 1440 1441 if (max98090->devtype == MAX98091) { 1442 snd_soc_add_component_controls(component, max98091_snd_controls, 1443 ARRAY_SIZE(max98091_snd_controls)); 1444 } 1445 1446 snd_soc_dapm_new_controls(dapm, max98090_dapm_widgets, 1447 ARRAY_SIZE(max98090_dapm_widgets)); 1448 1449 snd_soc_dapm_add_routes(dapm, max98090_dapm_routes, 1450 ARRAY_SIZE(max98090_dapm_routes)); 1451 1452 if (max98090->devtype == MAX98091) { 1453 snd_soc_dapm_new_controls(dapm, max98091_dapm_widgets, 1454 ARRAY_SIZE(max98091_dapm_widgets)); 1455 1456 snd_soc_dapm_add_routes(dapm, max98091_dapm_routes, 1457 ARRAY_SIZE(max98091_dapm_routes)); 1458 } 1459 1460 return 0; 1461 } 1462 1463 static const int pclk_rates[] = { 1464 12000000, 12000000, 13000000, 13000000, 1465 16000000, 16000000, 19200000, 19200000 1466 }; 1467 1468 static const int lrclk_rates[] = { 1469 8000, 16000, 8000, 16000, 1470 8000, 16000, 8000, 16000 1471 }; 1472 1473 static const int user_pclk_rates[] = { 1474 13000000, 13000000, 19200000, 19200000, 1475 }; 1476 1477 static const int user_lrclk_rates[] = { 1478 44100, 48000, 44100, 48000, 1479 }; 1480 1481 static const unsigned long long ni_value[] = { 1482 3528, 768, 441, 8 1483 }; 1484 1485 static const unsigned long long mi_value[] = { 1486 8125, 1625, 1500, 25 1487 }; 1488 1489 static void max98090_configure_bclk(struct snd_soc_component *component) 1490 { 1491 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1492 unsigned long long ni; 1493 int i; 1494 1495 if (!max98090->sysclk) { 1496 dev_err(component->dev, "No SYSCLK configured\n"); 1497 return; 1498 } 1499 1500 if (!max98090->bclk || !max98090->lrclk) { 1501 dev_err(component->dev, "No audio clocks configured\n"); 1502 return; 1503 } 1504 1505 /* Skip configuration when operating as slave */ 1506 if (!(snd_soc_component_read(component, M98090_REG_MASTER_MODE) & 1507 M98090_MAS_MASK)) { 1508 return; 1509 } 1510 1511 /* Check for supported PCLK to LRCLK ratios */ 1512 for (i = 0; i < ARRAY_SIZE(pclk_rates); i++) { 1513 if ((pclk_rates[i] == max98090->sysclk) && 1514 (lrclk_rates[i] == max98090->lrclk)) { 1515 dev_dbg(component->dev, 1516 "Found supported PCLK to LRCLK rates 0x%x\n", 1517 i + 0x8); 1518 1519 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1520 M98090_FREQ_MASK, 1521 (i + 0x8) << M98090_FREQ_SHIFT); 1522 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1523 M98090_USE_M1_MASK, 0); 1524 return; 1525 } 1526 } 1527 1528 /* Check for user calculated MI and NI ratios */ 1529 for (i = 0; i < ARRAY_SIZE(user_pclk_rates); i++) { 1530 if ((user_pclk_rates[i] == max98090->sysclk) && 1531 (user_lrclk_rates[i] == max98090->lrclk)) { 1532 dev_dbg(component->dev, 1533 "Found user supported PCLK to LRCLK rates\n"); 1534 dev_dbg(component->dev, "i %d ni %lld mi %lld\n", 1535 i, ni_value[i], mi_value[i]); 1536 1537 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1538 M98090_FREQ_MASK, 0); 1539 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1540 M98090_USE_M1_MASK, 1541 1 << M98090_USE_M1_SHIFT); 1542 1543 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB, 1544 (ni_value[i] >> 8) & 0x7F); 1545 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, 1546 ni_value[i] & 0xFF); 1547 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_MSB, 1548 (mi_value[i] >> 8) & 0x7F); 1549 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_MI_LSB, 1550 mi_value[i] & 0xFF); 1551 1552 return; 1553 } 1554 } 1555 1556 /* 1557 * Calculate based on MI = 65536 (not as good as either method above) 1558 */ 1559 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1560 M98090_FREQ_MASK, 0); 1561 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1562 M98090_USE_M1_MASK, 0); 1563 1564 /* 1565 * Configure NI when operating as master 1566 * Note: There is a small, but significant audio quality improvement 1567 * by calculating ni and mi. 1568 */ 1569 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) 1570 * (unsigned long long int)max98090->lrclk; 1571 do_div(ni, (unsigned long long int)max98090->sysclk); 1572 dev_info(component->dev, "No better method found\n"); 1573 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni); 1574 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_MSB, 1575 (ni >> 8) & 0x7F); 1576 snd_soc_component_write(component, M98090_REG_CLOCK_RATIO_NI_LSB, ni & 0xFF); 1577 } 1578 1579 static int max98090_dai_set_fmt(struct snd_soc_dai *codec_dai, 1580 unsigned int fmt) 1581 { 1582 struct snd_soc_component *component = codec_dai->component; 1583 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1584 struct max98090_cdata *cdata; 1585 u8 regval; 1586 1587 max98090->dai_fmt = fmt; 1588 cdata = &max98090->dai[0]; 1589 1590 if (fmt != cdata->fmt) { 1591 cdata->fmt = fmt; 1592 1593 regval = 0; 1594 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1595 case SND_SOC_DAIFMT_CBS_CFS: 1596 /* Set to slave mode PLL - MAS mode off */ 1597 snd_soc_component_write(component, 1598 M98090_REG_CLOCK_RATIO_NI_MSB, 0x00); 1599 snd_soc_component_write(component, 1600 M98090_REG_CLOCK_RATIO_NI_LSB, 0x00); 1601 snd_soc_component_update_bits(component, M98090_REG_CLOCK_MODE, 1602 M98090_USE_M1_MASK, 0); 1603 max98090->master = false; 1604 break; 1605 case SND_SOC_DAIFMT_CBM_CFM: 1606 /* Set to master mode */ 1607 if (max98090->tdm_slots == 4) { 1608 /* TDM */ 1609 regval |= M98090_MAS_MASK | 1610 M98090_BSEL_64; 1611 } else if (max98090->tdm_slots == 3) { 1612 /* TDM */ 1613 regval |= M98090_MAS_MASK | 1614 M98090_BSEL_48; 1615 } else { 1616 /* Few TDM slots, or No TDM */ 1617 regval |= M98090_MAS_MASK | 1618 M98090_BSEL_32; 1619 } 1620 max98090->master = true; 1621 break; 1622 case SND_SOC_DAIFMT_CBS_CFM: 1623 case SND_SOC_DAIFMT_CBM_CFS: 1624 default: 1625 dev_err(component->dev, "DAI clock mode unsupported"); 1626 return -EINVAL; 1627 } 1628 snd_soc_component_write(component, M98090_REG_MASTER_MODE, regval); 1629 1630 regval = 0; 1631 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1632 case SND_SOC_DAIFMT_I2S: 1633 regval |= M98090_DLY_MASK; 1634 break; 1635 case SND_SOC_DAIFMT_LEFT_J: 1636 break; 1637 case SND_SOC_DAIFMT_RIGHT_J: 1638 regval |= M98090_RJ_MASK; 1639 break; 1640 case SND_SOC_DAIFMT_DSP_A: 1641 /* Not supported mode */ 1642 default: 1643 dev_err(component->dev, "DAI format unsupported"); 1644 return -EINVAL; 1645 } 1646 1647 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1648 case SND_SOC_DAIFMT_NB_NF: 1649 break; 1650 case SND_SOC_DAIFMT_NB_IF: 1651 regval |= M98090_WCI_MASK; 1652 break; 1653 case SND_SOC_DAIFMT_IB_NF: 1654 regval |= M98090_BCI_MASK; 1655 break; 1656 case SND_SOC_DAIFMT_IB_IF: 1657 regval |= M98090_BCI_MASK|M98090_WCI_MASK; 1658 break; 1659 default: 1660 dev_err(component->dev, "DAI invert mode unsupported"); 1661 return -EINVAL; 1662 } 1663 1664 /* 1665 * This accommodates an inverted logic in the MAX98090 chip 1666 * for Bit Clock Invert (BCI). The inverted logic is only 1667 * seen for the case of TDM mode. The remaining cases have 1668 * normal logic. 1669 */ 1670 if (max98090->tdm_slots > 1) 1671 regval ^= M98090_BCI_MASK; 1672 1673 snd_soc_component_write(component, 1674 M98090_REG_INTERFACE_FORMAT, regval); 1675 } 1676 1677 return 0; 1678 } 1679 1680 static int max98090_set_tdm_slot(struct snd_soc_dai *codec_dai, 1681 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 1682 { 1683 struct snd_soc_component *component = codec_dai->component; 1684 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1685 struct max98090_cdata *cdata; 1686 cdata = &max98090->dai[0]; 1687 1688 if (slots < 0 || slots > 4) 1689 return -EINVAL; 1690 1691 max98090->tdm_slots = slots; 1692 max98090->tdm_width = slot_width; 1693 1694 if (max98090->tdm_slots > 1) { 1695 /* SLOTL SLOTR SLOTDLY */ 1696 snd_soc_component_write(component, M98090_REG_TDM_FORMAT, 1697 0 << M98090_TDM_SLOTL_SHIFT | 1698 1 << M98090_TDM_SLOTR_SHIFT | 1699 0 << M98090_TDM_SLOTDLY_SHIFT); 1700 1701 /* FSW TDM */ 1702 snd_soc_component_update_bits(component, M98090_REG_TDM_CONTROL, 1703 M98090_TDM_MASK, 1704 M98090_TDM_MASK); 1705 } 1706 1707 /* 1708 * Normally advisable to set TDM first, but this permits either order 1709 */ 1710 cdata->fmt = 0; 1711 max98090_dai_set_fmt(codec_dai, max98090->dai_fmt); 1712 1713 return 0; 1714 } 1715 1716 static int max98090_set_bias_level(struct snd_soc_component *component, 1717 enum snd_soc_bias_level level) 1718 { 1719 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1720 int ret; 1721 1722 switch (level) { 1723 case SND_SOC_BIAS_ON: 1724 break; 1725 1726 case SND_SOC_BIAS_PREPARE: 1727 /* 1728 * SND_SOC_BIAS_PREPARE is called while preparing for a 1729 * transition to ON or away from ON. If current bias_level 1730 * is SND_SOC_BIAS_ON, then it is preparing for a transition 1731 * away from ON. Disable the clock in that case, otherwise 1732 * enable it. 1733 */ 1734 if (IS_ERR(max98090->mclk)) 1735 break; 1736 1737 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) { 1738 clk_disable_unprepare(max98090->mclk); 1739 } else { 1740 ret = clk_prepare_enable(max98090->mclk); 1741 if (ret) 1742 return ret; 1743 } 1744 break; 1745 1746 case SND_SOC_BIAS_STANDBY: 1747 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) { 1748 ret = regcache_sync(max98090->regmap); 1749 if (ret != 0) { 1750 dev_err(component->dev, 1751 "Failed to sync cache: %d\n", ret); 1752 return ret; 1753 } 1754 } 1755 break; 1756 1757 case SND_SOC_BIAS_OFF: 1758 /* Set internal pull-up to lowest power mode */ 1759 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, 1760 M98090_JDWK_MASK, M98090_JDWK_MASK); 1761 regcache_mark_dirty(max98090->regmap); 1762 break; 1763 } 1764 return 0; 1765 } 1766 1767 static const int dmic_divisors[] = { 2, 3, 4, 5, 6, 8 }; 1768 1769 static const int comp_lrclk_rates[] = { 1770 8000, 16000, 32000, 44100, 48000, 96000 1771 }; 1772 1773 struct dmic_table { 1774 int pclk; 1775 struct { 1776 int freq; 1777 int comp[6]; /* One each for 8, 16, 32, 44.1, 48, and 96 kHz */ 1778 } settings[6]; /* One for each dmic divisor. */ 1779 }; 1780 1781 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */ 1782 { 1783 .pclk = 11289600, 1784 .settings = { 1785 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, 1786 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, 1787 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1788 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } }, 1789 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1790 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1791 }, 1792 }, 1793 { 1794 .pclk = 12000000, 1795 .settings = { 1796 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, 1797 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, 1798 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1799 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, 1800 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1801 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1802 } 1803 }, 1804 { 1805 .pclk = 12288000, 1806 .settings = { 1807 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } }, 1808 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } }, 1809 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1810 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } }, 1811 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1812 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } }, 1813 } 1814 }, 1815 { 1816 .pclk = 13000000, 1817 .settings = { 1818 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } }, 1819 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } }, 1820 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, 1821 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } }, 1822 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, 1823 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } }, 1824 } 1825 }, 1826 { 1827 .pclk = 19200000, 1828 .settings = { 1829 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } }, 1830 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } }, 1831 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, 1832 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } }, 1833 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } }, 1834 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } }, 1835 } 1836 }, 1837 }; 1838 1839 static int max98090_find_divisor(int target_freq, int pclk) 1840 { 1841 int current_diff = INT_MAX; 1842 int test_diff; 1843 int divisor_index = 0; 1844 int i; 1845 1846 for (i = 0; i < ARRAY_SIZE(dmic_divisors); i++) { 1847 test_diff = abs(target_freq - (pclk / dmic_divisors[i])); 1848 if (test_diff < current_diff) { 1849 current_diff = test_diff; 1850 divisor_index = i; 1851 } 1852 } 1853 1854 return divisor_index; 1855 } 1856 1857 static int max98090_find_closest_pclk(int pclk) 1858 { 1859 int m1; 1860 int m2; 1861 int i; 1862 1863 for (i = 0; i < ARRAY_SIZE(dmic_table); i++) { 1864 if (pclk == dmic_table[i].pclk) 1865 return i; 1866 if (pclk < dmic_table[i].pclk) { 1867 if (i == 0) 1868 return i; 1869 m1 = pclk - dmic_table[i-1].pclk; 1870 m2 = dmic_table[i].pclk - pclk; 1871 if (m1 < m2) 1872 return i - 1; 1873 else 1874 return i; 1875 } 1876 } 1877 1878 return -EINVAL; 1879 } 1880 1881 static int max98090_configure_dmic(struct max98090_priv *max98090, 1882 int target_dmic_clk, int pclk, int fs) 1883 { 1884 int micclk_index; 1885 int pclk_index; 1886 int dmic_freq; 1887 int dmic_comp; 1888 int i; 1889 1890 pclk_index = max98090_find_closest_pclk(pclk); 1891 if (pclk_index < 0) 1892 return pclk_index; 1893 1894 micclk_index = max98090_find_divisor(target_dmic_clk, pclk); 1895 1896 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { 1897 if (fs <= (comp_lrclk_rates[i] + comp_lrclk_rates[i+1]) / 2) 1898 break; 1899 } 1900 1901 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq; 1902 dmic_comp = dmic_table[pclk_index].settings[micclk_index].comp[i]; 1903 1904 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE, 1905 M98090_MICCLK_MASK, 1906 micclk_index << M98090_MICCLK_SHIFT); 1907 1908 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG, 1909 M98090_DMIC_COMP_MASK | M98090_DMIC_FREQ_MASK, 1910 dmic_comp << M98090_DMIC_COMP_SHIFT | 1911 dmic_freq << M98090_DMIC_FREQ_SHIFT); 1912 1913 return 0; 1914 } 1915 1916 static int max98090_dai_startup(struct snd_pcm_substream *substream, 1917 struct snd_soc_dai *dai) 1918 { 1919 struct snd_soc_component *component = dai->component; 1920 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1921 unsigned int fmt = max98090->dai_fmt; 1922 1923 /* Remove 24-bit format support if it is not in right justified mode. */ 1924 if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_RIGHT_J) { 1925 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; 1926 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16); 1927 } 1928 return 0; 1929 } 1930 1931 static int max98090_dai_hw_params(struct snd_pcm_substream *substream, 1932 struct snd_pcm_hw_params *params, 1933 struct snd_soc_dai *dai) 1934 { 1935 struct snd_soc_component *component = dai->component; 1936 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1937 struct max98090_cdata *cdata; 1938 1939 cdata = &max98090->dai[0]; 1940 max98090->bclk = snd_soc_params_to_bclk(params); 1941 if (params_channels(params) == 1) 1942 max98090->bclk *= 2; 1943 1944 max98090->lrclk = params_rate(params); 1945 1946 switch (params_width(params)) { 1947 case 16: 1948 snd_soc_component_update_bits(component, M98090_REG_INTERFACE_FORMAT, 1949 M98090_WS_MASK, 0); 1950 break; 1951 default: 1952 return -EINVAL; 1953 } 1954 1955 if (max98090->master) 1956 max98090_configure_bclk(component); 1957 1958 cdata->rate = max98090->lrclk; 1959 1960 /* Update filter mode */ 1961 if (max98090->lrclk < 24000) 1962 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 1963 M98090_MODE_MASK, 0); 1964 else 1965 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 1966 M98090_MODE_MASK, M98090_MODE_MASK); 1967 1968 /* Update sample rate mode */ 1969 if (max98090->lrclk < 50000) 1970 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 1971 M98090_DHF_MASK, 0); 1972 else 1973 snd_soc_component_update_bits(component, M98090_REG_FILTER_CONFIG, 1974 M98090_DHF_MASK, M98090_DHF_MASK); 1975 1976 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk, 1977 max98090->lrclk); 1978 1979 return 0; 1980 } 1981 1982 /* 1983 * PLL / Sysclk 1984 */ 1985 static int max98090_dai_set_sysclk(struct snd_soc_dai *dai, 1986 int clk_id, unsigned int freq, int dir) 1987 { 1988 struct snd_soc_component *component = dai->component; 1989 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 1990 1991 /* Requested clock frequency is already setup */ 1992 if (freq == max98090->sysclk) 1993 return 0; 1994 1995 if (!IS_ERR(max98090->mclk)) { 1996 freq = clk_round_rate(max98090->mclk, freq); 1997 clk_set_rate(max98090->mclk, freq); 1998 } 1999 2000 /* Setup clocks for slave mode, and using the PLL 2001 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 2002 * 0x02 (when master clk is 20MHz to 40MHz).. 2003 * 0x03 (when master clk is 40MHz to 60MHz).. 2004 */ 2005 if ((freq >= 10000000) && (freq <= 20000000)) { 2006 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2007 M98090_PSCLK_DIV1); 2008 max98090->pclk = freq; 2009 } else if ((freq > 20000000) && (freq <= 40000000)) { 2010 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2011 M98090_PSCLK_DIV2); 2012 max98090->pclk = freq >> 1; 2013 } else if ((freq > 40000000) && (freq <= 60000000)) { 2014 snd_soc_component_write(component, M98090_REG_SYSTEM_CLOCK, 2015 M98090_PSCLK_DIV4); 2016 max98090->pclk = freq >> 2; 2017 } else { 2018 dev_err(component->dev, "Invalid master clock frequency\n"); 2019 return -EINVAL; 2020 } 2021 2022 max98090->sysclk = freq; 2023 2024 return 0; 2025 } 2026 2027 static int max98090_dai_mute(struct snd_soc_dai *codec_dai, int mute, 2028 int direction) 2029 { 2030 struct snd_soc_component *component = codec_dai->component; 2031 int regval; 2032 2033 regval = mute ? M98090_DVM_MASK : 0; 2034 snd_soc_component_update_bits(component, M98090_REG_DAI_PLAYBACK_LEVEL, 2035 M98090_DVM_MASK, regval); 2036 2037 return 0; 2038 } 2039 2040 static int max98090_dai_trigger(struct snd_pcm_substream *substream, int cmd, 2041 struct snd_soc_dai *dai) 2042 { 2043 struct snd_soc_component *component = dai->component; 2044 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2045 2046 switch (cmd) { 2047 case SNDRV_PCM_TRIGGER_START: 2048 case SNDRV_PCM_TRIGGER_RESUME: 2049 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 2050 if (!max98090->master && snd_soc_dai_active(dai) == 1) 2051 queue_delayed_work(system_power_efficient_wq, 2052 &max98090->pll_det_enable_work, 2053 msecs_to_jiffies(10)); 2054 break; 2055 case SNDRV_PCM_TRIGGER_STOP: 2056 case SNDRV_PCM_TRIGGER_SUSPEND: 2057 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 2058 if (!max98090->master && snd_soc_dai_active(dai) == 1) 2059 schedule_work(&max98090->pll_det_disable_work); 2060 break; 2061 default: 2062 break; 2063 } 2064 2065 return 0; 2066 } 2067 2068 static void max98090_pll_det_enable_work(struct work_struct *work) 2069 { 2070 struct max98090_priv *max98090 = 2071 container_of(work, struct max98090_priv, 2072 pll_det_enable_work.work); 2073 struct snd_soc_component *component = max98090->component; 2074 unsigned int status, mask; 2075 2076 /* 2077 * Clear status register in order to clear possibly already occurred 2078 * PLL unlock. If PLL hasn't still locked, the status will be set 2079 * again and PLL unlock interrupt will occur. 2080 * Note this will clear all status bits 2081 */ 2082 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); 2083 2084 /* 2085 * Queue jack work in case jack state has just changed but handler 2086 * hasn't run yet 2087 */ 2088 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); 2089 status &= mask; 2090 if (status & M98090_JDET_MASK) 2091 queue_delayed_work(system_power_efficient_wq, 2092 &max98090->jack_work, 2093 msecs_to_jiffies(100)); 2094 2095 /* Enable PLL unlock interrupt */ 2096 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2097 M98090_IULK_MASK, 2098 1 << M98090_IULK_SHIFT); 2099 } 2100 2101 static void max98090_pll_det_disable_work(struct work_struct *work) 2102 { 2103 struct max98090_priv *max98090 = 2104 container_of(work, struct max98090_priv, pll_det_disable_work); 2105 struct snd_soc_component *component = max98090->component; 2106 2107 cancel_delayed_work_sync(&max98090->pll_det_enable_work); 2108 2109 /* Disable PLL unlock interrupt */ 2110 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2111 M98090_IULK_MASK, 0); 2112 } 2113 2114 static void max98090_pll_work(struct max98090_priv *max98090) 2115 { 2116 struct snd_soc_component *component = max98090->component; 2117 unsigned int pll; 2118 int i; 2119 2120 if (!snd_soc_component_active(component)) 2121 return; 2122 2123 dev_info_ratelimited(component->dev, "PLL unlocked\n"); 2124 2125 /* 2126 * As the datasheet suggested, the maximum PLL lock time should be 2127 * 7 msec. The workaround resets the codec softly by toggling SHDN 2128 * off and on if PLL failed to lock for 10 msec. Notably, there is 2129 * no suggested hold time for SHDN off. 2130 */ 2131 2132 /* Toggle shutdown OFF then ON */ 2133 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2134 M98090_SHDNN_MASK, 0); 2135 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2136 M98090_SHDNN_MASK, M98090_SHDNN_MASK); 2137 2138 for (i = 0; i < 10; ++i) { 2139 /* Give PLL time to lock */ 2140 usleep_range(1000, 1200); 2141 2142 /* Check lock status */ 2143 pll = snd_soc_component_read( 2144 component, M98090_REG_DEVICE_STATUS); 2145 if (!(pll & M98090_ULK_MASK)) 2146 break; 2147 } 2148 } 2149 2150 static void max98090_jack_work(struct work_struct *work) 2151 { 2152 struct max98090_priv *max98090 = container_of(work, 2153 struct max98090_priv, 2154 jack_work.work); 2155 struct snd_soc_component *component = max98090->component; 2156 int status = 0; 2157 int reg; 2158 2159 /* Read a second time */ 2160 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { 2161 2162 /* Strong pull up allows mic detection */ 2163 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, 2164 M98090_JDWK_MASK, 0); 2165 2166 msleep(50); 2167 2168 snd_soc_component_read(component, M98090_REG_JACK_STATUS); 2169 2170 /* Weak pull up allows only insertion detection */ 2171 snd_soc_component_update_bits(component, M98090_REG_JACK_DETECT, 2172 M98090_JDWK_MASK, M98090_JDWK_MASK); 2173 } 2174 2175 reg = snd_soc_component_read(component, M98090_REG_JACK_STATUS); 2176 2177 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { 2178 case M98090_LSNS_MASK | M98090_JKSNS_MASK: 2179 dev_dbg(component->dev, "No Headset Detected\n"); 2180 2181 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2182 2183 status |= 0; 2184 2185 break; 2186 2187 case 0: 2188 if (max98090->jack_state == 2189 M98090_JACK_STATE_HEADSET) { 2190 2191 dev_dbg(component->dev, 2192 "Headset Button Down Detected\n"); 2193 2194 /* 2195 * max98090_headset_button_event(codec) 2196 * could be defined, then called here. 2197 */ 2198 2199 status |= SND_JACK_HEADSET; 2200 status |= SND_JACK_BTN_0; 2201 2202 break; 2203 } 2204 2205 /* Line is reported as Headphone */ 2206 /* Nokia Headset is reported as Headphone */ 2207 /* Mono Headphone is reported as Headphone */ 2208 dev_dbg(component->dev, "Headphone Detected\n"); 2209 2210 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; 2211 2212 status |= SND_JACK_HEADPHONE; 2213 2214 break; 2215 2216 case M98090_JKSNS_MASK: 2217 dev_dbg(component->dev, "Headset Detected\n"); 2218 2219 max98090->jack_state = M98090_JACK_STATE_HEADSET; 2220 2221 status |= SND_JACK_HEADSET; 2222 2223 break; 2224 2225 default: 2226 dev_dbg(component->dev, "Unrecognized Jack Status\n"); 2227 break; 2228 } 2229 2230 snd_soc_jack_report(max98090->jack, status, 2231 SND_JACK_HEADSET | SND_JACK_BTN_0); 2232 } 2233 2234 static irqreturn_t max98090_interrupt(int irq, void *data) 2235 { 2236 struct max98090_priv *max98090 = data; 2237 struct snd_soc_component *component = max98090->component; 2238 int ret; 2239 unsigned int mask; 2240 unsigned int active; 2241 2242 /* Treat interrupt before codec is initialized as spurious */ 2243 if (component == NULL) 2244 return IRQ_NONE; 2245 2246 dev_dbg(component->dev, "***** max98090_interrupt *****\n"); 2247 2248 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); 2249 2250 if (ret != 0) { 2251 dev_err(component->dev, 2252 "failed to read M98090_REG_INTERRUPT_S: %d\n", 2253 ret); 2254 return IRQ_NONE; 2255 } 2256 2257 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); 2258 2259 if (ret != 0) { 2260 dev_err(component->dev, 2261 "failed to read M98090_REG_DEVICE_STATUS: %d\n", 2262 ret); 2263 return IRQ_NONE; 2264 } 2265 2266 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", 2267 active, mask, active & mask); 2268 2269 active &= mask; 2270 2271 if (!active) 2272 return IRQ_NONE; 2273 2274 if (active & M98090_CLD_MASK) 2275 dev_err(component->dev, "M98090_CLD_MASK\n"); 2276 2277 if (active & M98090_SLD_MASK) 2278 dev_dbg(component->dev, "M98090_SLD_MASK\n"); 2279 2280 if (active & M98090_ULK_MASK) { 2281 dev_dbg(component->dev, "M98090_ULK_MASK\n"); 2282 max98090_pll_work(max98090); 2283 } 2284 2285 if (active & M98090_JDET_MASK) { 2286 dev_dbg(component->dev, "M98090_JDET_MASK\n"); 2287 2288 pm_wakeup_event(component->dev, 100); 2289 2290 queue_delayed_work(system_power_efficient_wq, 2291 &max98090->jack_work, 2292 msecs_to_jiffies(100)); 2293 } 2294 2295 if (active & M98090_DRCACT_MASK) 2296 dev_dbg(component->dev, "M98090_DRCACT_MASK\n"); 2297 2298 if (active & M98090_DRCCLP_MASK) 2299 dev_err(component->dev, "M98090_DRCCLP_MASK\n"); 2300 2301 return IRQ_HANDLED; 2302 } 2303 2304 /** 2305 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ 2306 * 2307 * @component: MAX98090 component 2308 * @jack: jack to report detection events on 2309 * 2310 * Enable microphone detection via IRQ on the MAX98090. If GPIOs are 2311 * being used to bring out signals to the processor then only platform 2312 * data configuration is needed for MAX98090 and processor GPIOs should 2313 * be configured using snd_soc_jack_add_gpios() instead. 2314 * 2315 * If no jack is supplied detection will be disabled. 2316 */ 2317 int max98090_mic_detect(struct snd_soc_component *component, 2318 struct snd_soc_jack *jack) 2319 { 2320 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2321 2322 dev_dbg(component->dev, "max98090_mic_detect\n"); 2323 2324 max98090->jack = jack; 2325 if (jack) { 2326 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2327 M98090_IJDET_MASK, 2328 1 << M98090_IJDET_SHIFT); 2329 } else { 2330 snd_soc_component_update_bits(component, M98090_REG_INTERRUPT_S, 2331 M98090_IJDET_MASK, 2332 0); 2333 } 2334 2335 /* Send an initial empty report */ 2336 snd_soc_jack_report(max98090->jack, 0, 2337 SND_JACK_HEADSET | SND_JACK_BTN_0); 2338 2339 queue_delayed_work(system_power_efficient_wq, 2340 &max98090->jack_work, 2341 msecs_to_jiffies(100)); 2342 2343 return 0; 2344 } 2345 EXPORT_SYMBOL_GPL(max98090_mic_detect); 2346 2347 #define MAX98090_RATES SNDRV_PCM_RATE_8000_96000 2348 #define MAX98090_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 2349 2350 static const struct snd_soc_dai_ops max98090_dai_ops = { 2351 .startup = max98090_dai_startup, 2352 .set_sysclk = max98090_dai_set_sysclk, 2353 .set_fmt = max98090_dai_set_fmt, 2354 .set_tdm_slot = max98090_set_tdm_slot, 2355 .hw_params = max98090_dai_hw_params, 2356 .mute_stream = max98090_dai_mute, 2357 .trigger = max98090_dai_trigger, 2358 .no_capture_mute = 1, 2359 }; 2360 2361 static struct snd_soc_dai_driver max98090_dai[] = { 2362 { 2363 .name = "HiFi", 2364 .playback = { 2365 .stream_name = "HiFi Playback", 2366 .channels_min = 2, 2367 .channels_max = 2, 2368 .rates = MAX98090_RATES, 2369 .formats = MAX98090_FORMATS, 2370 }, 2371 .capture = { 2372 .stream_name = "HiFi Capture", 2373 .channels_min = 1, 2374 .channels_max = 2, 2375 .rates = MAX98090_RATES, 2376 .formats = MAX98090_FORMATS, 2377 }, 2378 .ops = &max98090_dai_ops, 2379 } 2380 }; 2381 2382 static int max98090_probe(struct snd_soc_component *component) 2383 { 2384 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2385 struct max98090_cdata *cdata; 2386 enum max98090_type devtype; 2387 int ret = 0; 2388 int err; 2389 unsigned int micbias; 2390 2391 dev_dbg(component->dev, "max98090_probe\n"); 2392 2393 max98090->mclk = devm_clk_get(component->dev, "mclk"); 2394 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER) 2395 return -EPROBE_DEFER; 2396 2397 max98090->component = component; 2398 2399 /* Reset the codec, the DSP core, and disable all interrupts */ 2400 max98090_reset(max98090); 2401 2402 /* Initialize private data */ 2403 2404 max98090->sysclk = (unsigned)-1; 2405 max98090->pclk = (unsigned)-1; 2406 max98090->master = false; 2407 2408 cdata = &max98090->dai[0]; 2409 cdata->rate = (unsigned)-1; 2410 cdata->fmt = (unsigned)-1; 2411 2412 max98090->lin_state = 0; 2413 max98090->pa1en = 0; 2414 max98090->pa2en = 0; 2415 2416 ret = snd_soc_component_read(component, M98090_REG_REVISION_ID); 2417 if (ret < 0) { 2418 dev_err(component->dev, "Failed to read device revision: %d\n", 2419 ret); 2420 goto err_access; 2421 } 2422 2423 if ((ret >= M98090_REVA) && (ret <= M98090_REVA + 0x0f)) { 2424 devtype = MAX98090; 2425 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret); 2426 } else if ((ret >= M98091_REVA) && (ret <= M98091_REVA + 0x0f)) { 2427 devtype = MAX98091; 2428 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret); 2429 } else { 2430 devtype = MAX98090; 2431 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret); 2432 } 2433 2434 if (max98090->devtype != devtype) { 2435 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n"); 2436 max98090->devtype = devtype; 2437 } 2438 2439 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; 2440 2441 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); 2442 INIT_DELAYED_WORK(&max98090->pll_det_enable_work, 2443 max98090_pll_det_enable_work); 2444 INIT_WORK(&max98090->pll_det_disable_work, 2445 max98090_pll_det_disable_work); 2446 2447 /* Enable jack detection */ 2448 snd_soc_component_write(component, M98090_REG_JACK_DETECT, 2449 M98090_JDETEN_MASK | M98090_JDEB_25MS); 2450 2451 /* 2452 * Clear any old interrupts. 2453 * An old interrupt ocurring prior to installing the ISR 2454 * can keep a new interrupt from generating a trigger. 2455 */ 2456 snd_soc_component_read(component, M98090_REG_DEVICE_STATUS); 2457 2458 /* High Performance is default */ 2459 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL, 2460 M98090_DACHP_MASK, 2461 1 << M98090_DACHP_SHIFT); 2462 snd_soc_component_update_bits(component, M98090_REG_DAC_CONTROL, 2463 M98090_PERFMODE_MASK, 2464 0 << M98090_PERFMODE_SHIFT); 2465 snd_soc_component_update_bits(component, M98090_REG_ADC_CONTROL, 2466 M98090_ADCHP_MASK, 2467 1 << M98090_ADCHP_SHIFT); 2468 2469 /* Turn on VCM bandgap reference */ 2470 snd_soc_component_write(component, M98090_REG_BIAS_CONTROL, 2471 M98090_VCM_MODE_MASK); 2472 2473 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias); 2474 if (err) { 2475 micbias = M98090_MBVSEL_2V8; 2476 dev_info(component->dev, "use default 2.8v micbias\n"); 2477 } else if (micbias > M98090_MBVSEL_2V8) { 2478 dev_err(component->dev, "micbias out of range 0x%x\n", micbias); 2479 micbias = M98090_MBVSEL_2V8; 2480 } 2481 2482 snd_soc_component_update_bits(component, M98090_REG_MIC_BIAS_VOLTAGE, 2483 M98090_MBVSEL_MASK, micbias); 2484 2485 max98090_add_widgets(component); 2486 2487 err_access: 2488 return ret; 2489 } 2490 2491 static void max98090_remove(struct snd_soc_component *component) 2492 { 2493 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2494 2495 cancel_delayed_work_sync(&max98090->jack_work); 2496 cancel_delayed_work_sync(&max98090->pll_det_enable_work); 2497 cancel_work_sync(&max98090->pll_det_disable_work); 2498 max98090->component = NULL; 2499 } 2500 2501 static void max98090_seq_notifier(struct snd_soc_component *component, 2502 enum snd_soc_dapm_type event, int subseq) 2503 { 2504 struct max98090_priv *max98090 = snd_soc_component_get_drvdata(component); 2505 2506 if (max98090->shdn_pending) { 2507 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2508 M98090_SHDNN_MASK, 0); 2509 msleep(40); 2510 snd_soc_component_update_bits(component, M98090_REG_DEVICE_SHUTDOWN, 2511 M98090_SHDNN_MASK, M98090_SHDNN_MASK); 2512 max98090->shdn_pending = false; 2513 } 2514 } 2515 2516 static const struct snd_soc_component_driver soc_component_dev_max98090 = { 2517 .probe = max98090_probe, 2518 .remove = max98090_remove, 2519 .seq_notifier = max98090_seq_notifier, 2520 .set_bias_level = max98090_set_bias_level, 2521 .idle_bias_on = 1, 2522 .use_pmdown_time = 1, 2523 .endianness = 1, 2524 .non_legacy_dai_naming = 1, 2525 }; 2526 2527 static const struct regmap_config max98090_regmap = { 2528 .reg_bits = 8, 2529 .val_bits = 8, 2530 2531 .max_register = MAX98090_MAX_REGISTER, 2532 .reg_defaults = max98090_reg, 2533 .num_reg_defaults = ARRAY_SIZE(max98090_reg), 2534 .volatile_reg = max98090_volatile_register, 2535 .readable_reg = max98090_readable_register, 2536 .cache_type = REGCACHE_RBTREE, 2537 }; 2538 2539 static const struct i2c_device_id max98090_i2c_id[] = { 2540 { "max98090", MAX98090 }, 2541 { "max98091", MAX98091 }, 2542 { } 2543 }; 2544 MODULE_DEVICE_TABLE(i2c, max98090_i2c_id); 2545 2546 static int max98090_i2c_probe(struct i2c_client *i2c) 2547 { 2548 struct max98090_priv *max98090; 2549 const struct acpi_device_id *acpi_id; 2550 kernel_ulong_t driver_data = 0; 2551 int ret; 2552 2553 pr_debug("max98090_i2c_probe\n"); 2554 2555 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), 2556 GFP_KERNEL); 2557 if (max98090 == NULL) 2558 return -ENOMEM; 2559 2560 if (ACPI_HANDLE(&i2c->dev)) { 2561 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table, 2562 &i2c->dev); 2563 if (!acpi_id) { 2564 dev_err(&i2c->dev, "No driver data\n"); 2565 return -EINVAL; 2566 } 2567 driver_data = acpi_id->driver_data; 2568 } else { 2569 const struct i2c_device_id *i2c_id = 2570 i2c_match_id(max98090_i2c_id, i2c); 2571 driver_data = i2c_id->driver_data; 2572 } 2573 2574 max98090->devtype = driver_data; 2575 i2c_set_clientdata(i2c, max98090); 2576 max98090->pdata = i2c->dev.platform_data; 2577 2578 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq", 2579 &max98090->dmic_freq); 2580 if (ret < 0) 2581 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ; 2582 2583 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); 2584 if (IS_ERR(max98090->regmap)) { 2585 ret = PTR_ERR(max98090->regmap); 2586 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); 2587 goto err_enable; 2588 } 2589 2590 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 2591 max98090_interrupt, IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 2592 "max98090_interrupt", max98090); 2593 if (ret < 0) { 2594 dev_err(&i2c->dev, "request_irq failed: %d\n", 2595 ret); 2596 return ret; 2597 } 2598 2599 ret = devm_snd_soc_register_component(&i2c->dev, 2600 &soc_component_dev_max98090, max98090_dai, 2601 ARRAY_SIZE(max98090_dai)); 2602 err_enable: 2603 return ret; 2604 } 2605 2606 static void max98090_i2c_shutdown(struct i2c_client *i2c) 2607 { 2608 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev); 2609 2610 /* 2611 * Enable volume smoothing, disable zero cross. This will cause 2612 * a quick 40ms ramp to mute on shutdown. 2613 */ 2614 regmap_write(max98090->regmap, 2615 M98090_REG_LEVEL_CONTROL, M98090_VSENN_MASK); 2616 regmap_write(max98090->regmap, 2617 M98090_REG_DEVICE_SHUTDOWN, 0x00); 2618 msleep(40); 2619 } 2620 2621 static int max98090_i2c_remove(struct i2c_client *client) 2622 { 2623 max98090_i2c_shutdown(client); 2624 2625 return 0; 2626 } 2627 2628 #ifdef CONFIG_PM 2629 static int max98090_runtime_resume(struct device *dev) 2630 { 2631 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2632 2633 regcache_cache_only(max98090->regmap, false); 2634 2635 max98090_reset(max98090); 2636 2637 regcache_sync(max98090->regmap); 2638 2639 return 0; 2640 } 2641 2642 static int max98090_runtime_suspend(struct device *dev) 2643 { 2644 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2645 2646 regcache_cache_only(max98090->regmap, true); 2647 2648 return 0; 2649 } 2650 #endif 2651 2652 #ifdef CONFIG_PM_SLEEP 2653 static int max98090_resume(struct device *dev) 2654 { 2655 struct max98090_priv *max98090 = dev_get_drvdata(dev); 2656 unsigned int status; 2657 2658 regcache_mark_dirty(max98090->regmap); 2659 2660 max98090_reset(max98090); 2661 2662 /* clear IRQ status */ 2663 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); 2664 2665 regcache_sync(max98090->regmap); 2666 2667 return 0; 2668 } 2669 #endif 2670 2671 static const struct dev_pm_ops max98090_pm = { 2672 SET_RUNTIME_PM_OPS(max98090_runtime_suspend, 2673 max98090_runtime_resume, NULL) 2674 SET_SYSTEM_SLEEP_PM_OPS(NULL, max98090_resume) 2675 }; 2676 2677 #ifdef CONFIG_OF 2678 static const struct of_device_id max98090_of_match[] = { 2679 { .compatible = "maxim,max98090", }, 2680 { .compatible = "maxim,max98091", }, 2681 { } 2682 }; 2683 MODULE_DEVICE_TABLE(of, max98090_of_match); 2684 #endif 2685 2686 #ifdef CONFIG_ACPI 2687 static const struct acpi_device_id max98090_acpi_match[] = { 2688 { "193C9890", MAX98090 }, 2689 { } 2690 }; 2691 MODULE_DEVICE_TABLE(acpi, max98090_acpi_match); 2692 #endif 2693 2694 static struct i2c_driver max98090_i2c_driver = { 2695 .driver = { 2696 .name = "max98090", 2697 .pm = &max98090_pm, 2698 .of_match_table = of_match_ptr(max98090_of_match), 2699 .acpi_match_table = ACPI_PTR(max98090_acpi_match), 2700 }, 2701 .probe_new = max98090_i2c_probe, 2702 .shutdown = max98090_i2c_shutdown, 2703 .remove = max98090_i2c_remove, 2704 .id_table = max98090_i2c_id, 2705 }; 2706 2707 module_i2c_driver(max98090_i2c_driver); 2708 2709 MODULE_DESCRIPTION("ALSA SoC MAX98090 driver"); 2710 MODULE_AUTHOR("Peter Hsiang, Jesse Marroqin, Jerry Wong"); 2711 MODULE_LICENSE("GPL"); 2712