1 /* 2 * max98088.c -- MAX98088 ALSA SoC Audio driver 3 * 4 * Copyright 2010 Maxim Integrated Products 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #include <linux/module.h> 12 #include <linux/moduleparam.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/delay.h> 16 #include <linux/pm.h> 17 #include <linux/i2c.h> 18 #include <linux/platform_device.h> 19 #include <sound/core.h> 20 #include <sound/pcm.h> 21 #include <sound/pcm_params.h> 22 #include <sound/soc.h> 23 #include <sound/initval.h> 24 #include <sound/tlv.h> 25 #include <linux/slab.h> 26 #include <asm/div64.h> 27 #include <sound/max98088.h> 28 #include "max98088.h" 29 30 enum max98088_type { 31 MAX98088, 32 MAX98089, 33 }; 34 35 struct max98088_cdata { 36 unsigned int rate; 37 unsigned int fmt; 38 int eq_sel; 39 }; 40 41 struct max98088_priv { 42 enum max98088_type devtype; 43 void *control_data; 44 struct max98088_pdata *pdata; 45 unsigned int sysclk; 46 struct max98088_cdata dai[2]; 47 int eq_textcnt; 48 const char **eq_texts; 49 struct soc_enum eq_enum; 50 u8 ina_state; 51 u8 inb_state; 52 unsigned int ex_mode; 53 unsigned int digmic; 54 unsigned int mic1pre; 55 unsigned int mic2pre; 56 unsigned int extmic_mode; 57 }; 58 59 static const u8 max98088_reg[M98088_REG_CNT] = { 60 0x00, /* 00 IRQ status */ 61 0x00, /* 01 MIC status */ 62 0x00, /* 02 jack status */ 63 0x00, /* 03 battery voltage */ 64 0x00, /* 04 */ 65 0x00, /* 05 */ 66 0x00, /* 06 */ 67 0x00, /* 07 */ 68 0x00, /* 08 */ 69 0x00, /* 09 */ 70 0x00, /* 0A */ 71 0x00, /* 0B */ 72 0x00, /* 0C */ 73 0x00, /* 0D */ 74 0x00, /* 0E */ 75 0x00, /* 0F interrupt enable */ 76 77 0x00, /* 10 master clock */ 78 0x00, /* 11 DAI1 clock mode */ 79 0x00, /* 12 DAI1 clock control */ 80 0x00, /* 13 DAI1 clock control */ 81 0x00, /* 14 DAI1 format */ 82 0x00, /* 15 DAI1 clock */ 83 0x00, /* 16 DAI1 config */ 84 0x00, /* 17 DAI1 TDM */ 85 0x00, /* 18 DAI1 filters */ 86 0x00, /* 19 DAI2 clock mode */ 87 0x00, /* 1A DAI2 clock control */ 88 0x00, /* 1B DAI2 clock control */ 89 0x00, /* 1C DAI2 format */ 90 0x00, /* 1D DAI2 clock */ 91 0x00, /* 1E DAI2 config */ 92 0x00, /* 1F DAI2 TDM */ 93 94 0x00, /* 20 DAI2 filters */ 95 0x00, /* 21 data config */ 96 0x00, /* 22 DAC mixer */ 97 0x00, /* 23 left ADC mixer */ 98 0x00, /* 24 right ADC mixer */ 99 0x00, /* 25 left HP mixer */ 100 0x00, /* 26 right HP mixer */ 101 0x00, /* 27 HP control */ 102 0x00, /* 28 left REC mixer */ 103 0x00, /* 29 right REC mixer */ 104 0x00, /* 2A REC control */ 105 0x00, /* 2B left SPK mixer */ 106 0x00, /* 2C right SPK mixer */ 107 0x00, /* 2D SPK control */ 108 0x00, /* 2E sidetone */ 109 0x00, /* 2F DAI1 playback level */ 110 111 0x00, /* 30 DAI1 playback level */ 112 0x00, /* 31 DAI2 playback level */ 113 0x00, /* 32 DAI2 playbakc level */ 114 0x00, /* 33 left ADC level */ 115 0x00, /* 34 right ADC level */ 116 0x00, /* 35 MIC1 level */ 117 0x00, /* 36 MIC2 level */ 118 0x00, /* 37 INA level */ 119 0x00, /* 38 INB level */ 120 0x00, /* 39 left HP volume */ 121 0x00, /* 3A right HP volume */ 122 0x00, /* 3B left REC volume */ 123 0x00, /* 3C right REC volume */ 124 0x00, /* 3D left SPK volume */ 125 0x00, /* 3E right SPK volume */ 126 0x00, /* 3F MIC config */ 127 128 0x00, /* 40 MIC threshold */ 129 0x00, /* 41 excursion limiter filter */ 130 0x00, /* 42 excursion limiter threshold */ 131 0x00, /* 43 ALC */ 132 0x00, /* 44 power limiter threshold */ 133 0x00, /* 45 power limiter config */ 134 0x00, /* 46 distortion limiter config */ 135 0x00, /* 47 audio input */ 136 0x00, /* 48 microphone */ 137 0x00, /* 49 level control */ 138 0x00, /* 4A bypass switches */ 139 0x00, /* 4B jack detect */ 140 0x00, /* 4C input enable */ 141 0x00, /* 4D output enable */ 142 0xF0, /* 4E bias control */ 143 0x00, /* 4F DAC power */ 144 145 0x0F, /* 50 DAC power */ 146 0x00, /* 51 system */ 147 0x00, /* 52 DAI1 EQ1 */ 148 0x00, /* 53 DAI1 EQ1 */ 149 0x00, /* 54 DAI1 EQ1 */ 150 0x00, /* 55 DAI1 EQ1 */ 151 0x00, /* 56 DAI1 EQ1 */ 152 0x00, /* 57 DAI1 EQ1 */ 153 0x00, /* 58 DAI1 EQ1 */ 154 0x00, /* 59 DAI1 EQ1 */ 155 0x00, /* 5A DAI1 EQ1 */ 156 0x00, /* 5B DAI1 EQ1 */ 157 0x00, /* 5C DAI1 EQ2 */ 158 0x00, /* 5D DAI1 EQ2 */ 159 0x00, /* 5E DAI1 EQ2 */ 160 0x00, /* 5F DAI1 EQ2 */ 161 162 0x00, /* 60 DAI1 EQ2 */ 163 0x00, /* 61 DAI1 EQ2 */ 164 0x00, /* 62 DAI1 EQ2 */ 165 0x00, /* 63 DAI1 EQ2 */ 166 0x00, /* 64 DAI1 EQ2 */ 167 0x00, /* 65 DAI1 EQ2 */ 168 0x00, /* 66 DAI1 EQ3 */ 169 0x00, /* 67 DAI1 EQ3 */ 170 0x00, /* 68 DAI1 EQ3 */ 171 0x00, /* 69 DAI1 EQ3 */ 172 0x00, /* 6A DAI1 EQ3 */ 173 0x00, /* 6B DAI1 EQ3 */ 174 0x00, /* 6C DAI1 EQ3 */ 175 0x00, /* 6D DAI1 EQ3 */ 176 0x00, /* 6E DAI1 EQ3 */ 177 0x00, /* 6F DAI1 EQ3 */ 178 179 0x00, /* 70 DAI1 EQ4 */ 180 0x00, /* 71 DAI1 EQ4 */ 181 0x00, /* 72 DAI1 EQ4 */ 182 0x00, /* 73 DAI1 EQ4 */ 183 0x00, /* 74 DAI1 EQ4 */ 184 0x00, /* 75 DAI1 EQ4 */ 185 0x00, /* 76 DAI1 EQ4 */ 186 0x00, /* 77 DAI1 EQ4 */ 187 0x00, /* 78 DAI1 EQ4 */ 188 0x00, /* 79 DAI1 EQ4 */ 189 0x00, /* 7A DAI1 EQ5 */ 190 0x00, /* 7B DAI1 EQ5 */ 191 0x00, /* 7C DAI1 EQ5 */ 192 0x00, /* 7D DAI1 EQ5 */ 193 0x00, /* 7E DAI1 EQ5 */ 194 0x00, /* 7F DAI1 EQ5 */ 195 196 0x00, /* 80 DAI1 EQ5 */ 197 0x00, /* 81 DAI1 EQ5 */ 198 0x00, /* 82 DAI1 EQ5 */ 199 0x00, /* 83 DAI1 EQ5 */ 200 0x00, /* 84 DAI2 EQ1 */ 201 0x00, /* 85 DAI2 EQ1 */ 202 0x00, /* 86 DAI2 EQ1 */ 203 0x00, /* 87 DAI2 EQ1 */ 204 0x00, /* 88 DAI2 EQ1 */ 205 0x00, /* 89 DAI2 EQ1 */ 206 0x00, /* 8A DAI2 EQ1 */ 207 0x00, /* 8B DAI2 EQ1 */ 208 0x00, /* 8C DAI2 EQ1 */ 209 0x00, /* 8D DAI2 EQ1 */ 210 0x00, /* 8E DAI2 EQ2 */ 211 0x00, /* 8F DAI2 EQ2 */ 212 213 0x00, /* 90 DAI2 EQ2 */ 214 0x00, /* 91 DAI2 EQ2 */ 215 0x00, /* 92 DAI2 EQ2 */ 216 0x00, /* 93 DAI2 EQ2 */ 217 0x00, /* 94 DAI2 EQ2 */ 218 0x00, /* 95 DAI2 EQ2 */ 219 0x00, /* 96 DAI2 EQ2 */ 220 0x00, /* 97 DAI2 EQ2 */ 221 0x00, /* 98 DAI2 EQ3 */ 222 0x00, /* 99 DAI2 EQ3 */ 223 0x00, /* 9A DAI2 EQ3 */ 224 0x00, /* 9B DAI2 EQ3 */ 225 0x00, /* 9C DAI2 EQ3 */ 226 0x00, /* 9D DAI2 EQ3 */ 227 0x00, /* 9E DAI2 EQ3 */ 228 0x00, /* 9F DAI2 EQ3 */ 229 230 0x00, /* A0 DAI2 EQ3 */ 231 0x00, /* A1 DAI2 EQ3 */ 232 0x00, /* A2 DAI2 EQ4 */ 233 0x00, /* A3 DAI2 EQ4 */ 234 0x00, /* A4 DAI2 EQ4 */ 235 0x00, /* A5 DAI2 EQ4 */ 236 0x00, /* A6 DAI2 EQ4 */ 237 0x00, /* A7 DAI2 EQ4 */ 238 0x00, /* A8 DAI2 EQ4 */ 239 0x00, /* A9 DAI2 EQ4 */ 240 0x00, /* AA DAI2 EQ4 */ 241 0x00, /* AB DAI2 EQ4 */ 242 0x00, /* AC DAI2 EQ5 */ 243 0x00, /* AD DAI2 EQ5 */ 244 0x00, /* AE DAI2 EQ5 */ 245 0x00, /* AF DAI2 EQ5 */ 246 247 0x00, /* B0 DAI2 EQ5 */ 248 0x00, /* B1 DAI2 EQ5 */ 249 0x00, /* B2 DAI2 EQ5 */ 250 0x00, /* B3 DAI2 EQ5 */ 251 0x00, /* B4 DAI2 EQ5 */ 252 0x00, /* B5 DAI2 EQ5 */ 253 0x00, /* B6 DAI1 biquad */ 254 0x00, /* B7 DAI1 biquad */ 255 0x00, /* B8 DAI1 biquad */ 256 0x00, /* B9 DAI1 biquad */ 257 0x00, /* BA DAI1 biquad */ 258 0x00, /* BB DAI1 biquad */ 259 0x00, /* BC DAI1 biquad */ 260 0x00, /* BD DAI1 biquad */ 261 0x00, /* BE DAI1 biquad */ 262 0x00, /* BF DAI1 biquad */ 263 264 0x00, /* C0 DAI2 biquad */ 265 0x00, /* C1 DAI2 biquad */ 266 0x00, /* C2 DAI2 biquad */ 267 0x00, /* C3 DAI2 biquad */ 268 0x00, /* C4 DAI2 biquad */ 269 0x00, /* C5 DAI2 biquad */ 270 0x00, /* C6 DAI2 biquad */ 271 0x00, /* C7 DAI2 biquad */ 272 0x00, /* C8 DAI2 biquad */ 273 0x00, /* C9 DAI2 biquad */ 274 0x00, /* CA */ 275 0x00, /* CB */ 276 0x00, /* CC */ 277 0x00, /* CD */ 278 0x00, /* CE */ 279 0x00, /* CF */ 280 281 0x00, /* D0 */ 282 0x00, /* D1 */ 283 0x00, /* D2 */ 284 0x00, /* D3 */ 285 0x00, /* D4 */ 286 0x00, /* D5 */ 287 0x00, /* D6 */ 288 0x00, /* D7 */ 289 0x00, /* D8 */ 290 0x00, /* D9 */ 291 0x00, /* DA */ 292 0x70, /* DB */ 293 0x00, /* DC */ 294 0x00, /* DD */ 295 0x00, /* DE */ 296 0x00, /* DF */ 297 298 0x00, /* E0 */ 299 0x00, /* E1 */ 300 0x00, /* E2 */ 301 0x00, /* E3 */ 302 0x00, /* E4 */ 303 0x00, /* E5 */ 304 0x00, /* E6 */ 305 0x00, /* E7 */ 306 0x00, /* E8 */ 307 0x00, /* E9 */ 308 0x00, /* EA */ 309 0x00, /* EB */ 310 0x00, /* EC */ 311 0x00, /* ED */ 312 0x00, /* EE */ 313 0x00, /* EF */ 314 315 0x00, /* F0 */ 316 0x00, /* F1 */ 317 0x00, /* F2 */ 318 0x00, /* F3 */ 319 0x00, /* F4 */ 320 0x00, /* F5 */ 321 0x00, /* F6 */ 322 0x00, /* F7 */ 323 0x00, /* F8 */ 324 0x00, /* F9 */ 325 0x00, /* FA */ 326 0x00, /* FB */ 327 0x00, /* FC */ 328 0x00, /* FD */ 329 0x00, /* FE */ 330 0x00, /* FF */ 331 }; 332 333 static struct { 334 int readable; 335 int writable; 336 int vol; 337 } max98088_access[M98088_REG_CNT] = { 338 { 0xFF, 0xFF, 1 }, /* 00 IRQ status */ 339 { 0xFF, 0x00, 1 }, /* 01 MIC status */ 340 { 0xFF, 0x00, 1 }, /* 02 jack status */ 341 { 0x1F, 0x1F, 1 }, /* 03 battery voltage */ 342 { 0xFF, 0xFF, 0 }, /* 04 */ 343 { 0xFF, 0xFF, 0 }, /* 05 */ 344 { 0xFF, 0xFF, 0 }, /* 06 */ 345 { 0xFF, 0xFF, 0 }, /* 07 */ 346 { 0xFF, 0xFF, 0 }, /* 08 */ 347 { 0xFF, 0xFF, 0 }, /* 09 */ 348 { 0xFF, 0xFF, 0 }, /* 0A */ 349 { 0xFF, 0xFF, 0 }, /* 0B */ 350 { 0xFF, 0xFF, 0 }, /* 0C */ 351 { 0xFF, 0xFF, 0 }, /* 0D */ 352 { 0xFF, 0xFF, 0 }, /* 0E */ 353 { 0xFF, 0xFF, 0 }, /* 0F interrupt enable */ 354 355 { 0xFF, 0xFF, 0 }, /* 10 master clock */ 356 { 0xFF, 0xFF, 0 }, /* 11 DAI1 clock mode */ 357 { 0xFF, 0xFF, 0 }, /* 12 DAI1 clock control */ 358 { 0xFF, 0xFF, 0 }, /* 13 DAI1 clock control */ 359 { 0xFF, 0xFF, 0 }, /* 14 DAI1 format */ 360 { 0xFF, 0xFF, 0 }, /* 15 DAI1 clock */ 361 { 0xFF, 0xFF, 0 }, /* 16 DAI1 config */ 362 { 0xFF, 0xFF, 0 }, /* 17 DAI1 TDM */ 363 { 0xFF, 0xFF, 0 }, /* 18 DAI1 filters */ 364 { 0xFF, 0xFF, 0 }, /* 19 DAI2 clock mode */ 365 { 0xFF, 0xFF, 0 }, /* 1A DAI2 clock control */ 366 { 0xFF, 0xFF, 0 }, /* 1B DAI2 clock control */ 367 { 0xFF, 0xFF, 0 }, /* 1C DAI2 format */ 368 { 0xFF, 0xFF, 0 }, /* 1D DAI2 clock */ 369 { 0xFF, 0xFF, 0 }, /* 1E DAI2 config */ 370 { 0xFF, 0xFF, 0 }, /* 1F DAI2 TDM */ 371 372 { 0xFF, 0xFF, 0 }, /* 20 DAI2 filters */ 373 { 0xFF, 0xFF, 0 }, /* 21 data config */ 374 { 0xFF, 0xFF, 0 }, /* 22 DAC mixer */ 375 { 0xFF, 0xFF, 0 }, /* 23 left ADC mixer */ 376 { 0xFF, 0xFF, 0 }, /* 24 right ADC mixer */ 377 { 0xFF, 0xFF, 0 }, /* 25 left HP mixer */ 378 { 0xFF, 0xFF, 0 }, /* 26 right HP mixer */ 379 { 0xFF, 0xFF, 0 }, /* 27 HP control */ 380 { 0xFF, 0xFF, 0 }, /* 28 left REC mixer */ 381 { 0xFF, 0xFF, 0 }, /* 29 right REC mixer */ 382 { 0xFF, 0xFF, 0 }, /* 2A REC control */ 383 { 0xFF, 0xFF, 0 }, /* 2B left SPK mixer */ 384 { 0xFF, 0xFF, 0 }, /* 2C right SPK mixer */ 385 { 0xFF, 0xFF, 0 }, /* 2D SPK control */ 386 { 0xFF, 0xFF, 0 }, /* 2E sidetone */ 387 { 0xFF, 0xFF, 0 }, /* 2F DAI1 playback level */ 388 389 { 0xFF, 0xFF, 0 }, /* 30 DAI1 playback level */ 390 { 0xFF, 0xFF, 0 }, /* 31 DAI2 playback level */ 391 { 0xFF, 0xFF, 0 }, /* 32 DAI2 playbakc level */ 392 { 0xFF, 0xFF, 0 }, /* 33 left ADC level */ 393 { 0xFF, 0xFF, 0 }, /* 34 right ADC level */ 394 { 0xFF, 0xFF, 0 }, /* 35 MIC1 level */ 395 { 0xFF, 0xFF, 0 }, /* 36 MIC2 level */ 396 { 0xFF, 0xFF, 0 }, /* 37 INA level */ 397 { 0xFF, 0xFF, 0 }, /* 38 INB level */ 398 { 0xFF, 0xFF, 0 }, /* 39 left HP volume */ 399 { 0xFF, 0xFF, 0 }, /* 3A right HP volume */ 400 { 0xFF, 0xFF, 0 }, /* 3B left REC volume */ 401 { 0xFF, 0xFF, 0 }, /* 3C right REC volume */ 402 { 0xFF, 0xFF, 0 }, /* 3D left SPK volume */ 403 { 0xFF, 0xFF, 0 }, /* 3E right SPK volume */ 404 { 0xFF, 0xFF, 0 }, /* 3F MIC config */ 405 406 { 0xFF, 0xFF, 0 }, /* 40 MIC threshold */ 407 { 0xFF, 0xFF, 0 }, /* 41 excursion limiter filter */ 408 { 0xFF, 0xFF, 0 }, /* 42 excursion limiter threshold */ 409 { 0xFF, 0xFF, 0 }, /* 43 ALC */ 410 { 0xFF, 0xFF, 0 }, /* 44 power limiter threshold */ 411 { 0xFF, 0xFF, 0 }, /* 45 power limiter config */ 412 { 0xFF, 0xFF, 0 }, /* 46 distortion limiter config */ 413 { 0xFF, 0xFF, 0 }, /* 47 audio input */ 414 { 0xFF, 0xFF, 0 }, /* 48 microphone */ 415 { 0xFF, 0xFF, 0 }, /* 49 level control */ 416 { 0xFF, 0xFF, 0 }, /* 4A bypass switches */ 417 { 0xFF, 0xFF, 0 }, /* 4B jack detect */ 418 { 0xFF, 0xFF, 0 }, /* 4C input enable */ 419 { 0xFF, 0xFF, 0 }, /* 4D output enable */ 420 { 0xFF, 0xFF, 0 }, /* 4E bias control */ 421 { 0xFF, 0xFF, 0 }, /* 4F DAC power */ 422 423 { 0xFF, 0xFF, 0 }, /* 50 DAC power */ 424 { 0xFF, 0xFF, 0 }, /* 51 system */ 425 { 0xFF, 0xFF, 0 }, /* 52 DAI1 EQ1 */ 426 { 0xFF, 0xFF, 0 }, /* 53 DAI1 EQ1 */ 427 { 0xFF, 0xFF, 0 }, /* 54 DAI1 EQ1 */ 428 { 0xFF, 0xFF, 0 }, /* 55 DAI1 EQ1 */ 429 { 0xFF, 0xFF, 0 }, /* 56 DAI1 EQ1 */ 430 { 0xFF, 0xFF, 0 }, /* 57 DAI1 EQ1 */ 431 { 0xFF, 0xFF, 0 }, /* 58 DAI1 EQ1 */ 432 { 0xFF, 0xFF, 0 }, /* 59 DAI1 EQ1 */ 433 { 0xFF, 0xFF, 0 }, /* 5A DAI1 EQ1 */ 434 { 0xFF, 0xFF, 0 }, /* 5B DAI1 EQ1 */ 435 { 0xFF, 0xFF, 0 }, /* 5C DAI1 EQ2 */ 436 { 0xFF, 0xFF, 0 }, /* 5D DAI1 EQ2 */ 437 { 0xFF, 0xFF, 0 }, /* 5E DAI1 EQ2 */ 438 { 0xFF, 0xFF, 0 }, /* 5F DAI1 EQ2 */ 439 440 { 0xFF, 0xFF, 0 }, /* 60 DAI1 EQ2 */ 441 { 0xFF, 0xFF, 0 }, /* 61 DAI1 EQ2 */ 442 { 0xFF, 0xFF, 0 }, /* 62 DAI1 EQ2 */ 443 { 0xFF, 0xFF, 0 }, /* 63 DAI1 EQ2 */ 444 { 0xFF, 0xFF, 0 }, /* 64 DAI1 EQ2 */ 445 { 0xFF, 0xFF, 0 }, /* 65 DAI1 EQ2 */ 446 { 0xFF, 0xFF, 0 }, /* 66 DAI1 EQ3 */ 447 { 0xFF, 0xFF, 0 }, /* 67 DAI1 EQ3 */ 448 { 0xFF, 0xFF, 0 }, /* 68 DAI1 EQ3 */ 449 { 0xFF, 0xFF, 0 }, /* 69 DAI1 EQ3 */ 450 { 0xFF, 0xFF, 0 }, /* 6A DAI1 EQ3 */ 451 { 0xFF, 0xFF, 0 }, /* 6B DAI1 EQ3 */ 452 { 0xFF, 0xFF, 0 }, /* 6C DAI1 EQ3 */ 453 { 0xFF, 0xFF, 0 }, /* 6D DAI1 EQ3 */ 454 { 0xFF, 0xFF, 0 }, /* 6E DAI1 EQ3 */ 455 { 0xFF, 0xFF, 0 }, /* 6F DAI1 EQ3 */ 456 457 { 0xFF, 0xFF, 0 }, /* 70 DAI1 EQ4 */ 458 { 0xFF, 0xFF, 0 }, /* 71 DAI1 EQ4 */ 459 { 0xFF, 0xFF, 0 }, /* 72 DAI1 EQ4 */ 460 { 0xFF, 0xFF, 0 }, /* 73 DAI1 EQ4 */ 461 { 0xFF, 0xFF, 0 }, /* 74 DAI1 EQ4 */ 462 { 0xFF, 0xFF, 0 }, /* 75 DAI1 EQ4 */ 463 { 0xFF, 0xFF, 0 }, /* 76 DAI1 EQ4 */ 464 { 0xFF, 0xFF, 0 }, /* 77 DAI1 EQ4 */ 465 { 0xFF, 0xFF, 0 }, /* 78 DAI1 EQ4 */ 466 { 0xFF, 0xFF, 0 }, /* 79 DAI1 EQ4 */ 467 { 0xFF, 0xFF, 0 }, /* 7A DAI1 EQ5 */ 468 { 0xFF, 0xFF, 0 }, /* 7B DAI1 EQ5 */ 469 { 0xFF, 0xFF, 0 }, /* 7C DAI1 EQ5 */ 470 { 0xFF, 0xFF, 0 }, /* 7D DAI1 EQ5 */ 471 { 0xFF, 0xFF, 0 }, /* 7E DAI1 EQ5 */ 472 { 0xFF, 0xFF, 0 }, /* 7F DAI1 EQ5 */ 473 474 { 0xFF, 0xFF, 0 }, /* 80 DAI1 EQ5 */ 475 { 0xFF, 0xFF, 0 }, /* 81 DAI1 EQ5 */ 476 { 0xFF, 0xFF, 0 }, /* 82 DAI1 EQ5 */ 477 { 0xFF, 0xFF, 0 }, /* 83 DAI1 EQ5 */ 478 { 0xFF, 0xFF, 0 }, /* 84 DAI2 EQ1 */ 479 { 0xFF, 0xFF, 0 }, /* 85 DAI2 EQ1 */ 480 { 0xFF, 0xFF, 0 }, /* 86 DAI2 EQ1 */ 481 { 0xFF, 0xFF, 0 }, /* 87 DAI2 EQ1 */ 482 { 0xFF, 0xFF, 0 }, /* 88 DAI2 EQ1 */ 483 { 0xFF, 0xFF, 0 }, /* 89 DAI2 EQ1 */ 484 { 0xFF, 0xFF, 0 }, /* 8A DAI2 EQ1 */ 485 { 0xFF, 0xFF, 0 }, /* 8B DAI2 EQ1 */ 486 { 0xFF, 0xFF, 0 }, /* 8C DAI2 EQ1 */ 487 { 0xFF, 0xFF, 0 }, /* 8D DAI2 EQ1 */ 488 { 0xFF, 0xFF, 0 }, /* 8E DAI2 EQ2 */ 489 { 0xFF, 0xFF, 0 }, /* 8F DAI2 EQ2 */ 490 491 { 0xFF, 0xFF, 0 }, /* 90 DAI2 EQ2 */ 492 { 0xFF, 0xFF, 0 }, /* 91 DAI2 EQ2 */ 493 { 0xFF, 0xFF, 0 }, /* 92 DAI2 EQ2 */ 494 { 0xFF, 0xFF, 0 }, /* 93 DAI2 EQ2 */ 495 { 0xFF, 0xFF, 0 }, /* 94 DAI2 EQ2 */ 496 { 0xFF, 0xFF, 0 }, /* 95 DAI2 EQ2 */ 497 { 0xFF, 0xFF, 0 }, /* 96 DAI2 EQ2 */ 498 { 0xFF, 0xFF, 0 }, /* 97 DAI2 EQ2 */ 499 { 0xFF, 0xFF, 0 }, /* 98 DAI2 EQ3 */ 500 { 0xFF, 0xFF, 0 }, /* 99 DAI2 EQ3 */ 501 { 0xFF, 0xFF, 0 }, /* 9A DAI2 EQ3 */ 502 { 0xFF, 0xFF, 0 }, /* 9B DAI2 EQ3 */ 503 { 0xFF, 0xFF, 0 }, /* 9C DAI2 EQ3 */ 504 { 0xFF, 0xFF, 0 }, /* 9D DAI2 EQ3 */ 505 { 0xFF, 0xFF, 0 }, /* 9E DAI2 EQ3 */ 506 { 0xFF, 0xFF, 0 }, /* 9F DAI2 EQ3 */ 507 508 { 0xFF, 0xFF, 0 }, /* A0 DAI2 EQ3 */ 509 { 0xFF, 0xFF, 0 }, /* A1 DAI2 EQ3 */ 510 { 0xFF, 0xFF, 0 }, /* A2 DAI2 EQ4 */ 511 { 0xFF, 0xFF, 0 }, /* A3 DAI2 EQ4 */ 512 { 0xFF, 0xFF, 0 }, /* A4 DAI2 EQ4 */ 513 { 0xFF, 0xFF, 0 }, /* A5 DAI2 EQ4 */ 514 { 0xFF, 0xFF, 0 }, /* A6 DAI2 EQ4 */ 515 { 0xFF, 0xFF, 0 }, /* A7 DAI2 EQ4 */ 516 { 0xFF, 0xFF, 0 }, /* A8 DAI2 EQ4 */ 517 { 0xFF, 0xFF, 0 }, /* A9 DAI2 EQ4 */ 518 { 0xFF, 0xFF, 0 }, /* AA DAI2 EQ4 */ 519 { 0xFF, 0xFF, 0 }, /* AB DAI2 EQ4 */ 520 { 0xFF, 0xFF, 0 }, /* AC DAI2 EQ5 */ 521 { 0xFF, 0xFF, 0 }, /* AD DAI2 EQ5 */ 522 { 0xFF, 0xFF, 0 }, /* AE DAI2 EQ5 */ 523 { 0xFF, 0xFF, 0 }, /* AF DAI2 EQ5 */ 524 525 { 0xFF, 0xFF, 0 }, /* B0 DAI2 EQ5 */ 526 { 0xFF, 0xFF, 0 }, /* B1 DAI2 EQ5 */ 527 { 0xFF, 0xFF, 0 }, /* B2 DAI2 EQ5 */ 528 { 0xFF, 0xFF, 0 }, /* B3 DAI2 EQ5 */ 529 { 0xFF, 0xFF, 0 }, /* B4 DAI2 EQ5 */ 530 { 0xFF, 0xFF, 0 }, /* B5 DAI2 EQ5 */ 531 { 0xFF, 0xFF, 0 }, /* B6 DAI1 biquad */ 532 { 0xFF, 0xFF, 0 }, /* B7 DAI1 biquad */ 533 { 0xFF, 0xFF, 0 }, /* B8 DAI1 biquad */ 534 { 0xFF, 0xFF, 0 }, /* B9 DAI1 biquad */ 535 { 0xFF, 0xFF, 0 }, /* BA DAI1 biquad */ 536 { 0xFF, 0xFF, 0 }, /* BB DAI1 biquad */ 537 { 0xFF, 0xFF, 0 }, /* BC DAI1 biquad */ 538 { 0xFF, 0xFF, 0 }, /* BD DAI1 biquad */ 539 { 0xFF, 0xFF, 0 }, /* BE DAI1 biquad */ 540 { 0xFF, 0xFF, 0 }, /* BF DAI1 biquad */ 541 542 { 0xFF, 0xFF, 0 }, /* C0 DAI2 biquad */ 543 { 0xFF, 0xFF, 0 }, /* C1 DAI2 biquad */ 544 { 0xFF, 0xFF, 0 }, /* C2 DAI2 biquad */ 545 { 0xFF, 0xFF, 0 }, /* C3 DAI2 biquad */ 546 { 0xFF, 0xFF, 0 }, /* C4 DAI2 biquad */ 547 { 0xFF, 0xFF, 0 }, /* C5 DAI2 biquad */ 548 { 0xFF, 0xFF, 0 }, /* C6 DAI2 biquad */ 549 { 0xFF, 0xFF, 0 }, /* C7 DAI2 biquad */ 550 { 0xFF, 0xFF, 0 }, /* C8 DAI2 biquad */ 551 { 0xFF, 0xFF, 0 }, /* C9 DAI2 biquad */ 552 { 0x00, 0x00, 0 }, /* CA */ 553 { 0x00, 0x00, 0 }, /* CB */ 554 { 0x00, 0x00, 0 }, /* CC */ 555 { 0x00, 0x00, 0 }, /* CD */ 556 { 0x00, 0x00, 0 }, /* CE */ 557 { 0x00, 0x00, 0 }, /* CF */ 558 559 { 0x00, 0x00, 0 }, /* D0 */ 560 { 0x00, 0x00, 0 }, /* D1 */ 561 { 0x00, 0x00, 0 }, /* D2 */ 562 { 0x00, 0x00, 0 }, /* D3 */ 563 { 0x00, 0x00, 0 }, /* D4 */ 564 { 0x00, 0x00, 0 }, /* D5 */ 565 { 0x00, 0x00, 0 }, /* D6 */ 566 { 0x00, 0x00, 0 }, /* D7 */ 567 { 0x00, 0x00, 0 }, /* D8 */ 568 { 0x00, 0x00, 0 }, /* D9 */ 569 { 0x00, 0x00, 0 }, /* DA */ 570 { 0x00, 0x00, 0 }, /* DB */ 571 { 0x00, 0x00, 0 }, /* DC */ 572 { 0x00, 0x00, 0 }, /* DD */ 573 { 0x00, 0x00, 0 }, /* DE */ 574 { 0x00, 0x00, 0 }, /* DF */ 575 576 { 0x00, 0x00, 0 }, /* E0 */ 577 { 0x00, 0x00, 0 }, /* E1 */ 578 { 0x00, 0x00, 0 }, /* E2 */ 579 { 0x00, 0x00, 0 }, /* E3 */ 580 { 0x00, 0x00, 0 }, /* E4 */ 581 { 0x00, 0x00, 0 }, /* E5 */ 582 { 0x00, 0x00, 0 }, /* E6 */ 583 { 0x00, 0x00, 0 }, /* E7 */ 584 { 0x00, 0x00, 0 }, /* E8 */ 585 { 0x00, 0x00, 0 }, /* E9 */ 586 { 0x00, 0x00, 0 }, /* EA */ 587 { 0x00, 0x00, 0 }, /* EB */ 588 { 0x00, 0x00, 0 }, /* EC */ 589 { 0x00, 0x00, 0 }, /* ED */ 590 { 0x00, 0x00, 0 }, /* EE */ 591 { 0x00, 0x00, 0 }, /* EF */ 592 593 { 0x00, 0x00, 0 }, /* F0 */ 594 { 0x00, 0x00, 0 }, /* F1 */ 595 { 0x00, 0x00, 0 }, /* F2 */ 596 { 0x00, 0x00, 0 }, /* F3 */ 597 { 0x00, 0x00, 0 }, /* F4 */ 598 { 0x00, 0x00, 0 }, /* F5 */ 599 { 0x00, 0x00, 0 }, /* F6 */ 600 { 0x00, 0x00, 0 }, /* F7 */ 601 { 0x00, 0x00, 0 }, /* F8 */ 602 { 0x00, 0x00, 0 }, /* F9 */ 603 { 0x00, 0x00, 0 }, /* FA */ 604 { 0x00, 0x00, 0 }, /* FB */ 605 { 0x00, 0x00, 0 }, /* FC */ 606 { 0x00, 0x00, 0 }, /* FD */ 607 { 0x00, 0x00, 0 }, /* FE */ 608 { 0xFF, 0x00, 1 }, /* FF */ 609 }; 610 611 static int max98088_volatile_register(struct snd_soc_codec *codec, unsigned int reg) 612 { 613 return max98088_access[reg].vol; 614 } 615 616 617 /* 618 * Load equalizer DSP coefficient configurations registers 619 */ 620 static void m98088_eq_band(struct snd_soc_codec *codec, unsigned int dai, 621 unsigned int band, u16 *coefs) 622 { 623 unsigned int eq_reg; 624 unsigned int i; 625 626 BUG_ON(band > 4); 627 BUG_ON(dai > 1); 628 629 /* Load the base register address */ 630 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE; 631 632 /* Add the band address offset, note adjustment for word address */ 633 eq_reg += band * (M98088_COEFS_PER_BAND << 1); 634 635 /* Step through the registers and coefs */ 636 for (i = 0; i < M98088_COEFS_PER_BAND; i++) { 637 snd_soc_write(codec, eq_reg++, M98088_BYTE1(coefs[i])); 638 snd_soc_write(codec, eq_reg++, M98088_BYTE0(coefs[i])); 639 } 640 } 641 642 /* 643 * Excursion limiter modes 644 */ 645 static const char *max98088_exmode_texts[] = { 646 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz", 647 "400-600Hz", "400-800Hz", 648 }; 649 650 static const unsigned int max98088_exmode_values[] = { 651 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32 652 }; 653 654 static const struct soc_enum max98088_exmode_enum = 655 SOC_VALUE_ENUM_SINGLE(M98088_REG_41_SPKDHP, 0, 127, 656 ARRAY_SIZE(max98088_exmode_texts), 657 max98088_exmode_texts, 658 max98088_exmode_values); 659 static const struct snd_kcontrol_new max98088_exmode_controls = 660 SOC_DAPM_VALUE_ENUM("Route", max98088_exmode_enum); 661 662 static const char *max98088_ex_thresh[] = { /* volts PP */ 663 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"}; 664 static const struct soc_enum max98088_ex_thresh_enum[] = { 665 SOC_ENUM_SINGLE(M98088_REG_42_SPKDHP_THRESH, 0, 8, 666 max98088_ex_thresh), 667 }; 668 669 static const char *max98088_fltr_mode[] = {"Voice", "Music" }; 670 static const struct soc_enum max98088_filter_mode_enum[] = { 671 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 7, 2, max98088_fltr_mode), 672 }; 673 674 static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" }; 675 676 static const struct soc_enum max98088_extmic_enum = 677 SOC_ENUM_SINGLE(M98088_REG_48_CFG_MIC, 0, 3, max98088_extmic_text); 678 679 static const struct snd_kcontrol_new max98088_extmic_mux = 680 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum); 681 682 static const char *max98088_dai1_fltr[] = { 683 "Off", "fc=258/fs=16k", "fc=500/fs=16k", 684 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"}; 685 static const struct soc_enum max98088_dai1_dac_filter_enum[] = { 686 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 0, 6, max98088_dai1_fltr), 687 }; 688 static const struct soc_enum max98088_dai1_adc_filter_enum[] = { 689 SOC_ENUM_SINGLE(M98088_REG_18_DAI1_FILTERS, 4, 6, max98088_dai1_fltr), 690 }; 691 692 static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol, 693 struct snd_ctl_elem_value *ucontrol) 694 { 695 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 696 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 697 unsigned int sel = ucontrol->value.integer.value[0]; 698 699 max98088->mic1pre = sel; 700 snd_soc_update_bits(codec, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK, 701 (1+sel)<<M98088_MICPRE_SHIFT); 702 703 return 0; 704 } 705 706 static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol, 707 struct snd_ctl_elem_value *ucontrol) 708 { 709 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 710 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 711 712 ucontrol->value.integer.value[0] = max98088->mic1pre; 713 return 0; 714 } 715 716 static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol, 717 struct snd_ctl_elem_value *ucontrol) 718 { 719 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 720 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 721 unsigned int sel = ucontrol->value.integer.value[0]; 722 723 max98088->mic2pre = sel; 724 snd_soc_update_bits(codec, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK, 725 (1+sel)<<M98088_MICPRE_SHIFT); 726 727 return 0; 728 } 729 730 static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol, 731 struct snd_ctl_elem_value *ucontrol) 732 { 733 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 734 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 735 736 ucontrol->value.integer.value[0] = max98088->mic2pre; 737 return 0; 738 } 739 740 static const unsigned int max98088_micboost_tlv[] = { 741 TLV_DB_RANGE_HEAD(2), 742 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 743 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0), 744 }; 745 746 static const struct snd_kcontrol_new max98088_snd_controls[] = { 747 748 SOC_DOUBLE_R("Headphone Volume", M98088_REG_39_LVL_HP_L, 749 M98088_REG_3A_LVL_HP_R, 0, 31, 0), 750 SOC_DOUBLE_R("Speaker Volume", M98088_REG_3D_LVL_SPK_L, 751 M98088_REG_3E_LVL_SPK_R, 0, 31, 0), 752 SOC_DOUBLE_R("Receiver Volume", M98088_REG_3B_LVL_REC_L, 753 M98088_REG_3C_LVL_REC_R, 0, 31, 0), 754 755 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L, 756 M98088_REG_3A_LVL_HP_R, 7, 1, 1), 757 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L, 758 M98088_REG_3E_LVL_SPK_R, 7, 1, 1), 759 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L, 760 M98088_REG_3C_LVL_REC_R, 7, 1, 1), 761 762 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1), 763 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1), 764 765 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 766 M98088_REG_35_LVL_MIC1, 5, 2, 0, 767 max98088_mic1pre_get, max98088_mic1pre_set, 768 max98088_micboost_tlv), 769 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 770 M98088_REG_36_LVL_MIC2, 5, 2, 0, 771 max98088_mic2pre_get, max98088_mic2pre_set, 772 max98088_micboost_tlv), 773 774 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1), 775 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1), 776 777 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0), 778 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0), 779 780 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0), 781 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0), 782 783 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0), 784 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0), 785 786 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum), 787 788 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum), 789 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum), 790 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum), 791 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS, 792 0, 1, 0), 793 794 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0), 795 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0), 796 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0), 797 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0), 798 799 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG, 800 4, 15, 0), 801 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0), 802 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0), 803 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0), 804 805 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0), 806 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0), 807 }; 808 809 /* Left speaker mixer switch */ 810 static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = { 811 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), 812 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), 813 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), 814 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), 815 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0), 816 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0), 817 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0), 818 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0), 819 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0), 820 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0), 821 }; 822 823 /* Right speaker mixer switch */ 824 static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = { 825 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), 826 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), 827 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), 828 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), 829 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0), 830 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0), 831 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0), 832 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0), 833 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0), 834 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0), 835 }; 836 837 /* Left headphone mixer switch */ 838 static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = { 839 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), 840 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), 841 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), 842 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), 843 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0), 844 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0), 845 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0), 846 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0), 847 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0), 848 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0), 849 }; 850 851 /* Right headphone mixer switch */ 852 static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = { 853 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), 854 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), 855 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), 856 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), 857 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0), 858 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0), 859 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0), 860 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0), 861 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0), 862 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0), 863 }; 864 865 /* Left earpiece/receiver mixer switch */ 866 static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = { 867 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), 868 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), 869 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), 870 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), 871 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0), 872 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0), 873 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0), 874 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0), 875 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0), 876 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0), 877 }; 878 879 /* Right earpiece/receiver mixer switch */ 880 static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = { 881 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), 882 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), 883 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), 884 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), 885 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0), 886 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0), 887 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0), 888 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0), 889 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0), 890 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0), 891 }; 892 893 /* Left ADC mixer switch */ 894 static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = { 895 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0), 896 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0), 897 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0), 898 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0), 899 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0), 900 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0), 901 }; 902 903 /* Right ADC mixer switch */ 904 static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = { 905 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0), 906 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0), 907 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0), 908 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0), 909 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0), 910 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0), 911 }; 912 913 static int max98088_mic_event(struct snd_soc_dapm_widget *w, 914 struct snd_kcontrol *kcontrol, int event) 915 { 916 struct snd_soc_codec *codec = w->codec; 917 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 918 919 switch (event) { 920 case SND_SOC_DAPM_POST_PMU: 921 if (w->reg == M98088_REG_35_LVL_MIC1) { 922 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 923 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT); 924 } else { 925 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 926 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT); 927 } 928 break; 929 case SND_SOC_DAPM_POST_PMD: 930 snd_soc_update_bits(codec, w->reg, M98088_MICPRE_MASK, 0); 931 break; 932 default: 933 return -EINVAL; 934 } 935 936 return 0; 937 } 938 939 /* 940 * The line inputs are 2-channel stereo inputs with the left 941 * and right channels sharing a common PGA power control signal. 942 */ 943 static int max98088_line_pga(struct snd_soc_dapm_widget *w, 944 int event, int line, u8 channel) 945 { 946 struct snd_soc_codec *codec = w->codec; 947 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 948 u8 *state; 949 950 BUG_ON(!((channel == 1) || (channel == 2))); 951 952 switch (line) { 953 case LINE_INA: 954 state = &max98088->ina_state; 955 break; 956 case LINE_INB: 957 state = &max98088->inb_state; 958 break; 959 default: 960 return -EINVAL; 961 } 962 963 switch (event) { 964 case SND_SOC_DAPM_POST_PMU: 965 *state |= channel; 966 snd_soc_update_bits(codec, w->reg, 967 (1 << w->shift), (1 << w->shift)); 968 break; 969 case SND_SOC_DAPM_POST_PMD: 970 *state &= ~channel; 971 if (*state == 0) { 972 snd_soc_update_bits(codec, w->reg, 973 (1 << w->shift), 0); 974 } 975 break; 976 default: 977 return -EINVAL; 978 } 979 980 return 0; 981 } 982 983 static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w, 984 struct snd_kcontrol *k, int event) 985 { 986 return max98088_line_pga(w, event, LINE_INA, 1); 987 } 988 989 static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w, 990 struct snd_kcontrol *k, int event) 991 { 992 return max98088_line_pga(w, event, LINE_INA, 2); 993 } 994 995 static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w, 996 struct snd_kcontrol *k, int event) 997 { 998 return max98088_line_pga(w, event, LINE_INB, 1); 999 } 1000 1001 static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w, 1002 struct snd_kcontrol *k, int event) 1003 { 1004 return max98088_line_pga(w, event, LINE_INB, 2); 1005 } 1006 1007 static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = { 1008 1009 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0), 1010 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0), 1011 1012 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", 1013 M98088_REG_4D_PWR_EN_OUT, 1, 0), 1014 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", 1015 M98088_REG_4D_PWR_EN_OUT, 0, 0), 1016 SND_SOC_DAPM_DAC("DACL2", "Aux Playback", 1017 M98088_REG_4D_PWR_EN_OUT, 1, 0), 1018 SND_SOC_DAPM_DAC("DACR2", "Aux Playback", 1019 M98088_REG_4D_PWR_EN_OUT, 0, 0), 1020 1021 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT, 1022 7, 0, NULL, 0), 1023 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT, 1024 6, 0, NULL, 0), 1025 1026 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT, 1027 5, 0, NULL, 0), 1028 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT, 1029 4, 0, NULL, 0), 1030 1031 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT, 1032 3, 0, NULL, 0), 1033 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT, 1034 2, 0, NULL, 0), 1035 1036 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, 1037 &max98088_extmic_mux), 1038 1039 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 1040 &max98088_left_hp_mixer_controls[0], 1041 ARRAY_SIZE(max98088_left_hp_mixer_controls)), 1042 1043 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 1044 &max98088_right_hp_mixer_controls[0], 1045 ARRAY_SIZE(max98088_right_hp_mixer_controls)), 1046 1047 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0, 1048 &max98088_left_speaker_mixer_controls[0], 1049 ARRAY_SIZE(max98088_left_speaker_mixer_controls)), 1050 1051 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0, 1052 &max98088_right_speaker_mixer_controls[0], 1053 ARRAY_SIZE(max98088_right_speaker_mixer_controls)), 1054 1055 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0, 1056 &max98088_left_rec_mixer_controls[0], 1057 ARRAY_SIZE(max98088_left_rec_mixer_controls)), 1058 1059 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0, 1060 &max98088_right_rec_mixer_controls[0], 1061 ARRAY_SIZE(max98088_right_rec_mixer_controls)), 1062 1063 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 1064 &max98088_left_ADC_mixer_controls[0], 1065 ARRAY_SIZE(max98088_left_ADC_mixer_controls)), 1066 1067 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 1068 &max98088_right_ADC_mixer_controls[0], 1069 ARRAY_SIZE(max98088_right_ADC_mixer_controls)), 1070 1071 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1, 1072 5, 0, NULL, 0, max98088_mic_event, 1073 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1074 1075 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2, 1076 5, 0, NULL, 0, max98088_mic_event, 1077 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1078 1079 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN, 1080 7, 0, NULL, 0, max98088_pga_ina1_event, 1081 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1082 1083 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN, 1084 7, 0, NULL, 0, max98088_pga_ina2_event, 1085 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1086 1087 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN, 1088 6, 0, NULL, 0, max98088_pga_inb1_event, 1089 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1090 1091 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN, 1092 6, 0, NULL, 0, max98088_pga_inb2_event, 1093 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 1094 1095 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0), 1096 1097 SND_SOC_DAPM_MUX("EX Limiter Mode", SND_SOC_NOPM, 0, 0, 1098 &max98088_exmode_controls), 1099 1100 SND_SOC_DAPM_OUTPUT("HPL"), 1101 SND_SOC_DAPM_OUTPUT("HPR"), 1102 SND_SOC_DAPM_OUTPUT("SPKL"), 1103 SND_SOC_DAPM_OUTPUT("SPKR"), 1104 SND_SOC_DAPM_OUTPUT("RECL"), 1105 SND_SOC_DAPM_OUTPUT("RECR"), 1106 1107 SND_SOC_DAPM_INPUT("MIC1"), 1108 SND_SOC_DAPM_INPUT("MIC2"), 1109 SND_SOC_DAPM_INPUT("INA1"), 1110 SND_SOC_DAPM_INPUT("INA2"), 1111 SND_SOC_DAPM_INPUT("INB1"), 1112 SND_SOC_DAPM_INPUT("INB2"), 1113 }; 1114 1115 static const struct snd_soc_dapm_route audio_map[] = { 1116 /* Left headphone output mixer */ 1117 {"Left HP Mixer", "Left DAC1 Switch", "DACL1"}, 1118 {"Left HP Mixer", "Left DAC2 Switch", "DACL2"}, 1119 {"Left HP Mixer", "Right DAC1 Switch", "DACR1"}, 1120 {"Left HP Mixer", "Right DAC2 Switch", "DACR2"}, 1121 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"}, 1122 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"}, 1123 {"Left HP Mixer", "INA1 Switch", "INA1 Input"}, 1124 {"Left HP Mixer", "INA2 Switch", "INA2 Input"}, 1125 {"Left HP Mixer", "INB1 Switch", "INB1 Input"}, 1126 {"Left HP Mixer", "INB2 Switch", "INB2 Input"}, 1127 1128 /* Right headphone output mixer */ 1129 {"Right HP Mixer", "Left DAC1 Switch", "DACL1"}, 1130 {"Right HP Mixer", "Left DAC2 Switch", "DACL2" }, 1131 {"Right HP Mixer", "Right DAC1 Switch", "DACR1"}, 1132 {"Right HP Mixer", "Right DAC2 Switch", "DACR2"}, 1133 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"}, 1134 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"}, 1135 {"Right HP Mixer", "INA1 Switch", "INA1 Input"}, 1136 {"Right HP Mixer", "INA2 Switch", "INA2 Input"}, 1137 {"Right HP Mixer", "INB1 Switch", "INB1 Input"}, 1138 {"Right HP Mixer", "INB2 Switch", "INB2 Input"}, 1139 1140 /* Left speaker output mixer */ 1141 {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"}, 1142 {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"}, 1143 {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"}, 1144 {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"}, 1145 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"}, 1146 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"}, 1147 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"}, 1148 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"}, 1149 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"}, 1150 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"}, 1151 1152 /* Right speaker output mixer */ 1153 {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"}, 1154 {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"}, 1155 {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"}, 1156 {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"}, 1157 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"}, 1158 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"}, 1159 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"}, 1160 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"}, 1161 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"}, 1162 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"}, 1163 1164 /* Earpiece/Receiver output mixer */ 1165 {"Left REC Mixer", "Left DAC1 Switch", "DACL1"}, 1166 {"Left REC Mixer", "Left DAC2 Switch", "DACL2"}, 1167 {"Left REC Mixer", "Right DAC1 Switch", "DACR1"}, 1168 {"Left REC Mixer", "Right DAC2 Switch", "DACR2"}, 1169 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"}, 1170 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"}, 1171 {"Left REC Mixer", "INA1 Switch", "INA1 Input"}, 1172 {"Left REC Mixer", "INA2 Switch", "INA2 Input"}, 1173 {"Left REC Mixer", "INB1 Switch", "INB1 Input"}, 1174 {"Left REC Mixer", "INB2 Switch", "INB2 Input"}, 1175 1176 /* Earpiece/Receiver output mixer */ 1177 {"Right REC Mixer", "Left DAC1 Switch", "DACL1"}, 1178 {"Right REC Mixer", "Left DAC2 Switch", "DACL2"}, 1179 {"Right REC Mixer", "Right DAC1 Switch", "DACR1"}, 1180 {"Right REC Mixer", "Right DAC2 Switch", "DACR2"}, 1181 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"}, 1182 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"}, 1183 {"Right REC Mixer", "INA1 Switch", "INA1 Input"}, 1184 {"Right REC Mixer", "INA2 Switch", "INA2 Input"}, 1185 {"Right REC Mixer", "INB1 Switch", "INB1 Input"}, 1186 {"Right REC Mixer", "INB2 Switch", "INB2 Input"}, 1187 1188 {"HP Left Out", NULL, "Left HP Mixer"}, 1189 {"HP Right Out", NULL, "Right HP Mixer"}, 1190 {"SPK Left Out", NULL, "Left SPK Mixer"}, 1191 {"SPK Right Out", NULL, "Right SPK Mixer"}, 1192 {"REC Left Out", NULL, "Left REC Mixer"}, 1193 {"REC Right Out", NULL, "Right REC Mixer"}, 1194 1195 {"HPL", NULL, "HP Left Out"}, 1196 {"HPR", NULL, "HP Right Out"}, 1197 {"SPKL", NULL, "SPK Left Out"}, 1198 {"SPKR", NULL, "SPK Right Out"}, 1199 {"RECL", NULL, "REC Left Out"}, 1200 {"RECR", NULL, "REC Right Out"}, 1201 1202 /* Left ADC input mixer */ 1203 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1204 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1205 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"}, 1206 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"}, 1207 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"}, 1208 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"}, 1209 1210 /* Right ADC input mixer */ 1211 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 1212 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 1213 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"}, 1214 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"}, 1215 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"}, 1216 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"}, 1217 1218 /* Inputs */ 1219 {"ADCL", NULL, "Left ADC Mixer"}, 1220 {"ADCR", NULL, "Right ADC Mixer"}, 1221 {"INA1 Input", NULL, "INA1"}, 1222 {"INA2 Input", NULL, "INA2"}, 1223 {"INB1 Input", NULL, "INB1"}, 1224 {"INB2 Input", NULL, "INB2"}, 1225 {"MIC1 Input", NULL, "MIC1"}, 1226 {"MIC2 Input", NULL, "MIC2"}, 1227 }; 1228 1229 static int max98088_add_widgets(struct snd_soc_codec *codec) 1230 { 1231 struct snd_soc_dapm_context *dapm = &codec->dapm; 1232 1233 snd_soc_dapm_new_controls(dapm, max98088_dapm_widgets, 1234 ARRAY_SIZE(max98088_dapm_widgets)); 1235 1236 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map)); 1237 1238 snd_soc_add_controls(codec, max98088_snd_controls, 1239 ARRAY_SIZE(max98088_snd_controls)); 1240 1241 snd_soc_dapm_new_widgets(dapm); 1242 return 0; 1243 } 1244 1245 /* codec mclk clock divider coefficients */ 1246 static const struct { 1247 u32 rate; 1248 u8 sr; 1249 } rate_table[] = { 1250 {8000, 0x10}, 1251 {11025, 0x20}, 1252 {16000, 0x30}, 1253 {22050, 0x40}, 1254 {24000, 0x50}, 1255 {32000, 0x60}, 1256 {44100, 0x70}, 1257 {48000, 0x80}, 1258 {88200, 0x90}, 1259 {96000, 0xA0}, 1260 }; 1261 1262 static inline int rate_value(int rate, u8 *value) 1263 { 1264 int i; 1265 1266 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 1267 if (rate_table[i].rate >= rate) { 1268 *value = rate_table[i].sr; 1269 return 0; 1270 } 1271 } 1272 *value = rate_table[0].sr; 1273 return -EINVAL; 1274 } 1275 1276 static int max98088_dai1_hw_params(struct snd_pcm_substream *substream, 1277 struct snd_pcm_hw_params *params, 1278 struct snd_soc_dai *dai) 1279 { 1280 struct snd_soc_codec *codec = dai->codec; 1281 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1282 struct max98088_cdata *cdata; 1283 unsigned long long ni; 1284 unsigned int rate; 1285 u8 regval; 1286 1287 cdata = &max98088->dai[0]; 1288 1289 rate = params_rate(params); 1290 1291 switch (params_format(params)) { 1292 case SNDRV_PCM_FORMAT_S16_LE: 1293 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, 1294 M98088_DAI_WS, 0); 1295 break; 1296 case SNDRV_PCM_FORMAT_S24_LE: 1297 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, 1298 M98088_DAI_WS, M98088_DAI_WS); 1299 break; 1300 default: 1301 return -EINVAL; 1302 } 1303 1304 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); 1305 1306 if (rate_value(rate, ®val)) 1307 return -EINVAL; 1308 1309 snd_soc_update_bits(codec, M98088_REG_11_DAI1_CLKMODE, 1310 M98088_CLKMODE_MASK, regval); 1311 cdata->rate = rate; 1312 1313 /* Configure NI when operating as master */ 1314 if (snd_soc_read(codec, M98088_REG_14_DAI1_FORMAT) 1315 & M98088_DAI_MAS) { 1316 if (max98088->sysclk == 0) { 1317 dev_err(codec->dev, "Invalid system clock frequency\n"); 1318 return -EINVAL; 1319 } 1320 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1321 * (unsigned long long int)rate; 1322 do_div(ni, (unsigned long long int)max98088->sysclk); 1323 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI, 1324 (ni >> 8) & 0x7F); 1325 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO, 1326 ni & 0xFF); 1327 } 1328 1329 /* Update sample rate mode */ 1330 if (rate < 50000) 1331 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS, 1332 M98088_DAI_DHF, 0); 1333 else 1334 snd_soc_update_bits(codec, M98088_REG_18_DAI1_FILTERS, 1335 M98088_DAI_DHF, M98088_DAI_DHF); 1336 1337 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 1338 M98088_SHDNRUN); 1339 1340 return 0; 1341 } 1342 1343 static int max98088_dai2_hw_params(struct snd_pcm_substream *substream, 1344 struct snd_pcm_hw_params *params, 1345 struct snd_soc_dai *dai) 1346 { 1347 struct snd_soc_codec *codec = dai->codec; 1348 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1349 struct max98088_cdata *cdata; 1350 unsigned long long ni; 1351 unsigned int rate; 1352 u8 regval; 1353 1354 cdata = &max98088->dai[1]; 1355 1356 rate = params_rate(params); 1357 1358 switch (params_format(params)) { 1359 case SNDRV_PCM_FORMAT_S16_LE: 1360 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, 1361 M98088_DAI_WS, 0); 1362 break; 1363 case SNDRV_PCM_FORMAT_S24_LE: 1364 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, 1365 M98088_DAI_WS, M98088_DAI_WS); 1366 break; 1367 default: 1368 return -EINVAL; 1369 } 1370 1371 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); 1372 1373 if (rate_value(rate, ®val)) 1374 return -EINVAL; 1375 1376 snd_soc_update_bits(codec, M98088_REG_19_DAI2_CLKMODE, 1377 M98088_CLKMODE_MASK, regval); 1378 cdata->rate = rate; 1379 1380 /* Configure NI when operating as master */ 1381 if (snd_soc_read(codec, M98088_REG_1C_DAI2_FORMAT) 1382 & M98088_DAI_MAS) { 1383 if (max98088->sysclk == 0) { 1384 dev_err(codec->dev, "Invalid system clock frequency\n"); 1385 return -EINVAL; 1386 } 1387 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1388 * (unsigned long long int)rate; 1389 do_div(ni, (unsigned long long int)max98088->sysclk); 1390 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI, 1391 (ni >> 8) & 0x7F); 1392 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO, 1393 ni & 0xFF); 1394 } 1395 1396 /* Update sample rate mode */ 1397 if (rate < 50000) 1398 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS, 1399 M98088_DAI_DHF, 0); 1400 else 1401 snd_soc_update_bits(codec, M98088_REG_20_DAI2_FILTERS, 1402 M98088_DAI_DHF, M98088_DAI_DHF); 1403 1404 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 1405 M98088_SHDNRUN); 1406 1407 return 0; 1408 } 1409 1410 static int max98088_dai_set_sysclk(struct snd_soc_dai *dai, 1411 int clk_id, unsigned int freq, int dir) 1412 { 1413 struct snd_soc_codec *codec = dai->codec; 1414 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1415 1416 /* Requested clock frequency is already setup */ 1417 if (freq == max98088->sysclk) 1418 return 0; 1419 1420 max98088->sysclk = freq; /* remember current sysclk */ 1421 1422 /* Setup clocks for slave mode, and using the PLL 1423 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1424 * 0x02 (when master clk is 20MHz to 30MHz).. 1425 */ 1426 if ((freq >= 10000000) && (freq < 20000000)) { 1427 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x10); 1428 } else if ((freq >= 20000000) && (freq < 30000000)) { 1429 snd_soc_write(codec, M98088_REG_10_SYS_CLK, 0x20); 1430 } else { 1431 dev_err(codec->dev, "Invalid master clock frequency\n"); 1432 return -EINVAL; 1433 } 1434 1435 if (snd_soc_read(codec, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) { 1436 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, 1437 M98088_SHDNRUN, 0); 1438 snd_soc_update_bits(codec, M98088_REG_51_PWR_SYS, 1439 M98088_SHDNRUN, M98088_SHDNRUN); 1440 } 1441 1442 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1443 1444 max98088->sysclk = freq; 1445 return 0; 1446 } 1447 1448 static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai, 1449 unsigned int fmt) 1450 { 1451 struct snd_soc_codec *codec = codec_dai->codec; 1452 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1453 struct max98088_cdata *cdata; 1454 u8 reg15val; 1455 u8 reg14val = 0; 1456 1457 cdata = &max98088->dai[0]; 1458 1459 if (fmt != cdata->fmt) { 1460 cdata->fmt = fmt; 1461 1462 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1463 case SND_SOC_DAIFMT_CBS_CFS: 1464 /* Slave mode PLL */ 1465 snd_soc_write(codec, M98088_REG_12_DAI1_CLKCFG_HI, 1466 0x80); 1467 snd_soc_write(codec, M98088_REG_13_DAI1_CLKCFG_LO, 1468 0x00); 1469 break; 1470 case SND_SOC_DAIFMT_CBM_CFM: 1471 /* Set to master mode */ 1472 reg14val |= M98088_DAI_MAS; 1473 break; 1474 case SND_SOC_DAIFMT_CBS_CFM: 1475 case SND_SOC_DAIFMT_CBM_CFS: 1476 default: 1477 dev_err(codec->dev, "Clock mode unsupported"); 1478 return -EINVAL; 1479 } 1480 1481 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1482 case SND_SOC_DAIFMT_I2S: 1483 reg14val |= M98088_DAI_DLY; 1484 break; 1485 case SND_SOC_DAIFMT_LEFT_J: 1486 break; 1487 default: 1488 return -EINVAL; 1489 } 1490 1491 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1492 case SND_SOC_DAIFMT_NB_NF: 1493 break; 1494 case SND_SOC_DAIFMT_NB_IF: 1495 reg14val |= M98088_DAI_WCI; 1496 break; 1497 case SND_SOC_DAIFMT_IB_NF: 1498 reg14val |= M98088_DAI_BCI; 1499 break; 1500 case SND_SOC_DAIFMT_IB_IF: 1501 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI; 1502 break; 1503 default: 1504 return -EINVAL; 1505 } 1506 1507 snd_soc_update_bits(codec, M98088_REG_14_DAI1_FORMAT, 1508 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | 1509 M98088_DAI_WCI, reg14val); 1510 1511 reg15val = M98088_DAI_BSEL64; 1512 if (max98088->digmic) 1513 reg15val |= M98088_DAI_OSR64; 1514 snd_soc_write(codec, M98088_REG_15_DAI1_CLOCK, reg15val); 1515 } 1516 1517 return 0; 1518 } 1519 1520 static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai, 1521 unsigned int fmt) 1522 { 1523 struct snd_soc_codec *codec = codec_dai->codec; 1524 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1525 struct max98088_cdata *cdata; 1526 u8 reg1Cval = 0; 1527 1528 cdata = &max98088->dai[1]; 1529 1530 if (fmt != cdata->fmt) { 1531 cdata->fmt = fmt; 1532 1533 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1534 case SND_SOC_DAIFMT_CBS_CFS: 1535 /* Slave mode PLL */ 1536 snd_soc_write(codec, M98088_REG_1A_DAI2_CLKCFG_HI, 1537 0x80); 1538 snd_soc_write(codec, M98088_REG_1B_DAI2_CLKCFG_LO, 1539 0x00); 1540 break; 1541 case SND_SOC_DAIFMT_CBM_CFM: 1542 /* Set to master mode */ 1543 reg1Cval |= M98088_DAI_MAS; 1544 break; 1545 case SND_SOC_DAIFMT_CBS_CFM: 1546 case SND_SOC_DAIFMT_CBM_CFS: 1547 default: 1548 dev_err(codec->dev, "Clock mode unsupported"); 1549 return -EINVAL; 1550 } 1551 1552 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1553 case SND_SOC_DAIFMT_I2S: 1554 reg1Cval |= M98088_DAI_DLY; 1555 break; 1556 case SND_SOC_DAIFMT_LEFT_J: 1557 break; 1558 default: 1559 return -EINVAL; 1560 } 1561 1562 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1563 case SND_SOC_DAIFMT_NB_NF: 1564 break; 1565 case SND_SOC_DAIFMT_NB_IF: 1566 reg1Cval |= M98088_DAI_WCI; 1567 break; 1568 case SND_SOC_DAIFMT_IB_NF: 1569 reg1Cval |= M98088_DAI_BCI; 1570 break; 1571 case SND_SOC_DAIFMT_IB_IF: 1572 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI; 1573 break; 1574 default: 1575 return -EINVAL; 1576 } 1577 1578 snd_soc_update_bits(codec, M98088_REG_1C_DAI2_FORMAT, 1579 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | 1580 M98088_DAI_WCI, reg1Cval); 1581 1582 snd_soc_write(codec, M98088_REG_1D_DAI2_CLOCK, 1583 M98088_DAI_BSEL64); 1584 } 1585 1586 return 0; 1587 } 1588 1589 static void max98088_sync_cache(struct snd_soc_codec *codec) 1590 { 1591 u16 *reg_cache = codec->reg_cache; 1592 int i; 1593 1594 if (!codec->cache_sync) 1595 return; 1596 1597 codec->cache_only = 0; 1598 1599 /* write back cached values if they're writeable and 1600 * different from the hardware default. 1601 */ 1602 for (i = 1; i < codec->driver->reg_cache_size; i++) { 1603 if (!max98088_access[i].writable) 1604 continue; 1605 1606 if (reg_cache[i] == max98088_reg[i]) 1607 continue; 1608 1609 snd_soc_write(codec, i, reg_cache[i]); 1610 } 1611 1612 codec->cache_sync = 0; 1613 } 1614 1615 static int max98088_set_bias_level(struct snd_soc_codec *codec, 1616 enum snd_soc_bias_level level) 1617 { 1618 switch (level) { 1619 case SND_SOC_BIAS_ON: 1620 break; 1621 1622 case SND_SOC_BIAS_PREPARE: 1623 break; 1624 1625 case SND_SOC_BIAS_STANDBY: 1626 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) 1627 max98088_sync_cache(codec); 1628 1629 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN, 1630 M98088_MBEN, M98088_MBEN); 1631 break; 1632 1633 case SND_SOC_BIAS_OFF: 1634 snd_soc_update_bits(codec, M98088_REG_4C_PWR_EN_IN, 1635 M98088_MBEN, 0); 1636 codec->cache_sync = 1; 1637 break; 1638 } 1639 codec->dapm.bias_level = level; 1640 return 0; 1641 } 1642 1643 #define MAX98088_RATES SNDRV_PCM_RATE_8000_96000 1644 #define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 1645 1646 static struct snd_soc_dai_ops max98088_dai1_ops = { 1647 .set_sysclk = max98088_dai_set_sysclk, 1648 .set_fmt = max98088_dai1_set_fmt, 1649 .hw_params = max98088_dai1_hw_params, 1650 }; 1651 1652 static struct snd_soc_dai_ops max98088_dai2_ops = { 1653 .set_sysclk = max98088_dai_set_sysclk, 1654 .set_fmt = max98088_dai2_set_fmt, 1655 .hw_params = max98088_dai2_hw_params, 1656 }; 1657 1658 static struct snd_soc_dai_driver max98088_dai[] = { 1659 { 1660 .name = "HiFi", 1661 .playback = { 1662 .stream_name = "HiFi Playback", 1663 .channels_min = 1, 1664 .channels_max = 2, 1665 .rates = MAX98088_RATES, 1666 .formats = MAX98088_FORMATS, 1667 }, 1668 .capture = { 1669 .stream_name = "HiFi Capture", 1670 .channels_min = 1, 1671 .channels_max = 2, 1672 .rates = MAX98088_RATES, 1673 .formats = MAX98088_FORMATS, 1674 }, 1675 .ops = &max98088_dai1_ops, 1676 }, 1677 { 1678 .name = "Aux", 1679 .playback = { 1680 .stream_name = "Aux Playback", 1681 .channels_min = 1, 1682 .channels_max = 2, 1683 .rates = MAX98088_RATES, 1684 .formats = MAX98088_FORMATS, 1685 }, 1686 .ops = &max98088_dai2_ops, 1687 } 1688 }; 1689 1690 static int max98088_get_channel(const char *name) 1691 { 1692 if (strcmp(name, "EQ1 Mode") == 0) 1693 return 0; 1694 if (strcmp(name, "EQ2 Mode") == 0) 1695 return 1; 1696 return -EINVAL; 1697 } 1698 1699 static void max98088_setup_eq1(struct snd_soc_codec *codec) 1700 { 1701 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1702 struct max98088_pdata *pdata = max98088->pdata; 1703 struct max98088_eq_cfg *coef_set; 1704 int best, best_val, save, i, sel, fs; 1705 struct max98088_cdata *cdata; 1706 1707 cdata = &max98088->dai[0]; 1708 1709 if (!pdata || !max98088->eq_textcnt) 1710 return; 1711 1712 /* Find the selected configuration with nearest sample rate */ 1713 fs = cdata->rate; 1714 sel = cdata->eq_sel; 1715 1716 best = 0; 1717 best_val = INT_MAX; 1718 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1719 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 && 1720 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1721 best = i; 1722 best_val = abs(pdata->eq_cfg[i].rate - fs); 1723 } 1724 } 1725 1726 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 1727 pdata->eq_cfg[best].name, 1728 pdata->eq_cfg[best].rate, fs); 1729 1730 /* Disable EQ while configuring, and save current on/off state */ 1731 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL); 1732 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0); 1733 1734 coef_set = &pdata->eq_cfg[sel]; 1735 1736 m98088_eq_band(codec, 0, 0, coef_set->band1); 1737 m98088_eq_band(codec, 0, 1, coef_set->band2); 1738 m98088_eq_band(codec, 0, 2, coef_set->band3); 1739 m98088_eq_band(codec, 0, 3, coef_set->band4); 1740 m98088_eq_band(codec, 0, 4, coef_set->band5); 1741 1742 /* Restore the original on/off state */ 1743 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save); 1744 } 1745 1746 static void max98088_setup_eq2(struct snd_soc_codec *codec) 1747 { 1748 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1749 struct max98088_pdata *pdata = max98088->pdata; 1750 struct max98088_eq_cfg *coef_set; 1751 int best, best_val, save, i, sel, fs; 1752 struct max98088_cdata *cdata; 1753 1754 cdata = &max98088->dai[1]; 1755 1756 if (!pdata || !max98088->eq_textcnt) 1757 return; 1758 1759 /* Find the selected configuration with nearest sample rate */ 1760 fs = cdata->rate; 1761 1762 sel = cdata->eq_sel; 1763 best = 0; 1764 best_val = INT_MAX; 1765 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1766 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 && 1767 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1768 best = i; 1769 best_val = abs(pdata->eq_cfg[i].rate - fs); 1770 } 1771 } 1772 1773 dev_dbg(codec->dev, "Selected %s/%dHz for %dHz sample rate\n", 1774 pdata->eq_cfg[best].name, 1775 pdata->eq_cfg[best].rate, fs); 1776 1777 /* Disable EQ while configuring, and save current on/off state */ 1778 save = snd_soc_read(codec, M98088_REG_49_CFG_LEVEL); 1779 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0); 1780 1781 coef_set = &pdata->eq_cfg[sel]; 1782 1783 m98088_eq_band(codec, 1, 0, coef_set->band1); 1784 m98088_eq_band(codec, 1, 1, coef_set->band2); 1785 m98088_eq_band(codec, 1, 2, coef_set->band3); 1786 m98088_eq_band(codec, 1, 3, coef_set->band4); 1787 m98088_eq_band(codec, 1, 4, coef_set->band5); 1788 1789 /* Restore the original on/off state */ 1790 snd_soc_update_bits(codec, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 1791 save); 1792 } 1793 1794 static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol, 1795 struct snd_ctl_elem_value *ucontrol) 1796 { 1797 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1798 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1799 struct max98088_pdata *pdata = max98088->pdata; 1800 int channel = max98088_get_channel(kcontrol->id.name); 1801 struct max98088_cdata *cdata; 1802 int sel = ucontrol->value.integer.value[0]; 1803 1804 cdata = &max98088->dai[channel]; 1805 1806 if (sel >= pdata->eq_cfgcnt) 1807 return -EINVAL; 1808 1809 cdata->eq_sel = sel; 1810 1811 switch (channel) { 1812 case 0: 1813 max98088_setup_eq1(codec); 1814 break; 1815 case 1: 1816 max98088_setup_eq2(codec); 1817 break; 1818 } 1819 1820 return 0; 1821 } 1822 1823 static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol, 1824 struct snd_ctl_elem_value *ucontrol) 1825 { 1826 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 1827 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1828 int channel = max98088_get_channel(kcontrol->id.name); 1829 struct max98088_cdata *cdata; 1830 1831 cdata = &max98088->dai[channel]; 1832 ucontrol->value.enumerated.item[0] = cdata->eq_sel; 1833 return 0; 1834 } 1835 1836 static void max98088_handle_eq_pdata(struct snd_soc_codec *codec) 1837 { 1838 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1839 struct max98088_pdata *pdata = max98088->pdata; 1840 struct max98088_eq_cfg *cfg; 1841 unsigned int cfgcnt; 1842 int i, j; 1843 const char **t; 1844 int ret; 1845 1846 struct snd_kcontrol_new controls[] = { 1847 SOC_ENUM_EXT("EQ1 Mode", 1848 max98088->eq_enum, 1849 max98088_get_eq_enum, 1850 max98088_put_eq_enum), 1851 SOC_ENUM_EXT("EQ2 Mode", 1852 max98088->eq_enum, 1853 max98088_get_eq_enum, 1854 max98088_put_eq_enum), 1855 }; 1856 1857 cfg = pdata->eq_cfg; 1858 cfgcnt = pdata->eq_cfgcnt; 1859 1860 /* Setup an array of texts for the equalizer enum. 1861 * This is based on Mark Brown's equalizer driver code. 1862 */ 1863 max98088->eq_textcnt = 0; 1864 max98088->eq_texts = NULL; 1865 for (i = 0; i < cfgcnt; i++) { 1866 for (j = 0; j < max98088->eq_textcnt; j++) { 1867 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0) 1868 break; 1869 } 1870 1871 if (j != max98088->eq_textcnt) 1872 continue; 1873 1874 /* Expand the array */ 1875 t = krealloc(max98088->eq_texts, 1876 sizeof(char *) * (max98088->eq_textcnt + 1), 1877 GFP_KERNEL); 1878 if (t == NULL) 1879 continue; 1880 1881 /* Store the new entry */ 1882 t[max98088->eq_textcnt] = cfg[i].name; 1883 max98088->eq_textcnt++; 1884 max98088->eq_texts = t; 1885 } 1886 1887 /* Now point the soc_enum to .texts array items */ 1888 max98088->eq_enum.texts = max98088->eq_texts; 1889 max98088->eq_enum.max = max98088->eq_textcnt; 1890 1891 ret = snd_soc_add_controls(codec, controls, ARRAY_SIZE(controls)); 1892 if (ret != 0) 1893 dev_err(codec->dev, "Failed to add EQ control: %d\n", ret); 1894 } 1895 1896 static void max98088_handle_pdata(struct snd_soc_codec *codec) 1897 { 1898 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1899 struct max98088_pdata *pdata = max98088->pdata; 1900 u8 regval = 0; 1901 1902 if (!pdata) { 1903 dev_dbg(codec->dev, "No platform data\n"); 1904 return; 1905 } 1906 1907 /* Configure mic for analog/digital mic mode */ 1908 if (pdata->digmic_left_mode) 1909 regval |= M98088_DIGMIC_L; 1910 1911 if (pdata->digmic_right_mode) 1912 regval |= M98088_DIGMIC_R; 1913 1914 max98088->digmic = (regval ? 1 : 0); 1915 1916 snd_soc_write(codec, M98088_REG_48_CFG_MIC, regval); 1917 1918 /* Configure receiver output */ 1919 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0); 1920 snd_soc_update_bits(codec, M98088_REG_2A_MIC_REC_CNTL, 1921 M98088_REC_LINEMODE_MASK, regval); 1922 1923 /* Configure equalizers */ 1924 if (pdata->eq_cfgcnt) 1925 max98088_handle_eq_pdata(codec); 1926 } 1927 1928 #ifdef CONFIG_PM 1929 static int max98088_suspend(struct snd_soc_codec *codec, pm_message_t state) 1930 { 1931 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF); 1932 1933 return 0; 1934 } 1935 1936 static int max98088_resume(struct snd_soc_codec *codec) 1937 { 1938 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1939 1940 return 0; 1941 } 1942 #else 1943 #define max98088_suspend NULL 1944 #define max98088_resume NULL 1945 #endif 1946 1947 static int max98088_probe(struct snd_soc_codec *codec) 1948 { 1949 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 1950 struct max98088_cdata *cdata; 1951 int ret = 0; 1952 1953 codec->cache_sync = 1; 1954 1955 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C); 1956 if (ret != 0) { 1957 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1958 return ret; 1959 } 1960 1961 /* initialize private data */ 1962 1963 max98088->sysclk = (unsigned)-1; 1964 max98088->eq_textcnt = 0; 1965 1966 cdata = &max98088->dai[0]; 1967 cdata->rate = (unsigned)-1; 1968 cdata->fmt = (unsigned)-1; 1969 cdata->eq_sel = 0; 1970 1971 cdata = &max98088->dai[1]; 1972 cdata->rate = (unsigned)-1; 1973 cdata->fmt = (unsigned)-1; 1974 cdata->eq_sel = 0; 1975 1976 max98088->ina_state = 0; 1977 max98088->inb_state = 0; 1978 max98088->ex_mode = 0; 1979 max98088->digmic = 0; 1980 max98088->mic1pre = 0; 1981 max98088->mic2pre = 0; 1982 1983 ret = snd_soc_read(codec, M98088_REG_FF_REV_ID); 1984 if (ret < 0) { 1985 dev_err(codec->dev, "Failed to read device revision: %d\n", 1986 ret); 1987 goto err_access; 1988 } 1989 dev_info(codec->dev, "revision %c\n", ret + 'A'); 1990 1991 snd_soc_write(codec, M98088_REG_51_PWR_SYS, M98088_PWRSV); 1992 1993 /* initialize registers cache to hardware default */ 1994 max98088_set_bias_level(codec, SND_SOC_BIAS_STANDBY); 1995 1996 snd_soc_write(codec, M98088_REG_0F_IRQ_ENABLE, 0x00); 1997 1998 snd_soc_write(codec, M98088_REG_22_MIX_DAC, 1999 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL| 2000 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR); 2001 2002 snd_soc_write(codec, M98088_REG_4E_BIAS_CNTL, 0xF0); 2003 snd_soc_write(codec, M98088_REG_50_DAC_BIAS2, 0x0F); 2004 2005 snd_soc_write(codec, M98088_REG_16_DAI1_IOCFG, 2006 M98088_S1NORMAL|M98088_SDATA); 2007 2008 snd_soc_write(codec, M98088_REG_1E_DAI2_IOCFG, 2009 M98088_S2NORMAL|M98088_SDATA); 2010 2011 max98088_handle_pdata(codec); 2012 2013 max98088_add_widgets(codec); 2014 2015 err_access: 2016 return ret; 2017 } 2018 2019 static int max98088_remove(struct snd_soc_codec *codec) 2020 { 2021 struct max98088_priv *max98088 = snd_soc_codec_get_drvdata(codec); 2022 2023 max98088_set_bias_level(codec, SND_SOC_BIAS_OFF); 2024 kfree(max98088->eq_texts); 2025 2026 return 0; 2027 } 2028 2029 static struct snd_soc_codec_driver soc_codec_dev_max98088 = { 2030 .probe = max98088_probe, 2031 .remove = max98088_remove, 2032 .suspend = max98088_suspend, 2033 .resume = max98088_resume, 2034 .set_bias_level = max98088_set_bias_level, 2035 .reg_cache_size = ARRAY_SIZE(max98088_reg), 2036 .reg_word_size = sizeof(u8), 2037 .reg_cache_default = max98088_reg, 2038 .volatile_register = max98088_volatile_register, 2039 }; 2040 2041 static int max98088_i2c_probe(struct i2c_client *i2c, 2042 const struct i2c_device_id *id) 2043 { 2044 struct max98088_priv *max98088; 2045 int ret; 2046 2047 max98088 = kzalloc(sizeof(struct max98088_priv), GFP_KERNEL); 2048 if (max98088 == NULL) 2049 return -ENOMEM; 2050 2051 max98088->devtype = id->driver_data; 2052 2053 i2c_set_clientdata(i2c, max98088); 2054 max98088->control_data = i2c; 2055 max98088->pdata = i2c->dev.platform_data; 2056 2057 ret = snd_soc_register_codec(&i2c->dev, 2058 &soc_codec_dev_max98088, &max98088_dai[0], 2); 2059 if (ret < 0) 2060 kfree(max98088); 2061 return ret; 2062 } 2063 2064 static int __devexit max98088_i2c_remove(struct i2c_client *client) 2065 { 2066 snd_soc_unregister_codec(&client->dev); 2067 kfree(i2c_get_clientdata(client)); 2068 return 0; 2069 } 2070 2071 static const struct i2c_device_id max98088_i2c_id[] = { 2072 { "max98088", MAX98088 }, 2073 { "max98089", MAX98089 }, 2074 { } 2075 }; 2076 MODULE_DEVICE_TABLE(i2c, max98088_i2c_id); 2077 2078 static struct i2c_driver max98088_i2c_driver = { 2079 .driver = { 2080 .name = "max98088", 2081 .owner = THIS_MODULE, 2082 }, 2083 .probe = max98088_i2c_probe, 2084 .remove = __devexit_p(max98088_i2c_remove), 2085 .id_table = max98088_i2c_id, 2086 }; 2087 2088 static int __init max98088_init(void) 2089 { 2090 int ret; 2091 2092 ret = i2c_add_driver(&max98088_i2c_driver); 2093 if (ret) 2094 pr_err("Failed to register max98088 I2C driver: %d\n", ret); 2095 2096 return ret; 2097 } 2098 module_init(max98088_init); 2099 2100 static void __exit max98088_exit(void) 2101 { 2102 i2c_del_driver(&max98088_i2c_driver); 2103 } 2104 module_exit(max98088_exit); 2105 2106 MODULE_DESCRIPTION("ALSA SoC MAX98088 driver"); 2107 MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin"); 2108 MODULE_LICENSE("GPL"); 2109