1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * max98088.c -- MAX98088 ALSA SoC Audio driver 4 * 5 * Copyright 2010 Maxim Integrated Products 6 */ 7 8 #include <linux/module.h> 9 #include <linux/moduleparam.h> 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/delay.h> 13 #include <linux/pm.h> 14 #include <linux/i2c.h> 15 #include <linux/regmap.h> 16 #include <linux/clk.h> 17 #include <sound/core.h> 18 #include <sound/pcm.h> 19 #include <sound/pcm_params.h> 20 #include <sound/soc.h> 21 #include <sound/initval.h> 22 #include <sound/tlv.h> 23 #include <linux/slab.h> 24 #include <asm/div64.h> 25 #include <sound/max98088.h> 26 #include "max98088.h" 27 28 enum max98088_type { 29 MAX98088, 30 MAX98089, 31 }; 32 33 struct max98088_cdata { 34 unsigned int rate; 35 unsigned int fmt; 36 int eq_sel; 37 }; 38 39 struct max98088_priv { 40 struct regmap *regmap; 41 enum max98088_type devtype; 42 struct max98088_pdata *pdata; 43 struct clk *mclk; 44 unsigned char mclk_prescaler; 45 unsigned int sysclk; 46 struct max98088_cdata dai[2]; 47 int eq_textcnt; 48 const char **eq_texts; 49 struct soc_enum eq_enum; 50 u8 ina_state; 51 u8 inb_state; 52 unsigned int ex_mode; 53 unsigned int digmic; 54 unsigned int mic1pre; 55 unsigned int mic2pre; 56 unsigned int extmic_mode; 57 }; 58 59 static const struct reg_default max98088_reg[] = { 60 { 0xf, 0x00 }, /* 0F interrupt enable */ 61 62 { 0x10, 0x00 }, /* 10 master clock */ 63 { 0x11, 0x00 }, /* 11 DAI1 clock mode */ 64 { 0x12, 0x00 }, /* 12 DAI1 clock control */ 65 { 0x13, 0x00 }, /* 13 DAI1 clock control */ 66 { 0x14, 0x00 }, /* 14 DAI1 format */ 67 { 0x15, 0x00 }, /* 15 DAI1 clock */ 68 { 0x16, 0x00 }, /* 16 DAI1 config */ 69 { 0x17, 0x00 }, /* 17 DAI1 TDM */ 70 { 0x18, 0x00 }, /* 18 DAI1 filters */ 71 { 0x19, 0x00 }, /* 19 DAI2 clock mode */ 72 { 0x1a, 0x00 }, /* 1A DAI2 clock control */ 73 { 0x1b, 0x00 }, /* 1B DAI2 clock control */ 74 { 0x1c, 0x00 }, /* 1C DAI2 format */ 75 { 0x1d, 0x00 }, /* 1D DAI2 clock */ 76 { 0x1e, 0x00 }, /* 1E DAI2 config */ 77 { 0x1f, 0x00 }, /* 1F DAI2 TDM */ 78 79 { 0x20, 0x00 }, /* 20 DAI2 filters */ 80 { 0x21, 0x00 }, /* 21 data config */ 81 { 0x22, 0x00 }, /* 22 DAC mixer */ 82 { 0x23, 0x00 }, /* 23 left ADC mixer */ 83 { 0x24, 0x00 }, /* 24 right ADC mixer */ 84 { 0x25, 0x00 }, /* 25 left HP mixer */ 85 { 0x26, 0x00 }, /* 26 right HP mixer */ 86 { 0x27, 0x00 }, /* 27 HP control */ 87 { 0x28, 0x00 }, /* 28 left REC mixer */ 88 { 0x29, 0x00 }, /* 29 right REC mixer */ 89 { 0x2a, 0x00 }, /* 2A REC control */ 90 { 0x2b, 0x00 }, /* 2B left SPK mixer */ 91 { 0x2c, 0x00 }, /* 2C right SPK mixer */ 92 { 0x2d, 0x00 }, /* 2D SPK control */ 93 { 0x2e, 0x00 }, /* 2E sidetone */ 94 { 0x2f, 0x00 }, /* 2F DAI1 playback level */ 95 96 { 0x30, 0x00 }, /* 30 DAI1 playback level */ 97 { 0x31, 0x00 }, /* 31 DAI2 playback level */ 98 { 0x32, 0x00 }, /* 32 DAI2 playbakc level */ 99 { 0x33, 0x00 }, /* 33 left ADC level */ 100 { 0x34, 0x00 }, /* 34 right ADC level */ 101 { 0x35, 0x00 }, /* 35 MIC1 level */ 102 { 0x36, 0x00 }, /* 36 MIC2 level */ 103 { 0x37, 0x00 }, /* 37 INA level */ 104 { 0x38, 0x00 }, /* 38 INB level */ 105 { 0x39, 0x00 }, /* 39 left HP volume */ 106 { 0x3a, 0x00 }, /* 3A right HP volume */ 107 { 0x3b, 0x00 }, /* 3B left REC volume */ 108 { 0x3c, 0x00 }, /* 3C right REC volume */ 109 { 0x3d, 0x00 }, /* 3D left SPK volume */ 110 { 0x3e, 0x00 }, /* 3E right SPK volume */ 111 { 0x3f, 0x00 }, /* 3F MIC config */ 112 113 { 0x40, 0x00 }, /* 40 MIC threshold */ 114 { 0x41, 0x00 }, /* 41 excursion limiter filter */ 115 { 0x42, 0x00 }, /* 42 excursion limiter threshold */ 116 { 0x43, 0x00 }, /* 43 ALC */ 117 { 0x44, 0x00 }, /* 44 power limiter threshold */ 118 { 0x45, 0x00 }, /* 45 power limiter config */ 119 { 0x46, 0x00 }, /* 46 distortion limiter config */ 120 { 0x47, 0x00 }, /* 47 audio input */ 121 { 0x48, 0x00 }, /* 48 microphone */ 122 { 0x49, 0x00 }, /* 49 level control */ 123 { 0x4a, 0x00 }, /* 4A bypass switches */ 124 { 0x4b, 0x00 }, /* 4B jack detect */ 125 { 0x4c, 0x00 }, /* 4C input enable */ 126 { 0x4d, 0x00 }, /* 4D output enable */ 127 { 0x4e, 0xF0 }, /* 4E bias control */ 128 { 0x4f, 0x00 }, /* 4F DAC power */ 129 130 { 0x50, 0x0F }, /* 50 DAC power */ 131 { 0x51, 0x00 }, /* 51 system */ 132 { 0x52, 0x00 }, /* 52 DAI1 EQ1 */ 133 { 0x53, 0x00 }, /* 53 DAI1 EQ1 */ 134 { 0x54, 0x00 }, /* 54 DAI1 EQ1 */ 135 { 0x55, 0x00 }, /* 55 DAI1 EQ1 */ 136 { 0x56, 0x00 }, /* 56 DAI1 EQ1 */ 137 { 0x57, 0x00 }, /* 57 DAI1 EQ1 */ 138 { 0x58, 0x00 }, /* 58 DAI1 EQ1 */ 139 { 0x59, 0x00 }, /* 59 DAI1 EQ1 */ 140 { 0x5a, 0x00 }, /* 5A DAI1 EQ1 */ 141 { 0x5b, 0x00 }, /* 5B DAI1 EQ1 */ 142 { 0x5c, 0x00 }, /* 5C DAI1 EQ2 */ 143 { 0x5d, 0x00 }, /* 5D DAI1 EQ2 */ 144 { 0x5e, 0x00 }, /* 5E DAI1 EQ2 */ 145 { 0x5f, 0x00 }, /* 5F DAI1 EQ2 */ 146 147 { 0x60, 0x00 }, /* 60 DAI1 EQ2 */ 148 { 0x61, 0x00 }, /* 61 DAI1 EQ2 */ 149 { 0x62, 0x00 }, /* 62 DAI1 EQ2 */ 150 { 0x63, 0x00 }, /* 63 DAI1 EQ2 */ 151 { 0x64, 0x00 }, /* 64 DAI1 EQ2 */ 152 { 0x65, 0x00 }, /* 65 DAI1 EQ2 */ 153 { 0x66, 0x00 }, /* 66 DAI1 EQ3 */ 154 { 0x67, 0x00 }, /* 67 DAI1 EQ3 */ 155 { 0x68, 0x00 }, /* 68 DAI1 EQ3 */ 156 { 0x69, 0x00 }, /* 69 DAI1 EQ3 */ 157 { 0x6a, 0x00 }, /* 6A DAI1 EQ3 */ 158 { 0x6b, 0x00 }, /* 6B DAI1 EQ3 */ 159 { 0x6c, 0x00 }, /* 6C DAI1 EQ3 */ 160 { 0x6d, 0x00 }, /* 6D DAI1 EQ3 */ 161 { 0x6e, 0x00 }, /* 6E DAI1 EQ3 */ 162 { 0x6f, 0x00 }, /* 6F DAI1 EQ3 */ 163 164 { 0x70, 0x00 }, /* 70 DAI1 EQ4 */ 165 { 0x71, 0x00 }, /* 71 DAI1 EQ4 */ 166 { 0x72, 0x00 }, /* 72 DAI1 EQ4 */ 167 { 0x73, 0x00 }, /* 73 DAI1 EQ4 */ 168 { 0x74, 0x00 }, /* 74 DAI1 EQ4 */ 169 { 0x75, 0x00 }, /* 75 DAI1 EQ4 */ 170 { 0x76, 0x00 }, /* 76 DAI1 EQ4 */ 171 { 0x77, 0x00 }, /* 77 DAI1 EQ4 */ 172 { 0x78, 0x00 }, /* 78 DAI1 EQ4 */ 173 { 0x79, 0x00 }, /* 79 DAI1 EQ4 */ 174 { 0x7a, 0x00 }, /* 7A DAI1 EQ5 */ 175 { 0x7b, 0x00 }, /* 7B DAI1 EQ5 */ 176 { 0x7c, 0x00 }, /* 7C DAI1 EQ5 */ 177 { 0x7d, 0x00 }, /* 7D DAI1 EQ5 */ 178 { 0x7e, 0x00 }, /* 7E DAI1 EQ5 */ 179 { 0x7f, 0x00 }, /* 7F DAI1 EQ5 */ 180 181 { 0x80, 0x00 }, /* 80 DAI1 EQ5 */ 182 { 0x81, 0x00 }, /* 81 DAI1 EQ5 */ 183 { 0x82, 0x00 }, /* 82 DAI1 EQ5 */ 184 { 0x83, 0x00 }, /* 83 DAI1 EQ5 */ 185 { 0x84, 0x00 }, /* 84 DAI2 EQ1 */ 186 { 0x85, 0x00 }, /* 85 DAI2 EQ1 */ 187 { 0x86, 0x00 }, /* 86 DAI2 EQ1 */ 188 { 0x87, 0x00 }, /* 87 DAI2 EQ1 */ 189 { 0x88, 0x00 }, /* 88 DAI2 EQ1 */ 190 { 0x89, 0x00 }, /* 89 DAI2 EQ1 */ 191 { 0x8a, 0x00 }, /* 8A DAI2 EQ1 */ 192 { 0x8b, 0x00 }, /* 8B DAI2 EQ1 */ 193 { 0x8c, 0x00 }, /* 8C DAI2 EQ1 */ 194 { 0x8d, 0x00 }, /* 8D DAI2 EQ1 */ 195 { 0x8e, 0x00 }, /* 8E DAI2 EQ2 */ 196 { 0x8f, 0x00 }, /* 8F DAI2 EQ2 */ 197 198 { 0x90, 0x00 }, /* 90 DAI2 EQ2 */ 199 { 0x91, 0x00 }, /* 91 DAI2 EQ2 */ 200 { 0x92, 0x00 }, /* 92 DAI2 EQ2 */ 201 { 0x93, 0x00 }, /* 93 DAI2 EQ2 */ 202 { 0x94, 0x00 }, /* 94 DAI2 EQ2 */ 203 { 0x95, 0x00 }, /* 95 DAI2 EQ2 */ 204 { 0x96, 0x00 }, /* 96 DAI2 EQ2 */ 205 { 0x97, 0x00 }, /* 97 DAI2 EQ2 */ 206 { 0x98, 0x00 }, /* 98 DAI2 EQ3 */ 207 { 0x99, 0x00 }, /* 99 DAI2 EQ3 */ 208 { 0x9a, 0x00 }, /* 9A DAI2 EQ3 */ 209 { 0x9b, 0x00 }, /* 9B DAI2 EQ3 */ 210 { 0x9c, 0x00 }, /* 9C DAI2 EQ3 */ 211 { 0x9d, 0x00 }, /* 9D DAI2 EQ3 */ 212 { 0x9e, 0x00 }, /* 9E DAI2 EQ3 */ 213 { 0x9f, 0x00 }, /* 9F DAI2 EQ3 */ 214 215 { 0xa0, 0x00 }, /* A0 DAI2 EQ3 */ 216 { 0xa1, 0x00 }, /* A1 DAI2 EQ3 */ 217 { 0xa2, 0x00 }, /* A2 DAI2 EQ4 */ 218 { 0xa3, 0x00 }, /* A3 DAI2 EQ4 */ 219 { 0xa4, 0x00 }, /* A4 DAI2 EQ4 */ 220 { 0xa5, 0x00 }, /* A5 DAI2 EQ4 */ 221 { 0xa6, 0x00 }, /* A6 DAI2 EQ4 */ 222 { 0xa7, 0x00 }, /* A7 DAI2 EQ4 */ 223 { 0xa8, 0x00 }, /* A8 DAI2 EQ4 */ 224 { 0xa9, 0x00 }, /* A9 DAI2 EQ4 */ 225 { 0xaa, 0x00 }, /* AA DAI2 EQ4 */ 226 { 0xab, 0x00 }, /* AB DAI2 EQ4 */ 227 { 0xac, 0x00 }, /* AC DAI2 EQ5 */ 228 { 0xad, 0x00 }, /* AD DAI2 EQ5 */ 229 { 0xae, 0x00 }, /* AE DAI2 EQ5 */ 230 { 0xaf, 0x00 }, /* AF DAI2 EQ5 */ 231 232 { 0xb0, 0x00 }, /* B0 DAI2 EQ5 */ 233 { 0xb1, 0x00 }, /* B1 DAI2 EQ5 */ 234 { 0xb2, 0x00 }, /* B2 DAI2 EQ5 */ 235 { 0xb3, 0x00 }, /* B3 DAI2 EQ5 */ 236 { 0xb4, 0x00 }, /* B4 DAI2 EQ5 */ 237 { 0xb5, 0x00 }, /* B5 DAI2 EQ5 */ 238 { 0xb6, 0x00 }, /* B6 DAI1 biquad */ 239 { 0xb7, 0x00 }, /* B7 DAI1 biquad */ 240 { 0xb8 ,0x00 }, /* B8 DAI1 biquad */ 241 { 0xb9, 0x00 }, /* B9 DAI1 biquad */ 242 { 0xba, 0x00 }, /* BA DAI1 biquad */ 243 { 0xbb, 0x00 }, /* BB DAI1 biquad */ 244 { 0xbc, 0x00 }, /* BC DAI1 biquad */ 245 { 0xbd, 0x00 }, /* BD DAI1 biquad */ 246 { 0xbe, 0x00 }, /* BE DAI1 biquad */ 247 { 0xbf, 0x00 }, /* BF DAI1 biquad */ 248 249 { 0xc0, 0x00 }, /* C0 DAI2 biquad */ 250 { 0xc1, 0x00 }, /* C1 DAI2 biquad */ 251 { 0xc2, 0x00 }, /* C2 DAI2 biquad */ 252 { 0xc3, 0x00 }, /* C3 DAI2 biquad */ 253 { 0xc4, 0x00 }, /* C4 DAI2 biquad */ 254 { 0xc5, 0x00 }, /* C5 DAI2 biquad */ 255 { 0xc6, 0x00 }, /* C6 DAI2 biquad */ 256 { 0xc7, 0x00 }, /* C7 DAI2 biquad */ 257 { 0xc8, 0x00 }, /* C8 DAI2 biquad */ 258 { 0xc9, 0x00 }, /* C9 DAI2 biquad */ 259 }; 260 261 static bool max98088_readable_register(struct device *dev, unsigned int reg) 262 { 263 switch (reg) { 264 case M98088_REG_00_IRQ_STATUS ... 0xC9: 265 case M98088_REG_FF_REV_ID: 266 return true; 267 default: 268 return false; 269 } 270 } 271 272 static bool max98088_writeable_register(struct device *dev, unsigned int reg) 273 { 274 switch (reg) { 275 case M98088_REG_03_BATTERY_VOLTAGE ... 0xC9: 276 return true; 277 default: 278 return false; 279 } 280 } 281 282 static bool max98088_volatile_register(struct device *dev, unsigned int reg) 283 { 284 switch (reg) { 285 case M98088_REG_00_IRQ_STATUS ... M98088_REG_03_BATTERY_VOLTAGE: 286 case M98088_REG_FF_REV_ID: 287 return true; 288 default: 289 return false; 290 } 291 } 292 293 static const struct regmap_config max98088_regmap = { 294 .reg_bits = 8, 295 .val_bits = 8, 296 297 .readable_reg = max98088_readable_register, 298 .writeable_reg = max98088_writeable_register, 299 .volatile_reg = max98088_volatile_register, 300 .max_register = 0xff, 301 302 .reg_defaults = max98088_reg, 303 .num_reg_defaults = ARRAY_SIZE(max98088_reg), 304 .cache_type = REGCACHE_RBTREE, 305 }; 306 307 /* 308 * Load equalizer DSP coefficient configurations registers 309 */ 310 static void m98088_eq_band(struct snd_soc_component *component, unsigned int dai, 311 unsigned int band, u16 *coefs) 312 { 313 unsigned int eq_reg; 314 unsigned int i; 315 316 if (WARN_ON(band > 4) || 317 WARN_ON(dai > 1)) 318 return; 319 320 /* Load the base register address */ 321 eq_reg = dai ? M98088_REG_84_DAI2_EQ_BASE : M98088_REG_52_DAI1_EQ_BASE; 322 323 /* Add the band address offset, note adjustment for word address */ 324 eq_reg += band * (M98088_COEFS_PER_BAND << 1); 325 326 /* Step through the registers and coefs */ 327 for (i = 0; i < M98088_COEFS_PER_BAND; i++) { 328 snd_soc_component_write(component, eq_reg++, M98088_BYTE1(coefs[i])); 329 snd_soc_component_write(component, eq_reg++, M98088_BYTE0(coefs[i])); 330 } 331 } 332 333 /* 334 * Excursion limiter modes 335 */ 336 static const char *max98088_exmode_texts[] = { 337 "Off", "100Hz", "400Hz", "600Hz", "800Hz", "1000Hz", "200-400Hz", 338 "400-600Hz", "400-800Hz", 339 }; 340 341 static const unsigned int max98088_exmode_values[] = { 342 0x00, 0x43, 0x10, 0x20, 0x30, 0x40, 0x11, 0x22, 0x32 343 }; 344 345 static SOC_VALUE_ENUM_SINGLE_DECL(max98088_exmode_enum, 346 M98088_REG_41_SPKDHP, 0, 127, 347 max98088_exmode_texts, 348 max98088_exmode_values); 349 350 static const char *max98088_ex_thresh[] = { /* volts PP */ 351 "0.6", "1.2", "1.8", "2.4", "3.0", "3.6", "4.2", "4.8"}; 352 static SOC_ENUM_SINGLE_DECL(max98088_ex_thresh_enum, 353 M98088_REG_42_SPKDHP_THRESH, 0, 354 max98088_ex_thresh); 355 356 static const char *max98088_fltr_mode[] = {"Voice", "Music" }; 357 static SOC_ENUM_SINGLE_DECL(max98088_filter_mode_enum, 358 M98088_REG_18_DAI1_FILTERS, 7, 359 max98088_fltr_mode); 360 361 static const char *max98088_extmic_text[] = { "None", "MIC1", "MIC2" }; 362 363 static SOC_ENUM_SINGLE_DECL(max98088_extmic_enum, 364 M98088_REG_48_CFG_MIC, 0, 365 max98088_extmic_text); 366 367 static const struct snd_kcontrol_new max98088_extmic_mux = 368 SOC_DAPM_ENUM("External MIC Mux", max98088_extmic_enum); 369 370 static const char *max98088_dai1_fltr[] = { 371 "Off", "fc=258/fs=16k", "fc=500/fs=16k", 372 "fc=258/fs=8k", "fc=500/fs=8k", "fc=200"}; 373 static SOC_ENUM_SINGLE_DECL(max98088_dai1_dac_filter_enum, 374 M98088_REG_18_DAI1_FILTERS, 0, 375 max98088_dai1_fltr); 376 static SOC_ENUM_SINGLE_DECL(max98088_dai1_adc_filter_enum, 377 M98088_REG_18_DAI1_FILTERS, 4, 378 max98088_dai1_fltr); 379 380 static int max98088_mic1pre_set(struct snd_kcontrol *kcontrol, 381 struct snd_ctl_elem_value *ucontrol) 382 { 383 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 384 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 385 unsigned int sel = ucontrol->value.integer.value[0]; 386 387 max98088->mic1pre = sel; 388 snd_soc_component_update_bits(component, M98088_REG_35_LVL_MIC1, M98088_MICPRE_MASK, 389 (1+sel)<<M98088_MICPRE_SHIFT); 390 391 return 0; 392 } 393 394 static int max98088_mic1pre_get(struct snd_kcontrol *kcontrol, 395 struct snd_ctl_elem_value *ucontrol) 396 { 397 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 398 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 399 400 ucontrol->value.integer.value[0] = max98088->mic1pre; 401 return 0; 402 } 403 404 static int max98088_mic2pre_set(struct snd_kcontrol *kcontrol, 405 struct snd_ctl_elem_value *ucontrol) 406 { 407 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 408 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 409 unsigned int sel = ucontrol->value.integer.value[0]; 410 411 max98088->mic2pre = sel; 412 snd_soc_component_update_bits(component, M98088_REG_36_LVL_MIC2, M98088_MICPRE_MASK, 413 (1+sel)<<M98088_MICPRE_SHIFT); 414 415 return 0; 416 } 417 418 static int max98088_mic2pre_get(struct snd_kcontrol *kcontrol, 419 struct snd_ctl_elem_value *ucontrol) 420 { 421 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 422 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 423 424 ucontrol->value.integer.value[0] = max98088->mic2pre; 425 return 0; 426 } 427 428 static const DECLARE_TLV_DB_RANGE(max98088_micboost_tlv, 429 0, 1, TLV_DB_SCALE_ITEM(0, 2000, 0), 430 2, 2, TLV_DB_SCALE_ITEM(3000, 0, 0) 431 ); 432 433 static const DECLARE_TLV_DB_RANGE(max98088_hp_tlv, 434 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0), 435 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0), 436 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0), 437 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0), 438 28, 31, TLV_DB_SCALE_ITEM(150, 50, 0) 439 ); 440 441 static const DECLARE_TLV_DB_RANGE(max98088_spk_tlv, 442 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0), 443 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0), 444 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0), 445 22, 27, TLV_DB_SCALE_ITEM(100, 100, 0), 446 28, 31, TLV_DB_SCALE_ITEM(650, 50, 0) 447 ); 448 449 static const struct snd_kcontrol_new max98088_snd_controls[] = { 450 451 SOC_DOUBLE_R_TLV("Headphone Volume", M98088_REG_39_LVL_HP_L, 452 M98088_REG_3A_LVL_HP_R, 0, 31, 0, max98088_hp_tlv), 453 SOC_DOUBLE_R_TLV("Speaker Volume", M98088_REG_3D_LVL_SPK_L, 454 M98088_REG_3E_LVL_SPK_R, 0, 31, 0, max98088_spk_tlv), 455 SOC_DOUBLE_R_TLV("Receiver Volume", M98088_REG_3B_LVL_REC_L, 456 M98088_REG_3C_LVL_REC_R, 0, 31, 0, max98088_spk_tlv), 457 458 SOC_DOUBLE_R("Headphone Switch", M98088_REG_39_LVL_HP_L, 459 M98088_REG_3A_LVL_HP_R, 7, 1, 1), 460 SOC_DOUBLE_R("Speaker Switch", M98088_REG_3D_LVL_SPK_L, 461 M98088_REG_3E_LVL_SPK_R, 7, 1, 1), 462 SOC_DOUBLE_R("Receiver Switch", M98088_REG_3B_LVL_REC_L, 463 M98088_REG_3C_LVL_REC_R, 7, 1, 1), 464 465 SOC_SINGLE("MIC1 Volume", M98088_REG_35_LVL_MIC1, 0, 31, 1), 466 SOC_SINGLE("MIC2 Volume", M98088_REG_36_LVL_MIC2, 0, 31, 1), 467 468 SOC_SINGLE_EXT_TLV("MIC1 Boost Volume", 469 M98088_REG_35_LVL_MIC1, 5, 2, 0, 470 max98088_mic1pre_get, max98088_mic1pre_set, 471 max98088_micboost_tlv), 472 SOC_SINGLE_EXT_TLV("MIC2 Boost Volume", 473 M98088_REG_36_LVL_MIC2, 5, 2, 0, 474 max98088_mic2pre_get, max98088_mic2pre_set, 475 max98088_micboost_tlv), 476 477 SOC_SINGLE("INA Volume", M98088_REG_37_LVL_INA, 0, 7, 1), 478 SOC_SINGLE("INB Volume", M98088_REG_38_LVL_INB, 0, 7, 1), 479 480 SOC_SINGLE("ADCL Volume", M98088_REG_33_LVL_ADC_L, 0, 15, 0), 481 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0), 482 483 SOC_SINGLE("ADCL Boost Volume", M98088_REG_33_LVL_ADC_L, 4, 3, 0), 484 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0), 485 486 SOC_SINGLE("EQ1 Switch", M98088_REG_49_CFG_LEVEL, 0, 1, 0), 487 SOC_SINGLE("EQ2 Switch", M98088_REG_49_CFG_LEVEL, 1, 1, 0), 488 489 SOC_ENUM("EX Limiter Mode", max98088_exmode_enum), 490 SOC_ENUM("EX Limiter Threshold", max98088_ex_thresh_enum), 491 492 SOC_ENUM("DAI1 Filter Mode", max98088_filter_mode_enum), 493 SOC_ENUM("DAI1 DAC Filter", max98088_dai1_dac_filter_enum), 494 SOC_ENUM("DAI1 ADC Filter", max98088_dai1_adc_filter_enum), 495 SOC_SINGLE("DAI2 DC Block Switch", M98088_REG_20_DAI2_FILTERS, 496 0, 1, 0), 497 498 SOC_SINGLE("ALC Switch", M98088_REG_43_SPKALC_COMP, 7, 1, 0), 499 SOC_SINGLE("ALC Threshold", M98088_REG_43_SPKALC_COMP, 0, 7, 0), 500 SOC_SINGLE("ALC Multiband", M98088_REG_43_SPKALC_COMP, 3, 1, 0), 501 SOC_SINGLE("ALC Release Time", M98088_REG_43_SPKALC_COMP, 4, 7, 0), 502 503 SOC_SINGLE("PWR Limiter Threshold", M98088_REG_44_PWRLMT_CFG, 504 4, 15, 0), 505 SOC_SINGLE("PWR Limiter Weight", M98088_REG_44_PWRLMT_CFG, 0, 7, 0), 506 SOC_SINGLE("PWR Limiter Time1", M98088_REG_45_PWRLMT_TIME, 0, 15, 0), 507 SOC_SINGLE("PWR Limiter Time2", M98088_REG_45_PWRLMT_TIME, 4, 15, 0), 508 509 SOC_SINGLE("THD Limiter Threshold", M98088_REG_46_THDLMT_CFG, 4, 15, 0), 510 SOC_SINGLE("THD Limiter Time", M98088_REG_46_THDLMT_CFG, 0, 7, 0), 511 }; 512 513 /* Left speaker mixer switch */ 514 static const struct snd_kcontrol_new max98088_left_speaker_mixer_controls[] = { 515 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), 516 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), 517 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 0, 1, 0), 518 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 7, 1, 0), 519 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 5, 1, 0), 520 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 6, 1, 0), 521 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 1, 1, 0), 522 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 2, 1, 0), 523 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2B_MIX_SPK_LEFT, 3, 1, 0), 524 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2B_MIX_SPK_LEFT, 4, 1, 0), 525 }; 526 527 /* Right speaker mixer switch */ 528 static const struct snd_kcontrol_new max98088_right_speaker_mixer_controls[] = { 529 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), 530 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), 531 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 7, 1, 0), 532 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 0, 1, 0), 533 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 5, 1, 0), 534 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 6, 1, 0), 535 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 1, 1, 0), 536 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 2, 1, 0), 537 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 3, 1, 0), 538 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_2C_MIX_SPK_RIGHT, 4, 1, 0), 539 }; 540 541 /* Left headphone mixer switch */ 542 static const struct snd_kcontrol_new max98088_left_hp_mixer_controls[] = { 543 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), 544 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), 545 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 0, 1, 0), 546 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_25_MIX_HP_LEFT, 7, 1, 0), 547 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_25_MIX_HP_LEFT, 5, 1, 0), 548 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_25_MIX_HP_LEFT, 6, 1, 0), 549 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_25_MIX_HP_LEFT, 1, 1, 0), 550 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_25_MIX_HP_LEFT, 2, 1, 0), 551 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_25_MIX_HP_LEFT, 3, 1, 0), 552 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_25_MIX_HP_LEFT, 4, 1, 0), 553 }; 554 555 /* Right headphone mixer switch */ 556 static const struct snd_kcontrol_new max98088_right_hp_mixer_controls[] = { 557 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), 558 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), 559 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 7, 1, 0), 560 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 0, 1, 0), 561 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_26_MIX_HP_RIGHT, 5, 1, 0), 562 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_26_MIX_HP_RIGHT, 6, 1, 0), 563 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_26_MIX_HP_RIGHT, 1, 1, 0), 564 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_26_MIX_HP_RIGHT, 2, 1, 0), 565 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_26_MIX_HP_RIGHT, 3, 1, 0), 566 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_26_MIX_HP_RIGHT, 4, 1, 0), 567 }; 568 569 /* Left earpiece/receiver mixer switch */ 570 static const struct snd_kcontrol_new max98088_left_rec_mixer_controls[] = { 571 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), 572 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), 573 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 0, 1, 0), 574 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_28_MIX_REC_LEFT, 7, 1, 0), 575 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_28_MIX_REC_LEFT, 5, 1, 0), 576 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_28_MIX_REC_LEFT, 6, 1, 0), 577 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_28_MIX_REC_LEFT, 1, 1, 0), 578 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_28_MIX_REC_LEFT, 2, 1, 0), 579 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_28_MIX_REC_LEFT, 3, 1, 0), 580 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_28_MIX_REC_LEFT, 4, 1, 0), 581 }; 582 583 /* Right earpiece/receiver mixer switch */ 584 static const struct snd_kcontrol_new max98088_right_rec_mixer_controls[] = { 585 SOC_DAPM_SINGLE("Left DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), 586 SOC_DAPM_SINGLE("Right DAC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), 587 SOC_DAPM_SINGLE("Left DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 7, 1, 0), 588 SOC_DAPM_SINGLE("Right DAC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 0, 1, 0), 589 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_29_MIX_REC_RIGHT, 5, 1, 0), 590 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_29_MIX_REC_RIGHT, 6, 1, 0), 591 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_29_MIX_REC_RIGHT, 1, 1, 0), 592 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_29_MIX_REC_RIGHT, 2, 1, 0), 593 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_29_MIX_REC_RIGHT, 3, 1, 0), 594 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_29_MIX_REC_RIGHT, 4, 1, 0), 595 }; 596 597 /* Left ADC mixer switch */ 598 static const struct snd_kcontrol_new max98088_left_ADC_mixer_controls[] = { 599 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_23_MIX_ADC_LEFT, 7, 1, 0), 600 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_23_MIX_ADC_LEFT, 6, 1, 0), 601 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_23_MIX_ADC_LEFT, 3, 1, 0), 602 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_23_MIX_ADC_LEFT, 2, 1, 0), 603 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_23_MIX_ADC_LEFT, 1, 1, 0), 604 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_23_MIX_ADC_LEFT, 0, 1, 0), 605 }; 606 607 /* Right ADC mixer switch */ 608 static const struct snd_kcontrol_new max98088_right_ADC_mixer_controls[] = { 609 SOC_DAPM_SINGLE("MIC1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 7, 1, 0), 610 SOC_DAPM_SINGLE("MIC2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 6, 1, 0), 611 SOC_DAPM_SINGLE("INA1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 3, 1, 0), 612 SOC_DAPM_SINGLE("INA2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 2, 1, 0), 613 SOC_DAPM_SINGLE("INB1 Switch", M98088_REG_24_MIX_ADC_RIGHT, 1, 1, 0), 614 SOC_DAPM_SINGLE("INB2 Switch", M98088_REG_24_MIX_ADC_RIGHT, 0, 1, 0), 615 }; 616 617 static int max98088_mic_event(struct snd_soc_dapm_widget *w, 618 struct snd_kcontrol *kcontrol, int event) 619 { 620 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 621 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 622 623 switch (event) { 624 case SND_SOC_DAPM_POST_PMU: 625 if (w->reg == M98088_REG_35_LVL_MIC1) { 626 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 627 (1+max98088->mic1pre)<<M98088_MICPRE_SHIFT); 628 } else { 629 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 630 (1+max98088->mic2pre)<<M98088_MICPRE_SHIFT); 631 } 632 break; 633 case SND_SOC_DAPM_POST_PMD: 634 snd_soc_component_update_bits(component, w->reg, M98088_MICPRE_MASK, 0); 635 break; 636 default: 637 return -EINVAL; 638 } 639 640 return 0; 641 } 642 643 /* 644 * The line inputs are 2-channel stereo inputs with the left 645 * and right channels sharing a common PGA power control signal. 646 */ 647 static int max98088_line_pga(struct snd_soc_dapm_widget *w, 648 int event, int line, u8 channel) 649 { 650 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 651 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 652 u8 *state; 653 654 if (WARN_ON(!(channel == 1 || channel == 2))) 655 return -EINVAL; 656 657 switch (line) { 658 case LINE_INA: 659 state = &max98088->ina_state; 660 break; 661 case LINE_INB: 662 state = &max98088->inb_state; 663 break; 664 default: 665 return -EINVAL; 666 } 667 668 switch (event) { 669 case SND_SOC_DAPM_POST_PMU: 670 *state |= channel; 671 snd_soc_component_update_bits(component, w->reg, 672 (1 << w->shift), (1 << w->shift)); 673 break; 674 case SND_SOC_DAPM_POST_PMD: 675 *state &= ~channel; 676 if (*state == 0) { 677 snd_soc_component_update_bits(component, w->reg, 678 (1 << w->shift), 0); 679 } 680 break; 681 default: 682 return -EINVAL; 683 } 684 685 return 0; 686 } 687 688 static int max98088_pga_ina1_event(struct snd_soc_dapm_widget *w, 689 struct snd_kcontrol *k, int event) 690 { 691 return max98088_line_pga(w, event, LINE_INA, 1); 692 } 693 694 static int max98088_pga_ina2_event(struct snd_soc_dapm_widget *w, 695 struct snd_kcontrol *k, int event) 696 { 697 return max98088_line_pga(w, event, LINE_INA, 2); 698 } 699 700 static int max98088_pga_inb1_event(struct snd_soc_dapm_widget *w, 701 struct snd_kcontrol *k, int event) 702 { 703 return max98088_line_pga(w, event, LINE_INB, 1); 704 } 705 706 static int max98088_pga_inb2_event(struct snd_soc_dapm_widget *w, 707 struct snd_kcontrol *k, int event) 708 { 709 return max98088_line_pga(w, event, LINE_INB, 2); 710 } 711 712 static const struct snd_soc_dapm_widget max98088_dapm_widgets[] = { 713 714 SND_SOC_DAPM_ADC("ADCL", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 1, 0), 715 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0), 716 717 SND_SOC_DAPM_DAC("DACL1", "HiFi Playback", 718 M98088_REG_4D_PWR_EN_OUT, 1, 0), 719 SND_SOC_DAPM_DAC("DACR1", "HiFi Playback", 720 M98088_REG_4D_PWR_EN_OUT, 0, 0), 721 SND_SOC_DAPM_DAC("DACL2", "Aux Playback", 722 M98088_REG_4D_PWR_EN_OUT, 1, 0), 723 SND_SOC_DAPM_DAC("DACR2", "Aux Playback", 724 M98088_REG_4D_PWR_EN_OUT, 0, 0), 725 726 SND_SOC_DAPM_PGA("HP Left Out", M98088_REG_4D_PWR_EN_OUT, 727 7, 0, NULL, 0), 728 SND_SOC_DAPM_PGA("HP Right Out", M98088_REG_4D_PWR_EN_OUT, 729 6, 0, NULL, 0), 730 731 SND_SOC_DAPM_PGA("SPK Left Out", M98088_REG_4D_PWR_EN_OUT, 732 5, 0, NULL, 0), 733 SND_SOC_DAPM_PGA("SPK Right Out", M98088_REG_4D_PWR_EN_OUT, 734 4, 0, NULL, 0), 735 736 SND_SOC_DAPM_PGA("REC Left Out", M98088_REG_4D_PWR_EN_OUT, 737 3, 0, NULL, 0), 738 SND_SOC_DAPM_PGA("REC Right Out", M98088_REG_4D_PWR_EN_OUT, 739 2, 0, NULL, 0), 740 741 SND_SOC_DAPM_MUX("External MIC", SND_SOC_NOPM, 0, 0, 742 &max98088_extmic_mux), 743 744 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0, 745 &max98088_left_hp_mixer_controls[0], 746 ARRAY_SIZE(max98088_left_hp_mixer_controls)), 747 748 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0, 749 &max98088_right_hp_mixer_controls[0], 750 ARRAY_SIZE(max98088_right_hp_mixer_controls)), 751 752 SND_SOC_DAPM_MIXER("Left SPK Mixer", SND_SOC_NOPM, 0, 0, 753 &max98088_left_speaker_mixer_controls[0], 754 ARRAY_SIZE(max98088_left_speaker_mixer_controls)), 755 756 SND_SOC_DAPM_MIXER("Right SPK Mixer", SND_SOC_NOPM, 0, 0, 757 &max98088_right_speaker_mixer_controls[0], 758 ARRAY_SIZE(max98088_right_speaker_mixer_controls)), 759 760 SND_SOC_DAPM_MIXER("Left REC Mixer", SND_SOC_NOPM, 0, 0, 761 &max98088_left_rec_mixer_controls[0], 762 ARRAY_SIZE(max98088_left_rec_mixer_controls)), 763 764 SND_SOC_DAPM_MIXER("Right REC Mixer", SND_SOC_NOPM, 0, 0, 765 &max98088_right_rec_mixer_controls[0], 766 ARRAY_SIZE(max98088_right_rec_mixer_controls)), 767 768 SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0, 769 &max98088_left_ADC_mixer_controls[0], 770 ARRAY_SIZE(max98088_left_ADC_mixer_controls)), 771 772 SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0, 773 &max98088_right_ADC_mixer_controls[0], 774 ARRAY_SIZE(max98088_right_ADC_mixer_controls)), 775 776 SND_SOC_DAPM_PGA_E("MIC1 Input", M98088_REG_35_LVL_MIC1, 777 5, 0, NULL, 0, max98088_mic_event, 778 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 779 780 SND_SOC_DAPM_PGA_E("MIC2 Input", M98088_REG_36_LVL_MIC2, 781 5, 0, NULL, 0, max98088_mic_event, 782 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 783 784 SND_SOC_DAPM_PGA_E("INA1 Input", M98088_REG_4C_PWR_EN_IN, 785 7, 0, NULL, 0, max98088_pga_ina1_event, 786 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 787 788 SND_SOC_DAPM_PGA_E("INA2 Input", M98088_REG_4C_PWR_EN_IN, 789 7, 0, NULL, 0, max98088_pga_ina2_event, 790 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 791 792 SND_SOC_DAPM_PGA_E("INB1 Input", M98088_REG_4C_PWR_EN_IN, 793 6, 0, NULL, 0, max98088_pga_inb1_event, 794 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 795 796 SND_SOC_DAPM_PGA_E("INB2 Input", M98088_REG_4C_PWR_EN_IN, 797 6, 0, NULL, 0, max98088_pga_inb2_event, 798 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 799 800 SND_SOC_DAPM_MICBIAS("MICBIAS", M98088_REG_4C_PWR_EN_IN, 3, 0), 801 802 SND_SOC_DAPM_OUTPUT("HPL"), 803 SND_SOC_DAPM_OUTPUT("HPR"), 804 SND_SOC_DAPM_OUTPUT("SPKL"), 805 SND_SOC_DAPM_OUTPUT("SPKR"), 806 SND_SOC_DAPM_OUTPUT("RECL"), 807 SND_SOC_DAPM_OUTPUT("RECR"), 808 809 SND_SOC_DAPM_INPUT("MIC1"), 810 SND_SOC_DAPM_INPUT("MIC2"), 811 SND_SOC_DAPM_INPUT("INA1"), 812 SND_SOC_DAPM_INPUT("INA2"), 813 SND_SOC_DAPM_INPUT("INB1"), 814 SND_SOC_DAPM_INPUT("INB2"), 815 }; 816 817 static const struct snd_soc_dapm_route max98088_audio_map[] = { 818 /* Left headphone output mixer */ 819 {"Left HP Mixer", "Left DAC1 Switch", "DACL1"}, 820 {"Left HP Mixer", "Left DAC2 Switch", "DACL2"}, 821 {"Left HP Mixer", "Right DAC1 Switch", "DACR1"}, 822 {"Left HP Mixer", "Right DAC2 Switch", "DACR2"}, 823 {"Left HP Mixer", "MIC1 Switch", "MIC1 Input"}, 824 {"Left HP Mixer", "MIC2 Switch", "MIC2 Input"}, 825 {"Left HP Mixer", "INA1 Switch", "INA1 Input"}, 826 {"Left HP Mixer", "INA2 Switch", "INA2 Input"}, 827 {"Left HP Mixer", "INB1 Switch", "INB1 Input"}, 828 {"Left HP Mixer", "INB2 Switch", "INB2 Input"}, 829 830 /* Right headphone output mixer */ 831 {"Right HP Mixer", "Left DAC1 Switch", "DACL1"}, 832 {"Right HP Mixer", "Left DAC2 Switch", "DACL2" }, 833 {"Right HP Mixer", "Right DAC1 Switch", "DACR1"}, 834 {"Right HP Mixer", "Right DAC2 Switch", "DACR2"}, 835 {"Right HP Mixer", "MIC1 Switch", "MIC1 Input"}, 836 {"Right HP Mixer", "MIC2 Switch", "MIC2 Input"}, 837 {"Right HP Mixer", "INA1 Switch", "INA1 Input"}, 838 {"Right HP Mixer", "INA2 Switch", "INA2 Input"}, 839 {"Right HP Mixer", "INB1 Switch", "INB1 Input"}, 840 {"Right HP Mixer", "INB2 Switch", "INB2 Input"}, 841 842 /* Left speaker output mixer */ 843 {"Left SPK Mixer", "Left DAC1 Switch", "DACL1"}, 844 {"Left SPK Mixer", "Left DAC2 Switch", "DACL2"}, 845 {"Left SPK Mixer", "Right DAC1 Switch", "DACR1"}, 846 {"Left SPK Mixer", "Right DAC2 Switch", "DACR2"}, 847 {"Left SPK Mixer", "MIC1 Switch", "MIC1 Input"}, 848 {"Left SPK Mixer", "MIC2 Switch", "MIC2 Input"}, 849 {"Left SPK Mixer", "INA1 Switch", "INA1 Input"}, 850 {"Left SPK Mixer", "INA2 Switch", "INA2 Input"}, 851 {"Left SPK Mixer", "INB1 Switch", "INB1 Input"}, 852 {"Left SPK Mixer", "INB2 Switch", "INB2 Input"}, 853 854 /* Right speaker output mixer */ 855 {"Right SPK Mixer", "Left DAC1 Switch", "DACL1"}, 856 {"Right SPK Mixer", "Left DAC2 Switch", "DACL2"}, 857 {"Right SPK Mixer", "Right DAC1 Switch", "DACR1"}, 858 {"Right SPK Mixer", "Right DAC2 Switch", "DACR2"}, 859 {"Right SPK Mixer", "MIC1 Switch", "MIC1 Input"}, 860 {"Right SPK Mixer", "MIC2 Switch", "MIC2 Input"}, 861 {"Right SPK Mixer", "INA1 Switch", "INA1 Input"}, 862 {"Right SPK Mixer", "INA2 Switch", "INA2 Input"}, 863 {"Right SPK Mixer", "INB1 Switch", "INB1 Input"}, 864 {"Right SPK Mixer", "INB2 Switch", "INB2 Input"}, 865 866 /* Earpiece/Receiver output mixer */ 867 {"Left REC Mixer", "Left DAC1 Switch", "DACL1"}, 868 {"Left REC Mixer", "Left DAC2 Switch", "DACL2"}, 869 {"Left REC Mixer", "Right DAC1 Switch", "DACR1"}, 870 {"Left REC Mixer", "Right DAC2 Switch", "DACR2"}, 871 {"Left REC Mixer", "MIC1 Switch", "MIC1 Input"}, 872 {"Left REC Mixer", "MIC2 Switch", "MIC2 Input"}, 873 {"Left REC Mixer", "INA1 Switch", "INA1 Input"}, 874 {"Left REC Mixer", "INA2 Switch", "INA2 Input"}, 875 {"Left REC Mixer", "INB1 Switch", "INB1 Input"}, 876 {"Left REC Mixer", "INB2 Switch", "INB2 Input"}, 877 878 /* Earpiece/Receiver output mixer */ 879 {"Right REC Mixer", "Left DAC1 Switch", "DACL1"}, 880 {"Right REC Mixer", "Left DAC2 Switch", "DACL2"}, 881 {"Right REC Mixer", "Right DAC1 Switch", "DACR1"}, 882 {"Right REC Mixer", "Right DAC2 Switch", "DACR2"}, 883 {"Right REC Mixer", "MIC1 Switch", "MIC1 Input"}, 884 {"Right REC Mixer", "MIC2 Switch", "MIC2 Input"}, 885 {"Right REC Mixer", "INA1 Switch", "INA1 Input"}, 886 {"Right REC Mixer", "INA2 Switch", "INA2 Input"}, 887 {"Right REC Mixer", "INB1 Switch", "INB1 Input"}, 888 {"Right REC Mixer", "INB2 Switch", "INB2 Input"}, 889 890 {"HP Left Out", NULL, "Left HP Mixer"}, 891 {"HP Right Out", NULL, "Right HP Mixer"}, 892 {"SPK Left Out", NULL, "Left SPK Mixer"}, 893 {"SPK Right Out", NULL, "Right SPK Mixer"}, 894 {"REC Left Out", NULL, "Left REC Mixer"}, 895 {"REC Right Out", NULL, "Right REC Mixer"}, 896 897 {"HPL", NULL, "HP Left Out"}, 898 {"HPR", NULL, "HP Right Out"}, 899 {"SPKL", NULL, "SPK Left Out"}, 900 {"SPKR", NULL, "SPK Right Out"}, 901 {"RECL", NULL, "REC Left Out"}, 902 {"RECR", NULL, "REC Right Out"}, 903 904 /* Left ADC input mixer */ 905 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 906 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 907 {"Left ADC Mixer", "INA1 Switch", "INA1 Input"}, 908 {"Left ADC Mixer", "INA2 Switch", "INA2 Input"}, 909 {"Left ADC Mixer", "INB1 Switch", "INB1 Input"}, 910 {"Left ADC Mixer", "INB2 Switch", "INB2 Input"}, 911 912 /* Right ADC input mixer */ 913 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"}, 914 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"}, 915 {"Right ADC Mixer", "INA1 Switch", "INA1 Input"}, 916 {"Right ADC Mixer", "INA2 Switch", "INA2 Input"}, 917 {"Right ADC Mixer", "INB1 Switch", "INB1 Input"}, 918 {"Right ADC Mixer", "INB2 Switch", "INB2 Input"}, 919 920 /* Inputs */ 921 {"ADCL", NULL, "Left ADC Mixer"}, 922 {"ADCR", NULL, "Right ADC Mixer"}, 923 {"INA1 Input", NULL, "INA1"}, 924 {"INA2 Input", NULL, "INA2"}, 925 {"INB1 Input", NULL, "INB1"}, 926 {"INB2 Input", NULL, "INB2"}, 927 {"MIC1 Input", NULL, "MIC1"}, 928 {"MIC2 Input", NULL, "MIC2"}, 929 }; 930 931 /* codec mclk clock divider coefficients */ 932 static const struct { 933 u32 rate; 934 u8 sr; 935 } rate_table[] = { 936 {8000, 0x10}, 937 {11025, 0x20}, 938 {16000, 0x30}, 939 {22050, 0x40}, 940 {24000, 0x50}, 941 {32000, 0x60}, 942 {44100, 0x70}, 943 {48000, 0x80}, 944 {88200, 0x90}, 945 {96000, 0xA0}, 946 }; 947 948 static inline int rate_value(int rate, u8 *value) 949 { 950 int i; 951 952 for (i = 0; i < ARRAY_SIZE(rate_table); i++) { 953 if (rate_table[i].rate >= rate) { 954 *value = rate_table[i].sr; 955 return 0; 956 } 957 } 958 *value = rate_table[0].sr; 959 return -EINVAL; 960 } 961 962 static int max98088_dai1_hw_params(struct snd_pcm_substream *substream, 963 struct snd_pcm_hw_params *params, 964 struct snd_soc_dai *dai) 965 { 966 struct snd_soc_component *component = dai->component; 967 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 968 struct max98088_cdata *cdata; 969 unsigned long long ni; 970 unsigned int rate; 971 u8 regval; 972 973 cdata = &max98088->dai[0]; 974 975 rate = params_rate(params); 976 977 switch (params_width(params)) { 978 case 16: 979 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT, 980 M98088_DAI_WS, 0); 981 break; 982 case 24: 983 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT, 984 M98088_DAI_WS, M98088_DAI_WS); 985 break; 986 default: 987 return -EINVAL; 988 } 989 990 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); 991 992 if (rate_value(rate, ®val)) 993 return -EINVAL; 994 995 snd_soc_component_update_bits(component, M98088_REG_11_DAI1_CLKMODE, 996 M98088_CLKMODE_MASK, regval); 997 cdata->rate = rate; 998 999 /* Configure NI when operating as master */ 1000 if (snd_soc_component_read(component, M98088_REG_14_DAI1_FORMAT) 1001 & M98088_DAI_MAS) { 1002 unsigned long pclk; 1003 1004 if (max98088->sysclk == 0) { 1005 dev_err(component->dev, "Invalid system clock frequency\n"); 1006 return -EINVAL; 1007 } 1008 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1009 * (unsigned long long int)rate; 1010 pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler); 1011 ni = DIV_ROUND_CLOSEST_ULL(ni, pclk); 1012 snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI, 1013 (ni >> 8) & 0x7F); 1014 snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO, 1015 ni & 0xFF); 1016 } 1017 1018 /* Update sample rate mode */ 1019 if (rate < 50000) 1020 snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS, 1021 M98088_DAI_DHF, 0); 1022 else 1023 snd_soc_component_update_bits(component, M98088_REG_18_DAI1_FILTERS, 1024 M98088_DAI_DHF, M98088_DAI_DHF); 1025 1026 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 1027 M98088_SHDNRUN); 1028 1029 return 0; 1030 } 1031 1032 static int max98088_dai2_hw_params(struct snd_pcm_substream *substream, 1033 struct snd_pcm_hw_params *params, 1034 struct snd_soc_dai *dai) 1035 { 1036 struct snd_soc_component *component = dai->component; 1037 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1038 struct max98088_cdata *cdata; 1039 unsigned long long ni; 1040 unsigned int rate; 1041 u8 regval; 1042 1043 cdata = &max98088->dai[1]; 1044 1045 rate = params_rate(params); 1046 1047 switch (params_width(params)) { 1048 case 16: 1049 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT, 1050 M98088_DAI_WS, 0); 1051 break; 1052 case 24: 1053 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT, 1054 M98088_DAI_WS, M98088_DAI_WS); 1055 break; 1056 default: 1057 return -EINVAL; 1058 } 1059 1060 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 0); 1061 1062 if (rate_value(rate, ®val)) 1063 return -EINVAL; 1064 1065 snd_soc_component_update_bits(component, M98088_REG_19_DAI2_CLKMODE, 1066 M98088_CLKMODE_MASK, regval); 1067 cdata->rate = rate; 1068 1069 /* Configure NI when operating as master */ 1070 if (snd_soc_component_read(component, M98088_REG_1C_DAI2_FORMAT) 1071 & M98088_DAI_MAS) { 1072 unsigned long pclk; 1073 1074 if (max98088->sysclk == 0) { 1075 dev_err(component->dev, "Invalid system clock frequency\n"); 1076 return -EINVAL; 1077 } 1078 ni = 65536ULL * (rate < 50000 ? 96ULL : 48ULL) 1079 * (unsigned long long int)rate; 1080 pclk = DIV_ROUND_CLOSEST(max98088->sysclk, max98088->mclk_prescaler); 1081 ni = DIV_ROUND_CLOSEST_ULL(ni, pclk); 1082 snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI, 1083 (ni >> 8) & 0x7F); 1084 snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO, 1085 ni & 0xFF); 1086 } 1087 1088 /* Update sample rate mode */ 1089 if (rate < 50000) 1090 snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS, 1091 M98088_DAI_DHF, 0); 1092 else 1093 snd_soc_component_update_bits(component, M98088_REG_20_DAI2_FILTERS, 1094 M98088_DAI_DHF, M98088_DAI_DHF); 1095 1096 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, M98088_SHDNRUN, 1097 M98088_SHDNRUN); 1098 1099 return 0; 1100 } 1101 1102 static int max98088_dai_set_sysclk(struct snd_soc_dai *dai, 1103 int clk_id, unsigned int freq, int dir) 1104 { 1105 struct snd_soc_component *component = dai->component; 1106 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1107 1108 /* Requested clock frequency is already setup */ 1109 if (freq == max98088->sysclk) 1110 return 0; 1111 1112 if (!IS_ERR(max98088->mclk)) { 1113 freq = clk_round_rate(max98088->mclk, freq); 1114 clk_set_rate(max98088->mclk, freq); 1115 } 1116 1117 /* Setup clocks for slave mode, and using the PLL 1118 * PSCLK = 0x01 (when master clk is 10MHz to 20MHz) 1119 * 0x02 (when master clk is 20MHz to 30MHz).. 1120 */ 1121 if ((freq >= 10000000) && (freq < 20000000)) { 1122 snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x10); 1123 max98088->mclk_prescaler = 1; 1124 } else if ((freq >= 20000000) && (freq < 30000000)) { 1125 snd_soc_component_write(component, M98088_REG_10_SYS_CLK, 0x20); 1126 max98088->mclk_prescaler = 2; 1127 } else { 1128 dev_err(component->dev, "Invalid master clock frequency\n"); 1129 return -EINVAL; 1130 } 1131 1132 if (snd_soc_component_read(component, M98088_REG_51_PWR_SYS) & M98088_SHDNRUN) { 1133 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, 1134 M98088_SHDNRUN, 0); 1135 snd_soc_component_update_bits(component, M98088_REG_51_PWR_SYS, 1136 M98088_SHDNRUN, M98088_SHDNRUN); 1137 } 1138 1139 dev_dbg(dai->dev, "Clock source is %d at %uHz\n", clk_id, freq); 1140 1141 max98088->sysclk = freq; 1142 return 0; 1143 } 1144 1145 static int max98088_dai1_set_fmt(struct snd_soc_dai *codec_dai, 1146 unsigned int fmt) 1147 { 1148 struct snd_soc_component *component = codec_dai->component; 1149 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1150 struct max98088_cdata *cdata; 1151 u8 reg15val; 1152 u8 reg14val = 0; 1153 1154 cdata = &max98088->dai[0]; 1155 1156 if (fmt != cdata->fmt) { 1157 cdata->fmt = fmt; 1158 1159 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1160 case SND_SOC_DAIFMT_CBS_CFS: 1161 /* Slave mode PLL */ 1162 snd_soc_component_write(component, M98088_REG_12_DAI1_CLKCFG_HI, 1163 0x80); 1164 snd_soc_component_write(component, M98088_REG_13_DAI1_CLKCFG_LO, 1165 0x00); 1166 break; 1167 case SND_SOC_DAIFMT_CBM_CFM: 1168 /* Set to master mode */ 1169 reg14val |= M98088_DAI_MAS; 1170 break; 1171 case SND_SOC_DAIFMT_CBS_CFM: 1172 case SND_SOC_DAIFMT_CBM_CFS: 1173 default: 1174 dev_err(component->dev, "Clock mode unsupported"); 1175 return -EINVAL; 1176 } 1177 1178 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1179 case SND_SOC_DAIFMT_I2S: 1180 reg14val |= M98088_DAI_DLY; 1181 break; 1182 case SND_SOC_DAIFMT_LEFT_J: 1183 break; 1184 default: 1185 return -EINVAL; 1186 } 1187 1188 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1189 case SND_SOC_DAIFMT_NB_NF: 1190 break; 1191 case SND_SOC_DAIFMT_NB_IF: 1192 reg14val |= M98088_DAI_WCI; 1193 break; 1194 case SND_SOC_DAIFMT_IB_NF: 1195 reg14val |= M98088_DAI_BCI; 1196 break; 1197 case SND_SOC_DAIFMT_IB_IF: 1198 reg14val |= M98088_DAI_BCI|M98088_DAI_WCI; 1199 break; 1200 default: 1201 return -EINVAL; 1202 } 1203 1204 snd_soc_component_update_bits(component, M98088_REG_14_DAI1_FORMAT, 1205 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | 1206 M98088_DAI_WCI, reg14val); 1207 1208 reg15val = M98088_DAI_BSEL64; 1209 if (max98088->digmic) 1210 reg15val |= M98088_DAI_OSR64; 1211 snd_soc_component_write(component, M98088_REG_15_DAI1_CLOCK, reg15val); 1212 } 1213 1214 return 0; 1215 } 1216 1217 static int max98088_dai2_set_fmt(struct snd_soc_dai *codec_dai, 1218 unsigned int fmt) 1219 { 1220 struct snd_soc_component *component = codec_dai->component; 1221 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1222 struct max98088_cdata *cdata; 1223 u8 reg1Cval = 0; 1224 1225 cdata = &max98088->dai[1]; 1226 1227 if (fmt != cdata->fmt) { 1228 cdata->fmt = fmt; 1229 1230 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1231 case SND_SOC_DAIFMT_CBS_CFS: 1232 /* Slave mode PLL */ 1233 snd_soc_component_write(component, M98088_REG_1A_DAI2_CLKCFG_HI, 1234 0x80); 1235 snd_soc_component_write(component, M98088_REG_1B_DAI2_CLKCFG_LO, 1236 0x00); 1237 break; 1238 case SND_SOC_DAIFMT_CBM_CFM: 1239 /* Set to master mode */ 1240 reg1Cval |= M98088_DAI_MAS; 1241 break; 1242 case SND_SOC_DAIFMT_CBS_CFM: 1243 case SND_SOC_DAIFMT_CBM_CFS: 1244 default: 1245 dev_err(component->dev, "Clock mode unsupported"); 1246 return -EINVAL; 1247 } 1248 1249 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1250 case SND_SOC_DAIFMT_I2S: 1251 reg1Cval |= M98088_DAI_DLY; 1252 break; 1253 case SND_SOC_DAIFMT_LEFT_J: 1254 break; 1255 default: 1256 return -EINVAL; 1257 } 1258 1259 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1260 case SND_SOC_DAIFMT_NB_NF: 1261 break; 1262 case SND_SOC_DAIFMT_NB_IF: 1263 reg1Cval |= M98088_DAI_WCI; 1264 break; 1265 case SND_SOC_DAIFMT_IB_NF: 1266 reg1Cval |= M98088_DAI_BCI; 1267 break; 1268 case SND_SOC_DAIFMT_IB_IF: 1269 reg1Cval |= M98088_DAI_BCI|M98088_DAI_WCI; 1270 break; 1271 default: 1272 return -EINVAL; 1273 } 1274 1275 snd_soc_component_update_bits(component, M98088_REG_1C_DAI2_FORMAT, 1276 M98088_DAI_MAS | M98088_DAI_DLY | M98088_DAI_BCI | 1277 M98088_DAI_WCI, reg1Cval); 1278 1279 snd_soc_component_write(component, M98088_REG_1D_DAI2_CLOCK, 1280 M98088_DAI_BSEL64); 1281 } 1282 1283 return 0; 1284 } 1285 1286 static int max98088_dai1_mute(struct snd_soc_dai *codec_dai, int mute, 1287 int direction) 1288 { 1289 struct snd_soc_component *component = codec_dai->component; 1290 int reg; 1291 1292 if (mute) 1293 reg = M98088_DAI_MUTE; 1294 else 1295 reg = 0; 1296 1297 snd_soc_component_update_bits(component, M98088_REG_2F_LVL_DAI1_PLAY, 1298 M98088_DAI_MUTE_MASK, reg); 1299 return 0; 1300 } 1301 1302 static int max98088_dai2_mute(struct snd_soc_dai *codec_dai, int mute, 1303 int direction) 1304 { 1305 struct snd_soc_component *component = codec_dai->component; 1306 int reg; 1307 1308 if (mute) 1309 reg = M98088_DAI_MUTE; 1310 else 1311 reg = 0; 1312 1313 snd_soc_component_update_bits(component, M98088_REG_31_LVL_DAI2_PLAY, 1314 M98088_DAI_MUTE_MASK, reg); 1315 return 0; 1316 } 1317 1318 static int max98088_set_bias_level(struct snd_soc_component *component, 1319 enum snd_soc_bias_level level) 1320 { 1321 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1322 1323 switch (level) { 1324 case SND_SOC_BIAS_ON: 1325 break; 1326 1327 case SND_SOC_BIAS_PREPARE: 1328 /* 1329 * SND_SOC_BIAS_PREPARE is called while preparing for a 1330 * transition to ON or away from ON. If current bias_level 1331 * is SND_SOC_BIAS_ON, then it is preparing for a transition 1332 * away from ON. Disable the clock in that case, otherwise 1333 * enable it. 1334 */ 1335 if (!IS_ERR(max98088->mclk)) { 1336 if (snd_soc_component_get_bias_level(component) == 1337 SND_SOC_BIAS_ON) 1338 clk_disable_unprepare(max98088->mclk); 1339 else 1340 clk_prepare_enable(max98088->mclk); 1341 } 1342 break; 1343 1344 case SND_SOC_BIAS_STANDBY: 1345 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) 1346 regcache_sync(max98088->regmap); 1347 1348 snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN, 1349 M98088_MBEN, M98088_MBEN); 1350 break; 1351 1352 case SND_SOC_BIAS_OFF: 1353 snd_soc_component_update_bits(component, M98088_REG_4C_PWR_EN_IN, 1354 M98088_MBEN, 0); 1355 regcache_mark_dirty(max98088->regmap); 1356 break; 1357 } 1358 return 0; 1359 } 1360 1361 #define MAX98088_RATES SNDRV_PCM_RATE_8000_96000 1362 #define MAX98088_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) 1363 1364 static const struct snd_soc_dai_ops max98088_dai1_ops = { 1365 .set_sysclk = max98088_dai_set_sysclk, 1366 .set_fmt = max98088_dai1_set_fmt, 1367 .hw_params = max98088_dai1_hw_params, 1368 .mute_stream = max98088_dai1_mute, 1369 .no_capture_mute = 1, 1370 }; 1371 1372 static const struct snd_soc_dai_ops max98088_dai2_ops = { 1373 .set_sysclk = max98088_dai_set_sysclk, 1374 .set_fmt = max98088_dai2_set_fmt, 1375 .hw_params = max98088_dai2_hw_params, 1376 .mute_stream = max98088_dai2_mute, 1377 .no_capture_mute = 1, 1378 }; 1379 1380 static struct snd_soc_dai_driver max98088_dai[] = { 1381 { 1382 .name = "HiFi", 1383 .playback = { 1384 .stream_name = "HiFi Playback", 1385 .channels_min = 1, 1386 .channels_max = 2, 1387 .rates = MAX98088_RATES, 1388 .formats = MAX98088_FORMATS, 1389 }, 1390 .capture = { 1391 .stream_name = "HiFi Capture", 1392 .channels_min = 1, 1393 .channels_max = 2, 1394 .rates = MAX98088_RATES, 1395 .formats = MAX98088_FORMATS, 1396 }, 1397 .ops = &max98088_dai1_ops, 1398 }, 1399 { 1400 .name = "Aux", 1401 .playback = { 1402 .stream_name = "Aux Playback", 1403 .channels_min = 1, 1404 .channels_max = 2, 1405 .rates = MAX98088_RATES, 1406 .formats = MAX98088_FORMATS, 1407 }, 1408 .ops = &max98088_dai2_ops, 1409 } 1410 }; 1411 1412 static const char *eq_mode_name[] = {"EQ1 Mode", "EQ2 Mode"}; 1413 1414 static int max98088_get_channel(struct snd_soc_component *component, const char *name) 1415 { 1416 int ret; 1417 1418 ret = match_string(eq_mode_name, ARRAY_SIZE(eq_mode_name), name); 1419 if (ret < 0) 1420 dev_err(component->dev, "Bad EQ channel name '%s'\n", name); 1421 return ret; 1422 } 1423 1424 static void max98088_setup_eq1(struct snd_soc_component *component) 1425 { 1426 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1427 struct max98088_pdata *pdata = max98088->pdata; 1428 struct max98088_eq_cfg *coef_set; 1429 int best, best_val, save, i, sel, fs; 1430 struct max98088_cdata *cdata; 1431 1432 cdata = &max98088->dai[0]; 1433 1434 if (!pdata || !max98088->eq_textcnt) 1435 return; 1436 1437 /* Find the selected configuration with nearest sample rate */ 1438 fs = cdata->rate; 1439 sel = cdata->eq_sel; 1440 1441 best = 0; 1442 best_val = INT_MAX; 1443 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1444 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 && 1445 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1446 best = i; 1447 best_val = abs(pdata->eq_cfg[i].rate - fs); 1448 } 1449 } 1450 1451 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n", 1452 pdata->eq_cfg[best].name, 1453 pdata->eq_cfg[best].rate, fs); 1454 1455 /* Disable EQ while configuring, and save current on/off state */ 1456 save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL); 1457 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, 0); 1458 1459 coef_set = &pdata->eq_cfg[sel]; 1460 1461 m98088_eq_band(component, 0, 0, coef_set->band1); 1462 m98088_eq_band(component, 0, 1, coef_set->band2); 1463 m98088_eq_band(component, 0, 2, coef_set->band3); 1464 m98088_eq_band(component, 0, 3, coef_set->band4); 1465 m98088_eq_band(component, 0, 4, coef_set->band5); 1466 1467 /* Restore the original on/off state */ 1468 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ1EN, save); 1469 } 1470 1471 static void max98088_setup_eq2(struct snd_soc_component *component) 1472 { 1473 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1474 struct max98088_pdata *pdata = max98088->pdata; 1475 struct max98088_eq_cfg *coef_set; 1476 int best, best_val, save, i, sel, fs; 1477 struct max98088_cdata *cdata; 1478 1479 cdata = &max98088->dai[1]; 1480 1481 if (!pdata || !max98088->eq_textcnt) 1482 return; 1483 1484 /* Find the selected configuration with nearest sample rate */ 1485 fs = cdata->rate; 1486 1487 sel = cdata->eq_sel; 1488 best = 0; 1489 best_val = INT_MAX; 1490 for (i = 0; i < pdata->eq_cfgcnt; i++) { 1491 if (strcmp(pdata->eq_cfg[i].name, max98088->eq_texts[sel]) == 0 && 1492 abs(pdata->eq_cfg[i].rate - fs) < best_val) { 1493 best = i; 1494 best_val = abs(pdata->eq_cfg[i].rate - fs); 1495 } 1496 } 1497 1498 dev_dbg(component->dev, "Selected %s/%dHz for %dHz sample rate\n", 1499 pdata->eq_cfg[best].name, 1500 pdata->eq_cfg[best].rate, fs); 1501 1502 /* Disable EQ while configuring, and save current on/off state */ 1503 save = snd_soc_component_read(component, M98088_REG_49_CFG_LEVEL); 1504 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 0); 1505 1506 coef_set = &pdata->eq_cfg[sel]; 1507 1508 m98088_eq_band(component, 1, 0, coef_set->band1); 1509 m98088_eq_band(component, 1, 1, coef_set->band2); 1510 m98088_eq_band(component, 1, 2, coef_set->band3); 1511 m98088_eq_band(component, 1, 3, coef_set->band4); 1512 m98088_eq_band(component, 1, 4, coef_set->band5); 1513 1514 /* Restore the original on/off state */ 1515 snd_soc_component_update_bits(component, M98088_REG_49_CFG_LEVEL, M98088_EQ2EN, 1516 save); 1517 } 1518 1519 static int max98088_put_eq_enum(struct snd_kcontrol *kcontrol, 1520 struct snd_ctl_elem_value *ucontrol) 1521 { 1522 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1523 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1524 struct max98088_pdata *pdata = max98088->pdata; 1525 int channel = max98088_get_channel(component, kcontrol->id.name); 1526 struct max98088_cdata *cdata; 1527 int sel = ucontrol->value.enumerated.item[0]; 1528 1529 if (channel < 0) 1530 return channel; 1531 1532 cdata = &max98088->dai[channel]; 1533 1534 if (sel >= pdata->eq_cfgcnt) 1535 return -EINVAL; 1536 1537 cdata->eq_sel = sel; 1538 1539 switch (channel) { 1540 case 0: 1541 max98088_setup_eq1(component); 1542 break; 1543 case 1: 1544 max98088_setup_eq2(component); 1545 break; 1546 } 1547 1548 return 0; 1549 } 1550 1551 static int max98088_get_eq_enum(struct snd_kcontrol *kcontrol, 1552 struct snd_ctl_elem_value *ucontrol) 1553 { 1554 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1555 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1556 int channel = max98088_get_channel(component, kcontrol->id.name); 1557 struct max98088_cdata *cdata; 1558 1559 if (channel < 0) 1560 return channel; 1561 1562 cdata = &max98088->dai[channel]; 1563 ucontrol->value.enumerated.item[0] = cdata->eq_sel; 1564 return 0; 1565 } 1566 1567 static void max98088_handle_eq_pdata(struct snd_soc_component *component) 1568 { 1569 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1570 struct max98088_pdata *pdata = max98088->pdata; 1571 struct max98088_eq_cfg *cfg; 1572 unsigned int cfgcnt; 1573 int i, j; 1574 const char **t; 1575 int ret; 1576 struct snd_kcontrol_new controls[] = { 1577 SOC_ENUM_EXT((char *)eq_mode_name[0], 1578 max98088->eq_enum, 1579 max98088_get_eq_enum, 1580 max98088_put_eq_enum), 1581 SOC_ENUM_EXT((char *)eq_mode_name[1], 1582 max98088->eq_enum, 1583 max98088_get_eq_enum, 1584 max98088_put_eq_enum), 1585 }; 1586 BUILD_BUG_ON(ARRAY_SIZE(controls) != ARRAY_SIZE(eq_mode_name)); 1587 1588 cfg = pdata->eq_cfg; 1589 cfgcnt = pdata->eq_cfgcnt; 1590 1591 /* Setup an array of texts for the equalizer enum. 1592 * This is based on Mark Brown's equalizer driver code. 1593 */ 1594 max98088->eq_textcnt = 0; 1595 max98088->eq_texts = NULL; 1596 for (i = 0; i < cfgcnt; i++) { 1597 for (j = 0; j < max98088->eq_textcnt; j++) { 1598 if (strcmp(cfg[i].name, max98088->eq_texts[j]) == 0) 1599 break; 1600 } 1601 1602 if (j != max98088->eq_textcnt) 1603 continue; 1604 1605 /* Expand the array */ 1606 t = krealloc(max98088->eq_texts, 1607 sizeof(char *) * (max98088->eq_textcnt + 1), 1608 GFP_KERNEL); 1609 if (t == NULL) 1610 continue; 1611 1612 /* Store the new entry */ 1613 t[max98088->eq_textcnt] = cfg[i].name; 1614 max98088->eq_textcnt++; 1615 max98088->eq_texts = t; 1616 } 1617 1618 /* Now point the soc_enum to .texts array items */ 1619 max98088->eq_enum.texts = max98088->eq_texts; 1620 max98088->eq_enum.items = max98088->eq_textcnt; 1621 1622 ret = snd_soc_add_component_controls(component, controls, ARRAY_SIZE(controls)); 1623 if (ret != 0) 1624 dev_err(component->dev, "Failed to add EQ control: %d\n", ret); 1625 } 1626 1627 static void max98088_handle_pdata(struct snd_soc_component *component) 1628 { 1629 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1630 struct max98088_pdata *pdata = max98088->pdata; 1631 u8 regval = 0; 1632 1633 if (!pdata) { 1634 dev_dbg(component->dev, "No platform data\n"); 1635 return; 1636 } 1637 1638 /* Configure mic for analog/digital mic mode */ 1639 if (pdata->digmic_left_mode) 1640 regval |= M98088_DIGMIC_L; 1641 1642 if (pdata->digmic_right_mode) 1643 regval |= M98088_DIGMIC_R; 1644 1645 max98088->digmic = (regval ? 1 : 0); 1646 1647 snd_soc_component_write(component, M98088_REG_48_CFG_MIC, regval); 1648 1649 /* Configure receiver output */ 1650 regval = ((pdata->receiver_mode) ? M98088_REC_LINEMODE : 0); 1651 snd_soc_component_update_bits(component, M98088_REG_2A_MIC_REC_CNTL, 1652 M98088_REC_LINEMODE_MASK, regval); 1653 1654 /* Configure equalizers */ 1655 if (pdata->eq_cfgcnt) 1656 max98088_handle_eq_pdata(component); 1657 } 1658 1659 static int max98088_probe(struct snd_soc_component *component) 1660 { 1661 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1662 struct max98088_cdata *cdata; 1663 int ret = 0; 1664 1665 regcache_mark_dirty(max98088->regmap); 1666 1667 /* initialize private data */ 1668 1669 max98088->sysclk = (unsigned)-1; 1670 max98088->eq_textcnt = 0; 1671 1672 cdata = &max98088->dai[0]; 1673 cdata->rate = (unsigned)-1; 1674 cdata->fmt = (unsigned)-1; 1675 cdata->eq_sel = 0; 1676 1677 cdata = &max98088->dai[1]; 1678 cdata->rate = (unsigned)-1; 1679 cdata->fmt = (unsigned)-1; 1680 cdata->eq_sel = 0; 1681 1682 max98088->ina_state = 0; 1683 max98088->inb_state = 0; 1684 max98088->ex_mode = 0; 1685 max98088->digmic = 0; 1686 max98088->mic1pre = 0; 1687 max98088->mic2pre = 0; 1688 1689 ret = snd_soc_component_read(component, M98088_REG_FF_REV_ID); 1690 if (ret < 0) { 1691 dev_err(component->dev, "Failed to read device revision: %d\n", 1692 ret); 1693 goto err_access; 1694 } 1695 dev_info(component->dev, "revision %c\n", ret - 0x40 + 'A'); 1696 1697 snd_soc_component_write(component, M98088_REG_51_PWR_SYS, M98088_PWRSV); 1698 1699 snd_soc_component_write(component, M98088_REG_0F_IRQ_ENABLE, 0x00); 1700 1701 snd_soc_component_write(component, M98088_REG_22_MIX_DAC, 1702 M98088_DAI1L_TO_DACL|M98088_DAI2L_TO_DACL| 1703 M98088_DAI1R_TO_DACR|M98088_DAI2R_TO_DACR); 1704 1705 snd_soc_component_write(component, M98088_REG_4E_BIAS_CNTL, 0xF0); 1706 snd_soc_component_write(component, M98088_REG_50_DAC_BIAS2, 0x0F); 1707 1708 snd_soc_component_write(component, M98088_REG_16_DAI1_IOCFG, 1709 M98088_S1NORMAL|M98088_SDATA); 1710 1711 snd_soc_component_write(component, M98088_REG_1E_DAI2_IOCFG, 1712 M98088_S2NORMAL|M98088_SDATA); 1713 1714 max98088_handle_pdata(component); 1715 1716 err_access: 1717 return ret; 1718 } 1719 1720 static void max98088_remove(struct snd_soc_component *component) 1721 { 1722 struct max98088_priv *max98088 = snd_soc_component_get_drvdata(component); 1723 1724 kfree(max98088->eq_texts); 1725 } 1726 1727 static const struct snd_soc_component_driver soc_component_dev_max98088 = { 1728 .probe = max98088_probe, 1729 .remove = max98088_remove, 1730 .set_bias_level = max98088_set_bias_level, 1731 .controls = max98088_snd_controls, 1732 .num_controls = ARRAY_SIZE(max98088_snd_controls), 1733 .dapm_widgets = max98088_dapm_widgets, 1734 .num_dapm_widgets = ARRAY_SIZE(max98088_dapm_widgets), 1735 .dapm_routes = max98088_audio_map, 1736 .num_dapm_routes = ARRAY_SIZE(max98088_audio_map), 1737 .suspend_bias_off = 1, 1738 .idle_bias_on = 1, 1739 .use_pmdown_time = 1, 1740 .endianness = 1, 1741 .non_legacy_dai_naming = 1, 1742 }; 1743 1744 static int max98088_i2c_probe(struct i2c_client *i2c, 1745 const struct i2c_device_id *id) 1746 { 1747 struct max98088_priv *max98088; 1748 int ret; 1749 1750 max98088 = devm_kzalloc(&i2c->dev, sizeof(struct max98088_priv), 1751 GFP_KERNEL); 1752 if (max98088 == NULL) 1753 return -ENOMEM; 1754 1755 max98088->regmap = devm_regmap_init_i2c(i2c, &max98088_regmap); 1756 if (IS_ERR(max98088->regmap)) 1757 return PTR_ERR(max98088->regmap); 1758 1759 max98088->mclk = devm_clk_get(&i2c->dev, "mclk"); 1760 if (IS_ERR(max98088->mclk)) 1761 if (PTR_ERR(max98088->mclk) == -EPROBE_DEFER) 1762 return PTR_ERR(max98088->mclk); 1763 1764 max98088->devtype = id->driver_data; 1765 1766 i2c_set_clientdata(i2c, max98088); 1767 max98088->pdata = i2c->dev.platform_data; 1768 1769 ret = devm_snd_soc_register_component(&i2c->dev, 1770 &soc_component_dev_max98088, &max98088_dai[0], 2); 1771 return ret; 1772 } 1773 1774 static const struct i2c_device_id max98088_i2c_id[] = { 1775 { "max98088", MAX98088 }, 1776 { "max98089", MAX98089 }, 1777 { } 1778 }; 1779 MODULE_DEVICE_TABLE(i2c, max98088_i2c_id); 1780 1781 #if defined(CONFIG_OF) 1782 static const struct of_device_id max98088_of_match[] = { 1783 { .compatible = "maxim,max98088" }, 1784 { .compatible = "maxim,max98089" }, 1785 { } 1786 }; 1787 MODULE_DEVICE_TABLE(of, max98088_of_match); 1788 #endif 1789 1790 static struct i2c_driver max98088_i2c_driver = { 1791 .driver = { 1792 .name = "max98088", 1793 .of_match_table = of_match_ptr(max98088_of_match), 1794 }, 1795 .probe = max98088_i2c_probe, 1796 .id_table = max98088_i2c_id, 1797 }; 1798 1799 module_i2c_driver(max98088_i2c_driver); 1800 1801 MODULE_DESCRIPTION("ALSA SoC MAX98088 driver"); 1802 MODULE_AUTHOR("Peter Hsiang, Jesse Marroquin"); 1803 MODULE_LICENSE("GPL"); 1804