1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/init.h> 6 #include <linux/io.h> 7 #include <linux/platform_device.h> 8 #include <linux/clk.h> 9 #include <linux/of_clk.h> 10 #include <linux/clk-provider.h> 11 #include <sound/soc.h> 12 #include <sound/soc-dapm.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/of_platform.h> 15 #include <sound/tlv.h> 16 #include "lpass-wsa-macro.h" 17 18 #define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 19 #define CDC_WSA_MCLK_EN_MASK BIT(0) 20 #define CDC_WSA_MCLK_ENABLE BIT(0) 21 #define CDC_WSA_MCLK_DISABLE 0 22 #define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 23 #define CDC_WSA_FS_CNT_EN_MASK BIT(0) 24 #define CDC_WSA_FS_CNT_ENABLE BIT(0) 25 #define CDC_WSA_FS_CNT_DISABLE 0 26 #define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL (0x0008) 27 #define CDC_WSA_SWR_CLK_EN_MASK BIT(0) 28 #define CDC_WSA_SWR_CLK_ENABLE BIT(0) 29 #define CDC_WSA_SWR_RST_EN_MASK BIT(1) 30 #define CDC_WSA_SWR_RST_ENABLE BIT(1) 31 #define CDC_WSA_SWR_RST_DISABLE 0 32 #define CDC_WSA_TOP_TOP_CFG0 (0x0080) 33 #define CDC_WSA_TOP_TOP_CFG1 (0x0084) 34 #define CDC_WSA_TOP_FREQ_MCLK (0x0088) 35 #define CDC_WSA_TOP_DEBUG_BUS_SEL (0x008C) 36 #define CDC_WSA_TOP_DEBUG_EN0 (0x0090) 37 #define CDC_WSA_TOP_DEBUG_EN1 (0x0094) 38 #define CDC_WSA_TOP_DEBUG_DSM_LB (0x0098) 39 #define CDC_WSA_TOP_RX_I2S_CTL (0x009C) 40 #define CDC_WSA_TOP_TX_I2S_CTL (0x00A0) 41 #define CDC_WSA_TOP_I2S_CLK (0x00A4) 42 #define CDC_WSA_TOP_I2S_RESET (0x00A8) 43 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 (0x0100) 44 #define CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(2, 0) 45 #define CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(5, 3) 46 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 (0x0104) 47 #define CDC_WSA_RX_INTX_2_SEL_MASK GENMASK(2, 0) 48 #define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(5, 3) 49 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 (0x0108) 50 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 (0x010C) 51 #define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 (0x0110) 52 #define CDC_WSA_RX_MIX_TX1_SEL_MASK GENMASK(5, 3) 53 #define CDC_WSA_RX_MIX_TX1_SEL_SHFT 3 54 #define CDC_WSA_RX_MIX_TX0_SEL_MASK GENMASK(2, 0) 55 #define CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (0x0114) 56 #define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (0x0118) 57 #define CDC_WSA_TX0_SPKR_PROT_PATH_CTL (0x0244) 58 #define CDC_WSA_TX_SPKR_PROT_RESET_MASK BIT(5) 59 #define CDC_WSA_TX_SPKR_PROT_RESET BIT(5) 60 #define CDC_WSA_TX_SPKR_PROT_NO_RESET 0 61 #define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK BIT(4) 62 #define CDC_WSA_TX_SPKR_PROT_CLK_ENABLE BIT(4) 63 #define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0 64 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0) 65 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K 0 66 #define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (0x0248) 67 #define CDC_WSA_TX1_SPKR_PROT_PATH_CTL (0x0264) 68 #define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (0x0268) 69 #define CDC_WSA_TX2_SPKR_PROT_PATH_CTL (0x0284) 70 #define CDC_WSA_TX2_SPKR_PROT_PATH_CFG0 (0x0288) 71 #define CDC_WSA_TX3_SPKR_PROT_PATH_CTL (0x02A4) 72 #define CDC_WSA_TX3_SPKR_PROT_PATH_CFG0 (0x02A8) 73 #define CDC_WSA_INTR_CTRL_CFG (0x0340) 74 #define CDC_WSA_INTR_CTRL_CLR_COMMIT (0x0344) 75 #define CDC_WSA_INTR_CTRL_PIN1_MASK0 (0x0360) 76 #define CDC_WSA_INTR_CTRL_PIN1_STATUS0 (0x0368) 77 #define CDC_WSA_INTR_CTRL_PIN1_CLEAR0 (0x0370) 78 #define CDC_WSA_INTR_CTRL_PIN2_MASK0 (0x0380) 79 #define CDC_WSA_INTR_CTRL_PIN2_STATUS0 (0x0388) 80 #define CDC_WSA_INTR_CTRL_PIN2_CLEAR0 (0x0390) 81 #define CDC_WSA_INTR_CTRL_LEVEL0 (0x03C0) 82 #define CDC_WSA_INTR_CTRL_BYPASS0 (0x03C8) 83 #define CDC_WSA_INTR_CTRL_SET0 (0x03D0) 84 #define CDC_WSA_RX0_RX_PATH_CTL (0x0400) 85 #define CDC_WSA_RX_PATH_CLK_EN_MASK BIT(5) 86 #define CDC_WSA_RX_PATH_CLK_ENABLE BIT(5) 87 #define CDC_WSA_RX_PATH_CLK_DISABLE 0 88 #define CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK BIT(4) 89 #define CDC_WSA_RX_PATH_PGA_MUTE_ENABLE BIT(4) 90 #define CDC_WSA_RX_PATH_PGA_MUTE_DISABLE 0 91 #define CDC_WSA_RX0_RX_PATH_CFG0 (0x0404) 92 #define CDC_WSA_RX_PATH_COMP_EN_MASK BIT(1) 93 #define CDC_WSA_RX_PATH_COMP_ENABLE BIT(1) 94 #define CDC_WSA_RX_PATH_HD2_EN_MASK BIT(2) 95 #define CDC_WSA_RX_PATH_HD2_ENABLE BIT(2) 96 #define CDC_WSA_RX_PATH_SPKR_RATE_MASK BIT(3) 97 #define CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072 BIT(3) 98 #define CDC_WSA_RX0_RX_PATH_CFG1 (0x0408) 99 #define CDC_WSA_RX_PATH_SMART_BST_EN_MASK BIT(0) 100 #define CDC_WSA_RX_PATH_SMART_BST_ENABLE BIT(0) 101 #define CDC_WSA_RX_PATH_SMART_BST_DISABLE 0 102 #define CDC_WSA_RX0_RX_PATH_CFG2 (0x040C) 103 #define CDC_WSA_RX0_RX_PATH_CFG3 (0x0410) 104 #define CDC_WSA_RX_DC_DCOEFF_MASK GENMASK(1, 0) 105 #define CDC_WSA_RX0_RX_VOL_CTL (0x0414) 106 #define CDC_WSA_RX0_RX_PATH_MIX_CTL (0x0418) 107 #define CDC_WSA_RX_PATH_MIX_CLK_EN_MASK BIT(5) 108 #define CDC_WSA_RX_PATH_MIX_CLK_ENABLE BIT(5) 109 #define CDC_WSA_RX_PATH_MIX_CLK_DISABLE 0 110 #define CDC_WSA_RX0_RX_PATH_MIX_CFG (0x041C) 111 #define CDC_WSA_RX0_RX_VOL_MIX_CTL (0x0420) 112 #define CDC_WSA_RX0_RX_PATH_SEC0 (0x0424) 113 #define CDC_WSA_RX0_RX_PATH_SEC1 (0x0428) 114 #define CDC_WSA_RX_PGA_HALF_DB_MASK BIT(0) 115 #define CDC_WSA_RX_PGA_HALF_DB_ENABLE BIT(0) 116 #define CDC_WSA_RX_PGA_HALF_DB_DISABLE 0 117 #define CDC_WSA_RX0_RX_PATH_SEC2 (0x042C) 118 #define CDC_WSA_RX0_RX_PATH_SEC3 (0x0430) 119 #define CDC_WSA_RX_PATH_HD2_SCALE_MASK GENMASK(1, 0) 120 #define CDC_WSA_RX_PATH_HD2_ALPHA_MASK GENMASK(5, 2) 121 #define CDC_WSA_RX0_RX_PATH_SEC5 (0x0438) 122 #define CDC_WSA_RX0_RX_PATH_SEC6 (0x043C) 123 #define CDC_WSA_RX0_RX_PATH_SEC7 (0x0440) 124 #define CDC_WSA_RX0_RX_PATH_MIX_SEC0 (0x0444) 125 #define CDC_WSA_RX0_RX_PATH_MIX_SEC1 (0x0448) 126 #define CDC_WSA_RX0_RX_PATH_DSMDEM_CTL (0x044C) 127 #define CDC_WSA_RX_DSMDEM_CLK_EN_MASK BIT(0) 128 #define CDC_WSA_RX_DSMDEM_CLK_ENABLE BIT(0) 129 #define CDC_WSA_RX1_RX_PATH_CTL (0x0480) 130 #define CDC_WSA_RX1_RX_PATH_CFG0 (0x0484) 131 #define CDC_WSA_RX1_RX_PATH_CFG1 (0x0488) 132 #define CDC_WSA_RX1_RX_PATH_CFG2 (0x048C) 133 #define CDC_WSA_RX1_RX_PATH_CFG3 (0x0490) 134 #define CDC_WSA_RX1_RX_VOL_CTL (0x0494) 135 #define CDC_WSA_RX1_RX_PATH_MIX_CTL (0x0498) 136 #define CDC_WSA_RX1_RX_PATH_MIX_CFG (0x049C) 137 #define CDC_WSA_RX1_RX_VOL_MIX_CTL (0x04A0) 138 #define CDC_WSA_RX1_RX_PATH_SEC0 (0x04A4) 139 #define CDC_WSA_RX1_RX_PATH_SEC1 (0x04A8) 140 #define CDC_WSA_RX1_RX_PATH_SEC2 (0x04AC) 141 #define CDC_WSA_RX1_RX_PATH_SEC3 (0x04B0) 142 #define CDC_WSA_RX1_RX_PATH_SEC5 (0x04B8) 143 #define CDC_WSA_RX1_RX_PATH_SEC6 (0x04BC) 144 #define CDC_WSA_RX1_RX_PATH_SEC7 (0x04C0) 145 #define CDC_WSA_RX1_RX_PATH_MIX_SEC0 (0x04C4) 146 #define CDC_WSA_RX1_RX_PATH_MIX_SEC1 (0x04C8) 147 #define CDC_WSA_RX1_RX_PATH_DSMDEM_CTL (0x04CC) 148 #define CDC_WSA_BOOST0_BOOST_PATH_CTL (0x0500) 149 #define CDC_WSA_BOOST_PATH_CLK_EN_MASK BIT(4) 150 #define CDC_WSA_BOOST_PATH_CLK_ENABLE BIT(4) 151 #define CDC_WSA_BOOST_PATH_CLK_DISABLE 0 152 #define CDC_WSA_BOOST0_BOOST_CTL (0x0504) 153 #define CDC_WSA_BOOST0_BOOST_CFG1 (0x0508) 154 #define CDC_WSA_BOOST0_BOOST_CFG2 (0x050C) 155 #define CDC_WSA_BOOST1_BOOST_PATH_CTL (0x0540) 156 #define CDC_WSA_BOOST1_BOOST_CTL (0x0544) 157 #define CDC_WSA_BOOST1_BOOST_CFG1 (0x0548) 158 #define CDC_WSA_BOOST1_BOOST_CFG2 (0x054C) 159 #define CDC_WSA_COMPANDER0_CTL0 (0x0580) 160 #define CDC_WSA_COMPANDER_CLK_EN_MASK BIT(0) 161 #define CDC_WSA_COMPANDER_CLK_ENABLE BIT(0) 162 #define CDC_WSA_COMPANDER_SOFT_RST_MASK BIT(1) 163 #define CDC_WSA_COMPANDER_SOFT_RST_ENABLE BIT(1) 164 #define CDC_WSA_COMPANDER_HALT_MASK BIT(2) 165 #define CDC_WSA_COMPANDER_HALT BIT(2) 166 #define CDC_WSA_COMPANDER0_CTL1 (0x0584) 167 #define CDC_WSA_COMPANDER0_CTL2 (0x0588) 168 #define CDC_WSA_COMPANDER0_CTL3 (0x058C) 169 #define CDC_WSA_COMPANDER0_CTL4 (0x0590) 170 #define CDC_WSA_COMPANDER0_CTL5 (0x0594) 171 #define CDC_WSA_COMPANDER0_CTL6 (0x0598) 172 #define CDC_WSA_COMPANDER0_CTL7 (0x059C) 173 #define CDC_WSA_COMPANDER1_CTL0 (0x05C0) 174 #define CDC_WSA_COMPANDER1_CTL1 (0x05C4) 175 #define CDC_WSA_COMPANDER1_CTL2 (0x05C8) 176 #define CDC_WSA_COMPANDER1_CTL3 (0x05CC) 177 #define CDC_WSA_COMPANDER1_CTL4 (0x05D0) 178 #define CDC_WSA_COMPANDER1_CTL5 (0x05D4) 179 #define CDC_WSA_COMPANDER1_CTL6 (0x05D8) 180 #define CDC_WSA_COMPANDER1_CTL7 (0x05DC) 181 #define CDC_WSA_SOFTCLIP0_CRC (0x0600) 182 #define CDC_WSA_SOFTCLIP_CLK_EN_MASK BIT(0) 183 #define CDC_WSA_SOFTCLIP_CLK_ENABLE BIT(0) 184 #define CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (0x0604) 185 #define CDC_WSA_SOFTCLIP_EN_MASK BIT(0) 186 #define CDC_WSA_SOFTCLIP_ENABLE BIT(0) 187 #define CDC_WSA_SOFTCLIP1_CRC (0x0640) 188 #define CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (0x0644) 189 #define CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL (0x0680) 190 #define CDC_WSA_EC_HQ_EC_CLK_EN_MASK BIT(0) 191 #define CDC_WSA_EC_HQ_EC_CLK_ENABLE BIT(0) 192 #define CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 (0x0684) 193 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK GENMASK(4, 1) 194 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K BIT(3) 195 #define CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL (0x06C0) 196 #define CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 (0x06C4) 197 #define CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL (0x0700) 198 #define CDC_WSA_SPLINE_ASRC0_CTL0 (0x0704) 199 #define CDC_WSA_SPLINE_ASRC0_CTL1 (0x0708) 200 #define CDC_WSA_SPLINE_ASRC0_FIFO_CTL (0x070C) 201 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB (0x0710) 202 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB (0x0714) 203 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB (0x0718) 204 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB (0x071C) 205 #define CDC_WSA_SPLINE_ASRC0_STATUS_FIFO (0x0720) 206 #define CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL (0x0740) 207 #define CDC_WSA_SPLINE_ASRC1_CTL0 (0x0744) 208 #define CDC_WSA_SPLINE_ASRC1_CTL1 (0x0748) 209 #define CDC_WSA_SPLINE_ASRC1_FIFO_CTL (0x074C) 210 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB (0x0750) 211 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB (0x0754) 212 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB (0x0758) 213 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB (0x075C) 214 #define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO (0x0760) 215 #define WSA_MAX_OFFSET (0x0760) 216 217 #define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 218 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 219 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 220 #define WSA_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\ 221 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 222 #define WSA_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 223 SNDRV_PCM_FMTBIT_S24_LE |\ 224 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 225 226 #define WSA_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 227 SNDRV_PCM_RATE_48000) 228 #define WSA_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 229 SNDRV_PCM_FMTBIT_S24_LE |\ 230 SNDRV_PCM_FMTBIT_S24_3LE) 231 232 #define NUM_INTERPOLATORS 2 233 #define WSA_NUM_CLKS_MAX 5 234 #define WSA_MACRO_MCLK_FREQ 19200000 235 #define WSA_MACRO_MUX_INP_MASK2 0x38 236 #define WSA_MACRO_MUX_CFG_OFFSET 0x8 237 #define WSA_MACRO_MUX_CFG1_OFFSET 0x4 238 #define WSA_MACRO_RX_COMP_OFFSET 0x40 239 #define WSA_MACRO_RX_SOFTCLIP_OFFSET 0x40 240 #define WSA_MACRO_RX_PATH_OFFSET 0x80 241 #define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10 242 #define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C 243 #define WSA_MACRO_FS_RATE_MASK 0x0F 244 #define WSA_MACRO_EC_MIX_TX0_MASK 0x03 245 #define WSA_MACRO_EC_MIX_TX1_MASK 0x18 246 #define WSA_MACRO_MAX_DMA_CH_PER_PORT 0x2 247 248 enum { 249 WSA_MACRO_GAIN_OFFSET_M1P5_DB, 250 WSA_MACRO_GAIN_OFFSET_0_DB, 251 }; 252 enum { 253 WSA_MACRO_RX0 = 0, 254 WSA_MACRO_RX1, 255 WSA_MACRO_RX_MIX, 256 WSA_MACRO_RX_MIX0 = WSA_MACRO_RX_MIX, 257 WSA_MACRO_RX_MIX1, 258 WSA_MACRO_RX_MAX, 259 }; 260 261 enum { 262 WSA_MACRO_TX0 = 0, 263 WSA_MACRO_TX1, 264 WSA_MACRO_TX_MAX, 265 }; 266 267 enum { 268 WSA_MACRO_EC0_MUX = 0, 269 WSA_MACRO_EC1_MUX, 270 WSA_MACRO_EC_MUX_MAX, 271 }; 272 273 enum { 274 WSA_MACRO_COMP1, /* SPK_L */ 275 WSA_MACRO_COMP2, /* SPK_R */ 276 WSA_MACRO_COMP_MAX 277 }; 278 279 enum { 280 WSA_MACRO_SOFTCLIP0, /* RX0 */ 281 WSA_MACRO_SOFTCLIP1, /* RX1 */ 282 WSA_MACRO_SOFTCLIP_MAX 283 }; 284 285 enum { 286 INTn_1_INP_SEL_ZERO = 0, 287 INTn_1_INP_SEL_RX0, 288 INTn_1_INP_SEL_RX1, 289 INTn_1_INP_SEL_RX2, 290 INTn_1_INP_SEL_RX3, 291 INTn_1_INP_SEL_DEC0, 292 INTn_1_INP_SEL_DEC1, 293 }; 294 295 enum { 296 INTn_2_INP_SEL_ZERO = 0, 297 INTn_2_INP_SEL_RX0, 298 INTn_2_INP_SEL_RX1, 299 INTn_2_INP_SEL_RX2, 300 INTn_2_INP_SEL_RX3, 301 }; 302 303 struct interp_sample_rate { 304 int sample_rate; 305 int rate_val; 306 }; 307 308 static struct interp_sample_rate int_prim_sample_rate_val[] = { 309 {8000, 0x0}, /* 8K */ 310 {16000, 0x1}, /* 16K */ 311 {24000, -EINVAL},/* 24K */ 312 {32000, 0x3}, /* 32K */ 313 {48000, 0x4}, /* 48K */ 314 {96000, 0x5}, /* 96K */ 315 {192000, 0x6}, /* 192K */ 316 {384000, 0x7}, /* 384K */ 317 {44100, 0x8}, /* 44.1K */ 318 }; 319 320 static struct interp_sample_rate int_mix_sample_rate_val[] = { 321 {48000, 0x4}, /* 48K */ 322 {96000, 0x5}, /* 96K */ 323 {192000, 0x6}, /* 192K */ 324 }; 325 326 enum { 327 WSA_MACRO_AIF_INVALID = 0, 328 WSA_MACRO_AIF1_PB, 329 WSA_MACRO_AIF_MIX1_PB, 330 WSA_MACRO_AIF_VI, 331 WSA_MACRO_AIF_ECHO, 332 WSA_MACRO_MAX_DAIS, 333 }; 334 335 struct wsa_macro { 336 struct device *dev; 337 int comp_enabled[WSA_MACRO_COMP_MAX]; 338 int ec_hq[WSA_MACRO_RX1 + 1]; 339 u16 prim_int_users[WSA_MACRO_RX1 + 1]; 340 u16 wsa_mclk_users; 341 unsigned long active_ch_mask[WSA_MACRO_MAX_DAIS]; 342 unsigned long active_ch_cnt[WSA_MACRO_MAX_DAIS]; 343 int rx_port_value[WSA_MACRO_RX_MAX]; 344 int ear_spkr_gain; 345 int spkr_gain_offset; 346 int spkr_mode; 347 int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX]; 348 int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX]; 349 struct regmap *regmap; 350 struct clk *mclk; 351 struct clk *npl; 352 struct clk *macro; 353 struct clk *dcodec; 354 struct clk *fsgen; 355 struct clk_hw hw; 356 }; 357 #define to_wsa_macro(_hw) container_of(_hw, struct wsa_macro, hw) 358 359 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 360 361 static const char *const rx_text[] = { 362 "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "DEC0", "DEC1" 363 }; 364 365 static const char *const rx_mix_text[] = { 366 "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1" 367 }; 368 369 static const char *const rx_mix_ec_text[] = { 370 "ZERO", "RX_MIX_TX0", "RX_MIX_TX1" 371 }; 372 373 static const char *const rx_mux_text[] = { 374 "ZERO", "AIF1_PB", "AIF_MIX1_PB" 375 }; 376 377 static const char *const rx_sidetone_mix_text[] = { 378 "ZERO", "SRC0" 379 }; 380 381 static const char * const wsa_macro_ear_spkr_pa_gain_text[] = { 382 "G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB", 383 "G_4_DB", "G_5_DB", "G_6_DB" 384 }; 385 386 static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum, 387 wsa_macro_ear_spkr_pa_gain_text); 388 389 /* RX INT0 */ 390 static const struct soc_enum rx0_prim_inp0_chain_enum = 391 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 392 0, 7, rx_text); 393 394 static const struct soc_enum rx0_prim_inp1_chain_enum = 395 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 396 3, 7, rx_text); 397 398 static const struct soc_enum rx0_prim_inp2_chain_enum = 399 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 400 3, 7, rx_text); 401 402 static const struct soc_enum rx0_mix_chain_enum = 403 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 404 0, 5, rx_mix_text); 405 406 static const struct soc_enum rx0_sidetone_mix_enum = 407 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text); 408 409 static const struct snd_kcontrol_new rx0_prim_inp0_mux = 410 SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum); 411 412 static const struct snd_kcontrol_new rx0_prim_inp1_mux = 413 SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum); 414 415 static const struct snd_kcontrol_new rx0_prim_inp2_mux = 416 SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum); 417 418 static const struct snd_kcontrol_new rx0_mix_mux = 419 SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum); 420 421 static const struct snd_kcontrol_new rx0_sidetone_mix_mux = 422 SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum); 423 424 /* RX INT1 */ 425 static const struct soc_enum rx1_prim_inp0_chain_enum = 426 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 427 0, 7, rx_text); 428 429 static const struct soc_enum rx1_prim_inp1_chain_enum = 430 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 431 3, 7, rx_text); 432 433 static const struct soc_enum rx1_prim_inp2_chain_enum = 434 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 435 3, 7, rx_text); 436 437 static const struct soc_enum rx1_mix_chain_enum = 438 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 439 0, 5, rx_mix_text); 440 441 static const struct snd_kcontrol_new rx1_prim_inp0_mux = 442 SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum); 443 444 static const struct snd_kcontrol_new rx1_prim_inp1_mux = 445 SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum); 446 447 static const struct snd_kcontrol_new rx1_prim_inp2_mux = 448 SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum); 449 450 static const struct snd_kcontrol_new rx1_mix_mux = 451 SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum); 452 453 static const struct soc_enum rx_mix_ec0_enum = 454 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 455 0, 3, rx_mix_ec_text); 456 457 static const struct soc_enum rx_mix_ec1_enum = 458 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 459 3, 3, rx_mix_ec_text); 460 461 static const struct snd_kcontrol_new rx_mix_ec0_mux = 462 SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum); 463 464 static const struct snd_kcontrol_new rx_mix_ec1_mux = 465 SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum); 466 467 static const struct reg_default wsa_defaults[] = { 468 /* WSA Macro */ 469 { CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, 470 { CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, 471 { CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 472 { CDC_WSA_TOP_TOP_CFG0, 0x00}, 473 { CDC_WSA_TOP_TOP_CFG1, 0x00}, 474 { CDC_WSA_TOP_FREQ_MCLK, 0x00}, 475 { CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00}, 476 { CDC_WSA_TOP_DEBUG_EN0, 0x00}, 477 { CDC_WSA_TOP_DEBUG_EN1, 0x00}, 478 { CDC_WSA_TOP_DEBUG_DSM_LB, 0x88}, 479 { CDC_WSA_TOP_RX_I2S_CTL, 0x0C}, 480 { CDC_WSA_TOP_TX_I2S_CTL, 0x0C}, 481 { CDC_WSA_TOP_I2S_CLK, 0x02}, 482 { CDC_WSA_TOP_I2S_RESET, 0x00}, 483 { CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00}, 484 { CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00}, 485 { CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00}, 486 { CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00}, 487 { CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00}, 488 { CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00}, 489 { CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00}, 490 { CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02}, 491 { CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00}, 492 { CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02}, 493 { CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00}, 494 { CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02}, 495 { CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00}, 496 { CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02}, 497 { CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00}, 498 { CDC_WSA_INTR_CTRL_CFG, 0x00}, 499 { CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00}, 500 { CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF}, 501 { CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00}, 502 { CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00}, 503 { CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF}, 504 { CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00}, 505 { CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00}, 506 { CDC_WSA_INTR_CTRL_LEVEL0, 0x00}, 507 { CDC_WSA_INTR_CTRL_BYPASS0, 0x00}, 508 { CDC_WSA_INTR_CTRL_SET0, 0x00}, 509 { CDC_WSA_RX0_RX_PATH_CTL, 0x04}, 510 { CDC_WSA_RX0_RX_PATH_CFG0, 0x00}, 511 { CDC_WSA_RX0_RX_PATH_CFG1, 0x64}, 512 { CDC_WSA_RX0_RX_PATH_CFG2, 0x8F}, 513 { CDC_WSA_RX0_RX_PATH_CFG3, 0x00}, 514 { CDC_WSA_RX0_RX_VOL_CTL, 0x00}, 515 { CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04}, 516 { CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E}, 517 { CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00}, 518 { CDC_WSA_RX0_RX_PATH_SEC0, 0x04}, 519 { CDC_WSA_RX0_RX_PATH_SEC1, 0x08}, 520 { CDC_WSA_RX0_RX_PATH_SEC2, 0x00}, 521 { CDC_WSA_RX0_RX_PATH_SEC3, 0x00}, 522 { CDC_WSA_RX0_RX_PATH_SEC5, 0x00}, 523 { CDC_WSA_RX0_RX_PATH_SEC6, 0x00}, 524 { CDC_WSA_RX0_RX_PATH_SEC7, 0x00}, 525 { CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08}, 526 { CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00}, 527 { CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00}, 528 { CDC_WSA_RX1_RX_PATH_CFG0, 0x00}, 529 { CDC_WSA_RX1_RX_PATH_CFG1, 0x64}, 530 { CDC_WSA_RX1_RX_PATH_CFG2, 0x8F}, 531 { CDC_WSA_RX1_RX_PATH_CFG3, 0x00}, 532 { CDC_WSA_RX1_RX_VOL_CTL, 0x00}, 533 { CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04}, 534 { CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E}, 535 { CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00}, 536 { CDC_WSA_RX1_RX_PATH_SEC0, 0x04}, 537 { CDC_WSA_RX1_RX_PATH_SEC1, 0x08}, 538 { CDC_WSA_RX1_RX_PATH_SEC2, 0x00}, 539 { CDC_WSA_RX1_RX_PATH_SEC3, 0x00}, 540 { CDC_WSA_RX1_RX_PATH_SEC5, 0x00}, 541 { CDC_WSA_RX1_RX_PATH_SEC6, 0x00}, 542 { CDC_WSA_RX1_RX_PATH_SEC7, 0x00}, 543 { CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08}, 544 { CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00}, 545 { CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00}, 546 { CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00}, 547 { CDC_WSA_BOOST0_BOOST_CTL, 0xD0}, 548 { CDC_WSA_BOOST0_BOOST_CFG1, 0x89}, 549 { CDC_WSA_BOOST0_BOOST_CFG2, 0x04}, 550 { CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00}, 551 { CDC_WSA_BOOST1_BOOST_CTL, 0xD0}, 552 { CDC_WSA_BOOST1_BOOST_CFG1, 0x89}, 553 { CDC_WSA_BOOST1_BOOST_CFG2, 0x04}, 554 { CDC_WSA_COMPANDER0_CTL0, 0x60}, 555 { CDC_WSA_COMPANDER0_CTL1, 0xDB}, 556 { CDC_WSA_COMPANDER0_CTL2, 0xFF}, 557 { CDC_WSA_COMPANDER0_CTL3, 0x35}, 558 { CDC_WSA_COMPANDER0_CTL4, 0xFF}, 559 { CDC_WSA_COMPANDER0_CTL5, 0x00}, 560 { CDC_WSA_COMPANDER0_CTL6, 0x01}, 561 { CDC_WSA_COMPANDER0_CTL7, 0x28}, 562 { CDC_WSA_COMPANDER1_CTL0, 0x60}, 563 { CDC_WSA_COMPANDER1_CTL1, 0xDB}, 564 { CDC_WSA_COMPANDER1_CTL2, 0xFF}, 565 { CDC_WSA_COMPANDER1_CTL3, 0x35}, 566 { CDC_WSA_COMPANDER1_CTL4, 0xFF}, 567 { CDC_WSA_COMPANDER1_CTL5, 0x00}, 568 { CDC_WSA_COMPANDER1_CTL6, 0x01}, 569 { CDC_WSA_COMPANDER1_CTL7, 0x28}, 570 { CDC_WSA_SOFTCLIP0_CRC, 0x00}, 571 { CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38}, 572 { CDC_WSA_SOFTCLIP1_CRC, 0x00}, 573 { CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38}, 574 { CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00}, 575 { CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01}, 576 { CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00}, 577 { CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01}, 578 { CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00}, 579 { CDC_WSA_SPLINE_ASRC0_CTL0, 0x00}, 580 { CDC_WSA_SPLINE_ASRC0_CTL1, 0x00}, 581 { CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8}, 582 { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00}, 583 { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00}, 584 { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00}, 585 { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00}, 586 { CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00}, 587 { CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00}, 588 { CDC_WSA_SPLINE_ASRC1_CTL0, 0x00}, 589 { CDC_WSA_SPLINE_ASRC1_CTL1, 0x00}, 590 { CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8}, 591 { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00}, 592 { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00}, 593 { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00}, 594 { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00}, 595 { CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00}, 596 }; 597 598 static bool wsa_is_wronly_register(struct device *dev, 599 unsigned int reg) 600 { 601 switch (reg) { 602 case CDC_WSA_INTR_CTRL_CLR_COMMIT: 603 case CDC_WSA_INTR_CTRL_PIN1_CLEAR0: 604 case CDC_WSA_INTR_CTRL_PIN2_CLEAR0: 605 return true; 606 } 607 608 return false; 609 } 610 611 static bool wsa_is_rw_register(struct device *dev, unsigned int reg) 612 { 613 switch (reg) { 614 case CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL: 615 case CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL: 616 case CDC_WSA_CLK_RST_CTRL_SWR_CONTROL: 617 case CDC_WSA_TOP_TOP_CFG0: 618 case CDC_WSA_TOP_TOP_CFG1: 619 case CDC_WSA_TOP_FREQ_MCLK: 620 case CDC_WSA_TOP_DEBUG_BUS_SEL: 621 case CDC_WSA_TOP_DEBUG_EN0: 622 case CDC_WSA_TOP_DEBUG_EN1: 623 case CDC_WSA_TOP_DEBUG_DSM_LB: 624 case CDC_WSA_TOP_RX_I2S_CTL: 625 case CDC_WSA_TOP_TX_I2S_CTL: 626 case CDC_WSA_TOP_I2S_CLK: 627 case CDC_WSA_TOP_I2S_RESET: 628 case CDC_WSA_RX_INP_MUX_RX_INT0_CFG0: 629 case CDC_WSA_RX_INP_MUX_RX_INT0_CFG1: 630 case CDC_WSA_RX_INP_MUX_RX_INT1_CFG0: 631 case CDC_WSA_RX_INP_MUX_RX_INT1_CFG1: 632 case CDC_WSA_RX_INP_MUX_RX_MIX_CFG0: 633 case CDC_WSA_RX_INP_MUX_RX_EC_CFG0: 634 case CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0: 635 case CDC_WSA_TX0_SPKR_PROT_PATH_CTL: 636 case CDC_WSA_TX0_SPKR_PROT_PATH_CFG0: 637 case CDC_WSA_TX1_SPKR_PROT_PATH_CTL: 638 case CDC_WSA_TX1_SPKR_PROT_PATH_CFG0: 639 case CDC_WSA_TX2_SPKR_PROT_PATH_CTL: 640 case CDC_WSA_TX2_SPKR_PROT_PATH_CFG0: 641 case CDC_WSA_TX3_SPKR_PROT_PATH_CTL: 642 case CDC_WSA_TX3_SPKR_PROT_PATH_CFG0: 643 case CDC_WSA_INTR_CTRL_CFG: 644 case CDC_WSA_INTR_CTRL_PIN1_MASK0: 645 case CDC_WSA_INTR_CTRL_PIN2_MASK0: 646 case CDC_WSA_INTR_CTRL_LEVEL0: 647 case CDC_WSA_INTR_CTRL_BYPASS0: 648 case CDC_WSA_INTR_CTRL_SET0: 649 case CDC_WSA_RX0_RX_PATH_CTL: 650 case CDC_WSA_RX0_RX_PATH_CFG0: 651 case CDC_WSA_RX0_RX_PATH_CFG1: 652 case CDC_WSA_RX0_RX_PATH_CFG2: 653 case CDC_WSA_RX0_RX_PATH_CFG3: 654 case CDC_WSA_RX0_RX_VOL_CTL: 655 case CDC_WSA_RX0_RX_PATH_MIX_CTL: 656 case CDC_WSA_RX0_RX_PATH_MIX_CFG: 657 case CDC_WSA_RX0_RX_VOL_MIX_CTL: 658 case CDC_WSA_RX0_RX_PATH_SEC0: 659 case CDC_WSA_RX0_RX_PATH_SEC1: 660 case CDC_WSA_RX0_RX_PATH_SEC2: 661 case CDC_WSA_RX0_RX_PATH_SEC3: 662 case CDC_WSA_RX0_RX_PATH_SEC5: 663 case CDC_WSA_RX0_RX_PATH_SEC6: 664 case CDC_WSA_RX0_RX_PATH_SEC7: 665 case CDC_WSA_RX0_RX_PATH_MIX_SEC0: 666 case CDC_WSA_RX0_RX_PATH_MIX_SEC1: 667 case CDC_WSA_RX0_RX_PATH_DSMDEM_CTL: 668 case CDC_WSA_RX1_RX_PATH_CTL: 669 case CDC_WSA_RX1_RX_PATH_CFG0: 670 case CDC_WSA_RX1_RX_PATH_CFG1: 671 case CDC_WSA_RX1_RX_PATH_CFG2: 672 case CDC_WSA_RX1_RX_PATH_CFG3: 673 case CDC_WSA_RX1_RX_VOL_CTL: 674 case CDC_WSA_RX1_RX_PATH_MIX_CTL: 675 case CDC_WSA_RX1_RX_PATH_MIX_CFG: 676 case CDC_WSA_RX1_RX_VOL_MIX_CTL: 677 case CDC_WSA_RX1_RX_PATH_SEC0: 678 case CDC_WSA_RX1_RX_PATH_SEC1: 679 case CDC_WSA_RX1_RX_PATH_SEC2: 680 case CDC_WSA_RX1_RX_PATH_SEC3: 681 case CDC_WSA_RX1_RX_PATH_SEC5: 682 case CDC_WSA_RX1_RX_PATH_SEC6: 683 case CDC_WSA_RX1_RX_PATH_SEC7: 684 case CDC_WSA_RX1_RX_PATH_MIX_SEC0: 685 case CDC_WSA_RX1_RX_PATH_MIX_SEC1: 686 case CDC_WSA_RX1_RX_PATH_DSMDEM_CTL: 687 case CDC_WSA_BOOST0_BOOST_PATH_CTL: 688 case CDC_WSA_BOOST0_BOOST_CTL: 689 case CDC_WSA_BOOST0_BOOST_CFG1: 690 case CDC_WSA_BOOST0_BOOST_CFG2: 691 case CDC_WSA_BOOST1_BOOST_PATH_CTL: 692 case CDC_WSA_BOOST1_BOOST_CTL: 693 case CDC_WSA_BOOST1_BOOST_CFG1: 694 case CDC_WSA_BOOST1_BOOST_CFG2: 695 case CDC_WSA_COMPANDER0_CTL0: 696 case CDC_WSA_COMPANDER0_CTL1: 697 case CDC_WSA_COMPANDER0_CTL2: 698 case CDC_WSA_COMPANDER0_CTL3: 699 case CDC_WSA_COMPANDER0_CTL4: 700 case CDC_WSA_COMPANDER0_CTL5: 701 case CDC_WSA_COMPANDER0_CTL7: 702 case CDC_WSA_COMPANDER1_CTL0: 703 case CDC_WSA_COMPANDER1_CTL1: 704 case CDC_WSA_COMPANDER1_CTL2: 705 case CDC_WSA_COMPANDER1_CTL3: 706 case CDC_WSA_COMPANDER1_CTL4: 707 case CDC_WSA_COMPANDER1_CTL5: 708 case CDC_WSA_COMPANDER1_CTL7: 709 case CDC_WSA_SOFTCLIP0_CRC: 710 case CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL: 711 case CDC_WSA_SOFTCLIP1_CRC: 712 case CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL: 713 case CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL: 714 case CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0: 715 case CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL: 716 case CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0: 717 case CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL: 718 case CDC_WSA_SPLINE_ASRC0_CTL0: 719 case CDC_WSA_SPLINE_ASRC0_CTL1: 720 case CDC_WSA_SPLINE_ASRC0_FIFO_CTL: 721 case CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL: 722 case CDC_WSA_SPLINE_ASRC1_CTL0: 723 case CDC_WSA_SPLINE_ASRC1_CTL1: 724 case CDC_WSA_SPLINE_ASRC1_FIFO_CTL: 725 return true; 726 } 727 728 return false; 729 } 730 731 static bool wsa_is_writeable_register(struct device *dev, unsigned int reg) 732 { 733 bool ret; 734 735 ret = wsa_is_rw_register(dev, reg); 736 if (!ret) 737 return wsa_is_wronly_register(dev, reg); 738 739 return ret; 740 } 741 742 static bool wsa_is_readable_register(struct device *dev, unsigned int reg) 743 { 744 switch (reg) { 745 case CDC_WSA_INTR_CTRL_CLR_COMMIT: 746 case CDC_WSA_INTR_CTRL_PIN1_CLEAR0: 747 case CDC_WSA_INTR_CTRL_PIN2_CLEAR0: 748 case CDC_WSA_INTR_CTRL_PIN1_STATUS0: 749 case CDC_WSA_INTR_CTRL_PIN2_STATUS0: 750 case CDC_WSA_COMPANDER0_CTL6: 751 case CDC_WSA_COMPANDER1_CTL6: 752 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: 753 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: 754 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: 755 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB: 756 case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO: 757 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB: 758 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB: 759 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB: 760 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB: 761 case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO: 762 return true; 763 } 764 765 return wsa_is_rw_register(dev, reg); 766 } 767 768 static bool wsa_is_volatile_register(struct device *dev, unsigned int reg) 769 { 770 /* Update volatile list for rx/tx macros */ 771 switch (reg) { 772 case CDC_WSA_INTR_CTRL_PIN1_STATUS0: 773 case CDC_WSA_INTR_CTRL_PIN2_STATUS0: 774 case CDC_WSA_COMPANDER0_CTL6: 775 case CDC_WSA_COMPANDER1_CTL6: 776 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: 777 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: 778 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: 779 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB: 780 case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO: 781 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB: 782 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB: 783 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB: 784 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB: 785 case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO: 786 return true; 787 } 788 return false; 789 } 790 791 static const struct regmap_config wsa_regmap_config = { 792 .name = "wsa_macro", 793 .reg_bits = 16, 794 .val_bits = 32, /* 8 but with 32 bit read/write */ 795 .reg_stride = 4, 796 .cache_type = REGCACHE_FLAT, 797 .reg_defaults = wsa_defaults, 798 .num_reg_defaults = ARRAY_SIZE(wsa_defaults), 799 .max_register = WSA_MAX_OFFSET, 800 .writeable_reg = wsa_is_writeable_register, 801 .volatile_reg = wsa_is_volatile_register, 802 .readable_reg = wsa_is_readable_register, 803 }; 804 805 /** 806 * wsa_macro_set_spkr_mode - Configures speaker compander and smartboost 807 * settings based on speaker mode. 808 * 809 * @component: codec instance 810 * @mode: Indicates speaker configuration mode. 811 * 812 * Returns 0 on success or -EINVAL on error. 813 */ 814 int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode) 815 { 816 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 817 818 wsa->spkr_mode = mode; 819 820 switch (mode) { 821 case WSA_MACRO_SPKR_MODE_1: 822 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00); 823 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00); 824 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00); 825 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00); 826 snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44); 827 snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44); 828 break; 829 default: 830 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80); 831 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80); 832 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01); 833 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01); 834 snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58); 835 snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58); 836 break; 837 } 838 return 0; 839 } 840 EXPORT_SYMBOL(wsa_macro_set_spkr_mode); 841 842 static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, 843 u8 int_prim_fs_rate_reg_val, 844 u32 sample_rate) 845 { 846 u8 int_1_mix1_inp; 847 u32 j, port; 848 u16 int_mux_cfg0, int_mux_cfg1; 849 u16 int_fs_reg; 850 u8 inp0_sel, inp1_sel, inp2_sel; 851 struct snd_soc_component *component = dai->component; 852 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 853 854 for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) { 855 int_1_mix1_inp = port; 856 if ((int_1_mix1_inp < WSA_MACRO_RX0) || (int_1_mix1_inp > WSA_MACRO_RX_MIX1)) { 857 dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n", 858 __func__, dai->id); 859 return -EINVAL; 860 } 861 862 int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0; 863 864 /* 865 * Loop through all interpolator MUX inputs and find out 866 * to which interpolator input, the cdc_dma rx port 867 * is connected 868 */ 869 for (j = 0; j < NUM_INTERPOLATORS; j++) { 870 int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET; 871 inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0, 872 CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK); 873 inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0, 874 CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK); 875 inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1, 876 CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK); 877 878 if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 879 (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 880 (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) { 881 int_fs_reg = CDC_WSA_RX0_RX_PATH_CTL + 882 WSA_MACRO_RX_PATH_OFFSET * j; 883 /* sample_rate is in Hz */ 884 snd_soc_component_update_bits(component, int_fs_reg, 885 WSA_MACRO_FS_RATE_MASK, 886 int_prim_fs_rate_reg_val); 887 } 888 int_mux_cfg0 += WSA_MACRO_MUX_CFG_OFFSET; 889 } 890 } 891 892 return 0; 893 } 894 895 static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, 896 u8 int_mix_fs_rate_reg_val, 897 u32 sample_rate) 898 { 899 u8 int_2_inp; 900 u32 j, port; 901 u16 int_mux_cfg1, int_fs_reg; 902 u8 int_mux_cfg1_val; 903 struct snd_soc_component *component = dai->component; 904 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 905 906 for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) { 907 int_2_inp = port; 908 if ((int_2_inp < WSA_MACRO_RX0) || (int_2_inp > WSA_MACRO_RX_MIX1)) { 909 dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n", 910 __func__, dai->id); 911 return -EINVAL; 912 } 913 914 int_mux_cfg1 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG1; 915 for (j = 0; j < NUM_INTERPOLATORS; j++) { 916 int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1, 917 CDC_WSA_RX_INTX_2_SEL_MASK); 918 919 if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) { 920 int_fs_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL + 921 WSA_MACRO_RX_PATH_OFFSET * j; 922 923 snd_soc_component_update_bits(component, 924 int_fs_reg, 925 WSA_MACRO_FS_RATE_MASK, 926 int_mix_fs_rate_reg_val); 927 } 928 int_mux_cfg1 += WSA_MACRO_MUX_CFG_OFFSET; 929 } 930 } 931 return 0; 932 } 933 934 static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai, 935 u32 sample_rate) 936 { 937 int rate_val = 0; 938 int i, ret; 939 940 /* set mixing path rate */ 941 for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) { 942 if (sample_rate == int_mix_sample_rate_val[i].sample_rate) { 943 rate_val = int_mix_sample_rate_val[i].rate_val; 944 break; 945 } 946 } 947 if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) || (rate_val < 0)) 948 goto prim_rate; 949 950 ret = wsa_macro_set_mix_interpolator_rate(dai, (u8) rate_val, sample_rate); 951 if (ret < 0) 952 return ret; 953 prim_rate: 954 /* set primary path sample rate */ 955 for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) { 956 if (sample_rate == int_prim_sample_rate_val[i].sample_rate) { 957 rate_val = int_prim_sample_rate_val[i].rate_val; 958 break; 959 } 960 } 961 if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) || (rate_val < 0)) 962 return -EINVAL; 963 964 ret = wsa_macro_set_prim_interpolator_rate(dai, (u8) rate_val, sample_rate); 965 966 return ret; 967 } 968 969 static int wsa_macro_hw_params(struct snd_pcm_substream *substream, 970 struct snd_pcm_hw_params *params, 971 struct snd_soc_dai *dai) 972 { 973 struct snd_soc_component *component = dai->component; 974 int ret; 975 976 switch (substream->stream) { 977 case SNDRV_PCM_STREAM_PLAYBACK: 978 ret = wsa_macro_set_interpolator_rate(dai, params_rate(params)); 979 if (ret) { 980 dev_err(component->dev, 981 "%s: cannot set sample rate: %u\n", 982 __func__, params_rate(params)); 983 return ret; 984 } 985 break; 986 default: 987 break; 988 } 989 return 0; 990 } 991 992 static int wsa_macro_get_channel_map(struct snd_soc_dai *dai, 993 unsigned int *tx_num, unsigned int *tx_slot, 994 unsigned int *rx_num, unsigned int *rx_slot) 995 { 996 struct snd_soc_component *component = dai->component; 997 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 998 u16 val, mask = 0, cnt = 0, temp; 999 1000 switch (dai->id) { 1001 case WSA_MACRO_AIF_VI: 1002 *tx_slot = wsa->active_ch_mask[dai->id]; 1003 *tx_num = wsa->active_ch_cnt[dai->id]; 1004 break; 1005 case WSA_MACRO_AIF1_PB: 1006 case WSA_MACRO_AIF_MIX1_PB: 1007 for_each_set_bit(temp, &wsa->active_ch_mask[dai->id], 1008 WSA_MACRO_RX_MAX) { 1009 mask |= (1 << temp); 1010 if (++cnt == WSA_MACRO_MAX_DMA_CH_PER_PORT) 1011 break; 1012 } 1013 if (mask & 0x0C) 1014 mask = mask >> 0x2; 1015 *rx_slot = mask; 1016 *rx_num = cnt; 1017 break; 1018 case WSA_MACRO_AIF_ECHO: 1019 val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0); 1020 if (val & WSA_MACRO_EC_MIX_TX1_MASK) { 1021 mask |= 0x2; 1022 cnt++; 1023 } 1024 if (val & WSA_MACRO_EC_MIX_TX0_MASK) { 1025 mask |= 0x1; 1026 cnt++; 1027 } 1028 *tx_slot = mask; 1029 *tx_num = cnt; 1030 break; 1031 default: 1032 dev_err(component->dev, "%s: Invalid AIF\n", __func__); 1033 break; 1034 } 1035 return 0; 1036 } 1037 1038 static const struct snd_soc_dai_ops wsa_macro_dai_ops = { 1039 .hw_params = wsa_macro_hw_params, 1040 .get_channel_map = wsa_macro_get_channel_map, 1041 }; 1042 1043 static struct snd_soc_dai_driver wsa_macro_dai[] = { 1044 { 1045 .name = "wsa_macro_rx1", 1046 .id = WSA_MACRO_AIF1_PB, 1047 .playback = { 1048 .stream_name = "WSA_AIF1 Playback", 1049 .rates = WSA_MACRO_RX_RATES, 1050 .formats = WSA_MACRO_RX_FORMATS, 1051 .rate_max = 384000, 1052 .rate_min = 8000, 1053 .channels_min = 1, 1054 .channels_max = 2, 1055 }, 1056 .ops = &wsa_macro_dai_ops, 1057 }, 1058 { 1059 .name = "wsa_macro_rx_mix", 1060 .id = WSA_MACRO_AIF_MIX1_PB, 1061 .playback = { 1062 .stream_name = "WSA_AIF_MIX1 Playback", 1063 .rates = WSA_MACRO_RX_MIX_RATES, 1064 .formats = WSA_MACRO_RX_FORMATS, 1065 .rate_max = 192000, 1066 .rate_min = 48000, 1067 .channels_min = 1, 1068 .channels_max = 2, 1069 }, 1070 .ops = &wsa_macro_dai_ops, 1071 }, 1072 { 1073 .name = "wsa_macro_vifeedback", 1074 .id = WSA_MACRO_AIF_VI, 1075 .capture = { 1076 .stream_name = "WSA_AIF_VI Capture", 1077 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000, 1078 .formats = WSA_MACRO_RX_FORMATS, 1079 .rate_max = 48000, 1080 .rate_min = 8000, 1081 .channels_min = 1, 1082 .channels_max = 4, 1083 }, 1084 .ops = &wsa_macro_dai_ops, 1085 }, 1086 { 1087 .name = "wsa_macro_echo", 1088 .id = WSA_MACRO_AIF_ECHO, 1089 .capture = { 1090 .stream_name = "WSA_AIF_ECHO Capture", 1091 .rates = WSA_MACRO_ECHO_RATES, 1092 .formats = WSA_MACRO_ECHO_FORMATS, 1093 .rate_max = 48000, 1094 .rate_min = 8000, 1095 .channels_min = 1, 1096 .channels_max = 2, 1097 }, 1098 .ops = &wsa_macro_dai_ops, 1099 }, 1100 }; 1101 1102 static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable) 1103 { 1104 struct regmap *regmap = wsa->regmap; 1105 1106 if (mclk_enable) { 1107 if (wsa->wsa_mclk_users == 0) { 1108 regcache_mark_dirty(regmap); 1109 regcache_sync(regmap); 1110 /* 9.6MHz MCLK, set value 0x00 if other frequency */ 1111 regmap_update_bits(regmap, CDC_WSA_TOP_FREQ_MCLK, 0x01, 0x01); 1112 regmap_update_bits(regmap, 1113 CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 1114 CDC_WSA_MCLK_EN_MASK, 1115 CDC_WSA_MCLK_ENABLE); 1116 regmap_update_bits(regmap, 1117 CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 1118 CDC_WSA_FS_CNT_EN_MASK, 1119 CDC_WSA_FS_CNT_ENABLE); 1120 } 1121 wsa->wsa_mclk_users++; 1122 } else { 1123 if (wsa->wsa_mclk_users <= 0) { 1124 dev_err(wsa->dev, "clock already disabled\n"); 1125 wsa->wsa_mclk_users = 0; 1126 return; 1127 } 1128 wsa->wsa_mclk_users--; 1129 if (wsa->wsa_mclk_users == 0) { 1130 regmap_update_bits(regmap, 1131 CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 1132 CDC_WSA_FS_CNT_EN_MASK, 1133 CDC_WSA_FS_CNT_DISABLE); 1134 regmap_update_bits(regmap, 1135 CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 1136 CDC_WSA_MCLK_EN_MASK, 1137 CDC_WSA_MCLK_DISABLE); 1138 } 1139 } 1140 } 1141 1142 static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w, 1143 struct snd_kcontrol *kcontrol, int event) 1144 { 1145 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1146 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1147 1148 wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU); 1149 return 0; 1150 } 1151 1152 static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w, 1153 struct snd_kcontrol *kcontrol, 1154 int event) 1155 { 1156 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1157 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1158 u32 tx_reg0, tx_reg1; 1159 1160 if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 1161 tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL; 1162 tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL; 1163 } else if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 1164 tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL; 1165 tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL; 1166 } 1167 1168 switch (event) { 1169 case SND_SOC_DAPM_POST_PMU: 1170 /* Enable V&I sensing */ 1171 snd_soc_component_update_bits(component, tx_reg0, 1172 CDC_WSA_TX_SPKR_PROT_RESET_MASK, 1173 CDC_WSA_TX_SPKR_PROT_RESET); 1174 snd_soc_component_update_bits(component, tx_reg1, 1175 CDC_WSA_TX_SPKR_PROT_RESET_MASK, 1176 CDC_WSA_TX_SPKR_PROT_RESET); 1177 snd_soc_component_update_bits(component, tx_reg0, 1178 CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK, 1179 CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K); 1180 snd_soc_component_update_bits(component, tx_reg1, 1181 CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK, 1182 CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K); 1183 snd_soc_component_update_bits(component, tx_reg0, 1184 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 1185 CDC_WSA_TX_SPKR_PROT_CLK_ENABLE); 1186 snd_soc_component_update_bits(component, tx_reg1, 1187 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 1188 CDC_WSA_TX_SPKR_PROT_CLK_ENABLE); 1189 snd_soc_component_update_bits(component, tx_reg0, 1190 CDC_WSA_TX_SPKR_PROT_RESET_MASK, 1191 CDC_WSA_TX_SPKR_PROT_NO_RESET); 1192 snd_soc_component_update_bits(component, tx_reg1, 1193 CDC_WSA_TX_SPKR_PROT_RESET_MASK, 1194 CDC_WSA_TX_SPKR_PROT_NO_RESET); 1195 break; 1196 case SND_SOC_DAPM_POST_PMD: 1197 /* Disable V&I sensing */ 1198 snd_soc_component_update_bits(component, tx_reg0, 1199 CDC_WSA_TX_SPKR_PROT_RESET_MASK, 1200 CDC_WSA_TX_SPKR_PROT_RESET); 1201 snd_soc_component_update_bits(component, tx_reg1, 1202 CDC_WSA_TX_SPKR_PROT_RESET_MASK, 1203 CDC_WSA_TX_SPKR_PROT_RESET); 1204 snd_soc_component_update_bits(component, tx_reg0, 1205 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 1206 CDC_WSA_TX_SPKR_PROT_CLK_DISABLE); 1207 snd_soc_component_update_bits(component, tx_reg1, 1208 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 1209 CDC_WSA_TX_SPKR_PROT_CLK_DISABLE); 1210 break; 1211 } 1212 1213 return 0; 1214 } 1215 1216 static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w, 1217 struct snd_kcontrol *kcontrol, int event) 1218 { 1219 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1220 u16 path_reg, gain_reg; 1221 int val; 1222 1223 switch (w->shift) { 1224 case WSA_MACRO_RX_MIX0: 1225 path_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL; 1226 gain_reg = CDC_WSA_RX0_RX_VOL_MIX_CTL; 1227 break; 1228 case WSA_MACRO_RX_MIX1: 1229 path_reg = CDC_WSA_RX1_RX_PATH_MIX_CTL; 1230 gain_reg = CDC_WSA_RX1_RX_VOL_MIX_CTL; 1231 break; 1232 default: 1233 return 0; 1234 } 1235 1236 switch (event) { 1237 case SND_SOC_DAPM_POST_PMU: 1238 val = snd_soc_component_read(component, gain_reg); 1239 snd_soc_component_write(component, gain_reg, val); 1240 break; 1241 case SND_SOC_DAPM_POST_PMD: 1242 snd_soc_component_update_bits(component, path_reg, 1243 CDC_WSA_RX_PATH_MIX_CLK_EN_MASK, 1244 CDC_WSA_RX_PATH_MIX_CLK_DISABLE); 1245 break; 1246 } 1247 1248 return 0; 1249 } 1250 1251 static void wsa_macro_hd2_control(struct snd_soc_component *component, 1252 u16 reg, int event) 1253 { 1254 u16 hd2_scale_reg; 1255 u16 hd2_enable_reg; 1256 1257 if (reg == CDC_WSA_RX0_RX_PATH_CTL) { 1258 hd2_scale_reg = CDC_WSA_RX0_RX_PATH_SEC3; 1259 hd2_enable_reg = CDC_WSA_RX0_RX_PATH_CFG0; 1260 } 1261 if (reg == CDC_WSA_RX1_RX_PATH_CTL) { 1262 hd2_scale_reg = CDC_WSA_RX1_RX_PATH_SEC3; 1263 hd2_enable_reg = CDC_WSA_RX1_RX_PATH_CFG0; 1264 } 1265 1266 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 1267 snd_soc_component_update_bits(component, hd2_scale_reg, 1268 CDC_WSA_RX_PATH_HD2_ALPHA_MASK, 1269 0x10); 1270 snd_soc_component_update_bits(component, hd2_scale_reg, 1271 CDC_WSA_RX_PATH_HD2_SCALE_MASK, 1272 0x1); 1273 snd_soc_component_update_bits(component, hd2_enable_reg, 1274 CDC_WSA_RX_PATH_HD2_EN_MASK, 1275 CDC_WSA_RX_PATH_HD2_ENABLE); 1276 } 1277 1278 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 1279 snd_soc_component_update_bits(component, hd2_enable_reg, 1280 CDC_WSA_RX_PATH_HD2_EN_MASK, 0); 1281 snd_soc_component_update_bits(component, hd2_scale_reg, 1282 CDC_WSA_RX_PATH_HD2_SCALE_MASK, 1283 0); 1284 snd_soc_component_update_bits(component, hd2_scale_reg, 1285 CDC_WSA_RX_PATH_HD2_ALPHA_MASK, 1286 0); 1287 } 1288 } 1289 1290 static int wsa_macro_config_compander(struct snd_soc_component *component, 1291 int comp, int event) 1292 { 1293 u16 comp_ctl0_reg, rx_path_cfg0_reg; 1294 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1295 1296 if (!wsa->comp_enabled[comp]) 1297 return 0; 1298 1299 comp_ctl0_reg = CDC_WSA_COMPANDER0_CTL0 + 1300 (comp * WSA_MACRO_RX_COMP_OFFSET); 1301 rx_path_cfg0_reg = CDC_WSA_RX0_RX_PATH_CFG0 + 1302 (comp * WSA_MACRO_RX_PATH_OFFSET); 1303 1304 if (SND_SOC_DAPM_EVENT_ON(event)) { 1305 /* Enable Compander Clock */ 1306 snd_soc_component_update_bits(component, comp_ctl0_reg, 1307 CDC_WSA_COMPANDER_CLK_EN_MASK, 1308 CDC_WSA_COMPANDER_CLK_ENABLE); 1309 snd_soc_component_update_bits(component, comp_ctl0_reg, 1310 CDC_WSA_COMPANDER_SOFT_RST_MASK, 1311 CDC_WSA_COMPANDER_SOFT_RST_ENABLE); 1312 snd_soc_component_update_bits(component, comp_ctl0_reg, 1313 CDC_WSA_COMPANDER_SOFT_RST_MASK, 1314 0); 1315 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 1316 CDC_WSA_RX_PATH_COMP_EN_MASK, 1317 CDC_WSA_RX_PATH_COMP_ENABLE); 1318 } 1319 1320 if (SND_SOC_DAPM_EVENT_OFF(event)) { 1321 snd_soc_component_update_bits(component, comp_ctl0_reg, 1322 CDC_WSA_COMPANDER_HALT_MASK, 1323 CDC_WSA_COMPANDER_HALT); 1324 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 1325 CDC_WSA_RX_PATH_COMP_EN_MASK, 0); 1326 snd_soc_component_update_bits(component, comp_ctl0_reg, 1327 CDC_WSA_COMPANDER_SOFT_RST_MASK, 1328 CDC_WSA_COMPANDER_SOFT_RST_ENABLE); 1329 snd_soc_component_update_bits(component, comp_ctl0_reg, 1330 CDC_WSA_COMPANDER_SOFT_RST_MASK, 1331 0); 1332 snd_soc_component_update_bits(component, comp_ctl0_reg, 1333 CDC_WSA_COMPANDER_CLK_EN_MASK, 0); 1334 snd_soc_component_update_bits(component, comp_ctl0_reg, 1335 CDC_WSA_COMPANDER_HALT_MASK, 0); 1336 } 1337 1338 return 0; 1339 } 1340 1341 static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component, 1342 struct wsa_macro *wsa, 1343 int path, 1344 bool enable) 1345 { 1346 u16 softclip_clk_reg = CDC_WSA_SOFTCLIP0_CRC + 1347 (path * WSA_MACRO_RX_SOFTCLIP_OFFSET); 1348 u8 softclip_mux_mask = (1 << path); 1349 u8 softclip_mux_value = (1 << path); 1350 1351 if (enable) { 1352 if (wsa->softclip_clk_users[path] == 0) { 1353 snd_soc_component_update_bits(component, 1354 softclip_clk_reg, 1355 CDC_WSA_SOFTCLIP_CLK_EN_MASK, 1356 CDC_WSA_SOFTCLIP_CLK_ENABLE); 1357 snd_soc_component_update_bits(component, 1358 CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 1359 softclip_mux_mask, softclip_mux_value); 1360 } 1361 wsa->softclip_clk_users[path]++; 1362 } else { 1363 wsa->softclip_clk_users[path]--; 1364 if (wsa->softclip_clk_users[path] == 0) { 1365 snd_soc_component_update_bits(component, 1366 softclip_clk_reg, 1367 CDC_WSA_SOFTCLIP_CLK_EN_MASK, 1368 0); 1369 snd_soc_component_update_bits(component, 1370 CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 1371 softclip_mux_mask, 0x00); 1372 } 1373 } 1374 } 1375 1376 static int wsa_macro_config_softclip(struct snd_soc_component *component, 1377 int path, int event) 1378 { 1379 u16 softclip_ctrl_reg; 1380 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1381 int softclip_path = 0; 1382 1383 if (path == WSA_MACRO_COMP1) 1384 softclip_path = WSA_MACRO_SOFTCLIP0; 1385 else if (path == WSA_MACRO_COMP2) 1386 softclip_path = WSA_MACRO_SOFTCLIP1; 1387 1388 if (!wsa->is_softclip_on[softclip_path]) 1389 return 0; 1390 1391 softclip_ctrl_reg = CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL + 1392 (softclip_path * WSA_MACRO_RX_SOFTCLIP_OFFSET); 1393 1394 if (SND_SOC_DAPM_EVENT_ON(event)) { 1395 /* Enable Softclip clock and mux */ 1396 wsa_macro_enable_softclip_clk(component, wsa, softclip_path, 1397 true); 1398 /* Enable Softclip control */ 1399 snd_soc_component_update_bits(component, softclip_ctrl_reg, 1400 CDC_WSA_SOFTCLIP_EN_MASK, 1401 CDC_WSA_SOFTCLIP_ENABLE); 1402 } 1403 1404 if (SND_SOC_DAPM_EVENT_OFF(event)) { 1405 snd_soc_component_update_bits(component, softclip_ctrl_reg, 1406 CDC_WSA_SOFTCLIP_EN_MASK, 0); 1407 wsa_macro_enable_softclip_clk(component, wsa, softclip_path, 1408 false); 1409 } 1410 1411 return 0; 1412 } 1413 1414 static bool wsa_macro_adie_lb(struct snd_soc_component *component, 1415 int interp_idx) 1416 { 1417 u16 int_mux_cfg0, int_mux_cfg1; 1418 u8 int_n_inp0, int_n_inp1, int_n_inp2; 1419 1420 int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8; 1421 int_mux_cfg1 = int_mux_cfg0 + 4; 1422 1423 int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0, 1424 CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK); 1425 if (int_n_inp0 == INTn_1_INP_SEL_DEC0 || 1426 int_n_inp0 == INTn_1_INP_SEL_DEC1) 1427 return true; 1428 1429 int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0, 1430 CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK); 1431 if (int_n_inp1 == INTn_1_INP_SEL_DEC0 || 1432 int_n_inp1 == INTn_1_INP_SEL_DEC1) 1433 return true; 1434 1435 int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1, 1436 CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK); 1437 if (int_n_inp2 == INTn_1_INP_SEL_DEC0 || 1438 int_n_inp2 == INTn_1_INP_SEL_DEC1) 1439 return true; 1440 1441 return false; 1442 } 1443 1444 static int wsa_macro_enable_main_path(struct snd_soc_dapm_widget *w, 1445 struct snd_kcontrol *kcontrol, 1446 int event) 1447 { 1448 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1449 u16 reg; 1450 1451 reg = CDC_WSA_RX0_RX_PATH_CTL + WSA_MACRO_RX_PATH_OFFSET * w->shift; 1452 switch (event) { 1453 case SND_SOC_DAPM_PRE_PMU: 1454 if (wsa_macro_adie_lb(component, w->shift)) { 1455 snd_soc_component_update_bits(component, reg, 1456 CDC_WSA_RX_PATH_CLK_EN_MASK, 1457 CDC_WSA_RX_PATH_CLK_ENABLE); 1458 } 1459 break; 1460 default: 1461 break; 1462 } 1463 return 0; 1464 } 1465 1466 static int wsa_macro_interp_get_primary_reg(u16 reg, u16 *ind) 1467 { 1468 u16 prim_int_reg = 0; 1469 1470 switch (reg) { 1471 case CDC_WSA_RX0_RX_PATH_CTL: 1472 case CDC_WSA_RX0_RX_PATH_MIX_CTL: 1473 prim_int_reg = CDC_WSA_RX0_RX_PATH_CTL; 1474 *ind = 0; 1475 break; 1476 case CDC_WSA_RX1_RX_PATH_CTL: 1477 case CDC_WSA_RX1_RX_PATH_MIX_CTL: 1478 prim_int_reg = CDC_WSA_RX1_RX_PATH_CTL; 1479 *ind = 1; 1480 break; 1481 } 1482 1483 return prim_int_reg; 1484 } 1485 1486 static int wsa_macro_enable_prim_interpolator(struct snd_soc_component *component, 1487 u16 reg, int event) 1488 { 1489 u16 prim_int_reg; 1490 u16 ind = 0; 1491 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1492 1493 prim_int_reg = wsa_macro_interp_get_primary_reg(reg, &ind); 1494 1495 switch (event) { 1496 case SND_SOC_DAPM_PRE_PMU: 1497 wsa->prim_int_users[ind]++; 1498 if (wsa->prim_int_users[ind] == 1) { 1499 snd_soc_component_update_bits(component, 1500 prim_int_reg + WSA_MACRO_RX_PATH_CFG3_OFFSET, 1501 CDC_WSA_RX_DC_DCOEFF_MASK, 1502 0x3); 1503 snd_soc_component_update_bits(component, prim_int_reg, 1504 CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK, 1505 CDC_WSA_RX_PATH_PGA_MUTE_ENABLE); 1506 wsa_macro_hd2_control(component, prim_int_reg, event); 1507 snd_soc_component_update_bits(component, 1508 prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET, 1509 CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 1510 CDC_WSA_RX_DSMDEM_CLK_ENABLE); 1511 } 1512 if ((reg != prim_int_reg) && 1513 ((snd_soc_component_read( 1514 component, prim_int_reg)) & 0x10)) 1515 snd_soc_component_update_bits(component, reg, 1516 0x10, 0x10); 1517 break; 1518 case SND_SOC_DAPM_POST_PMD: 1519 wsa->prim_int_users[ind]--; 1520 if (wsa->prim_int_users[ind] == 0) { 1521 snd_soc_component_update_bits(component, 1522 prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET, 1523 CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 0); 1524 wsa_macro_hd2_control(component, prim_int_reg, event); 1525 } 1526 break; 1527 } 1528 1529 return 0; 1530 } 1531 1532 static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component, 1533 struct wsa_macro *wsa, 1534 int event, int gain_reg) 1535 { 1536 int comp_gain_offset, val; 1537 1538 switch (wsa->spkr_mode) { 1539 /* Compander gain in WSA_MACRO_SPKR_MODE1 case is 12 dB */ 1540 case WSA_MACRO_SPKR_MODE_1: 1541 comp_gain_offset = -12; 1542 break; 1543 /* Default case compander gain is 15 dB */ 1544 default: 1545 comp_gain_offset = -15; 1546 break; 1547 } 1548 1549 switch (event) { 1550 case SND_SOC_DAPM_POST_PMU: 1551 /* Apply ear spkr gain only if compander is enabled */ 1552 if (wsa->comp_enabled[WSA_MACRO_COMP1] && 1553 (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) && 1554 (wsa->ear_spkr_gain != 0)) { 1555 /* For example, val is -8(-12+5-1) for 4dB of gain */ 1556 val = comp_gain_offset + wsa->ear_spkr_gain - 1; 1557 snd_soc_component_write(component, gain_reg, val); 1558 } 1559 break; 1560 case SND_SOC_DAPM_POST_PMD: 1561 /* 1562 * Reset RX0 volume to 0 dB if compander is enabled and 1563 * ear_spkr_gain is non-zero. 1564 */ 1565 if (wsa->comp_enabled[WSA_MACRO_COMP1] && 1566 (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) && 1567 (wsa->ear_spkr_gain != 0)) { 1568 snd_soc_component_write(component, gain_reg, 0x0); 1569 } 1570 break; 1571 } 1572 1573 return 0; 1574 } 1575 1576 static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w, 1577 struct snd_kcontrol *kcontrol, 1578 int event) 1579 { 1580 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1581 u16 gain_reg; 1582 u16 reg; 1583 int val; 1584 int offset_val = 0; 1585 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1586 1587 if (w->shift == WSA_MACRO_COMP1) { 1588 reg = CDC_WSA_RX0_RX_PATH_CTL; 1589 gain_reg = CDC_WSA_RX0_RX_VOL_CTL; 1590 } else if (w->shift == WSA_MACRO_COMP2) { 1591 reg = CDC_WSA_RX1_RX_PATH_CTL; 1592 gain_reg = CDC_WSA_RX1_RX_VOL_CTL; 1593 } 1594 1595 switch (event) { 1596 case SND_SOC_DAPM_PRE_PMU: 1597 /* Reset if needed */ 1598 wsa_macro_enable_prim_interpolator(component, reg, event); 1599 break; 1600 case SND_SOC_DAPM_POST_PMU: 1601 wsa_macro_config_compander(component, w->shift, event); 1602 wsa_macro_config_softclip(component, w->shift, event); 1603 /* apply gain after int clk is enabled */ 1604 if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) && 1605 (wsa->comp_enabled[WSA_MACRO_COMP1] || 1606 wsa->comp_enabled[WSA_MACRO_COMP2])) { 1607 snd_soc_component_update_bits(component, 1608 CDC_WSA_RX0_RX_PATH_SEC1, 1609 CDC_WSA_RX_PGA_HALF_DB_MASK, 1610 CDC_WSA_RX_PGA_HALF_DB_ENABLE); 1611 snd_soc_component_update_bits(component, 1612 CDC_WSA_RX0_RX_PATH_MIX_SEC0, 1613 CDC_WSA_RX_PGA_HALF_DB_MASK, 1614 CDC_WSA_RX_PGA_HALF_DB_ENABLE); 1615 snd_soc_component_update_bits(component, 1616 CDC_WSA_RX1_RX_PATH_SEC1, 1617 CDC_WSA_RX_PGA_HALF_DB_MASK, 1618 CDC_WSA_RX_PGA_HALF_DB_ENABLE); 1619 snd_soc_component_update_bits(component, 1620 CDC_WSA_RX1_RX_PATH_MIX_SEC0, 1621 CDC_WSA_RX_PGA_HALF_DB_MASK, 1622 CDC_WSA_RX_PGA_HALF_DB_ENABLE); 1623 offset_val = -2; 1624 } 1625 val = snd_soc_component_read(component, gain_reg); 1626 val += offset_val; 1627 snd_soc_component_write(component, gain_reg, val); 1628 wsa_macro_config_ear_spkr_gain(component, wsa, 1629 event, gain_reg); 1630 break; 1631 case SND_SOC_DAPM_POST_PMD: 1632 wsa_macro_config_compander(component, w->shift, event); 1633 wsa_macro_config_softclip(component, w->shift, event); 1634 wsa_macro_enable_prim_interpolator(component, reg, event); 1635 if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) && 1636 (wsa->comp_enabled[WSA_MACRO_COMP1] || 1637 wsa->comp_enabled[WSA_MACRO_COMP2])) { 1638 snd_soc_component_update_bits(component, 1639 CDC_WSA_RX0_RX_PATH_SEC1, 1640 CDC_WSA_RX_PGA_HALF_DB_MASK, 1641 CDC_WSA_RX_PGA_HALF_DB_DISABLE); 1642 snd_soc_component_update_bits(component, 1643 CDC_WSA_RX0_RX_PATH_MIX_SEC0, 1644 CDC_WSA_RX_PGA_HALF_DB_MASK, 1645 CDC_WSA_RX_PGA_HALF_DB_DISABLE); 1646 snd_soc_component_update_bits(component, 1647 CDC_WSA_RX1_RX_PATH_SEC1, 1648 CDC_WSA_RX_PGA_HALF_DB_MASK, 1649 CDC_WSA_RX_PGA_HALF_DB_DISABLE); 1650 snd_soc_component_update_bits(component, 1651 CDC_WSA_RX1_RX_PATH_MIX_SEC0, 1652 CDC_WSA_RX_PGA_HALF_DB_MASK, 1653 CDC_WSA_RX_PGA_HALF_DB_DISABLE); 1654 offset_val = 2; 1655 val = snd_soc_component_read(component, gain_reg); 1656 val += offset_val; 1657 snd_soc_component_write(component, gain_reg, val); 1658 } 1659 wsa_macro_config_ear_spkr_gain(component, wsa, 1660 event, gain_reg); 1661 break; 1662 } 1663 1664 return 0; 1665 } 1666 1667 static int wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w, 1668 struct snd_kcontrol *kcontrol, 1669 int event) 1670 { 1671 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1672 u16 boost_path_ctl, boost_path_cfg1; 1673 u16 reg, reg_mix; 1674 1675 if (!strcmp(w->name, "WSA_RX INT0 CHAIN")) { 1676 boost_path_ctl = CDC_WSA_BOOST0_BOOST_PATH_CTL; 1677 boost_path_cfg1 = CDC_WSA_RX0_RX_PATH_CFG1; 1678 reg = CDC_WSA_RX0_RX_PATH_CTL; 1679 reg_mix = CDC_WSA_RX0_RX_PATH_MIX_CTL; 1680 } else if (!strcmp(w->name, "WSA_RX INT1 CHAIN")) { 1681 boost_path_ctl = CDC_WSA_BOOST1_BOOST_PATH_CTL; 1682 boost_path_cfg1 = CDC_WSA_RX1_RX_PATH_CFG1; 1683 reg = CDC_WSA_RX1_RX_PATH_CTL; 1684 reg_mix = CDC_WSA_RX1_RX_PATH_MIX_CTL; 1685 } 1686 1687 switch (event) { 1688 case SND_SOC_DAPM_PRE_PMU: 1689 snd_soc_component_update_bits(component, boost_path_cfg1, 1690 CDC_WSA_RX_PATH_SMART_BST_EN_MASK, 1691 CDC_WSA_RX_PATH_SMART_BST_ENABLE); 1692 snd_soc_component_update_bits(component, boost_path_ctl, 1693 CDC_WSA_BOOST_PATH_CLK_EN_MASK, 1694 CDC_WSA_BOOST_PATH_CLK_ENABLE); 1695 if ((snd_soc_component_read(component, reg_mix)) & 0x10) 1696 snd_soc_component_update_bits(component, reg_mix, 1697 0x10, 0x00); 1698 break; 1699 case SND_SOC_DAPM_POST_PMU: 1700 snd_soc_component_update_bits(component, reg, 0x10, 0x00); 1701 break; 1702 case SND_SOC_DAPM_POST_PMD: 1703 snd_soc_component_update_bits(component, boost_path_ctl, 1704 CDC_WSA_BOOST_PATH_CLK_EN_MASK, 1705 CDC_WSA_BOOST_PATH_CLK_DISABLE); 1706 snd_soc_component_update_bits(component, boost_path_cfg1, 1707 CDC_WSA_RX_PATH_SMART_BST_EN_MASK, 1708 CDC_WSA_RX_PATH_SMART_BST_DISABLE); 1709 break; 1710 } 1711 1712 return 0; 1713 } 1714 1715 static int wsa_macro_enable_echo(struct snd_soc_dapm_widget *w, 1716 struct snd_kcontrol *kcontrol, 1717 int event) 1718 { 1719 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1720 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1721 u16 val, ec_tx, ec_hq_reg; 1722 1723 val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0); 1724 1725 switch (w->shift) { 1726 case WSA_MACRO_EC0_MUX: 1727 val = val & CDC_WSA_RX_MIX_TX0_SEL_MASK; 1728 ec_tx = val - 1; 1729 break; 1730 case WSA_MACRO_EC1_MUX: 1731 val = val & CDC_WSA_RX_MIX_TX1_SEL_MASK; 1732 ec_tx = (val >> CDC_WSA_RX_MIX_TX1_SEL_SHFT) - 1; 1733 break; 1734 default: 1735 dev_err(component->dev, "%s: Invalid shift %u\n", 1736 __func__, w->shift); 1737 return -EINVAL; 1738 } 1739 1740 if (wsa->ec_hq[ec_tx]) { 1741 ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL + 0x40 * ec_tx; 1742 snd_soc_component_update_bits(component, ec_hq_reg, 1743 CDC_WSA_EC_HQ_EC_CLK_EN_MASK, 1744 CDC_WSA_EC_HQ_EC_CLK_ENABLE); 1745 ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 + 0x40 * ec_tx; 1746 /* default set to 48k */ 1747 snd_soc_component_update_bits(component, ec_hq_reg, 1748 CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK, 1749 CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K); 1750 } 1751 1752 return 0; 1753 } 1754 1755 static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol, 1756 struct snd_ctl_elem_value *ucontrol) 1757 { 1758 1759 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1760 int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1761 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1762 1763 ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx]; 1764 1765 return 0; 1766 } 1767 1768 static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol, 1769 struct snd_ctl_elem_value *ucontrol) 1770 { 1771 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1772 int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1773 int value = ucontrol->value.integer.value[0]; 1774 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1775 1776 wsa->ec_hq[ec_tx] = value; 1777 1778 return 0; 1779 } 1780 1781 static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol, 1782 struct snd_ctl_elem_value *ucontrol) 1783 { 1784 1785 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1786 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1787 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1788 1789 ucontrol->value.integer.value[0] = wsa->comp_enabled[comp]; 1790 return 0; 1791 } 1792 1793 static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol, 1794 struct snd_ctl_elem_value *ucontrol) 1795 { 1796 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1797 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1798 int value = ucontrol->value.integer.value[0]; 1799 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1800 1801 wsa->comp_enabled[comp] = value; 1802 1803 return 0; 1804 } 1805 1806 static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol, 1807 struct snd_ctl_elem_value *ucontrol) 1808 { 1809 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1810 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1811 1812 ucontrol->value.integer.value[0] = wsa->ear_spkr_gain; 1813 1814 return 0; 1815 } 1816 1817 static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol, 1818 struct snd_ctl_elem_value *ucontrol) 1819 { 1820 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1821 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1822 1823 wsa->ear_spkr_gain = ucontrol->value.integer.value[0]; 1824 1825 return 0; 1826 } 1827 1828 static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol, 1829 struct snd_ctl_elem_value *ucontrol) 1830 { 1831 struct snd_soc_dapm_widget *widget = 1832 snd_soc_dapm_kcontrol_widget(kcontrol); 1833 struct snd_soc_component *component = 1834 snd_soc_dapm_to_component(widget->dapm); 1835 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1836 1837 ucontrol->value.integer.value[0] = 1838 wsa->rx_port_value[widget->shift]; 1839 return 0; 1840 } 1841 1842 static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol, 1843 struct snd_ctl_elem_value *ucontrol) 1844 { 1845 struct snd_soc_dapm_widget *widget = 1846 snd_soc_dapm_kcontrol_widget(kcontrol); 1847 struct snd_soc_component *component = 1848 snd_soc_dapm_to_component(widget->dapm); 1849 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1850 struct snd_soc_dapm_update *update = NULL; 1851 u32 rx_port_value = ucontrol->value.integer.value[0]; 1852 u32 bit_input; 1853 u32 aif_rst; 1854 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1855 1856 aif_rst = wsa->rx_port_value[widget->shift]; 1857 if (!rx_port_value) { 1858 if (aif_rst == 0) { 1859 dev_err(component->dev, "%s: AIF reset already\n", __func__); 1860 return 0; 1861 } 1862 if (aif_rst >= WSA_MACRO_RX_MAX) { 1863 dev_err(component->dev, "%s: Invalid AIF reset\n", __func__); 1864 return 0; 1865 } 1866 } 1867 wsa->rx_port_value[widget->shift] = rx_port_value; 1868 1869 bit_input = widget->shift; 1870 1871 switch (rx_port_value) { 1872 case 0: 1873 if (wsa->active_ch_cnt[aif_rst]) { 1874 clear_bit(bit_input, 1875 &wsa->active_ch_mask[aif_rst]); 1876 wsa->active_ch_cnt[aif_rst]--; 1877 } 1878 break; 1879 case 1: 1880 case 2: 1881 set_bit(bit_input, 1882 &wsa->active_ch_mask[rx_port_value]); 1883 wsa->active_ch_cnt[rx_port_value]++; 1884 break; 1885 default: 1886 dev_err(component->dev, 1887 "%s: Invalid AIF_ID for WSA RX MUX %d\n", 1888 __func__, rx_port_value); 1889 return -EINVAL; 1890 } 1891 1892 snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, 1893 rx_port_value, e, update); 1894 return 0; 1895 } 1896 1897 static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, 1898 struct snd_ctl_elem_value *ucontrol) 1899 { 1900 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1901 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1902 int path = ((struct soc_mixer_control *)kcontrol->private_value)->shift; 1903 1904 ucontrol->value.integer.value[0] = wsa->is_softclip_on[path]; 1905 1906 return 0; 1907 } 1908 1909 static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, 1910 struct snd_ctl_elem_value *ucontrol) 1911 { 1912 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1913 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1914 int path = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1915 1916 wsa->is_softclip_on[path] = ucontrol->value.integer.value[0]; 1917 1918 return 0; 1919 } 1920 1921 static const struct snd_kcontrol_new wsa_macro_snd_controls[] = { 1922 SOC_ENUM_EXT("EAR SPKR PA Gain", wsa_macro_ear_spkr_pa_gain_enum, 1923 wsa_macro_ear_spkr_pa_gain_get, 1924 wsa_macro_ear_spkr_pa_gain_put), 1925 SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM, 1926 WSA_MACRO_SOFTCLIP0, 1, 0, 1927 wsa_macro_soft_clip_enable_get, 1928 wsa_macro_soft_clip_enable_put), 1929 SOC_SINGLE_EXT("WSA_Softclip1 Enable", SND_SOC_NOPM, 1930 WSA_MACRO_SOFTCLIP1, 1, 0, 1931 wsa_macro_soft_clip_enable_get, 1932 wsa_macro_soft_clip_enable_put), 1933 1934 SOC_SINGLE_S8_TLV("WSA_RX0 Digital Volume", CDC_WSA_RX0_RX_VOL_CTL, 1935 -84, 40, digital_gain), 1936 SOC_SINGLE_S8_TLV("WSA_RX1 Digital Volume", CDC_WSA_RX1_RX_VOL_CTL, 1937 -84, 40, digital_gain), 1938 1939 SOC_SINGLE("WSA_RX0 Digital Mute", CDC_WSA_RX0_RX_PATH_CTL, 4, 1, 0), 1940 SOC_SINGLE("WSA_RX1 Digital Mute", CDC_WSA_RX1_RX_PATH_CTL, 4, 1, 0), 1941 SOC_SINGLE("WSA_RX0_MIX Digital Mute", CDC_WSA_RX0_RX_PATH_MIX_CTL, 4, 1942 1, 0), 1943 SOC_SINGLE("WSA_RX1_MIX Digital Mute", CDC_WSA_RX1_RX_PATH_MIX_CTL, 4, 1944 1, 0), 1945 SOC_SINGLE_EXT("WSA_COMP1 Switch", SND_SOC_NOPM, WSA_MACRO_COMP1, 1, 0, 1946 wsa_macro_get_compander, wsa_macro_set_compander), 1947 SOC_SINGLE_EXT("WSA_COMP2 Switch", SND_SOC_NOPM, WSA_MACRO_COMP2, 1, 0, 1948 wsa_macro_get_compander, wsa_macro_set_compander), 1949 SOC_SINGLE_EXT("WSA_RX0 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX0, 1, 0, 1950 wsa_macro_get_ec_hq, wsa_macro_set_ec_hq), 1951 SOC_SINGLE_EXT("WSA_RX1 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX1, 1, 0, 1952 wsa_macro_get_ec_hq, wsa_macro_set_ec_hq), 1953 }; 1954 1955 static const struct soc_enum rx_mux_enum = 1956 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_mux_text), rx_mux_text); 1957 1958 static const struct snd_kcontrol_new rx_mux[WSA_MACRO_RX_MAX] = { 1959 SOC_DAPM_ENUM_EXT("WSA RX0 Mux", rx_mux_enum, 1960 wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 1961 SOC_DAPM_ENUM_EXT("WSA RX1 Mux", rx_mux_enum, 1962 wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 1963 SOC_DAPM_ENUM_EXT("WSA RX_MIX0 Mux", rx_mux_enum, 1964 wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 1965 SOC_DAPM_ENUM_EXT("WSA RX_MIX1 Mux", rx_mux_enum, 1966 wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 1967 }; 1968 1969 static int wsa_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol, 1970 struct snd_ctl_elem_value *ucontrol) 1971 { 1972 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 1973 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 1974 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1975 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1976 u32 spk_tx_id = mixer->shift; 1977 u32 dai_id = widget->shift; 1978 1979 if (test_bit(spk_tx_id, &wsa->active_ch_mask[dai_id])) 1980 ucontrol->value.integer.value[0] = 1; 1981 else 1982 ucontrol->value.integer.value[0] = 0; 1983 1984 return 0; 1985 } 1986 1987 static int wsa_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol, 1988 struct snd_ctl_elem_value *ucontrol) 1989 { 1990 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 1991 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 1992 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1993 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1994 u32 enable = ucontrol->value.integer.value[0]; 1995 u32 spk_tx_id = mixer->shift; 1996 1997 if (enable) { 1998 if (spk_tx_id == WSA_MACRO_TX0 && 1999 !test_bit(WSA_MACRO_TX0, 2000 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 2001 set_bit(WSA_MACRO_TX0, 2002 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 2003 wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++; 2004 } 2005 if (spk_tx_id == WSA_MACRO_TX1 && 2006 !test_bit(WSA_MACRO_TX1, 2007 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 2008 set_bit(WSA_MACRO_TX1, 2009 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 2010 wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++; 2011 } 2012 } else { 2013 if (spk_tx_id == WSA_MACRO_TX0 && 2014 test_bit(WSA_MACRO_TX0, 2015 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 2016 clear_bit(WSA_MACRO_TX0, 2017 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 2018 wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--; 2019 } 2020 if (spk_tx_id == WSA_MACRO_TX1 && 2021 test_bit(WSA_MACRO_TX1, 2022 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 2023 clear_bit(WSA_MACRO_TX1, 2024 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 2025 wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--; 2026 } 2027 } 2028 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL); 2029 2030 return 0; 2031 } 2032 2033 static const struct snd_kcontrol_new aif_vi_mixer[] = { 2034 SOC_SINGLE_EXT("WSA_SPKR_VI_1", SND_SOC_NOPM, WSA_MACRO_TX0, 1, 0, 2035 wsa_macro_vi_feed_mixer_get, 2036 wsa_macro_vi_feed_mixer_put), 2037 SOC_SINGLE_EXT("WSA_SPKR_VI_2", SND_SOC_NOPM, WSA_MACRO_TX1, 1, 0, 2038 wsa_macro_vi_feed_mixer_get, 2039 wsa_macro_vi_feed_mixer_put), 2040 }; 2041 2042 static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = { 2043 SND_SOC_DAPM_AIF_IN("WSA AIF1 PB", "WSA_AIF1 Playback", 0, 2044 SND_SOC_NOPM, 0, 0), 2045 SND_SOC_DAPM_AIF_IN("WSA AIF_MIX1 PB", "WSA_AIF_MIX1 Playback", 0, 2046 SND_SOC_NOPM, 0, 0), 2047 2048 SND_SOC_DAPM_AIF_OUT_E("WSA AIF_VI", "WSA_AIF_VI Capture", 0, 2049 SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0, 2050 wsa_macro_enable_vi_feedback, 2051 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 2052 SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0, 2053 SND_SOC_NOPM, 0, 0), 2054 2055 SND_SOC_DAPM_MIXER("WSA_AIF_VI Mixer", SND_SOC_NOPM, WSA_MACRO_AIF_VI, 2056 0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)), 2057 SND_SOC_DAPM_MUX_E("WSA RX_MIX EC0_MUX", SND_SOC_NOPM, 2058 WSA_MACRO_EC0_MUX, 0, 2059 &rx_mix_ec0_mux, wsa_macro_enable_echo, 2060 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2061 SND_SOC_DAPM_MUX_E("WSA RX_MIX EC1_MUX", SND_SOC_NOPM, 2062 WSA_MACRO_EC1_MUX, 0, 2063 &rx_mix_ec1_mux, wsa_macro_enable_echo, 2064 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2065 2066 SND_SOC_DAPM_MUX("WSA RX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX0, 0, 2067 &rx_mux[WSA_MACRO_RX0]), 2068 SND_SOC_DAPM_MUX("WSA RX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX1, 0, 2069 &rx_mux[WSA_MACRO_RX1]), 2070 SND_SOC_DAPM_MUX("WSA RX_MIX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 0, 2071 &rx_mux[WSA_MACRO_RX_MIX0]), 2072 SND_SOC_DAPM_MUX("WSA RX_MIX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 0, 2073 &rx_mux[WSA_MACRO_RX_MIX1]), 2074 2075 SND_SOC_DAPM_MIXER("WSA RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 2076 SND_SOC_DAPM_MIXER("WSA RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 2077 SND_SOC_DAPM_MIXER("WSA RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0), 2078 SND_SOC_DAPM_MIXER("WSA RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 2079 2080 SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, &rx0_prim_inp0_mux), 2081 SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, &rx0_prim_inp1_mux), 2082 SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, &rx0_prim_inp2_mux), 2083 SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 2084 0, &rx0_mix_mux, wsa_macro_enable_mix_path, 2085 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2086 SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, &rx1_prim_inp0_mux), 2087 SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, &rx1_prim_inp1_mux), 2088 SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, &rx1_prim_inp2_mux), 2089 SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 2090 0, &rx1_mix_mux, wsa_macro_enable_mix_path, 2091 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2092 2093 SND_SOC_DAPM_MIXER_E("WSA_RX INT0 MIX", SND_SOC_NOPM, 0, 0, NULL, 0, 2094 wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU), 2095 SND_SOC_DAPM_MIXER_E("WSA_RX INT1 MIX", SND_SOC_NOPM, 1, 0, NULL, 0, 2096 wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU), 2097 2098 SND_SOC_DAPM_MIXER("WSA_RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2099 SND_SOC_DAPM_MIXER("WSA_RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2100 2101 SND_SOC_DAPM_MUX("WSA_RX0 INT0 SIDETONE MIX", CDC_WSA_RX0_RX_PATH_CFG1, 2102 4, 0, &rx0_sidetone_mix_mux), 2103 2104 SND_SOC_DAPM_INPUT("WSA SRC0_INP"), 2105 SND_SOC_DAPM_INPUT("WSA_TX DEC0_INP"), 2106 SND_SOC_DAPM_INPUT("WSA_TX DEC1_INP"), 2107 2108 SND_SOC_DAPM_MIXER_E("WSA_RX INT0 INTERP", SND_SOC_NOPM, 2109 WSA_MACRO_COMP1, 0, NULL, 0, 2110 wsa_macro_enable_interpolator, 2111 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2112 SND_SOC_DAPM_POST_PMD), 2113 2114 SND_SOC_DAPM_MIXER_E("WSA_RX INT1 INTERP", SND_SOC_NOPM, 2115 WSA_MACRO_COMP2, 0, NULL, 0, 2116 wsa_macro_enable_interpolator, 2117 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2118 SND_SOC_DAPM_POST_PMD), 2119 2120 SND_SOC_DAPM_MIXER_E("WSA_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0, 2121 NULL, 0, wsa_macro_spk_boost_event, 2122 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2123 SND_SOC_DAPM_POST_PMD), 2124 2125 SND_SOC_DAPM_MIXER_E("WSA_RX INT1 CHAIN", SND_SOC_NOPM, 0, 0, 2126 NULL, 0, wsa_macro_spk_boost_event, 2127 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2128 SND_SOC_DAPM_POST_PMD), 2129 2130 SND_SOC_DAPM_INPUT("VIINPUT_WSA"), 2131 SND_SOC_DAPM_OUTPUT("WSA_SPK1 OUT"), 2132 SND_SOC_DAPM_OUTPUT("WSA_SPK2 OUT"), 2133 2134 SND_SOC_DAPM_SUPPLY("WSA_RX0_CLK", CDC_WSA_RX0_RX_PATH_CTL, 5, 0, NULL, 0), 2135 SND_SOC_DAPM_SUPPLY("WSA_RX1_CLK", CDC_WSA_RX1_RX_PATH_CTL, 5, 0, NULL, 0), 2136 SND_SOC_DAPM_SUPPLY("WSA_RX_MIX0_CLK", CDC_WSA_RX0_RX_PATH_MIX_CTL, 5, 0, NULL, 0), 2137 SND_SOC_DAPM_SUPPLY("WSA_RX_MIX1_CLK", CDC_WSA_RX1_RX_PATH_MIX_CTL, 5, 0, NULL, 0), 2138 SND_SOC_DAPM_SUPPLY_S("WSA_MCLK", 0, SND_SOC_NOPM, 0, 0, 2139 wsa_macro_mclk_event, 2140 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2141 }; 2142 2143 static const struct snd_soc_dapm_route wsa_audio_map[] = { 2144 /* VI Feedback */ 2145 {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_1", "VIINPUT_WSA"}, 2146 {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_2", "VIINPUT_WSA"}, 2147 {"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"}, 2148 {"WSA AIF_VI", NULL, "WSA_MCLK"}, 2149 2150 {"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"}, 2151 {"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"}, 2152 {"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"}, 2153 {"WSA RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"}, 2154 {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC0_MUX"}, 2155 {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC1_MUX"}, 2156 {"WSA AIF_ECHO", NULL, "WSA_MCLK"}, 2157 2158 {"WSA AIF1 PB", NULL, "WSA_MCLK"}, 2159 {"WSA AIF_MIX1 PB", NULL, "WSA_MCLK"}, 2160 2161 {"WSA RX0 MUX", "AIF1_PB", "WSA AIF1 PB"}, 2162 {"WSA RX1 MUX", "AIF1_PB", "WSA AIF1 PB"}, 2163 {"WSA RX_MIX0 MUX", "AIF1_PB", "WSA AIF1 PB"}, 2164 {"WSA RX_MIX1 MUX", "AIF1_PB", "WSA AIF1 PB"}, 2165 2166 {"WSA RX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 2167 {"WSA RX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 2168 {"WSA RX_MIX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 2169 {"WSA RX_MIX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 2170 2171 {"WSA RX0", NULL, "WSA RX0 MUX"}, 2172 {"WSA RX1", NULL, "WSA RX1 MUX"}, 2173 {"WSA RX_MIX0", NULL, "WSA RX_MIX0 MUX"}, 2174 {"WSA RX_MIX1", NULL, "WSA RX_MIX1 MUX"}, 2175 2176 {"WSA RX0", NULL, "WSA_RX0_CLK"}, 2177 {"WSA RX1", NULL, "WSA_RX1_CLK"}, 2178 {"WSA RX_MIX0", NULL, "WSA_RX_MIX0_CLK"}, 2179 {"WSA RX_MIX1", NULL, "WSA_RX_MIX1_CLK"}, 2180 2181 {"WSA_RX0 INP0", "RX0", "WSA RX0"}, 2182 {"WSA_RX0 INP0", "RX1", "WSA RX1"}, 2183 {"WSA_RX0 INP0", "RX_MIX0", "WSA RX_MIX0"}, 2184 {"WSA_RX0 INP0", "RX_MIX1", "WSA RX_MIX1"}, 2185 {"WSA_RX0 INP0", "DEC0", "WSA_TX DEC0_INP"}, 2186 {"WSA_RX0 INP0", "DEC1", "WSA_TX DEC1_INP"}, 2187 {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP0"}, 2188 2189 {"WSA_RX0 INP1", "RX0", "WSA RX0"}, 2190 {"WSA_RX0 INP1", "RX1", "WSA RX1"}, 2191 {"WSA_RX0 INP1", "RX_MIX0", "WSA RX_MIX0"}, 2192 {"WSA_RX0 INP1", "RX_MIX1", "WSA RX_MIX1"}, 2193 {"WSA_RX0 INP1", "DEC0", "WSA_TX DEC0_INP"}, 2194 {"WSA_RX0 INP1", "DEC1", "WSA_TX DEC1_INP"}, 2195 {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP1"}, 2196 2197 {"WSA_RX0 INP2", "RX0", "WSA RX0"}, 2198 {"WSA_RX0 INP2", "RX1", "WSA RX1"}, 2199 {"WSA_RX0 INP2", "RX_MIX0", "WSA RX_MIX0"}, 2200 {"WSA_RX0 INP2", "RX_MIX1", "WSA RX_MIX1"}, 2201 {"WSA_RX0 INP2", "DEC0", "WSA_TX DEC0_INP"}, 2202 {"WSA_RX0 INP2", "DEC1", "WSA_TX DEC1_INP"}, 2203 {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP2"}, 2204 2205 {"WSA_RX0 MIX INP", "RX0", "WSA RX0"}, 2206 {"WSA_RX0 MIX INP", "RX1", "WSA RX1"}, 2207 {"WSA_RX0 MIX INP", "RX_MIX0", "WSA RX_MIX0"}, 2208 {"WSA_RX0 MIX INP", "RX_MIX1", "WSA RX_MIX1"}, 2209 {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX0 MIX INP"}, 2210 2211 {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX INT0 MIX"}, 2212 {"WSA_RX INT0 INTERP", NULL, "WSA_RX INT0 SEC MIX"}, 2213 {"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"}, 2214 {"WSA_RX INT0 INTERP", NULL, "WSA_RX0 INT0 SIDETONE MIX"}, 2215 {"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 INTERP"}, 2216 2217 {"WSA_SPK1 OUT", NULL, "WSA_RX INT0 CHAIN"}, 2218 {"WSA_SPK1 OUT", NULL, "WSA_MCLK"}, 2219 2220 {"WSA_RX1 INP0", "RX0", "WSA RX0"}, 2221 {"WSA_RX1 INP0", "RX1", "WSA RX1"}, 2222 {"WSA_RX1 INP0", "RX_MIX0", "WSA RX_MIX0"}, 2223 {"WSA_RX1 INP0", "RX_MIX1", "WSA RX_MIX1"}, 2224 {"WSA_RX1 INP0", "DEC0", "WSA_TX DEC0_INP"}, 2225 {"WSA_RX1 INP0", "DEC1", "WSA_TX DEC1_INP"}, 2226 {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP0"}, 2227 2228 {"WSA_RX1 INP1", "RX0", "WSA RX0"}, 2229 {"WSA_RX1 INP1", "RX1", "WSA RX1"}, 2230 {"WSA_RX1 INP1", "RX_MIX0", "WSA RX_MIX0"}, 2231 {"WSA_RX1 INP1", "RX_MIX1", "WSA RX_MIX1"}, 2232 {"WSA_RX1 INP1", "DEC0", "WSA_TX DEC0_INP"}, 2233 {"WSA_RX1 INP1", "DEC1", "WSA_TX DEC1_INP"}, 2234 {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP1"}, 2235 2236 {"WSA_RX1 INP2", "RX0", "WSA RX0"}, 2237 {"WSA_RX1 INP2", "RX1", "WSA RX1"}, 2238 {"WSA_RX1 INP2", "RX_MIX0", "WSA RX_MIX0"}, 2239 {"WSA_RX1 INP2", "RX_MIX1", "WSA RX_MIX1"}, 2240 {"WSA_RX1 INP2", "DEC0", "WSA_TX DEC0_INP"}, 2241 {"WSA_RX1 INP2", "DEC1", "WSA_TX DEC1_INP"}, 2242 {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP2"}, 2243 2244 {"WSA_RX1 MIX INP", "RX0", "WSA RX0"}, 2245 {"WSA_RX1 MIX INP", "RX1", "WSA RX1"}, 2246 {"WSA_RX1 MIX INP", "RX_MIX0", "WSA RX_MIX0"}, 2247 {"WSA_RX1 MIX INP", "RX_MIX1", "WSA RX_MIX1"}, 2248 {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX1 MIX INP"}, 2249 2250 {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX INT1 MIX"}, 2251 {"WSA_RX INT1 INTERP", NULL, "WSA_RX INT1 SEC MIX"}, 2252 2253 {"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 INTERP"}, 2254 {"WSA_SPK2 OUT", NULL, "WSA_RX INT1 CHAIN"}, 2255 {"WSA_SPK2 OUT", NULL, "WSA_MCLK"}, 2256 }; 2257 2258 static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable) 2259 { 2260 struct regmap *regmap = wsa->regmap; 2261 2262 if (enable) { 2263 int ret; 2264 2265 ret = clk_prepare_enable(wsa->mclk); 2266 if (ret) { 2267 dev_err(wsa->dev, "failed to enable mclk\n"); 2268 return ret; 2269 } 2270 wsa_macro_mclk_enable(wsa, true); 2271 2272 /* reset swr ip */ 2273 regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2274 CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_ENABLE); 2275 2276 regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2277 CDC_WSA_SWR_CLK_EN_MASK, 2278 CDC_WSA_SWR_CLK_ENABLE); 2279 2280 /* Bring out of reset */ 2281 regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2282 CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_DISABLE); 2283 } else { 2284 regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2285 CDC_WSA_SWR_CLK_EN_MASK, 0); 2286 wsa_macro_mclk_enable(wsa, false); 2287 clk_disable_unprepare(wsa->mclk); 2288 } 2289 2290 return 0; 2291 } 2292 2293 static int wsa_macro_component_probe(struct snd_soc_component *comp) 2294 { 2295 struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp); 2296 2297 snd_soc_component_init_regmap(comp, wsa->regmap); 2298 2299 wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB; 2300 2301 /* set SPKR rate to FS_2P4_3P072 */ 2302 snd_soc_component_update_bits(comp, CDC_WSA_RX0_RX_PATH_CFG1, 2303 CDC_WSA_RX_PATH_SPKR_RATE_MASK, 2304 CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072); 2305 2306 snd_soc_component_update_bits(comp, CDC_WSA_RX1_RX_PATH_CFG1, 2307 CDC_WSA_RX_PATH_SPKR_RATE_MASK, 2308 CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072); 2309 2310 wsa_macro_set_spkr_mode(comp, WSA_MACRO_SPKR_MODE_1); 2311 2312 return 0; 2313 } 2314 2315 static int swclk_gate_enable(struct clk_hw *hw) 2316 { 2317 return wsa_swrm_clock(to_wsa_macro(hw), true); 2318 } 2319 2320 static void swclk_gate_disable(struct clk_hw *hw) 2321 { 2322 wsa_swrm_clock(to_wsa_macro(hw), false); 2323 } 2324 2325 static int swclk_gate_is_enabled(struct clk_hw *hw) 2326 { 2327 struct wsa_macro *wsa = to_wsa_macro(hw); 2328 int ret, val; 2329 2330 regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val); 2331 ret = val & BIT(0); 2332 2333 return ret; 2334 } 2335 2336 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2337 unsigned long parent_rate) 2338 { 2339 return parent_rate / 2; 2340 } 2341 2342 static const struct clk_ops swclk_gate_ops = { 2343 .prepare = swclk_gate_enable, 2344 .unprepare = swclk_gate_disable, 2345 .is_enabled = swclk_gate_is_enabled, 2346 .recalc_rate = swclk_recalc_rate, 2347 }; 2348 2349 static int wsa_macro_register_mclk_output(struct wsa_macro *wsa) 2350 { 2351 struct device *dev = wsa->dev; 2352 const char *parent_clk_name; 2353 const char *clk_name = "mclk"; 2354 struct clk_hw *hw; 2355 struct clk_init_data init; 2356 int ret; 2357 2358 parent_clk_name = __clk_get_name(wsa->npl); 2359 2360 init.name = clk_name; 2361 init.ops = &swclk_gate_ops; 2362 init.flags = 0; 2363 init.parent_names = &parent_clk_name; 2364 init.num_parents = 1; 2365 wsa->hw.init = &init; 2366 hw = &wsa->hw; 2367 ret = clk_hw_register(wsa->dev, hw); 2368 if (ret) 2369 return ret; 2370 2371 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 2372 } 2373 2374 static const struct snd_soc_component_driver wsa_macro_component_drv = { 2375 .name = "WSA MACRO", 2376 .probe = wsa_macro_component_probe, 2377 .controls = wsa_macro_snd_controls, 2378 .num_controls = ARRAY_SIZE(wsa_macro_snd_controls), 2379 .dapm_widgets = wsa_macro_dapm_widgets, 2380 .num_dapm_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets), 2381 .dapm_routes = wsa_audio_map, 2382 .num_dapm_routes = ARRAY_SIZE(wsa_audio_map), 2383 }; 2384 2385 static int wsa_macro_probe(struct platform_device *pdev) 2386 { 2387 struct device *dev = &pdev->dev; 2388 struct wsa_macro *wsa; 2389 void __iomem *base; 2390 int ret; 2391 2392 wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL); 2393 if (!wsa) 2394 return -ENOMEM; 2395 2396 wsa->macro = devm_clk_get_optional(dev, "macro"); 2397 if (IS_ERR(wsa->macro)) 2398 return PTR_ERR(wsa->macro); 2399 2400 wsa->dcodec = devm_clk_get_optional(dev, "dcodec"); 2401 if (IS_ERR(wsa->dcodec)) 2402 return PTR_ERR(wsa->dcodec); 2403 2404 wsa->mclk = devm_clk_get(dev, "mclk"); 2405 if (IS_ERR(wsa->mclk)) 2406 return PTR_ERR(wsa->mclk); 2407 2408 wsa->npl = devm_clk_get(dev, "npl"); 2409 if (IS_ERR(wsa->npl)) 2410 return PTR_ERR(wsa->npl); 2411 2412 wsa->fsgen = devm_clk_get(dev, "fsgen"); 2413 if (IS_ERR(wsa->fsgen)) 2414 return PTR_ERR(wsa->fsgen); 2415 2416 base = devm_platform_ioremap_resource(pdev, 0); 2417 if (IS_ERR(base)) 2418 return PTR_ERR(base); 2419 2420 wsa->regmap = devm_regmap_init_mmio(dev, base, &wsa_regmap_config); 2421 if (IS_ERR(wsa->regmap)) 2422 return PTR_ERR(wsa->regmap); 2423 2424 dev_set_drvdata(dev, wsa); 2425 2426 wsa->dev = dev; 2427 2428 /* set MCLK and NPL rates */ 2429 clk_set_rate(wsa->mclk, WSA_MACRO_MCLK_FREQ); 2430 clk_set_rate(wsa->npl, WSA_MACRO_MCLK_FREQ); 2431 2432 ret = clk_prepare_enable(wsa->macro); 2433 if (ret) 2434 goto err; 2435 2436 ret = clk_prepare_enable(wsa->dcodec); 2437 if (ret) 2438 goto err_dcodec; 2439 2440 ret = clk_prepare_enable(wsa->mclk); 2441 if (ret) 2442 goto err_mclk; 2443 2444 ret = clk_prepare_enable(wsa->npl); 2445 if (ret) 2446 goto err_npl; 2447 2448 ret = clk_prepare_enable(wsa->fsgen); 2449 if (ret) 2450 goto err_fsgen; 2451 2452 ret = wsa_macro_register_mclk_output(wsa); 2453 if (ret) 2454 goto err_clkout; 2455 2456 2457 ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv, 2458 wsa_macro_dai, 2459 ARRAY_SIZE(wsa_macro_dai)); 2460 if (ret) 2461 goto err_clkout; 2462 2463 pm_runtime_set_autosuspend_delay(dev, 3000); 2464 pm_runtime_use_autosuspend(dev); 2465 pm_runtime_mark_last_busy(dev); 2466 pm_runtime_set_active(dev); 2467 pm_runtime_enable(dev); 2468 2469 return 0; 2470 2471 err_clkout: 2472 clk_disable_unprepare(wsa->fsgen); 2473 err_fsgen: 2474 clk_disable_unprepare(wsa->npl); 2475 err_npl: 2476 clk_disable_unprepare(wsa->mclk); 2477 err_mclk: 2478 clk_disable_unprepare(wsa->dcodec); 2479 err_dcodec: 2480 clk_disable_unprepare(wsa->macro); 2481 err: 2482 return ret; 2483 2484 } 2485 2486 static int wsa_macro_remove(struct platform_device *pdev) 2487 { 2488 struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev); 2489 2490 clk_disable_unprepare(wsa->macro); 2491 clk_disable_unprepare(wsa->dcodec); 2492 clk_disable_unprepare(wsa->mclk); 2493 clk_disable_unprepare(wsa->npl); 2494 clk_disable_unprepare(wsa->fsgen); 2495 2496 return 0; 2497 } 2498 2499 static int __maybe_unused wsa_macro_runtime_suspend(struct device *dev) 2500 { 2501 struct wsa_macro *wsa = dev_get_drvdata(dev); 2502 2503 regcache_cache_only(wsa->regmap, true); 2504 regcache_mark_dirty(wsa->regmap); 2505 2506 clk_disable_unprepare(wsa->mclk); 2507 clk_disable_unprepare(wsa->npl); 2508 clk_disable_unprepare(wsa->fsgen); 2509 2510 return 0; 2511 } 2512 2513 static int __maybe_unused wsa_macro_runtime_resume(struct device *dev) 2514 { 2515 struct wsa_macro *wsa = dev_get_drvdata(dev); 2516 int ret; 2517 2518 ret = clk_prepare_enable(wsa->mclk); 2519 if (ret) { 2520 dev_err(dev, "unable to prepare mclk\n"); 2521 return ret; 2522 } 2523 2524 ret = clk_prepare_enable(wsa->npl); 2525 if (ret) { 2526 dev_err(dev, "unable to prepare mclkx2\n"); 2527 goto err_npl; 2528 } 2529 2530 ret = clk_prepare_enable(wsa->fsgen); 2531 if (ret) { 2532 dev_err(dev, "unable to prepare fsgen\n"); 2533 goto err_fsgen; 2534 } 2535 2536 regcache_cache_only(wsa->regmap, false); 2537 regcache_sync(wsa->regmap); 2538 2539 return 0; 2540 err_fsgen: 2541 clk_disable_unprepare(wsa->npl); 2542 err_npl: 2543 clk_disable_unprepare(wsa->mclk); 2544 2545 return ret; 2546 } 2547 2548 static const struct dev_pm_ops wsa_macro_pm_ops = { 2549 SET_RUNTIME_PM_OPS(wsa_macro_runtime_suspend, wsa_macro_runtime_resume, NULL) 2550 }; 2551 2552 static const struct of_device_id wsa_macro_dt_match[] = { 2553 {.compatible = "qcom,sc7280-lpass-wsa-macro"}, 2554 {.compatible = "qcom,sm8250-lpass-wsa-macro"}, 2555 {.compatible = "qcom,sm8450-lpass-wsa-macro"}, 2556 {.compatible = "qcom,sc8280xp-lpass-wsa-macro" }, 2557 {} 2558 }; 2559 MODULE_DEVICE_TABLE(of, wsa_macro_dt_match); 2560 2561 static struct platform_driver wsa_macro_driver = { 2562 .driver = { 2563 .name = "wsa_macro", 2564 .of_match_table = wsa_macro_dt_match, 2565 .pm = &wsa_macro_pm_ops, 2566 }, 2567 .probe = wsa_macro_probe, 2568 .remove = wsa_macro_remove, 2569 }; 2570 2571 module_platform_driver(wsa_macro_driver); 2572 MODULE_DESCRIPTION("WSA macro driver"); 2573 MODULE_LICENSE("GPL"); 2574