1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/init.h> 6 #include <linux/io.h> 7 #include <linux/platform_device.h> 8 #include <linux/clk.h> 9 #include <linux/of_clk.h> 10 #include <linux/clk-provider.h> 11 #include <sound/soc.h> 12 #include <sound/soc-dapm.h> 13 #include <linux/of_platform.h> 14 #include <sound/tlv.h> 15 #include "lpass-wsa-macro.h" 16 17 #define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 18 #define CDC_WSA_MCLK_EN_MASK BIT(0) 19 #define CDC_WSA_MCLK_ENABLE BIT(0) 20 #define CDC_WSA_MCLK_DISABLE 0 21 #define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 22 #define CDC_WSA_FS_CNT_EN_MASK BIT(0) 23 #define CDC_WSA_FS_CNT_ENABLE BIT(0) 24 #define CDC_WSA_FS_CNT_DISABLE 0 25 #define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL (0x0008) 26 #define CDC_WSA_SWR_CLK_EN_MASK BIT(0) 27 #define CDC_WSA_SWR_CLK_ENABLE BIT(0) 28 #define CDC_WSA_SWR_RST_EN_MASK BIT(1) 29 #define CDC_WSA_SWR_RST_ENABLE BIT(1) 30 #define CDC_WSA_SWR_RST_DISABLE 0 31 #define CDC_WSA_TOP_TOP_CFG0 (0x0080) 32 #define CDC_WSA_TOP_TOP_CFG1 (0x0084) 33 #define CDC_WSA_TOP_FREQ_MCLK (0x0088) 34 #define CDC_WSA_TOP_DEBUG_BUS_SEL (0x008C) 35 #define CDC_WSA_TOP_DEBUG_EN0 (0x0090) 36 #define CDC_WSA_TOP_DEBUG_EN1 (0x0094) 37 #define CDC_WSA_TOP_DEBUG_DSM_LB (0x0098) 38 #define CDC_WSA_TOP_RX_I2S_CTL (0x009C) 39 #define CDC_WSA_TOP_TX_I2S_CTL (0x00A0) 40 #define CDC_WSA_TOP_I2S_CLK (0x00A4) 41 #define CDC_WSA_TOP_I2S_RESET (0x00A8) 42 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 (0x0100) 43 #define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(5, 3) 44 #define CDC_WSA_RX_INTX_2_SEL_MASK GENMASK(2, 0) 45 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 (0x0104) 46 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 (0x0108) 47 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 (0x010C) 48 #define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 (0x0110) 49 #define CDC_WSA_RX_MIX_TX1_SEL_MASK GENMASK(5, 3) 50 #define CDC_WSA_RX_MIX_TX1_SEL_SHFT 3 51 #define CDC_WSA_RX_MIX_TX0_SEL_MASK GENMASK(2, 0) 52 #define CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (0x0114) 53 #define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (0x0118) 54 #define CDC_WSA_TX0_SPKR_PROT_PATH_CTL (0x0244) 55 #define CDC_WSA_TX_SPKR_PROT_RESET_MASK BIT(5) 56 #define CDC_WSA_TX_SPKR_PROT_RESET BIT(5) 57 #define CDC_WSA_TX_SPKR_PROT_NO_RESET 0 58 #define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK BIT(4) 59 #define CDC_WSA_TX_SPKR_PROT_CLK_ENABLE BIT(4) 60 #define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0 61 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0) 62 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K 0 63 #define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (0x0248) 64 #define CDC_WSA_TX1_SPKR_PROT_PATH_CTL (0x0264) 65 #define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (0x0268) 66 #define CDC_WSA_TX2_SPKR_PROT_PATH_CTL (0x0284) 67 #define CDC_WSA_TX2_SPKR_PROT_PATH_CFG0 (0x0288) 68 #define CDC_WSA_TX3_SPKR_PROT_PATH_CTL (0x02A4) 69 #define CDC_WSA_TX3_SPKR_PROT_PATH_CFG0 (0x02A8) 70 #define CDC_WSA_INTR_CTRL_CFG (0x0340) 71 #define CDC_WSA_INTR_CTRL_CLR_COMMIT (0x0344) 72 #define CDC_WSA_INTR_CTRL_PIN1_MASK0 (0x0360) 73 #define CDC_WSA_INTR_CTRL_PIN1_STATUS0 (0x0368) 74 #define CDC_WSA_INTR_CTRL_PIN1_CLEAR0 (0x0370) 75 #define CDC_WSA_INTR_CTRL_PIN2_MASK0 (0x0380) 76 #define CDC_WSA_INTR_CTRL_PIN2_STATUS0 (0x0388) 77 #define CDC_WSA_INTR_CTRL_PIN2_CLEAR0 (0x0390) 78 #define CDC_WSA_INTR_CTRL_LEVEL0 (0x03C0) 79 #define CDC_WSA_INTR_CTRL_BYPASS0 (0x03C8) 80 #define CDC_WSA_INTR_CTRL_SET0 (0x03D0) 81 #define CDC_WSA_RX0_RX_PATH_CTL (0x0400) 82 #define CDC_WSA_RX_PATH_CLK_EN_MASK BIT(5) 83 #define CDC_WSA_RX_PATH_CLK_ENABLE BIT(5) 84 #define CDC_WSA_RX_PATH_CLK_DISABLE 0 85 #define CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK BIT(4) 86 #define CDC_WSA_RX_PATH_PGA_MUTE_ENABLE BIT(4) 87 #define CDC_WSA_RX_PATH_PGA_MUTE_DISABLE 0 88 #define CDC_WSA_RX0_RX_PATH_CFG0 (0x0404) 89 #define CDC_WSA_RX_PATH_COMP_EN_MASK BIT(1) 90 #define CDC_WSA_RX_PATH_COMP_ENABLE BIT(1) 91 #define CDC_WSA_RX_PATH_HD2_EN_MASK BIT(2) 92 #define CDC_WSA_RX_PATH_HD2_ENABLE BIT(2) 93 #define CDC_WSA_RX_PATH_SPKR_RATE_MASK BIT(3) 94 #define CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072 BIT(3) 95 #define CDC_WSA_RX0_RX_PATH_CFG1 (0x0408) 96 #define CDC_WSA_RX_PATH_SMART_BST_EN_MASK BIT(0) 97 #define CDC_WSA_RX_PATH_SMART_BST_ENABLE BIT(0) 98 #define CDC_WSA_RX_PATH_SMART_BST_DISABLE 0 99 #define CDC_WSA_RX0_RX_PATH_CFG2 (0x040C) 100 #define CDC_WSA_RX0_RX_PATH_CFG3 (0x0410) 101 #define CDC_WSA_RX_DC_DCOEFF_MASK GENMASK(1, 0) 102 #define CDC_WSA_RX0_RX_VOL_CTL (0x0414) 103 #define CDC_WSA_RX0_RX_PATH_MIX_CTL (0x0418) 104 #define CDC_WSA_RX_PATH_MIX_CLK_EN_MASK BIT(5) 105 #define CDC_WSA_RX_PATH_MIX_CLK_ENABLE BIT(5) 106 #define CDC_WSA_RX_PATH_MIX_CLK_DISABLE 0 107 #define CDC_WSA_RX0_RX_PATH_MIX_CFG (0x041C) 108 #define CDC_WSA_RX0_RX_VOL_MIX_CTL (0x0420) 109 #define CDC_WSA_RX0_RX_PATH_SEC0 (0x0424) 110 #define CDC_WSA_RX0_RX_PATH_SEC1 (0x0428) 111 #define CDC_WSA_RX_PGA_HALF_DB_MASK BIT(0) 112 #define CDC_WSA_RX_PGA_HALF_DB_ENABLE BIT(0) 113 #define CDC_WSA_RX_PGA_HALF_DB_DISABLE 0 114 #define CDC_WSA_RX0_RX_PATH_SEC2 (0x042C) 115 #define CDC_WSA_RX0_RX_PATH_SEC3 (0x0430) 116 #define CDC_WSA_RX_PATH_HD2_SCALE_MASK GENMASK(1, 0) 117 #define CDC_WSA_RX_PATH_HD2_ALPHA_MASK GENMASK(5, 2) 118 #define CDC_WSA_RX0_RX_PATH_SEC5 (0x0438) 119 #define CDC_WSA_RX0_RX_PATH_SEC6 (0x043C) 120 #define CDC_WSA_RX0_RX_PATH_SEC7 (0x0440) 121 #define CDC_WSA_RX0_RX_PATH_MIX_SEC0 (0x0444) 122 #define CDC_WSA_RX0_RX_PATH_MIX_SEC1 (0x0448) 123 #define CDC_WSA_RX0_RX_PATH_DSMDEM_CTL (0x044C) 124 #define CDC_WSA_RX_DSMDEM_CLK_EN_MASK BIT(0) 125 #define CDC_WSA_RX_DSMDEM_CLK_ENABLE BIT(0) 126 #define CDC_WSA_RX1_RX_PATH_CTL (0x0480) 127 #define CDC_WSA_RX1_RX_PATH_CFG0 (0x0484) 128 #define CDC_WSA_RX1_RX_PATH_CFG1 (0x0488) 129 #define CDC_WSA_RX1_RX_PATH_CFG2 (0x048C) 130 #define CDC_WSA_RX1_RX_PATH_CFG3 (0x0490) 131 #define CDC_WSA_RX1_RX_VOL_CTL (0x0494) 132 #define CDC_WSA_RX1_RX_PATH_MIX_CTL (0x0498) 133 #define CDC_WSA_RX1_RX_PATH_MIX_CFG (0x049C) 134 #define CDC_WSA_RX1_RX_VOL_MIX_CTL (0x04A0) 135 #define CDC_WSA_RX1_RX_PATH_SEC0 (0x04A4) 136 #define CDC_WSA_RX1_RX_PATH_SEC1 (0x04A8) 137 #define CDC_WSA_RX1_RX_PATH_SEC2 (0x04AC) 138 #define CDC_WSA_RX1_RX_PATH_SEC3 (0x04B0) 139 #define CDC_WSA_RX1_RX_PATH_SEC5 (0x04B8) 140 #define CDC_WSA_RX1_RX_PATH_SEC6 (0x04BC) 141 #define CDC_WSA_RX1_RX_PATH_SEC7 (0x04C0) 142 #define CDC_WSA_RX1_RX_PATH_MIX_SEC0 (0x04C4) 143 #define CDC_WSA_RX1_RX_PATH_MIX_SEC1 (0x04C8) 144 #define CDC_WSA_RX1_RX_PATH_DSMDEM_CTL (0x04CC) 145 #define CDC_WSA_BOOST0_BOOST_PATH_CTL (0x0500) 146 #define CDC_WSA_BOOST_PATH_CLK_EN_MASK BIT(4) 147 #define CDC_WSA_BOOST_PATH_CLK_ENABLE BIT(4) 148 #define CDC_WSA_BOOST_PATH_CLK_DISABLE 0 149 #define CDC_WSA_BOOST0_BOOST_CTL (0x0504) 150 #define CDC_WSA_BOOST0_BOOST_CFG1 (0x0508) 151 #define CDC_WSA_BOOST0_BOOST_CFG2 (0x050C) 152 #define CDC_WSA_BOOST1_BOOST_PATH_CTL (0x0540) 153 #define CDC_WSA_BOOST1_BOOST_CTL (0x0544) 154 #define CDC_WSA_BOOST1_BOOST_CFG1 (0x0548) 155 #define CDC_WSA_BOOST1_BOOST_CFG2 (0x054C) 156 #define CDC_WSA_COMPANDER0_CTL0 (0x0580) 157 #define CDC_WSA_COMPANDER_CLK_EN_MASK BIT(0) 158 #define CDC_WSA_COMPANDER_CLK_ENABLE BIT(0) 159 #define CDC_WSA_COMPANDER_SOFT_RST_MASK BIT(1) 160 #define CDC_WSA_COMPANDER_SOFT_RST_ENABLE BIT(1) 161 #define CDC_WSA_COMPANDER_HALT_MASK BIT(2) 162 #define CDC_WSA_COMPANDER_HALT BIT(2) 163 #define CDC_WSA_COMPANDER0_CTL1 (0x0584) 164 #define CDC_WSA_COMPANDER0_CTL2 (0x0588) 165 #define CDC_WSA_COMPANDER0_CTL3 (0x058C) 166 #define CDC_WSA_COMPANDER0_CTL4 (0x0590) 167 #define CDC_WSA_COMPANDER0_CTL5 (0x0594) 168 #define CDC_WSA_COMPANDER0_CTL6 (0x0598) 169 #define CDC_WSA_COMPANDER0_CTL7 (0x059C) 170 #define CDC_WSA_COMPANDER1_CTL0 (0x05C0) 171 #define CDC_WSA_COMPANDER1_CTL1 (0x05C4) 172 #define CDC_WSA_COMPANDER1_CTL2 (0x05C8) 173 #define CDC_WSA_COMPANDER1_CTL3 (0x05CC) 174 #define CDC_WSA_COMPANDER1_CTL4 (0x05D0) 175 #define CDC_WSA_COMPANDER1_CTL5 (0x05D4) 176 #define CDC_WSA_COMPANDER1_CTL6 (0x05D8) 177 #define CDC_WSA_COMPANDER1_CTL7 (0x05DC) 178 #define CDC_WSA_SOFTCLIP0_CRC (0x0600) 179 #define CDC_WSA_SOFTCLIP_CLK_EN_MASK BIT(0) 180 #define CDC_WSA_SOFTCLIP_CLK_ENABLE BIT(0) 181 #define CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (0x0604) 182 #define CDC_WSA_SOFTCLIP_EN_MASK BIT(0) 183 #define CDC_WSA_SOFTCLIP_ENABLE BIT(0) 184 #define CDC_WSA_SOFTCLIP1_CRC (0x0640) 185 #define CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (0x0644) 186 #define CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL (0x0680) 187 #define CDC_WSA_EC_HQ_EC_CLK_EN_MASK BIT(0) 188 #define CDC_WSA_EC_HQ_EC_CLK_ENABLE BIT(0) 189 #define CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 (0x0684) 190 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK GENMASK(4, 1) 191 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K BIT(3) 192 #define CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL (0x06C0) 193 #define CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 (0x06C4) 194 #define CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL (0x0700) 195 #define CDC_WSA_SPLINE_ASRC0_CTL0 (0x0704) 196 #define CDC_WSA_SPLINE_ASRC0_CTL1 (0x0708) 197 #define CDC_WSA_SPLINE_ASRC0_FIFO_CTL (0x070C) 198 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB (0x0710) 199 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB (0x0714) 200 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB (0x0718) 201 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB (0x071C) 202 #define CDC_WSA_SPLINE_ASRC0_STATUS_FIFO (0x0720) 203 #define CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL (0x0740) 204 #define CDC_WSA_SPLINE_ASRC1_CTL0 (0x0744) 205 #define CDC_WSA_SPLINE_ASRC1_CTL1 (0x0748) 206 #define CDC_WSA_SPLINE_ASRC1_FIFO_CTL (0x074C) 207 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB (0x0750) 208 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB (0x0754) 209 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB (0x0758) 210 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB (0x075C) 211 #define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO (0x0760) 212 #define WSA_MAX_OFFSET (0x0760) 213 214 #define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 215 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 216 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 217 #define WSA_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\ 218 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 219 #define WSA_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 220 SNDRV_PCM_FMTBIT_S24_LE |\ 221 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 222 223 #define WSA_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 224 SNDRV_PCM_RATE_48000) 225 #define WSA_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 226 SNDRV_PCM_FMTBIT_S24_LE |\ 227 SNDRV_PCM_FMTBIT_S24_3LE) 228 229 #define NUM_INTERPOLATORS 2 230 #define WSA_NUM_CLKS_MAX 5 231 #define WSA_MACRO_MCLK_FREQ 19200000 232 #define WSA_MACRO_MUX_INP_SHFT 0x3 233 #define WSA_MACRO_MUX_INP_MASK1 0x07 234 #define WSA_MACRO_MUX_INP_MASK2 0x38 235 #define WSA_MACRO_MUX_CFG_OFFSET 0x8 236 #define WSA_MACRO_MUX_CFG1_OFFSET 0x4 237 #define WSA_MACRO_RX_COMP_OFFSET 0x40 238 #define WSA_MACRO_RX_SOFTCLIP_OFFSET 0x40 239 #define WSA_MACRO_RX_PATH_OFFSET 0x80 240 #define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10 241 #define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C 242 #define WSA_MACRO_FS_RATE_MASK 0x0F 243 #define WSA_MACRO_EC_MIX_TX0_MASK 0x03 244 #define WSA_MACRO_EC_MIX_TX1_MASK 0x18 245 #define WSA_MACRO_MAX_DMA_CH_PER_PORT 0x2 246 247 enum { 248 WSA_MACRO_GAIN_OFFSET_M1P5_DB, 249 WSA_MACRO_GAIN_OFFSET_0_DB, 250 }; 251 enum { 252 WSA_MACRO_RX0 = 0, 253 WSA_MACRO_RX1, 254 WSA_MACRO_RX_MIX, 255 WSA_MACRO_RX_MIX0 = WSA_MACRO_RX_MIX, 256 WSA_MACRO_RX_MIX1, 257 WSA_MACRO_RX_MAX, 258 }; 259 260 enum { 261 WSA_MACRO_TX0 = 0, 262 WSA_MACRO_TX1, 263 WSA_MACRO_TX_MAX, 264 }; 265 266 enum { 267 WSA_MACRO_EC0_MUX = 0, 268 WSA_MACRO_EC1_MUX, 269 WSA_MACRO_EC_MUX_MAX, 270 }; 271 272 enum { 273 WSA_MACRO_COMP1, /* SPK_L */ 274 WSA_MACRO_COMP2, /* SPK_R */ 275 WSA_MACRO_COMP_MAX 276 }; 277 278 enum { 279 WSA_MACRO_SOFTCLIP0, /* RX0 */ 280 WSA_MACRO_SOFTCLIP1, /* RX1 */ 281 WSA_MACRO_SOFTCLIP_MAX 282 }; 283 284 enum { 285 INTn_1_INP_SEL_ZERO = 0, 286 INTn_1_INP_SEL_RX0, 287 INTn_1_INP_SEL_RX1, 288 INTn_1_INP_SEL_RX2, 289 INTn_1_INP_SEL_RX3, 290 INTn_1_INP_SEL_DEC0, 291 INTn_1_INP_SEL_DEC1, 292 }; 293 294 enum { 295 INTn_2_INP_SEL_ZERO = 0, 296 INTn_2_INP_SEL_RX0, 297 INTn_2_INP_SEL_RX1, 298 INTn_2_INP_SEL_RX2, 299 INTn_2_INP_SEL_RX3, 300 }; 301 302 struct interp_sample_rate { 303 int sample_rate; 304 int rate_val; 305 }; 306 307 static struct interp_sample_rate int_prim_sample_rate_val[] = { 308 {8000, 0x0}, /* 8K */ 309 {16000, 0x1}, /* 16K */ 310 {24000, -EINVAL},/* 24K */ 311 {32000, 0x3}, /* 32K */ 312 {48000, 0x4}, /* 48K */ 313 {96000, 0x5}, /* 96K */ 314 {192000, 0x6}, /* 192K */ 315 {384000, 0x7}, /* 384K */ 316 {44100, 0x8}, /* 44.1K */ 317 }; 318 319 static struct interp_sample_rate int_mix_sample_rate_val[] = { 320 {48000, 0x4}, /* 48K */ 321 {96000, 0x5}, /* 96K */ 322 {192000, 0x6}, /* 192K */ 323 }; 324 325 enum { 326 WSA_MACRO_AIF_INVALID = 0, 327 WSA_MACRO_AIF1_PB, 328 WSA_MACRO_AIF_MIX1_PB, 329 WSA_MACRO_AIF_VI, 330 WSA_MACRO_AIF_ECHO, 331 WSA_MACRO_MAX_DAIS, 332 }; 333 334 struct wsa_macro { 335 struct device *dev; 336 int comp_enabled[WSA_MACRO_COMP_MAX]; 337 int ec_hq[WSA_MACRO_RX1 + 1]; 338 u16 prim_int_users[WSA_MACRO_RX1 + 1]; 339 u16 wsa_mclk_users; 340 bool reset_swr; 341 unsigned long active_ch_mask[WSA_MACRO_MAX_DAIS]; 342 unsigned long active_ch_cnt[WSA_MACRO_MAX_DAIS]; 343 int rx_port_value[WSA_MACRO_RX_MAX]; 344 int ear_spkr_gain; 345 int spkr_gain_offset; 346 int spkr_mode; 347 int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX]; 348 int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX]; 349 struct regmap *regmap; 350 struct clk_bulk_data clks[WSA_NUM_CLKS_MAX]; 351 struct clk_hw hw; 352 }; 353 #define to_wsa_macro(_hw) container_of(_hw, struct wsa_macro, hw) 354 355 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 356 357 static const char * const wsa_macro_ear_spkr_pa_gain_text[] = { 358 "G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB", 359 "G_4_DB", "G_5_DB", "G_6_DB" 360 }; 361 362 static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum, 363 wsa_macro_ear_spkr_pa_gain_text); 364 365 static const struct reg_default wsa_defaults[] = { 366 /* WSA Macro */ 367 { CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, 368 { CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, 369 { CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 370 { CDC_WSA_TOP_TOP_CFG0, 0x00}, 371 { CDC_WSA_TOP_TOP_CFG1, 0x00}, 372 { CDC_WSA_TOP_FREQ_MCLK, 0x00}, 373 { CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00}, 374 { CDC_WSA_TOP_DEBUG_EN0, 0x00}, 375 { CDC_WSA_TOP_DEBUG_EN1, 0x00}, 376 { CDC_WSA_TOP_DEBUG_DSM_LB, 0x88}, 377 { CDC_WSA_TOP_RX_I2S_CTL, 0x0C}, 378 { CDC_WSA_TOP_TX_I2S_CTL, 0x0C}, 379 { CDC_WSA_TOP_I2S_CLK, 0x02}, 380 { CDC_WSA_TOP_I2S_RESET, 0x00}, 381 { CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00}, 382 { CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00}, 383 { CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00}, 384 { CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00}, 385 { CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00}, 386 { CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00}, 387 { CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00}, 388 { CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02}, 389 { CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00}, 390 { CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02}, 391 { CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00}, 392 { CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02}, 393 { CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00}, 394 { CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02}, 395 { CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00}, 396 { CDC_WSA_INTR_CTRL_CFG, 0x00}, 397 { CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00}, 398 { CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF}, 399 { CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00}, 400 { CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00}, 401 { CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF}, 402 { CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00}, 403 { CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00}, 404 { CDC_WSA_INTR_CTRL_LEVEL0, 0x00}, 405 { CDC_WSA_INTR_CTRL_BYPASS0, 0x00}, 406 { CDC_WSA_INTR_CTRL_SET0, 0x00}, 407 { CDC_WSA_RX0_RX_PATH_CTL, 0x04}, 408 { CDC_WSA_RX0_RX_PATH_CFG0, 0x00}, 409 { CDC_WSA_RX0_RX_PATH_CFG1, 0x64}, 410 { CDC_WSA_RX0_RX_PATH_CFG2, 0x8F}, 411 { CDC_WSA_RX0_RX_PATH_CFG3, 0x00}, 412 { CDC_WSA_RX0_RX_VOL_CTL, 0x00}, 413 { CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04}, 414 { CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E}, 415 { CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00}, 416 { CDC_WSA_RX0_RX_PATH_SEC0, 0x04}, 417 { CDC_WSA_RX0_RX_PATH_SEC1, 0x08}, 418 { CDC_WSA_RX0_RX_PATH_SEC2, 0x00}, 419 { CDC_WSA_RX0_RX_PATH_SEC3, 0x00}, 420 { CDC_WSA_RX0_RX_PATH_SEC5, 0x00}, 421 { CDC_WSA_RX0_RX_PATH_SEC6, 0x00}, 422 { CDC_WSA_RX0_RX_PATH_SEC7, 0x00}, 423 { CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08}, 424 { CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00}, 425 { CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00}, 426 { CDC_WSA_RX1_RX_PATH_CFG0, 0x00}, 427 { CDC_WSA_RX1_RX_PATH_CFG1, 0x64}, 428 { CDC_WSA_RX1_RX_PATH_CFG2, 0x8F}, 429 { CDC_WSA_RX1_RX_PATH_CFG3, 0x00}, 430 { CDC_WSA_RX1_RX_VOL_CTL, 0x00}, 431 { CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04}, 432 { CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E}, 433 { CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00}, 434 { CDC_WSA_RX1_RX_PATH_SEC0, 0x04}, 435 { CDC_WSA_RX1_RX_PATH_SEC1, 0x08}, 436 { CDC_WSA_RX1_RX_PATH_SEC2, 0x00}, 437 { CDC_WSA_RX1_RX_PATH_SEC3, 0x00}, 438 { CDC_WSA_RX1_RX_PATH_SEC5, 0x00}, 439 { CDC_WSA_RX1_RX_PATH_SEC6, 0x00}, 440 { CDC_WSA_RX1_RX_PATH_SEC7, 0x00}, 441 { CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08}, 442 { CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00}, 443 { CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00}, 444 { CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00}, 445 { CDC_WSA_BOOST0_BOOST_CTL, 0xD0}, 446 { CDC_WSA_BOOST0_BOOST_CFG1, 0x89}, 447 { CDC_WSA_BOOST0_BOOST_CFG2, 0x04}, 448 { CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00}, 449 { CDC_WSA_BOOST1_BOOST_CTL, 0xD0}, 450 { CDC_WSA_BOOST1_BOOST_CFG1, 0x89}, 451 { CDC_WSA_BOOST1_BOOST_CFG2, 0x04}, 452 { CDC_WSA_COMPANDER0_CTL0, 0x60}, 453 { CDC_WSA_COMPANDER0_CTL1, 0xDB}, 454 { CDC_WSA_COMPANDER0_CTL2, 0xFF}, 455 { CDC_WSA_COMPANDER0_CTL3, 0x35}, 456 { CDC_WSA_COMPANDER0_CTL4, 0xFF}, 457 { CDC_WSA_COMPANDER0_CTL5, 0x00}, 458 { CDC_WSA_COMPANDER0_CTL6, 0x01}, 459 { CDC_WSA_COMPANDER0_CTL7, 0x28}, 460 { CDC_WSA_COMPANDER1_CTL0, 0x60}, 461 { CDC_WSA_COMPANDER1_CTL1, 0xDB}, 462 { CDC_WSA_COMPANDER1_CTL2, 0xFF}, 463 { CDC_WSA_COMPANDER1_CTL3, 0x35}, 464 { CDC_WSA_COMPANDER1_CTL4, 0xFF}, 465 { CDC_WSA_COMPANDER1_CTL5, 0x00}, 466 { CDC_WSA_COMPANDER1_CTL6, 0x01}, 467 { CDC_WSA_COMPANDER1_CTL7, 0x28}, 468 { CDC_WSA_SOFTCLIP0_CRC, 0x00}, 469 { CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38}, 470 { CDC_WSA_SOFTCLIP1_CRC, 0x00}, 471 { CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38}, 472 { CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00}, 473 { CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01}, 474 { CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00}, 475 { CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01}, 476 { CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00}, 477 { CDC_WSA_SPLINE_ASRC0_CTL0, 0x00}, 478 { CDC_WSA_SPLINE_ASRC0_CTL1, 0x00}, 479 { CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8}, 480 { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00}, 481 { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00}, 482 { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00}, 483 { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00}, 484 { CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00}, 485 { CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00}, 486 { CDC_WSA_SPLINE_ASRC1_CTL0, 0x00}, 487 { CDC_WSA_SPLINE_ASRC1_CTL1, 0x00}, 488 { CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8}, 489 { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00}, 490 { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00}, 491 { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00}, 492 { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00}, 493 { CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00}, 494 }; 495 496 static bool wsa_is_wronly_register(struct device *dev, 497 unsigned int reg) 498 { 499 switch (reg) { 500 case CDC_WSA_INTR_CTRL_CLR_COMMIT: 501 case CDC_WSA_INTR_CTRL_PIN1_CLEAR0: 502 case CDC_WSA_INTR_CTRL_PIN2_CLEAR0: 503 return true; 504 } 505 506 return false; 507 } 508 509 static bool wsa_is_rw_register(struct device *dev, unsigned int reg) 510 { 511 switch (reg) { 512 case CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL: 513 case CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL: 514 case CDC_WSA_CLK_RST_CTRL_SWR_CONTROL: 515 case CDC_WSA_TOP_TOP_CFG0: 516 case CDC_WSA_TOP_TOP_CFG1: 517 case CDC_WSA_TOP_FREQ_MCLK: 518 case CDC_WSA_TOP_DEBUG_BUS_SEL: 519 case CDC_WSA_TOP_DEBUG_EN0: 520 case CDC_WSA_TOP_DEBUG_EN1: 521 case CDC_WSA_TOP_DEBUG_DSM_LB: 522 case CDC_WSA_TOP_RX_I2S_CTL: 523 case CDC_WSA_TOP_TX_I2S_CTL: 524 case CDC_WSA_TOP_I2S_CLK: 525 case CDC_WSA_TOP_I2S_RESET: 526 case CDC_WSA_RX_INP_MUX_RX_INT0_CFG0: 527 case CDC_WSA_RX_INP_MUX_RX_INT0_CFG1: 528 case CDC_WSA_RX_INP_MUX_RX_INT1_CFG0: 529 case CDC_WSA_RX_INP_MUX_RX_INT1_CFG1: 530 case CDC_WSA_RX_INP_MUX_RX_MIX_CFG0: 531 case CDC_WSA_RX_INP_MUX_RX_EC_CFG0: 532 case CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0: 533 case CDC_WSA_TX0_SPKR_PROT_PATH_CTL: 534 case CDC_WSA_TX0_SPKR_PROT_PATH_CFG0: 535 case CDC_WSA_TX1_SPKR_PROT_PATH_CTL: 536 case CDC_WSA_TX1_SPKR_PROT_PATH_CFG0: 537 case CDC_WSA_TX2_SPKR_PROT_PATH_CTL: 538 case CDC_WSA_TX2_SPKR_PROT_PATH_CFG0: 539 case CDC_WSA_TX3_SPKR_PROT_PATH_CTL: 540 case CDC_WSA_TX3_SPKR_PROT_PATH_CFG0: 541 case CDC_WSA_INTR_CTRL_CFG: 542 case CDC_WSA_INTR_CTRL_PIN1_MASK0: 543 case CDC_WSA_INTR_CTRL_PIN2_MASK0: 544 case CDC_WSA_INTR_CTRL_LEVEL0: 545 case CDC_WSA_INTR_CTRL_BYPASS0: 546 case CDC_WSA_INTR_CTRL_SET0: 547 case CDC_WSA_RX0_RX_PATH_CTL: 548 case CDC_WSA_RX0_RX_PATH_CFG0: 549 case CDC_WSA_RX0_RX_PATH_CFG1: 550 case CDC_WSA_RX0_RX_PATH_CFG2: 551 case CDC_WSA_RX0_RX_PATH_CFG3: 552 case CDC_WSA_RX0_RX_VOL_CTL: 553 case CDC_WSA_RX0_RX_PATH_MIX_CTL: 554 case CDC_WSA_RX0_RX_PATH_MIX_CFG: 555 case CDC_WSA_RX0_RX_VOL_MIX_CTL: 556 case CDC_WSA_RX0_RX_PATH_SEC0: 557 case CDC_WSA_RX0_RX_PATH_SEC1: 558 case CDC_WSA_RX0_RX_PATH_SEC2: 559 case CDC_WSA_RX0_RX_PATH_SEC3: 560 case CDC_WSA_RX0_RX_PATH_SEC5: 561 case CDC_WSA_RX0_RX_PATH_SEC6: 562 case CDC_WSA_RX0_RX_PATH_SEC7: 563 case CDC_WSA_RX0_RX_PATH_MIX_SEC0: 564 case CDC_WSA_RX0_RX_PATH_MIX_SEC1: 565 case CDC_WSA_RX0_RX_PATH_DSMDEM_CTL: 566 case CDC_WSA_RX1_RX_PATH_CTL: 567 case CDC_WSA_RX1_RX_PATH_CFG0: 568 case CDC_WSA_RX1_RX_PATH_CFG1: 569 case CDC_WSA_RX1_RX_PATH_CFG2: 570 case CDC_WSA_RX1_RX_PATH_CFG3: 571 case CDC_WSA_RX1_RX_VOL_CTL: 572 case CDC_WSA_RX1_RX_PATH_MIX_CTL: 573 case CDC_WSA_RX1_RX_PATH_MIX_CFG: 574 case CDC_WSA_RX1_RX_VOL_MIX_CTL: 575 case CDC_WSA_RX1_RX_PATH_SEC0: 576 case CDC_WSA_RX1_RX_PATH_SEC1: 577 case CDC_WSA_RX1_RX_PATH_SEC2: 578 case CDC_WSA_RX1_RX_PATH_SEC3: 579 case CDC_WSA_RX1_RX_PATH_SEC5: 580 case CDC_WSA_RX1_RX_PATH_SEC6: 581 case CDC_WSA_RX1_RX_PATH_SEC7: 582 case CDC_WSA_RX1_RX_PATH_MIX_SEC0: 583 case CDC_WSA_RX1_RX_PATH_MIX_SEC1: 584 case CDC_WSA_RX1_RX_PATH_DSMDEM_CTL: 585 case CDC_WSA_BOOST0_BOOST_PATH_CTL: 586 case CDC_WSA_BOOST0_BOOST_CTL: 587 case CDC_WSA_BOOST0_BOOST_CFG1: 588 case CDC_WSA_BOOST0_BOOST_CFG2: 589 case CDC_WSA_BOOST1_BOOST_PATH_CTL: 590 case CDC_WSA_BOOST1_BOOST_CTL: 591 case CDC_WSA_BOOST1_BOOST_CFG1: 592 case CDC_WSA_BOOST1_BOOST_CFG2: 593 case CDC_WSA_COMPANDER0_CTL0: 594 case CDC_WSA_COMPANDER0_CTL1: 595 case CDC_WSA_COMPANDER0_CTL2: 596 case CDC_WSA_COMPANDER0_CTL3: 597 case CDC_WSA_COMPANDER0_CTL4: 598 case CDC_WSA_COMPANDER0_CTL5: 599 case CDC_WSA_COMPANDER0_CTL7: 600 case CDC_WSA_COMPANDER1_CTL0: 601 case CDC_WSA_COMPANDER1_CTL1: 602 case CDC_WSA_COMPANDER1_CTL2: 603 case CDC_WSA_COMPANDER1_CTL3: 604 case CDC_WSA_COMPANDER1_CTL4: 605 case CDC_WSA_COMPANDER1_CTL5: 606 case CDC_WSA_COMPANDER1_CTL7: 607 case CDC_WSA_SOFTCLIP0_CRC: 608 case CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL: 609 case CDC_WSA_SOFTCLIP1_CRC: 610 case CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL: 611 case CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL: 612 case CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0: 613 case CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL: 614 case CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0: 615 case CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL: 616 case CDC_WSA_SPLINE_ASRC0_CTL0: 617 case CDC_WSA_SPLINE_ASRC0_CTL1: 618 case CDC_WSA_SPLINE_ASRC0_FIFO_CTL: 619 case CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL: 620 case CDC_WSA_SPLINE_ASRC1_CTL0: 621 case CDC_WSA_SPLINE_ASRC1_CTL1: 622 case CDC_WSA_SPLINE_ASRC1_FIFO_CTL: 623 return true; 624 } 625 626 return false; 627 } 628 629 static bool wsa_is_writeable_register(struct device *dev, unsigned int reg) 630 { 631 bool ret; 632 633 ret = wsa_is_rw_register(dev, reg); 634 if (!ret) 635 return wsa_is_wronly_register(dev, reg); 636 637 return ret; 638 } 639 640 static bool wsa_is_readable_register(struct device *dev, unsigned int reg) 641 { 642 switch (reg) { 643 case CDC_WSA_INTR_CTRL_CLR_COMMIT: 644 case CDC_WSA_INTR_CTRL_PIN1_CLEAR0: 645 case CDC_WSA_INTR_CTRL_PIN2_CLEAR0: 646 case CDC_WSA_INTR_CTRL_PIN1_STATUS0: 647 case CDC_WSA_INTR_CTRL_PIN2_STATUS0: 648 case CDC_WSA_COMPANDER0_CTL6: 649 case CDC_WSA_COMPANDER1_CTL6: 650 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: 651 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: 652 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: 653 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB: 654 case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO: 655 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB: 656 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB: 657 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB: 658 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB: 659 case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO: 660 return true; 661 } 662 663 return wsa_is_rw_register(dev, reg); 664 } 665 666 static bool wsa_is_volatile_register(struct device *dev, unsigned int reg) 667 { 668 /* Update volatile list for rx/tx macros */ 669 switch (reg) { 670 case CDC_WSA_INTR_CTRL_PIN1_STATUS0: 671 case CDC_WSA_INTR_CTRL_PIN2_STATUS0: 672 case CDC_WSA_COMPANDER0_CTL6: 673 case CDC_WSA_COMPANDER1_CTL6: 674 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: 675 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: 676 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: 677 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB: 678 case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO: 679 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB: 680 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB: 681 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB: 682 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB: 683 case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO: 684 return true; 685 } 686 return false; 687 } 688 689 static const struct regmap_config wsa_regmap_config = { 690 .name = "wsa_macro", 691 .reg_bits = 16, 692 .val_bits = 32, /* 8 but with 32 bit read/write */ 693 .reg_stride = 4, 694 .cache_type = REGCACHE_FLAT, 695 .reg_defaults = wsa_defaults, 696 .num_reg_defaults = ARRAY_SIZE(wsa_defaults), 697 .max_register = WSA_MAX_OFFSET, 698 .writeable_reg = wsa_is_writeable_register, 699 .volatile_reg = wsa_is_volatile_register, 700 .readable_reg = wsa_is_readable_register, 701 }; 702 703 /** 704 * wsa_macro_set_spkr_mode - Configures speaker compander and smartboost 705 * settings based on speaker mode. 706 * 707 * @component: codec instance 708 * @mode: Indicates speaker configuration mode. 709 * 710 * Returns 0 on success or -EINVAL on error. 711 */ 712 int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode) 713 { 714 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 715 716 wsa->spkr_mode = mode; 717 718 switch (mode) { 719 case WSA_MACRO_SPKR_MODE_1: 720 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00); 721 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00); 722 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00); 723 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00); 724 snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44); 725 snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44); 726 break; 727 default: 728 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80); 729 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80); 730 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01); 731 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01); 732 snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58); 733 snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58); 734 break; 735 } 736 return 0; 737 } 738 EXPORT_SYMBOL(wsa_macro_set_spkr_mode); 739 740 static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, 741 u8 int_prim_fs_rate_reg_val, 742 u32 sample_rate) 743 { 744 u8 int_1_mix1_inp; 745 u32 j, port; 746 u16 int_mux_cfg0, int_mux_cfg1; 747 u16 int_fs_reg; 748 u8 int_mux_cfg0_val, int_mux_cfg1_val; 749 u8 inp0_sel, inp1_sel, inp2_sel; 750 struct snd_soc_component *component = dai->component; 751 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 752 753 for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) { 754 int_1_mix1_inp = port; 755 if ((int_1_mix1_inp < WSA_MACRO_RX0) || (int_1_mix1_inp > WSA_MACRO_RX_MIX1)) { 756 dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n", 757 __func__, dai->id); 758 return -EINVAL; 759 } 760 761 int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0; 762 763 /* 764 * Loop through all interpolator MUX inputs and find out 765 * to which interpolator input, the cdc_dma rx port 766 * is connected 767 */ 768 for (j = 0; j < NUM_INTERPOLATORS; j++) { 769 int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET; 770 int_mux_cfg0_val = snd_soc_component_read(component, 771 int_mux_cfg0); 772 int_mux_cfg1_val = snd_soc_component_read(component, 773 int_mux_cfg1); 774 inp0_sel = int_mux_cfg0_val & WSA_MACRO_MUX_INP_MASK1; 775 inp1_sel = (int_mux_cfg0_val >> WSA_MACRO_MUX_INP_SHFT) & 776 WSA_MACRO_MUX_INP_MASK1; 777 inp2_sel = (int_mux_cfg1_val >> WSA_MACRO_MUX_INP_SHFT) & 778 WSA_MACRO_MUX_INP_MASK1; 779 if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 780 (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 781 (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) { 782 int_fs_reg = CDC_WSA_RX0_RX_PATH_CTL + 783 WSA_MACRO_RX_PATH_OFFSET * j; 784 /* sample_rate is in Hz */ 785 snd_soc_component_update_bits(component, int_fs_reg, 786 WSA_MACRO_FS_RATE_MASK, 787 int_prim_fs_rate_reg_val); 788 } 789 int_mux_cfg0 += WSA_MACRO_MUX_CFG_OFFSET; 790 } 791 } 792 793 return 0; 794 } 795 796 static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, 797 u8 int_mix_fs_rate_reg_val, 798 u32 sample_rate) 799 { 800 u8 int_2_inp; 801 u32 j, port; 802 u16 int_mux_cfg1, int_fs_reg; 803 u8 int_mux_cfg1_val; 804 struct snd_soc_component *component = dai->component; 805 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 806 807 for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) { 808 int_2_inp = port; 809 if ((int_2_inp < WSA_MACRO_RX0) || (int_2_inp > WSA_MACRO_RX_MIX1)) { 810 dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n", 811 __func__, dai->id); 812 return -EINVAL; 813 } 814 815 int_mux_cfg1 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG1; 816 for (j = 0; j < NUM_INTERPOLATORS; j++) { 817 int_mux_cfg1_val = snd_soc_component_read(component, 818 int_mux_cfg1) & 819 WSA_MACRO_MUX_INP_MASK1; 820 if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) { 821 int_fs_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL + 822 WSA_MACRO_RX_PATH_OFFSET * j; 823 824 snd_soc_component_update_bits(component, 825 int_fs_reg, 826 WSA_MACRO_FS_RATE_MASK, 827 int_mix_fs_rate_reg_val); 828 } 829 int_mux_cfg1 += WSA_MACRO_MUX_CFG_OFFSET; 830 } 831 } 832 return 0; 833 } 834 835 static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai, 836 u32 sample_rate) 837 { 838 int rate_val = 0; 839 int i, ret; 840 841 /* set mixing path rate */ 842 for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) { 843 if (sample_rate == int_mix_sample_rate_val[i].sample_rate) { 844 rate_val = int_mix_sample_rate_val[i].rate_val; 845 break; 846 } 847 } 848 if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) || (rate_val < 0)) 849 goto prim_rate; 850 851 ret = wsa_macro_set_mix_interpolator_rate(dai, (u8) rate_val, sample_rate); 852 prim_rate: 853 /* set primary path sample rate */ 854 for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) { 855 if (sample_rate == int_prim_sample_rate_val[i].sample_rate) { 856 rate_val = int_prim_sample_rate_val[i].rate_val; 857 break; 858 } 859 } 860 if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) || (rate_val < 0)) 861 return -EINVAL; 862 863 ret = wsa_macro_set_prim_interpolator_rate(dai, (u8) rate_val, sample_rate); 864 865 return ret; 866 } 867 868 static int wsa_macro_hw_params(struct snd_pcm_substream *substream, 869 struct snd_pcm_hw_params *params, 870 struct snd_soc_dai *dai) 871 { 872 struct snd_soc_component *component = dai->component; 873 int ret; 874 875 switch (substream->stream) { 876 case SNDRV_PCM_STREAM_PLAYBACK: 877 ret = wsa_macro_set_interpolator_rate(dai, params_rate(params)); 878 if (ret) { 879 dev_err(component->dev, 880 "%s: cannot set sample rate: %u\n", 881 __func__, params_rate(params)); 882 return ret; 883 } 884 break; 885 default: 886 break; 887 } 888 return 0; 889 } 890 891 static int wsa_macro_get_channel_map(struct snd_soc_dai *dai, 892 unsigned int *tx_num, unsigned int *tx_slot, 893 unsigned int *rx_num, unsigned int *rx_slot) 894 { 895 struct snd_soc_component *component = dai->component; 896 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 897 u16 val, mask = 0, cnt = 0, temp; 898 899 switch (dai->id) { 900 case WSA_MACRO_AIF_VI: 901 *tx_slot = wsa->active_ch_mask[dai->id]; 902 *tx_num = wsa->active_ch_cnt[dai->id]; 903 break; 904 case WSA_MACRO_AIF1_PB: 905 case WSA_MACRO_AIF_MIX1_PB: 906 for_each_set_bit(temp, &wsa->active_ch_mask[dai->id], 907 WSA_MACRO_RX_MAX) { 908 mask |= (1 << temp); 909 if (++cnt == WSA_MACRO_MAX_DMA_CH_PER_PORT) 910 break; 911 } 912 if (mask & 0x0C) 913 mask = mask >> 0x2; 914 *rx_slot = mask; 915 *rx_num = cnt; 916 break; 917 case WSA_MACRO_AIF_ECHO: 918 val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0); 919 if (val & WSA_MACRO_EC_MIX_TX1_MASK) { 920 mask |= 0x2; 921 cnt++; 922 } 923 if (val & WSA_MACRO_EC_MIX_TX0_MASK) { 924 mask |= 0x1; 925 cnt++; 926 } 927 *tx_slot = mask; 928 *tx_num = cnt; 929 break; 930 default: 931 dev_err(component->dev, "%s: Invalid AIF\n", __func__); 932 break; 933 } 934 return 0; 935 } 936 937 static struct snd_soc_dai_ops wsa_macro_dai_ops = { 938 .hw_params = wsa_macro_hw_params, 939 .get_channel_map = wsa_macro_get_channel_map, 940 }; 941 942 static struct snd_soc_dai_driver wsa_macro_dai[] = { 943 { 944 .name = "wsa_macro_rx1", 945 .id = WSA_MACRO_AIF1_PB, 946 .playback = { 947 .stream_name = "WSA_AIF1 Playback", 948 .rates = WSA_MACRO_RX_RATES, 949 .formats = WSA_MACRO_RX_FORMATS, 950 .rate_max = 384000, 951 .rate_min = 8000, 952 .channels_min = 1, 953 .channels_max = 2, 954 }, 955 .ops = &wsa_macro_dai_ops, 956 }, 957 { 958 .name = "wsa_macro_rx_mix", 959 .id = WSA_MACRO_AIF_MIX1_PB, 960 .playback = { 961 .stream_name = "WSA_AIF_MIX1 Playback", 962 .rates = WSA_MACRO_RX_MIX_RATES, 963 .formats = WSA_MACRO_RX_FORMATS, 964 .rate_max = 192000, 965 .rate_min = 48000, 966 .channels_min = 1, 967 .channels_max = 2, 968 }, 969 .ops = &wsa_macro_dai_ops, 970 }, 971 { 972 .name = "wsa_macro_vifeedback", 973 .id = WSA_MACRO_AIF_VI, 974 .capture = { 975 .stream_name = "WSA_AIF_VI Capture", 976 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000, 977 .formats = WSA_MACRO_RX_FORMATS, 978 .rate_max = 48000, 979 .rate_min = 8000, 980 .channels_min = 1, 981 .channels_max = 4, 982 }, 983 .ops = &wsa_macro_dai_ops, 984 }, 985 { 986 .name = "wsa_macro_echo", 987 .id = WSA_MACRO_AIF_ECHO, 988 .capture = { 989 .stream_name = "WSA_AIF_ECHO Capture", 990 .rates = WSA_MACRO_ECHO_RATES, 991 .formats = WSA_MACRO_ECHO_FORMATS, 992 .rate_max = 48000, 993 .rate_min = 8000, 994 .channels_min = 1, 995 .channels_max = 2, 996 }, 997 .ops = &wsa_macro_dai_ops, 998 }, 999 }; 1000 1001 static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable) 1002 { 1003 struct regmap *regmap = wsa->regmap; 1004 1005 if (mclk_enable) { 1006 if (wsa->wsa_mclk_users == 0) { 1007 regcache_mark_dirty(regmap); 1008 regcache_sync(regmap); 1009 /* 9.6MHz MCLK, set value 0x00 if other frequency */ 1010 regmap_update_bits(regmap, CDC_WSA_TOP_FREQ_MCLK, 0x01, 0x01); 1011 regmap_update_bits(regmap, 1012 CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 1013 CDC_WSA_MCLK_EN_MASK, 1014 CDC_WSA_MCLK_ENABLE); 1015 regmap_update_bits(regmap, 1016 CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 1017 CDC_WSA_FS_CNT_EN_MASK, 1018 CDC_WSA_FS_CNT_ENABLE); 1019 } 1020 wsa->wsa_mclk_users++; 1021 } else { 1022 if (wsa->wsa_mclk_users <= 0) { 1023 dev_err(wsa->dev, "clock already disabled\n"); 1024 wsa->wsa_mclk_users = 0; 1025 return; 1026 } 1027 wsa->wsa_mclk_users--; 1028 if (wsa->wsa_mclk_users == 0) { 1029 regmap_update_bits(regmap, 1030 CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 1031 CDC_WSA_FS_CNT_EN_MASK, 1032 CDC_WSA_FS_CNT_DISABLE); 1033 regmap_update_bits(regmap, 1034 CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 1035 CDC_WSA_MCLK_EN_MASK, 1036 CDC_WSA_MCLK_DISABLE); 1037 } 1038 } 1039 } 1040 1041 static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol, 1042 struct snd_ctl_elem_value *ucontrol) 1043 { 1044 1045 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1046 int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1047 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1048 1049 ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx]; 1050 1051 return 0; 1052 } 1053 1054 static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol, 1055 struct snd_ctl_elem_value *ucontrol) 1056 { 1057 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1058 int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1059 int value = ucontrol->value.integer.value[0]; 1060 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1061 1062 wsa->ec_hq[ec_tx] = value; 1063 1064 return 0; 1065 } 1066 1067 static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol, 1068 struct snd_ctl_elem_value *ucontrol) 1069 { 1070 1071 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1072 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1073 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1074 1075 ucontrol->value.integer.value[0] = wsa->comp_enabled[comp]; 1076 return 0; 1077 } 1078 1079 static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol, 1080 struct snd_ctl_elem_value *ucontrol) 1081 { 1082 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1083 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1084 int value = ucontrol->value.integer.value[0]; 1085 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1086 1087 wsa->comp_enabled[comp] = value; 1088 1089 return 0; 1090 } 1091 1092 static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol, 1093 struct snd_ctl_elem_value *ucontrol) 1094 { 1095 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1096 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1097 1098 ucontrol->value.integer.value[0] = wsa->ear_spkr_gain; 1099 1100 return 0; 1101 } 1102 1103 static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol, 1104 struct snd_ctl_elem_value *ucontrol) 1105 { 1106 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1107 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1108 1109 wsa->ear_spkr_gain = ucontrol->value.integer.value[0]; 1110 1111 return 0; 1112 } 1113 1114 static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, 1115 struct snd_ctl_elem_value *ucontrol) 1116 { 1117 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1118 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1119 int path = ((struct soc_mixer_control *)kcontrol->private_value)->shift; 1120 1121 ucontrol->value.integer.value[0] = wsa->is_softclip_on[path]; 1122 1123 return 0; 1124 } 1125 1126 static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, 1127 struct snd_ctl_elem_value *ucontrol) 1128 { 1129 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1130 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1131 int path = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1132 1133 wsa->is_softclip_on[path] = ucontrol->value.integer.value[0]; 1134 1135 return 0; 1136 } 1137 1138 static const struct snd_kcontrol_new wsa_macro_snd_controls[] = { 1139 SOC_ENUM_EXT("EAR SPKR PA Gain", wsa_macro_ear_spkr_pa_gain_enum, 1140 wsa_macro_ear_spkr_pa_gain_get, 1141 wsa_macro_ear_spkr_pa_gain_put), 1142 SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM, 1143 WSA_MACRO_SOFTCLIP0, 1, 0, 1144 wsa_macro_soft_clip_enable_get, 1145 wsa_macro_soft_clip_enable_put), 1146 SOC_SINGLE_EXT("WSA_Softclip1 Enable", SND_SOC_NOPM, 1147 WSA_MACRO_SOFTCLIP1, 1, 0, 1148 wsa_macro_soft_clip_enable_get, 1149 wsa_macro_soft_clip_enable_put), 1150 1151 SOC_SINGLE_S8_TLV("WSA_RX0 Digital Volume", CDC_WSA_RX0_RX_VOL_CTL, 1152 -84, 40, digital_gain), 1153 SOC_SINGLE_S8_TLV("WSA_RX1 Digital Volume", CDC_WSA_RX1_RX_VOL_CTL, 1154 -84, 40, digital_gain), 1155 1156 SOC_SINGLE("WSA_RX0 Digital Mute", CDC_WSA_RX0_RX_PATH_CTL, 4, 1, 0), 1157 SOC_SINGLE("WSA_RX1 Digital Mute", CDC_WSA_RX1_RX_PATH_CTL, 4, 1, 0), 1158 SOC_SINGLE("WSA_RX0_MIX Digital Mute", CDC_WSA_RX0_RX_PATH_MIX_CTL, 4, 1159 1, 0), 1160 SOC_SINGLE("WSA_RX1_MIX Digital Mute", CDC_WSA_RX1_RX_PATH_MIX_CTL, 4, 1161 1, 0), 1162 SOC_SINGLE_EXT("WSA_COMP1 Switch", SND_SOC_NOPM, WSA_MACRO_COMP1, 1, 0, 1163 wsa_macro_get_compander, wsa_macro_set_compander), 1164 SOC_SINGLE_EXT("WSA_COMP2 Switch", SND_SOC_NOPM, WSA_MACRO_COMP2, 1, 0, 1165 wsa_macro_get_compander, wsa_macro_set_compander), 1166 SOC_SINGLE_EXT("WSA_RX0 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX0, 1, 0, 1167 wsa_macro_get_ec_hq, wsa_macro_set_ec_hq), 1168 SOC_SINGLE_EXT("WSA_RX1 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX1, 1, 0, 1169 wsa_macro_get_ec_hq, wsa_macro_set_ec_hq), 1170 }; 1171 1172 static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable) 1173 { 1174 struct regmap *regmap = wsa->regmap; 1175 1176 if (enable) { 1177 wsa_macro_mclk_enable(wsa, true); 1178 1179 /* reset swr ip */ 1180 if (wsa->reset_swr) 1181 regmap_update_bits(regmap, 1182 CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 1183 CDC_WSA_SWR_RST_EN_MASK, 1184 CDC_WSA_SWR_RST_ENABLE); 1185 1186 regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 1187 CDC_WSA_SWR_CLK_EN_MASK, 1188 CDC_WSA_SWR_CLK_ENABLE); 1189 1190 /* Bring out of reset */ 1191 if (wsa->reset_swr) 1192 regmap_update_bits(regmap, 1193 CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 1194 CDC_WSA_SWR_RST_EN_MASK, 1195 CDC_WSA_SWR_RST_DISABLE); 1196 wsa->reset_swr = false; 1197 } else { 1198 regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 1199 CDC_WSA_SWR_CLK_EN_MASK, 0); 1200 wsa_macro_mclk_enable(wsa, false); 1201 } 1202 1203 return 0; 1204 } 1205 1206 static int wsa_macro_component_probe(struct snd_soc_component *comp) 1207 { 1208 struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp); 1209 1210 snd_soc_component_init_regmap(comp, wsa->regmap); 1211 1212 wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB; 1213 1214 /* set SPKR rate to FS_2P4_3P072 */ 1215 snd_soc_component_update_bits(comp, CDC_WSA_RX0_RX_PATH_CFG1, 1216 CDC_WSA_RX_PATH_SPKR_RATE_MASK, 1217 CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072); 1218 1219 snd_soc_component_update_bits(comp, CDC_WSA_RX1_RX_PATH_CFG1, 1220 CDC_WSA_RX_PATH_SPKR_RATE_MASK, 1221 CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072); 1222 1223 wsa_macro_set_spkr_mode(comp, WSA_MACRO_SPKR_MODE_1); 1224 1225 return 0; 1226 } 1227 1228 static int swclk_gate_enable(struct clk_hw *hw) 1229 { 1230 return wsa_swrm_clock(to_wsa_macro(hw), true); 1231 } 1232 1233 static void swclk_gate_disable(struct clk_hw *hw) 1234 { 1235 wsa_swrm_clock(to_wsa_macro(hw), false); 1236 } 1237 1238 static int swclk_gate_is_enabled(struct clk_hw *hw) 1239 { 1240 struct wsa_macro *wsa = to_wsa_macro(hw); 1241 int ret, val; 1242 1243 regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val); 1244 ret = val & BIT(0); 1245 1246 return ret; 1247 } 1248 1249 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 1250 unsigned long parent_rate) 1251 { 1252 return parent_rate / 2; 1253 } 1254 1255 static const struct clk_ops swclk_gate_ops = { 1256 .prepare = swclk_gate_enable, 1257 .unprepare = swclk_gate_disable, 1258 .is_enabled = swclk_gate_is_enabled, 1259 .recalc_rate = swclk_recalc_rate, 1260 }; 1261 1262 static struct clk *wsa_macro_register_mclk_output(struct wsa_macro *wsa) 1263 { 1264 struct device *dev = wsa->dev; 1265 struct device_node *np = dev->of_node; 1266 const char *parent_clk_name; 1267 const char *clk_name = "mclk"; 1268 struct clk_hw *hw; 1269 struct clk_init_data init; 1270 int ret; 1271 1272 parent_clk_name = __clk_get_name(wsa->clks[2].clk); 1273 1274 init.name = clk_name; 1275 init.ops = &swclk_gate_ops; 1276 init.flags = 0; 1277 init.parent_names = &parent_clk_name; 1278 init.num_parents = 1; 1279 wsa->hw.init = &init; 1280 hw = &wsa->hw; 1281 ret = clk_hw_register(wsa->dev, hw); 1282 if (ret) 1283 return ERR_PTR(ret); 1284 1285 of_clk_add_provider(np, of_clk_src_simple_get, hw->clk); 1286 1287 return NULL; 1288 } 1289 1290 static const struct snd_soc_component_driver wsa_macro_component_drv = { 1291 .name = "WSA MACRO", 1292 .probe = wsa_macro_component_probe, 1293 .controls = wsa_macro_snd_controls, 1294 .num_controls = ARRAY_SIZE(wsa_macro_snd_controls), 1295 }; 1296 1297 static int wsa_macro_probe(struct platform_device *pdev) 1298 { 1299 struct device *dev = &pdev->dev; 1300 struct wsa_macro *wsa; 1301 void __iomem *base; 1302 int ret; 1303 1304 wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL); 1305 if (!wsa) 1306 return -ENOMEM; 1307 1308 wsa->clks[0].id = "macro"; 1309 wsa->clks[1].id = "dcodec"; 1310 wsa->clks[2].id = "mclk"; 1311 wsa->clks[3].id = "npl"; 1312 wsa->clks[4].id = "fsgen"; 1313 1314 ret = devm_clk_bulk_get(dev, WSA_NUM_CLKS_MAX, wsa->clks); 1315 if (ret) { 1316 dev_err(dev, "Error getting WSA Clocks (%d)\n", ret); 1317 return ret; 1318 } 1319 1320 base = devm_platform_ioremap_resource(pdev, 0); 1321 if (IS_ERR(base)) 1322 return PTR_ERR(base); 1323 1324 wsa->regmap = devm_regmap_init_mmio(dev, base, &wsa_regmap_config); 1325 1326 dev_set_drvdata(dev, wsa); 1327 1328 wsa->reset_swr = true; 1329 wsa->dev = dev; 1330 1331 /* set MCLK and NPL rates */ 1332 clk_set_rate(wsa->clks[2].clk, WSA_MACRO_MCLK_FREQ); 1333 clk_set_rate(wsa->clks[3].clk, WSA_MACRO_MCLK_FREQ); 1334 1335 ret = clk_bulk_prepare_enable(WSA_NUM_CLKS_MAX, wsa->clks); 1336 if (ret) 1337 return ret; 1338 1339 wsa_macro_register_mclk_output(wsa); 1340 1341 ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv, 1342 wsa_macro_dai, 1343 ARRAY_SIZE(wsa_macro_dai)); 1344 if (ret) 1345 goto err; 1346 1347 return ret; 1348 err: 1349 clk_bulk_disable_unprepare(WSA_NUM_CLKS_MAX, wsa->clks); 1350 1351 return ret; 1352 1353 } 1354 1355 static int wsa_macro_remove(struct platform_device *pdev) 1356 { 1357 struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev); 1358 1359 of_clk_del_provider(pdev->dev.of_node); 1360 1361 clk_bulk_disable_unprepare(WSA_NUM_CLKS_MAX, wsa->clks); 1362 1363 return 0; 1364 } 1365 1366 static const struct of_device_id wsa_macro_dt_match[] = { 1367 {.compatible = "qcom,sm8250-lpass-wsa-macro"}, 1368 {} 1369 }; 1370 MODULE_DEVICE_TABLE(of, wsa_macro_dt_match); 1371 1372 static struct platform_driver wsa_macro_driver = { 1373 .driver = { 1374 .name = "wsa_macro", 1375 .of_match_table = wsa_macro_dt_match, 1376 }, 1377 .probe = wsa_macro_probe, 1378 .remove = wsa_macro_remove, 1379 }; 1380 1381 module_platform_driver(wsa_macro_driver); 1382 MODULE_DESCRIPTION("WSA macro driver"); 1383 MODULE_LICENSE("GPL"); 1384