1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3 
4 #include <linux/module.h>
5 #include <linux/init.h>
6 #include <linux/io.h>
7 #include <linux/platform_device.h>
8 #include <linux/clk.h>
9 #include <linux/of_clk.h>
10 #include <linux/clk-provider.h>
11 #include <sound/soc.h>
12 #include <sound/soc-dapm.h>
13 #include <linux/of_platform.h>
14 #include <sound/tlv.h>
15 #include "lpass-wsa-macro.h"
16 
17 #define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL	(0x0000)
18 #define CDC_WSA_MCLK_EN_MASK			BIT(0)
19 #define CDC_WSA_MCLK_ENABLE			BIT(0)
20 #define CDC_WSA_MCLK_DISABLE			0
21 #define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL	(0x0004)
22 #define CDC_WSA_FS_CNT_EN_MASK			BIT(0)
23 #define CDC_WSA_FS_CNT_ENABLE			BIT(0)
24 #define CDC_WSA_FS_CNT_DISABLE			0
25 #define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL	(0x0008)
26 #define CDC_WSA_SWR_CLK_EN_MASK			BIT(0)
27 #define CDC_WSA_SWR_CLK_ENABLE			BIT(0)
28 #define CDC_WSA_SWR_RST_EN_MASK			BIT(1)
29 #define CDC_WSA_SWR_RST_ENABLE			BIT(1)
30 #define CDC_WSA_SWR_RST_DISABLE			0
31 #define CDC_WSA_TOP_TOP_CFG0			(0x0080)
32 #define CDC_WSA_TOP_TOP_CFG1			(0x0084)
33 #define CDC_WSA_TOP_FREQ_MCLK			(0x0088)
34 #define CDC_WSA_TOP_DEBUG_BUS_SEL		(0x008C)
35 #define CDC_WSA_TOP_DEBUG_EN0			(0x0090)
36 #define CDC_WSA_TOP_DEBUG_EN1			(0x0094)
37 #define CDC_WSA_TOP_DEBUG_DSM_LB		(0x0098)
38 #define CDC_WSA_TOP_RX_I2S_CTL			(0x009C)
39 #define CDC_WSA_TOP_TX_I2S_CTL			(0x00A0)
40 #define CDC_WSA_TOP_I2S_CLK			(0x00A4)
41 #define CDC_WSA_TOP_I2S_RESET			(0x00A8)
42 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0		(0x0100)
43 #define CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK	GENMASK(2, 0)
44 #define CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK	GENMASK(5, 3)
45 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1		(0x0104)
46 #define CDC_WSA_RX_INTX_2_SEL_MASK		GENMASK(2, 0)
47 #define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK	GENMASK(5, 3)
48 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0		(0x0108)
49 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1		(0x010C)
50 #define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0		(0x0110)
51 #define CDC_WSA_RX_MIX_TX1_SEL_MASK		GENMASK(5, 3)
52 #define CDC_WSA_RX_MIX_TX1_SEL_SHFT		3
53 #define CDC_WSA_RX_MIX_TX0_SEL_MASK		GENMASK(2, 0)
54 #define CDC_WSA_RX_INP_MUX_RX_EC_CFG0		(0x0114)
55 #define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0	(0x0118)
56 #define CDC_WSA_TX0_SPKR_PROT_PATH_CTL		(0x0244)
57 #define CDC_WSA_TX_SPKR_PROT_RESET_MASK		BIT(5)
58 #define CDC_WSA_TX_SPKR_PROT_RESET		BIT(5)
59 #define CDC_WSA_TX_SPKR_PROT_NO_RESET		0
60 #define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK	BIT(4)
61 #define CDC_WSA_TX_SPKR_PROT_CLK_ENABLE		BIT(4)
62 #define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE	0
63 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK	GENMASK(3, 0)
64 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K	0
65 #define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0		(0x0248)
66 #define CDC_WSA_TX1_SPKR_PROT_PATH_CTL		(0x0264)
67 #define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0		(0x0268)
68 #define CDC_WSA_TX2_SPKR_PROT_PATH_CTL		(0x0284)
69 #define CDC_WSA_TX2_SPKR_PROT_PATH_CFG0		(0x0288)
70 #define CDC_WSA_TX3_SPKR_PROT_PATH_CTL		(0x02A4)
71 #define CDC_WSA_TX3_SPKR_PROT_PATH_CFG0		(0x02A8)
72 #define CDC_WSA_INTR_CTRL_CFG			(0x0340)
73 #define CDC_WSA_INTR_CTRL_CLR_COMMIT		(0x0344)
74 #define CDC_WSA_INTR_CTRL_PIN1_MASK0		(0x0360)
75 #define CDC_WSA_INTR_CTRL_PIN1_STATUS0		(0x0368)
76 #define CDC_WSA_INTR_CTRL_PIN1_CLEAR0		(0x0370)
77 #define CDC_WSA_INTR_CTRL_PIN2_MASK0		(0x0380)
78 #define CDC_WSA_INTR_CTRL_PIN2_STATUS0		(0x0388)
79 #define CDC_WSA_INTR_CTRL_PIN2_CLEAR0		(0x0390)
80 #define CDC_WSA_INTR_CTRL_LEVEL0		(0x03C0)
81 #define CDC_WSA_INTR_CTRL_BYPASS0		(0x03C8)
82 #define CDC_WSA_INTR_CTRL_SET0			(0x03D0)
83 #define CDC_WSA_RX0_RX_PATH_CTL			(0x0400)
84 #define CDC_WSA_RX_PATH_CLK_EN_MASK		BIT(5)
85 #define CDC_WSA_RX_PATH_CLK_ENABLE		BIT(5)
86 #define CDC_WSA_RX_PATH_CLK_DISABLE		0
87 #define CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK	BIT(4)
88 #define CDC_WSA_RX_PATH_PGA_MUTE_ENABLE		BIT(4)
89 #define CDC_WSA_RX_PATH_PGA_MUTE_DISABLE	0
90 #define CDC_WSA_RX0_RX_PATH_CFG0		(0x0404)
91 #define CDC_WSA_RX_PATH_COMP_EN_MASK		BIT(1)
92 #define CDC_WSA_RX_PATH_COMP_ENABLE		BIT(1)
93 #define CDC_WSA_RX_PATH_HD2_EN_MASK		BIT(2)
94 #define CDC_WSA_RX_PATH_HD2_ENABLE		BIT(2)
95 #define CDC_WSA_RX_PATH_SPKR_RATE_MASK		BIT(3)
96 #define CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072	BIT(3)
97 #define CDC_WSA_RX0_RX_PATH_CFG1		(0x0408)
98 #define CDC_WSA_RX_PATH_SMART_BST_EN_MASK	BIT(0)
99 #define CDC_WSA_RX_PATH_SMART_BST_ENABLE	BIT(0)
100 #define CDC_WSA_RX_PATH_SMART_BST_DISABLE	0
101 #define CDC_WSA_RX0_RX_PATH_CFG2		(0x040C)
102 #define CDC_WSA_RX0_RX_PATH_CFG3		(0x0410)
103 #define CDC_WSA_RX_DC_DCOEFF_MASK		GENMASK(1, 0)
104 #define CDC_WSA_RX0_RX_VOL_CTL			(0x0414)
105 #define CDC_WSA_RX0_RX_PATH_MIX_CTL		(0x0418)
106 #define CDC_WSA_RX_PATH_MIX_CLK_EN_MASK		BIT(5)
107 #define CDC_WSA_RX_PATH_MIX_CLK_ENABLE		BIT(5)
108 #define CDC_WSA_RX_PATH_MIX_CLK_DISABLE		0
109 #define CDC_WSA_RX0_RX_PATH_MIX_CFG		(0x041C)
110 #define CDC_WSA_RX0_RX_VOL_MIX_CTL		(0x0420)
111 #define CDC_WSA_RX0_RX_PATH_SEC0		(0x0424)
112 #define CDC_WSA_RX0_RX_PATH_SEC1		(0x0428)
113 #define CDC_WSA_RX_PGA_HALF_DB_MASK		BIT(0)
114 #define CDC_WSA_RX_PGA_HALF_DB_ENABLE		BIT(0)
115 #define CDC_WSA_RX_PGA_HALF_DB_DISABLE		0
116 #define CDC_WSA_RX0_RX_PATH_SEC2		(0x042C)
117 #define CDC_WSA_RX0_RX_PATH_SEC3		(0x0430)
118 #define CDC_WSA_RX_PATH_HD2_SCALE_MASK		GENMASK(1, 0)
119 #define CDC_WSA_RX_PATH_HD2_ALPHA_MASK		GENMASK(5, 2)
120 #define CDC_WSA_RX0_RX_PATH_SEC5		(0x0438)
121 #define CDC_WSA_RX0_RX_PATH_SEC6		(0x043C)
122 #define CDC_WSA_RX0_RX_PATH_SEC7		(0x0440)
123 #define CDC_WSA_RX0_RX_PATH_MIX_SEC0		(0x0444)
124 #define CDC_WSA_RX0_RX_PATH_MIX_SEC1		(0x0448)
125 #define CDC_WSA_RX0_RX_PATH_DSMDEM_CTL		(0x044C)
126 #define CDC_WSA_RX_DSMDEM_CLK_EN_MASK		BIT(0)
127 #define CDC_WSA_RX_DSMDEM_CLK_ENABLE		BIT(0)
128 #define CDC_WSA_RX1_RX_PATH_CTL			(0x0480)
129 #define CDC_WSA_RX1_RX_PATH_CFG0		(0x0484)
130 #define CDC_WSA_RX1_RX_PATH_CFG1		(0x0488)
131 #define CDC_WSA_RX1_RX_PATH_CFG2		(0x048C)
132 #define CDC_WSA_RX1_RX_PATH_CFG3		(0x0490)
133 #define CDC_WSA_RX1_RX_VOL_CTL			(0x0494)
134 #define CDC_WSA_RX1_RX_PATH_MIX_CTL		(0x0498)
135 #define CDC_WSA_RX1_RX_PATH_MIX_CFG		(0x049C)
136 #define CDC_WSA_RX1_RX_VOL_MIX_CTL		(0x04A0)
137 #define CDC_WSA_RX1_RX_PATH_SEC0		(0x04A4)
138 #define CDC_WSA_RX1_RX_PATH_SEC1		(0x04A8)
139 #define CDC_WSA_RX1_RX_PATH_SEC2		(0x04AC)
140 #define CDC_WSA_RX1_RX_PATH_SEC3		(0x04B0)
141 #define CDC_WSA_RX1_RX_PATH_SEC5		(0x04B8)
142 #define CDC_WSA_RX1_RX_PATH_SEC6		(0x04BC)
143 #define CDC_WSA_RX1_RX_PATH_SEC7		(0x04C0)
144 #define CDC_WSA_RX1_RX_PATH_MIX_SEC0		(0x04C4)
145 #define CDC_WSA_RX1_RX_PATH_MIX_SEC1		(0x04C8)
146 #define CDC_WSA_RX1_RX_PATH_DSMDEM_CTL		(0x04CC)
147 #define CDC_WSA_BOOST0_BOOST_PATH_CTL		(0x0500)
148 #define CDC_WSA_BOOST_PATH_CLK_EN_MASK		BIT(4)
149 #define CDC_WSA_BOOST_PATH_CLK_ENABLE		BIT(4)
150 #define CDC_WSA_BOOST_PATH_CLK_DISABLE		0
151 #define CDC_WSA_BOOST0_BOOST_CTL		(0x0504)
152 #define CDC_WSA_BOOST0_BOOST_CFG1		(0x0508)
153 #define CDC_WSA_BOOST0_BOOST_CFG2		(0x050C)
154 #define CDC_WSA_BOOST1_BOOST_PATH_CTL		(0x0540)
155 #define CDC_WSA_BOOST1_BOOST_CTL		(0x0544)
156 #define CDC_WSA_BOOST1_BOOST_CFG1		(0x0548)
157 #define CDC_WSA_BOOST1_BOOST_CFG2		(0x054C)
158 #define CDC_WSA_COMPANDER0_CTL0			(0x0580)
159 #define CDC_WSA_COMPANDER_CLK_EN_MASK		BIT(0)
160 #define CDC_WSA_COMPANDER_CLK_ENABLE		BIT(0)
161 #define CDC_WSA_COMPANDER_SOFT_RST_MASK		BIT(1)
162 #define CDC_WSA_COMPANDER_SOFT_RST_ENABLE	BIT(1)
163 #define CDC_WSA_COMPANDER_HALT_MASK		BIT(2)
164 #define CDC_WSA_COMPANDER_HALT			BIT(2)
165 #define CDC_WSA_COMPANDER0_CTL1			(0x0584)
166 #define CDC_WSA_COMPANDER0_CTL2			(0x0588)
167 #define CDC_WSA_COMPANDER0_CTL3			(0x058C)
168 #define CDC_WSA_COMPANDER0_CTL4			(0x0590)
169 #define CDC_WSA_COMPANDER0_CTL5			(0x0594)
170 #define CDC_WSA_COMPANDER0_CTL6			(0x0598)
171 #define CDC_WSA_COMPANDER0_CTL7			(0x059C)
172 #define CDC_WSA_COMPANDER1_CTL0			(0x05C0)
173 #define CDC_WSA_COMPANDER1_CTL1			(0x05C4)
174 #define CDC_WSA_COMPANDER1_CTL2			(0x05C8)
175 #define CDC_WSA_COMPANDER1_CTL3			(0x05CC)
176 #define CDC_WSA_COMPANDER1_CTL4			(0x05D0)
177 #define CDC_WSA_COMPANDER1_CTL5			(0x05D4)
178 #define CDC_WSA_COMPANDER1_CTL6			(0x05D8)
179 #define CDC_WSA_COMPANDER1_CTL7			(0x05DC)
180 #define CDC_WSA_SOFTCLIP0_CRC			(0x0600)
181 #define CDC_WSA_SOFTCLIP_CLK_EN_MASK		BIT(0)
182 #define CDC_WSA_SOFTCLIP_CLK_ENABLE		BIT(0)
183 #define CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL		(0x0604)
184 #define CDC_WSA_SOFTCLIP_EN_MASK		BIT(0)
185 #define CDC_WSA_SOFTCLIP_ENABLE			BIT(0)
186 #define CDC_WSA_SOFTCLIP1_CRC			(0x0640)
187 #define CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL		(0x0644)
188 #define CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL	(0x0680)
189 #define CDC_WSA_EC_HQ_EC_CLK_EN_MASK		BIT(0)
190 #define CDC_WSA_EC_HQ_EC_CLK_ENABLE		BIT(0)
191 #define CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0		(0x0684)
192 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK	GENMASK(4, 1)
193 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K	BIT(3)
194 #define CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL	(0x06C0)
195 #define CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0		(0x06C4)
196 #define CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL	(0x0700)
197 #define CDC_WSA_SPLINE_ASRC0_CTL0		(0x0704)
198 #define CDC_WSA_SPLINE_ASRC0_CTL1		(0x0708)
199 #define CDC_WSA_SPLINE_ASRC0_FIFO_CTL		(0x070C)
200 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB	(0x0710)
201 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB	(0x0714)
202 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB	(0x0718)
203 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB	(0x071C)
204 #define CDC_WSA_SPLINE_ASRC0_STATUS_FIFO		(0x0720)
205 #define CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL		(0x0740)
206 #define CDC_WSA_SPLINE_ASRC1_CTL0		(0x0744)
207 #define CDC_WSA_SPLINE_ASRC1_CTL1		(0x0748)
208 #define CDC_WSA_SPLINE_ASRC1_FIFO_CTL		(0x074C)
209 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB (0x0750)
210 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB (0x0754)
211 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB (0x0758)
212 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB (0x075C)
213 #define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO	(0x0760)
214 #define WSA_MAX_OFFSET				(0x0760)
215 
216 #define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
217 			SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
218 			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
219 #define WSA_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\
220 			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
221 #define WSA_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
222 		SNDRV_PCM_FMTBIT_S24_LE |\
223 		SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
224 
225 #define WSA_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
226 			SNDRV_PCM_RATE_48000)
227 #define WSA_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
228 		SNDRV_PCM_FMTBIT_S24_LE |\
229 		SNDRV_PCM_FMTBIT_S24_3LE)
230 
231 #define NUM_INTERPOLATORS 2
232 #define WSA_NUM_CLKS_MAX	5
233 #define WSA_MACRO_MCLK_FREQ 19200000
234 #define WSA_MACRO_MUX_INP_MASK2 0x38
235 #define WSA_MACRO_MUX_CFG_OFFSET 0x8
236 #define WSA_MACRO_MUX_CFG1_OFFSET 0x4
237 #define WSA_MACRO_RX_COMP_OFFSET 0x40
238 #define WSA_MACRO_RX_SOFTCLIP_OFFSET 0x40
239 #define WSA_MACRO_RX_PATH_OFFSET 0x80
240 #define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10
241 #define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C
242 #define WSA_MACRO_FS_RATE_MASK 0x0F
243 #define WSA_MACRO_EC_MIX_TX0_MASK 0x03
244 #define WSA_MACRO_EC_MIX_TX1_MASK 0x18
245 #define WSA_MACRO_MAX_DMA_CH_PER_PORT 0x2
246 
247 enum {
248 	WSA_MACRO_GAIN_OFFSET_M1P5_DB,
249 	WSA_MACRO_GAIN_OFFSET_0_DB,
250 };
251 enum {
252 	WSA_MACRO_RX0 = 0,
253 	WSA_MACRO_RX1,
254 	WSA_MACRO_RX_MIX,
255 	WSA_MACRO_RX_MIX0 = WSA_MACRO_RX_MIX,
256 	WSA_MACRO_RX_MIX1,
257 	WSA_MACRO_RX_MAX,
258 };
259 
260 enum {
261 	WSA_MACRO_TX0 = 0,
262 	WSA_MACRO_TX1,
263 	WSA_MACRO_TX_MAX,
264 };
265 
266 enum {
267 	WSA_MACRO_EC0_MUX = 0,
268 	WSA_MACRO_EC1_MUX,
269 	WSA_MACRO_EC_MUX_MAX,
270 };
271 
272 enum {
273 	WSA_MACRO_COMP1, /* SPK_L */
274 	WSA_MACRO_COMP2, /* SPK_R */
275 	WSA_MACRO_COMP_MAX
276 };
277 
278 enum {
279 	WSA_MACRO_SOFTCLIP0, /* RX0 */
280 	WSA_MACRO_SOFTCLIP1, /* RX1 */
281 	WSA_MACRO_SOFTCLIP_MAX
282 };
283 
284 enum {
285 	INTn_1_INP_SEL_ZERO = 0,
286 	INTn_1_INP_SEL_RX0,
287 	INTn_1_INP_SEL_RX1,
288 	INTn_1_INP_SEL_RX2,
289 	INTn_1_INP_SEL_RX3,
290 	INTn_1_INP_SEL_DEC0,
291 	INTn_1_INP_SEL_DEC1,
292 };
293 
294 enum {
295 	INTn_2_INP_SEL_ZERO = 0,
296 	INTn_2_INP_SEL_RX0,
297 	INTn_2_INP_SEL_RX1,
298 	INTn_2_INP_SEL_RX2,
299 	INTn_2_INP_SEL_RX3,
300 };
301 
302 struct interp_sample_rate {
303 	int sample_rate;
304 	int rate_val;
305 };
306 
307 static struct interp_sample_rate int_prim_sample_rate_val[] = {
308 	{8000, 0x0},	/* 8K */
309 	{16000, 0x1},	/* 16K */
310 	{24000, -EINVAL},/* 24K */
311 	{32000, 0x3},	/* 32K */
312 	{48000, 0x4},	/* 48K */
313 	{96000, 0x5},	/* 96K */
314 	{192000, 0x6},	/* 192K */
315 	{384000, 0x7},	/* 384K */
316 	{44100, 0x8}, /* 44.1K */
317 };
318 
319 static struct interp_sample_rate int_mix_sample_rate_val[] = {
320 	{48000, 0x4},	/* 48K */
321 	{96000, 0x5},	/* 96K */
322 	{192000, 0x6},	/* 192K */
323 };
324 
325 enum {
326 	WSA_MACRO_AIF_INVALID = 0,
327 	WSA_MACRO_AIF1_PB,
328 	WSA_MACRO_AIF_MIX1_PB,
329 	WSA_MACRO_AIF_VI,
330 	WSA_MACRO_AIF_ECHO,
331 	WSA_MACRO_MAX_DAIS,
332 };
333 
334 struct wsa_macro {
335 	struct device *dev;
336 	int comp_enabled[WSA_MACRO_COMP_MAX];
337 	int ec_hq[WSA_MACRO_RX1 + 1];
338 	u16 prim_int_users[WSA_MACRO_RX1 + 1];
339 	u16 wsa_mclk_users;
340 	bool reset_swr;
341 	unsigned long active_ch_mask[WSA_MACRO_MAX_DAIS];
342 	unsigned long active_ch_cnt[WSA_MACRO_MAX_DAIS];
343 	int rx_port_value[WSA_MACRO_RX_MAX];
344 	int ear_spkr_gain;
345 	int spkr_gain_offset;
346 	int spkr_mode;
347 	int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX];
348 	int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX];
349 	struct regmap *regmap;
350 	struct clk_bulk_data clks[WSA_NUM_CLKS_MAX];
351 	struct clk_hw hw;
352 };
353 #define to_wsa_macro(_hw) container_of(_hw, struct wsa_macro, hw)
354 
355 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
356 
357 static const char *const rx_text[] = {
358 	"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "DEC0", "DEC1"
359 };
360 
361 static const char *const rx_mix_text[] = {
362 	"ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1"
363 };
364 
365 static const char *const rx_mix_ec_text[] = {
366 	"ZERO", "RX_MIX_TX0", "RX_MIX_TX1"
367 };
368 
369 static const char *const rx_mux_text[] = {
370 	"ZERO", "AIF1_PB", "AIF_MIX1_PB"
371 };
372 
373 static const char *const rx_sidetone_mix_text[] = {
374 	"ZERO", "SRC0"
375 };
376 
377 static const char * const wsa_macro_ear_spkr_pa_gain_text[] = {
378 	"G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB",
379 	"G_4_DB", "G_5_DB", "G_6_DB"
380 };
381 
382 static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum,
383 				wsa_macro_ear_spkr_pa_gain_text);
384 
385 /* RX INT0 */
386 static const struct soc_enum rx0_prim_inp0_chain_enum =
387 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
388 		0, 7, rx_text);
389 
390 static const struct soc_enum rx0_prim_inp1_chain_enum =
391 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0,
392 		3, 7, rx_text);
393 
394 static const struct soc_enum rx0_prim_inp2_chain_enum =
395 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
396 		3, 7, rx_text);
397 
398 static const struct soc_enum rx0_mix_chain_enum =
399 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1,
400 		0, 5, rx_mix_text);
401 
402 static const struct soc_enum rx0_sidetone_mix_enum =
403 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text);
404 
405 static const struct snd_kcontrol_new rx0_prim_inp0_mux =
406 	SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum);
407 
408 static const struct snd_kcontrol_new rx0_prim_inp1_mux =
409 	SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum);
410 
411 static const struct snd_kcontrol_new rx0_prim_inp2_mux =
412 	SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum);
413 
414 static const struct snd_kcontrol_new rx0_mix_mux =
415 	SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum);
416 
417 static const struct snd_kcontrol_new rx0_sidetone_mix_mux =
418 	SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum);
419 
420 /* RX INT1 */
421 static const struct soc_enum rx1_prim_inp0_chain_enum =
422 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
423 		0, 7, rx_text);
424 
425 static const struct soc_enum rx1_prim_inp1_chain_enum =
426 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0,
427 		3, 7, rx_text);
428 
429 static const struct soc_enum rx1_prim_inp2_chain_enum =
430 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
431 		3, 7, rx_text);
432 
433 static const struct soc_enum rx1_mix_chain_enum =
434 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1,
435 		0, 5, rx_mix_text);
436 
437 static const struct snd_kcontrol_new rx1_prim_inp0_mux =
438 	SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum);
439 
440 static const struct snd_kcontrol_new rx1_prim_inp1_mux =
441 	SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum);
442 
443 static const struct snd_kcontrol_new rx1_prim_inp2_mux =
444 	SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum);
445 
446 static const struct snd_kcontrol_new rx1_mix_mux =
447 	SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum);
448 
449 static const struct soc_enum rx_mix_ec0_enum =
450 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
451 		0, 3, rx_mix_ec_text);
452 
453 static const struct soc_enum rx_mix_ec1_enum =
454 	SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0,
455 		3, 3, rx_mix_ec_text);
456 
457 static const struct snd_kcontrol_new rx_mix_ec0_mux =
458 	SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum);
459 
460 static const struct snd_kcontrol_new rx_mix_ec1_mux =
461 	SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum);
462 
463 static const struct reg_default wsa_defaults[] = {
464 	/* WSA Macro */
465 	{ CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00},
466 	{ CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00},
467 	{ CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00},
468 	{ CDC_WSA_TOP_TOP_CFG0, 0x00},
469 	{ CDC_WSA_TOP_TOP_CFG1, 0x00},
470 	{ CDC_WSA_TOP_FREQ_MCLK, 0x00},
471 	{ CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00},
472 	{ CDC_WSA_TOP_DEBUG_EN0, 0x00},
473 	{ CDC_WSA_TOP_DEBUG_EN1, 0x00},
474 	{ CDC_WSA_TOP_DEBUG_DSM_LB, 0x88},
475 	{ CDC_WSA_TOP_RX_I2S_CTL, 0x0C},
476 	{ CDC_WSA_TOP_TX_I2S_CTL, 0x0C},
477 	{ CDC_WSA_TOP_I2S_CLK, 0x02},
478 	{ CDC_WSA_TOP_I2S_RESET, 0x00},
479 	{ CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00},
480 	{ CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00},
481 	{ CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00},
482 	{ CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00},
483 	{ CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00},
484 	{ CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00},
485 	{ CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00},
486 	{ CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02},
487 	{ CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00},
488 	{ CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02},
489 	{ CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00},
490 	{ CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02},
491 	{ CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00},
492 	{ CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02},
493 	{ CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00},
494 	{ CDC_WSA_INTR_CTRL_CFG, 0x00},
495 	{ CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00},
496 	{ CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF},
497 	{ CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00},
498 	{ CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00},
499 	{ CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF},
500 	{ CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00},
501 	{ CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00},
502 	{ CDC_WSA_INTR_CTRL_LEVEL0, 0x00},
503 	{ CDC_WSA_INTR_CTRL_BYPASS0, 0x00},
504 	{ CDC_WSA_INTR_CTRL_SET0, 0x00},
505 	{ CDC_WSA_RX0_RX_PATH_CTL, 0x04},
506 	{ CDC_WSA_RX0_RX_PATH_CFG0, 0x00},
507 	{ CDC_WSA_RX0_RX_PATH_CFG1, 0x64},
508 	{ CDC_WSA_RX0_RX_PATH_CFG2, 0x8F},
509 	{ CDC_WSA_RX0_RX_PATH_CFG3, 0x00},
510 	{ CDC_WSA_RX0_RX_VOL_CTL, 0x00},
511 	{ CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04},
512 	{ CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E},
513 	{ CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00},
514 	{ CDC_WSA_RX0_RX_PATH_SEC0, 0x04},
515 	{ CDC_WSA_RX0_RX_PATH_SEC1, 0x08},
516 	{ CDC_WSA_RX0_RX_PATH_SEC2, 0x00},
517 	{ CDC_WSA_RX0_RX_PATH_SEC3, 0x00},
518 	{ CDC_WSA_RX0_RX_PATH_SEC5, 0x00},
519 	{ CDC_WSA_RX0_RX_PATH_SEC6, 0x00},
520 	{ CDC_WSA_RX0_RX_PATH_SEC7, 0x00},
521 	{ CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08},
522 	{ CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00},
523 	{ CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00},
524 	{ CDC_WSA_RX1_RX_PATH_CFG0, 0x00},
525 	{ CDC_WSA_RX1_RX_PATH_CFG1, 0x64},
526 	{ CDC_WSA_RX1_RX_PATH_CFG2, 0x8F},
527 	{ CDC_WSA_RX1_RX_PATH_CFG3, 0x00},
528 	{ CDC_WSA_RX1_RX_VOL_CTL, 0x00},
529 	{ CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04},
530 	{ CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E},
531 	{ CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00},
532 	{ CDC_WSA_RX1_RX_PATH_SEC0, 0x04},
533 	{ CDC_WSA_RX1_RX_PATH_SEC1, 0x08},
534 	{ CDC_WSA_RX1_RX_PATH_SEC2, 0x00},
535 	{ CDC_WSA_RX1_RX_PATH_SEC3, 0x00},
536 	{ CDC_WSA_RX1_RX_PATH_SEC5, 0x00},
537 	{ CDC_WSA_RX1_RX_PATH_SEC6, 0x00},
538 	{ CDC_WSA_RX1_RX_PATH_SEC7, 0x00},
539 	{ CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08},
540 	{ CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00},
541 	{ CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00},
542 	{ CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00},
543 	{ CDC_WSA_BOOST0_BOOST_CTL, 0xD0},
544 	{ CDC_WSA_BOOST0_BOOST_CFG1, 0x89},
545 	{ CDC_WSA_BOOST0_BOOST_CFG2, 0x04},
546 	{ CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00},
547 	{ CDC_WSA_BOOST1_BOOST_CTL, 0xD0},
548 	{ CDC_WSA_BOOST1_BOOST_CFG1, 0x89},
549 	{ CDC_WSA_BOOST1_BOOST_CFG2, 0x04},
550 	{ CDC_WSA_COMPANDER0_CTL0, 0x60},
551 	{ CDC_WSA_COMPANDER0_CTL1, 0xDB},
552 	{ CDC_WSA_COMPANDER0_CTL2, 0xFF},
553 	{ CDC_WSA_COMPANDER0_CTL3, 0x35},
554 	{ CDC_WSA_COMPANDER0_CTL4, 0xFF},
555 	{ CDC_WSA_COMPANDER0_CTL5, 0x00},
556 	{ CDC_WSA_COMPANDER0_CTL6, 0x01},
557 	{ CDC_WSA_COMPANDER0_CTL7, 0x28},
558 	{ CDC_WSA_COMPANDER1_CTL0, 0x60},
559 	{ CDC_WSA_COMPANDER1_CTL1, 0xDB},
560 	{ CDC_WSA_COMPANDER1_CTL2, 0xFF},
561 	{ CDC_WSA_COMPANDER1_CTL3, 0x35},
562 	{ CDC_WSA_COMPANDER1_CTL4, 0xFF},
563 	{ CDC_WSA_COMPANDER1_CTL5, 0x00},
564 	{ CDC_WSA_COMPANDER1_CTL6, 0x01},
565 	{ CDC_WSA_COMPANDER1_CTL7, 0x28},
566 	{ CDC_WSA_SOFTCLIP0_CRC, 0x00},
567 	{ CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38},
568 	{ CDC_WSA_SOFTCLIP1_CRC, 0x00},
569 	{ CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38},
570 	{ CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00},
571 	{ CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01},
572 	{ CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00},
573 	{ CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01},
574 	{ CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00},
575 	{ CDC_WSA_SPLINE_ASRC0_CTL0, 0x00},
576 	{ CDC_WSA_SPLINE_ASRC0_CTL1, 0x00},
577 	{ CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8},
578 	{ CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00},
579 	{ CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00},
580 	{ CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00},
581 	{ CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00},
582 	{ CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00},
583 	{ CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00},
584 	{ CDC_WSA_SPLINE_ASRC1_CTL0, 0x00},
585 	{ CDC_WSA_SPLINE_ASRC1_CTL1, 0x00},
586 	{ CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8},
587 	{ CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00},
588 	{ CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00},
589 	{ CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00},
590 	{ CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00},
591 	{ CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00},
592 };
593 
594 static bool wsa_is_wronly_register(struct device *dev,
595 					unsigned int reg)
596 {
597 	switch (reg) {
598 	case CDC_WSA_INTR_CTRL_CLR_COMMIT:
599 	case CDC_WSA_INTR_CTRL_PIN1_CLEAR0:
600 	case CDC_WSA_INTR_CTRL_PIN2_CLEAR0:
601 		return true;
602 	}
603 
604 	return false;
605 }
606 
607 static bool wsa_is_rw_register(struct device *dev, unsigned int reg)
608 {
609 	switch (reg) {
610 	case CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL:
611 	case CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL:
612 	case CDC_WSA_CLK_RST_CTRL_SWR_CONTROL:
613 	case CDC_WSA_TOP_TOP_CFG0:
614 	case CDC_WSA_TOP_TOP_CFG1:
615 	case CDC_WSA_TOP_FREQ_MCLK:
616 	case CDC_WSA_TOP_DEBUG_BUS_SEL:
617 	case CDC_WSA_TOP_DEBUG_EN0:
618 	case CDC_WSA_TOP_DEBUG_EN1:
619 	case CDC_WSA_TOP_DEBUG_DSM_LB:
620 	case CDC_WSA_TOP_RX_I2S_CTL:
621 	case CDC_WSA_TOP_TX_I2S_CTL:
622 	case CDC_WSA_TOP_I2S_CLK:
623 	case CDC_WSA_TOP_I2S_RESET:
624 	case CDC_WSA_RX_INP_MUX_RX_INT0_CFG0:
625 	case CDC_WSA_RX_INP_MUX_RX_INT0_CFG1:
626 	case CDC_WSA_RX_INP_MUX_RX_INT1_CFG0:
627 	case CDC_WSA_RX_INP_MUX_RX_INT1_CFG1:
628 	case CDC_WSA_RX_INP_MUX_RX_MIX_CFG0:
629 	case CDC_WSA_RX_INP_MUX_RX_EC_CFG0:
630 	case CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0:
631 	case CDC_WSA_TX0_SPKR_PROT_PATH_CTL:
632 	case CDC_WSA_TX0_SPKR_PROT_PATH_CFG0:
633 	case CDC_WSA_TX1_SPKR_PROT_PATH_CTL:
634 	case CDC_WSA_TX1_SPKR_PROT_PATH_CFG0:
635 	case CDC_WSA_TX2_SPKR_PROT_PATH_CTL:
636 	case CDC_WSA_TX2_SPKR_PROT_PATH_CFG0:
637 	case CDC_WSA_TX3_SPKR_PROT_PATH_CTL:
638 	case CDC_WSA_TX3_SPKR_PROT_PATH_CFG0:
639 	case CDC_WSA_INTR_CTRL_CFG:
640 	case CDC_WSA_INTR_CTRL_PIN1_MASK0:
641 	case CDC_WSA_INTR_CTRL_PIN2_MASK0:
642 	case CDC_WSA_INTR_CTRL_LEVEL0:
643 	case CDC_WSA_INTR_CTRL_BYPASS0:
644 	case CDC_WSA_INTR_CTRL_SET0:
645 	case CDC_WSA_RX0_RX_PATH_CTL:
646 	case CDC_WSA_RX0_RX_PATH_CFG0:
647 	case CDC_WSA_RX0_RX_PATH_CFG1:
648 	case CDC_WSA_RX0_RX_PATH_CFG2:
649 	case CDC_WSA_RX0_RX_PATH_CFG3:
650 	case CDC_WSA_RX0_RX_VOL_CTL:
651 	case CDC_WSA_RX0_RX_PATH_MIX_CTL:
652 	case CDC_WSA_RX0_RX_PATH_MIX_CFG:
653 	case CDC_WSA_RX0_RX_VOL_MIX_CTL:
654 	case CDC_WSA_RX0_RX_PATH_SEC0:
655 	case CDC_WSA_RX0_RX_PATH_SEC1:
656 	case CDC_WSA_RX0_RX_PATH_SEC2:
657 	case CDC_WSA_RX0_RX_PATH_SEC3:
658 	case CDC_WSA_RX0_RX_PATH_SEC5:
659 	case CDC_WSA_RX0_RX_PATH_SEC6:
660 	case CDC_WSA_RX0_RX_PATH_SEC7:
661 	case CDC_WSA_RX0_RX_PATH_MIX_SEC0:
662 	case CDC_WSA_RX0_RX_PATH_MIX_SEC1:
663 	case CDC_WSA_RX0_RX_PATH_DSMDEM_CTL:
664 	case CDC_WSA_RX1_RX_PATH_CTL:
665 	case CDC_WSA_RX1_RX_PATH_CFG0:
666 	case CDC_WSA_RX1_RX_PATH_CFG1:
667 	case CDC_WSA_RX1_RX_PATH_CFG2:
668 	case CDC_WSA_RX1_RX_PATH_CFG3:
669 	case CDC_WSA_RX1_RX_VOL_CTL:
670 	case CDC_WSA_RX1_RX_PATH_MIX_CTL:
671 	case CDC_WSA_RX1_RX_PATH_MIX_CFG:
672 	case CDC_WSA_RX1_RX_VOL_MIX_CTL:
673 	case CDC_WSA_RX1_RX_PATH_SEC0:
674 	case CDC_WSA_RX1_RX_PATH_SEC1:
675 	case CDC_WSA_RX1_RX_PATH_SEC2:
676 	case CDC_WSA_RX1_RX_PATH_SEC3:
677 	case CDC_WSA_RX1_RX_PATH_SEC5:
678 	case CDC_WSA_RX1_RX_PATH_SEC6:
679 	case CDC_WSA_RX1_RX_PATH_SEC7:
680 	case CDC_WSA_RX1_RX_PATH_MIX_SEC0:
681 	case CDC_WSA_RX1_RX_PATH_MIX_SEC1:
682 	case CDC_WSA_RX1_RX_PATH_DSMDEM_CTL:
683 	case CDC_WSA_BOOST0_BOOST_PATH_CTL:
684 	case CDC_WSA_BOOST0_BOOST_CTL:
685 	case CDC_WSA_BOOST0_BOOST_CFG1:
686 	case CDC_WSA_BOOST0_BOOST_CFG2:
687 	case CDC_WSA_BOOST1_BOOST_PATH_CTL:
688 	case CDC_WSA_BOOST1_BOOST_CTL:
689 	case CDC_WSA_BOOST1_BOOST_CFG1:
690 	case CDC_WSA_BOOST1_BOOST_CFG2:
691 	case CDC_WSA_COMPANDER0_CTL0:
692 	case CDC_WSA_COMPANDER0_CTL1:
693 	case CDC_WSA_COMPANDER0_CTL2:
694 	case CDC_WSA_COMPANDER0_CTL3:
695 	case CDC_WSA_COMPANDER0_CTL4:
696 	case CDC_WSA_COMPANDER0_CTL5:
697 	case CDC_WSA_COMPANDER0_CTL7:
698 	case CDC_WSA_COMPANDER1_CTL0:
699 	case CDC_WSA_COMPANDER1_CTL1:
700 	case CDC_WSA_COMPANDER1_CTL2:
701 	case CDC_WSA_COMPANDER1_CTL3:
702 	case CDC_WSA_COMPANDER1_CTL4:
703 	case CDC_WSA_COMPANDER1_CTL5:
704 	case CDC_WSA_COMPANDER1_CTL7:
705 	case CDC_WSA_SOFTCLIP0_CRC:
706 	case CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL:
707 	case CDC_WSA_SOFTCLIP1_CRC:
708 	case CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL:
709 	case CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL:
710 	case CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0:
711 	case CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL:
712 	case CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0:
713 	case CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL:
714 	case CDC_WSA_SPLINE_ASRC0_CTL0:
715 	case CDC_WSA_SPLINE_ASRC0_CTL1:
716 	case CDC_WSA_SPLINE_ASRC0_FIFO_CTL:
717 	case CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL:
718 	case CDC_WSA_SPLINE_ASRC1_CTL0:
719 	case CDC_WSA_SPLINE_ASRC1_CTL1:
720 	case CDC_WSA_SPLINE_ASRC1_FIFO_CTL:
721 		return true;
722 	}
723 
724 	return false;
725 }
726 
727 static bool wsa_is_writeable_register(struct device *dev, unsigned int reg)
728 {
729 	bool ret;
730 
731 	ret = wsa_is_rw_register(dev, reg);
732 	if (!ret)
733 		return wsa_is_wronly_register(dev, reg);
734 
735 	return ret;
736 }
737 
738 static bool wsa_is_readable_register(struct device *dev, unsigned int reg)
739 {
740 	switch (reg) {
741 	case CDC_WSA_INTR_CTRL_CLR_COMMIT:
742 	case CDC_WSA_INTR_CTRL_PIN1_CLEAR0:
743 	case CDC_WSA_INTR_CTRL_PIN2_CLEAR0:
744 	case CDC_WSA_INTR_CTRL_PIN1_STATUS0:
745 	case CDC_WSA_INTR_CTRL_PIN2_STATUS0:
746 	case CDC_WSA_COMPANDER0_CTL6:
747 	case CDC_WSA_COMPANDER1_CTL6:
748 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
749 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
750 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
751 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
752 	case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
753 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
754 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
755 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
756 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
757 	case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
758 		return true;
759 	}
760 
761 	return wsa_is_rw_register(dev, reg);
762 }
763 
764 static bool wsa_is_volatile_register(struct device *dev, unsigned int reg)
765 {
766 	/* Update volatile list for rx/tx macros */
767 	switch (reg) {
768 	case CDC_WSA_INTR_CTRL_PIN1_STATUS0:
769 	case CDC_WSA_INTR_CTRL_PIN2_STATUS0:
770 	case CDC_WSA_COMPANDER0_CTL6:
771 	case CDC_WSA_COMPANDER1_CTL6:
772 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB:
773 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB:
774 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB:
775 	case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB:
776 	case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO:
777 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB:
778 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB:
779 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB:
780 	case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB:
781 	case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO:
782 		return true;
783 	}
784 	return false;
785 }
786 
787 static const struct regmap_config wsa_regmap_config = {
788 	.name = "wsa_macro",
789 	.reg_bits = 16,
790 	.val_bits = 32, /* 8 but with 32 bit read/write */
791 	.reg_stride = 4,
792 	.cache_type = REGCACHE_FLAT,
793 	.reg_defaults = wsa_defaults,
794 	.num_reg_defaults = ARRAY_SIZE(wsa_defaults),
795 	.max_register = WSA_MAX_OFFSET,
796 	.writeable_reg = wsa_is_writeable_register,
797 	.volatile_reg = wsa_is_volatile_register,
798 	.readable_reg = wsa_is_readable_register,
799 };
800 
801 /**
802  * wsa_macro_set_spkr_mode - Configures speaker compander and smartboost
803  * settings based on speaker mode.
804  *
805  * @component: codec instance
806  * @mode: Indicates speaker configuration mode.
807  *
808  * Returns 0 on success or -EINVAL on error.
809  */
810 int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode)
811 {
812 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
813 
814 	wsa->spkr_mode = mode;
815 
816 	switch (mode) {
817 	case WSA_MACRO_SPKR_MODE_1:
818 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00);
819 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00);
820 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00);
821 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00);
822 		snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44);
823 		snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44);
824 		break;
825 	default:
826 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80);
827 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80);
828 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01);
829 		snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01);
830 		snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58);
831 		snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58);
832 		break;
833 	}
834 	return 0;
835 }
836 EXPORT_SYMBOL(wsa_macro_set_spkr_mode);
837 
838 static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
839 						u8 int_prim_fs_rate_reg_val,
840 						u32 sample_rate)
841 {
842 	u8 int_1_mix1_inp;
843 	u32 j, port;
844 	u16 int_mux_cfg0, int_mux_cfg1;
845 	u16 int_fs_reg;
846 	u8 inp0_sel, inp1_sel, inp2_sel;
847 	struct snd_soc_component *component = dai->component;
848 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
849 
850 	for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
851 		int_1_mix1_inp = port;
852 		if ((int_1_mix1_inp < WSA_MACRO_RX0) || (int_1_mix1_inp > WSA_MACRO_RX_MIX1)) {
853 			dev_err(component->dev,	"%s: Invalid RX port, Dai ID is %d\n",
854 				__func__, dai->id);
855 			return -EINVAL;
856 		}
857 
858 		int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0;
859 
860 		/*
861 		 * Loop through all interpolator MUX inputs and find out
862 		 * to which interpolator input, the cdc_dma rx port
863 		 * is connected
864 		 */
865 		for (j = 0; j < NUM_INTERPOLATORS; j++) {
866 			int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET;
867 			inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0,
868 								CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK);
869 			inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0,
870 								CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK);
871 			inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1,
872 								CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK);
873 
874 			if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
875 			    (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
876 			    (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
877 				int_fs_reg = CDC_WSA_RX0_RX_PATH_CTL +
878 					     WSA_MACRO_RX_PATH_OFFSET * j;
879 				/* sample_rate is in Hz */
880 				snd_soc_component_update_bits(component, int_fs_reg,
881 							      WSA_MACRO_FS_RATE_MASK,
882 							      int_prim_fs_rate_reg_val);
883 			}
884 			int_mux_cfg0 += WSA_MACRO_MUX_CFG_OFFSET;
885 		}
886 	}
887 
888 	return 0;
889 }
890 
891 static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
892 					       u8 int_mix_fs_rate_reg_val,
893 					       u32 sample_rate)
894 {
895 	u8 int_2_inp;
896 	u32 j, port;
897 	u16 int_mux_cfg1, int_fs_reg;
898 	u8 int_mux_cfg1_val;
899 	struct snd_soc_component *component = dai->component;
900 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
901 
902 	for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) {
903 		int_2_inp = port;
904 		if ((int_2_inp < WSA_MACRO_RX0) || (int_2_inp > WSA_MACRO_RX_MIX1)) {
905 			dev_err(component->dev,	"%s: Invalid RX port, Dai ID is %d\n",
906 				__func__, dai->id);
907 			return -EINVAL;
908 		}
909 
910 		int_mux_cfg1 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG1;
911 		for (j = 0; j < NUM_INTERPOLATORS; j++) {
912 			int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1,
913 									CDC_WSA_RX_INTX_2_SEL_MASK);
914 
915 			if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
916 				int_fs_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL +
917 					WSA_MACRO_RX_PATH_OFFSET * j;
918 
919 				snd_soc_component_update_bits(component,
920 						      int_fs_reg,
921 						      WSA_MACRO_FS_RATE_MASK,
922 						      int_mix_fs_rate_reg_val);
923 			}
924 			int_mux_cfg1 += WSA_MACRO_MUX_CFG_OFFSET;
925 		}
926 	}
927 	return 0;
928 }
929 
930 static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai,
931 					   u32 sample_rate)
932 {
933 	int rate_val = 0;
934 	int i, ret;
935 
936 	/* set mixing path rate */
937 	for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) {
938 		if (sample_rate == int_mix_sample_rate_val[i].sample_rate) {
939 			rate_val = int_mix_sample_rate_val[i].rate_val;
940 			break;
941 		}
942 	}
943 	if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) || (rate_val < 0))
944 		goto prim_rate;
945 
946 	ret = wsa_macro_set_mix_interpolator_rate(dai, (u8) rate_val, sample_rate);
947 	if (ret < 0)
948 		return ret;
949 prim_rate:
950 	/* set primary path sample rate */
951 	for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) {
952 		if (sample_rate == int_prim_sample_rate_val[i].sample_rate) {
953 			rate_val = int_prim_sample_rate_val[i].rate_val;
954 			break;
955 		}
956 	}
957 	if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) || (rate_val < 0))
958 		return -EINVAL;
959 
960 	ret = wsa_macro_set_prim_interpolator_rate(dai, (u8) rate_val, sample_rate);
961 
962 	return ret;
963 }
964 
965 static int wsa_macro_hw_params(struct snd_pcm_substream *substream,
966 			       struct snd_pcm_hw_params *params,
967 			       struct snd_soc_dai *dai)
968 {
969 	struct snd_soc_component *component = dai->component;
970 	int ret;
971 
972 	switch (substream->stream) {
973 	case SNDRV_PCM_STREAM_PLAYBACK:
974 		ret = wsa_macro_set_interpolator_rate(dai, params_rate(params));
975 		if (ret) {
976 			dev_err(component->dev,
977 				"%s: cannot set sample rate: %u\n",
978 				__func__, params_rate(params));
979 			return ret;
980 		}
981 		break;
982 	default:
983 		break;
984 	}
985 	return 0;
986 }
987 
988 static int wsa_macro_get_channel_map(struct snd_soc_dai *dai,
989 				     unsigned int *tx_num, unsigned int *tx_slot,
990 				     unsigned int *rx_num, unsigned int *rx_slot)
991 {
992 	struct snd_soc_component *component = dai->component;
993 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
994 	u16 val, mask = 0, cnt = 0, temp;
995 
996 	switch (dai->id) {
997 	case WSA_MACRO_AIF_VI:
998 		*tx_slot = wsa->active_ch_mask[dai->id];
999 		*tx_num = wsa->active_ch_cnt[dai->id];
1000 		break;
1001 	case WSA_MACRO_AIF1_PB:
1002 	case WSA_MACRO_AIF_MIX1_PB:
1003 		for_each_set_bit(temp, &wsa->active_ch_mask[dai->id],
1004 					WSA_MACRO_RX_MAX) {
1005 			mask |= (1 << temp);
1006 			if (++cnt == WSA_MACRO_MAX_DMA_CH_PER_PORT)
1007 				break;
1008 		}
1009 		if (mask & 0x0C)
1010 			mask = mask >> 0x2;
1011 		*rx_slot = mask;
1012 		*rx_num = cnt;
1013 		break;
1014 	case WSA_MACRO_AIF_ECHO:
1015 		val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
1016 		if (val & WSA_MACRO_EC_MIX_TX1_MASK) {
1017 			mask |= 0x2;
1018 			cnt++;
1019 		}
1020 		if (val & WSA_MACRO_EC_MIX_TX0_MASK) {
1021 			mask |= 0x1;
1022 			cnt++;
1023 		}
1024 		*tx_slot = mask;
1025 		*tx_num = cnt;
1026 		break;
1027 	default:
1028 		dev_err(component->dev, "%s: Invalid AIF\n", __func__);
1029 		break;
1030 	}
1031 	return 0;
1032 }
1033 
1034 static const struct snd_soc_dai_ops wsa_macro_dai_ops = {
1035 	.hw_params = wsa_macro_hw_params,
1036 	.get_channel_map = wsa_macro_get_channel_map,
1037 };
1038 
1039 static struct snd_soc_dai_driver wsa_macro_dai[] = {
1040 	{
1041 		.name = "wsa_macro_rx1",
1042 		.id = WSA_MACRO_AIF1_PB,
1043 		.playback = {
1044 			.stream_name = "WSA_AIF1 Playback",
1045 			.rates = WSA_MACRO_RX_RATES,
1046 			.formats = WSA_MACRO_RX_FORMATS,
1047 			.rate_max = 384000,
1048 			.rate_min = 8000,
1049 			.channels_min = 1,
1050 			.channels_max = 2,
1051 		},
1052 		.ops = &wsa_macro_dai_ops,
1053 	},
1054 	{
1055 		.name = "wsa_macro_rx_mix",
1056 		.id = WSA_MACRO_AIF_MIX1_PB,
1057 		.playback = {
1058 			.stream_name = "WSA_AIF_MIX1 Playback",
1059 			.rates = WSA_MACRO_RX_MIX_RATES,
1060 			.formats = WSA_MACRO_RX_FORMATS,
1061 			.rate_max = 192000,
1062 			.rate_min = 48000,
1063 			.channels_min = 1,
1064 			.channels_max = 2,
1065 		},
1066 		.ops = &wsa_macro_dai_ops,
1067 	},
1068 	{
1069 		.name = "wsa_macro_vifeedback",
1070 		.id = WSA_MACRO_AIF_VI,
1071 		.capture = {
1072 			.stream_name = "WSA_AIF_VI Capture",
1073 			.rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000,
1074 			.formats = WSA_MACRO_RX_FORMATS,
1075 			.rate_max = 48000,
1076 			.rate_min = 8000,
1077 			.channels_min = 1,
1078 			.channels_max = 4,
1079 		},
1080 		.ops = &wsa_macro_dai_ops,
1081 	},
1082 	{
1083 		.name = "wsa_macro_echo",
1084 		.id = WSA_MACRO_AIF_ECHO,
1085 		.capture = {
1086 			.stream_name = "WSA_AIF_ECHO Capture",
1087 			.rates = WSA_MACRO_ECHO_RATES,
1088 			.formats = WSA_MACRO_ECHO_FORMATS,
1089 			.rate_max = 48000,
1090 			.rate_min = 8000,
1091 			.channels_min = 1,
1092 			.channels_max = 2,
1093 		},
1094 		.ops = &wsa_macro_dai_ops,
1095 	},
1096 };
1097 
1098 static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable)
1099 {
1100 	struct regmap *regmap = wsa->regmap;
1101 
1102 	if (mclk_enable) {
1103 		if (wsa->wsa_mclk_users == 0) {
1104 			regcache_mark_dirty(regmap);
1105 			regcache_sync(regmap);
1106 			/* 9.6MHz MCLK, set value 0x00 if other frequency */
1107 			regmap_update_bits(regmap, CDC_WSA_TOP_FREQ_MCLK, 0x01, 0x01);
1108 			regmap_update_bits(regmap,
1109 					   CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL,
1110 					   CDC_WSA_MCLK_EN_MASK,
1111 					   CDC_WSA_MCLK_ENABLE);
1112 			regmap_update_bits(regmap,
1113 					   CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
1114 					   CDC_WSA_FS_CNT_EN_MASK,
1115 					   CDC_WSA_FS_CNT_ENABLE);
1116 		}
1117 		wsa->wsa_mclk_users++;
1118 	} else {
1119 		if (wsa->wsa_mclk_users <= 0) {
1120 			dev_err(wsa->dev, "clock already disabled\n");
1121 			wsa->wsa_mclk_users = 0;
1122 			return;
1123 		}
1124 		wsa->wsa_mclk_users--;
1125 		if (wsa->wsa_mclk_users == 0) {
1126 			regmap_update_bits(regmap,
1127 					   CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL,
1128 					   CDC_WSA_FS_CNT_EN_MASK,
1129 					   CDC_WSA_FS_CNT_DISABLE);
1130 			regmap_update_bits(regmap,
1131 					   CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL,
1132 					   CDC_WSA_MCLK_EN_MASK,
1133 					   CDC_WSA_MCLK_DISABLE);
1134 		}
1135 	}
1136 }
1137 
1138 static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w,
1139 				struct snd_kcontrol *kcontrol, int event)
1140 {
1141 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1142 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1143 
1144 	wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU);
1145 	return 0;
1146 }
1147 
1148 static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
1149 					struct snd_kcontrol *kcontrol,
1150 					int event)
1151 {
1152 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1153 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1154 	u32 tx_reg0, tx_reg1;
1155 
1156 	if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
1157 		tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL;
1158 		tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL;
1159 	} else if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
1160 		tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL;
1161 		tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL;
1162 	}
1163 
1164 	switch (event) {
1165 	case SND_SOC_DAPM_POST_PMU:
1166 			/* Enable V&I sensing */
1167 		snd_soc_component_update_bits(component, tx_reg0,
1168 					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1169 					      CDC_WSA_TX_SPKR_PROT_RESET);
1170 		snd_soc_component_update_bits(component, tx_reg1,
1171 					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1172 					      CDC_WSA_TX_SPKR_PROT_RESET);
1173 		snd_soc_component_update_bits(component, tx_reg0,
1174 					      CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1175 					      CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K);
1176 		snd_soc_component_update_bits(component, tx_reg1,
1177 					      CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1178 					      CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K);
1179 		snd_soc_component_update_bits(component, tx_reg0,
1180 					      CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1181 					      CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1182 		snd_soc_component_update_bits(component, tx_reg1,
1183 					      CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1184 					      CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1185 		snd_soc_component_update_bits(component, tx_reg0,
1186 					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1187 					      CDC_WSA_TX_SPKR_PROT_NO_RESET);
1188 		snd_soc_component_update_bits(component, tx_reg1,
1189 					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1190 					      CDC_WSA_TX_SPKR_PROT_NO_RESET);
1191 		break;
1192 	case SND_SOC_DAPM_POST_PMD:
1193 		/* Disable V&I sensing */
1194 		snd_soc_component_update_bits(component, tx_reg0,
1195 					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1196 					      CDC_WSA_TX_SPKR_PROT_RESET);
1197 		snd_soc_component_update_bits(component, tx_reg1,
1198 					      CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1199 					      CDC_WSA_TX_SPKR_PROT_RESET);
1200 		snd_soc_component_update_bits(component, tx_reg0,
1201 					      CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1202 					      CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1203 		snd_soc_component_update_bits(component, tx_reg1,
1204 					      CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1205 					      CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1206 		break;
1207 	}
1208 
1209 	return 0;
1210 }
1211 
1212 static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
1213 				     struct snd_kcontrol *kcontrol, int event)
1214 {
1215 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1216 	u16 path_reg, gain_reg;
1217 	int val;
1218 
1219 	switch (w->shift) {
1220 	case WSA_MACRO_RX_MIX0:
1221 		path_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL;
1222 		gain_reg = CDC_WSA_RX0_RX_VOL_MIX_CTL;
1223 		break;
1224 	case WSA_MACRO_RX_MIX1:
1225 		path_reg = CDC_WSA_RX1_RX_PATH_MIX_CTL;
1226 		gain_reg = CDC_WSA_RX1_RX_VOL_MIX_CTL;
1227 		break;
1228 	default:
1229 		return 0;
1230 	}
1231 
1232 	switch (event) {
1233 	case SND_SOC_DAPM_POST_PMU:
1234 		val = snd_soc_component_read(component, gain_reg);
1235 		snd_soc_component_write(component, gain_reg, val);
1236 		break;
1237 	case SND_SOC_DAPM_POST_PMD:
1238 		snd_soc_component_update_bits(component, path_reg,
1239 					      CDC_WSA_RX_PATH_MIX_CLK_EN_MASK,
1240 					      CDC_WSA_RX_PATH_MIX_CLK_DISABLE);
1241 		break;
1242 	}
1243 
1244 	return 0;
1245 }
1246 
1247 static void wsa_macro_hd2_control(struct snd_soc_component *component,
1248 				  u16 reg, int event)
1249 {
1250 	u16 hd2_scale_reg;
1251 	u16 hd2_enable_reg;
1252 
1253 	if (reg == CDC_WSA_RX0_RX_PATH_CTL) {
1254 		hd2_scale_reg = CDC_WSA_RX0_RX_PATH_SEC3;
1255 		hd2_enable_reg = CDC_WSA_RX0_RX_PATH_CFG0;
1256 	}
1257 	if (reg == CDC_WSA_RX1_RX_PATH_CTL) {
1258 		hd2_scale_reg = CDC_WSA_RX1_RX_PATH_SEC3;
1259 		hd2_enable_reg = CDC_WSA_RX1_RX_PATH_CFG0;
1260 	}
1261 
1262 	if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
1263 		snd_soc_component_update_bits(component, hd2_scale_reg,
1264 					      CDC_WSA_RX_PATH_HD2_ALPHA_MASK,
1265 					      0x10);
1266 		snd_soc_component_update_bits(component, hd2_scale_reg,
1267 					      CDC_WSA_RX_PATH_HD2_SCALE_MASK,
1268 					      0x1);
1269 		snd_soc_component_update_bits(component, hd2_enable_reg,
1270 					      CDC_WSA_RX_PATH_HD2_EN_MASK,
1271 					      CDC_WSA_RX_PATH_HD2_ENABLE);
1272 	}
1273 
1274 	if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
1275 		snd_soc_component_update_bits(component, hd2_enable_reg,
1276 					      CDC_WSA_RX_PATH_HD2_EN_MASK, 0);
1277 		snd_soc_component_update_bits(component, hd2_scale_reg,
1278 					      CDC_WSA_RX_PATH_HD2_SCALE_MASK,
1279 					      0);
1280 		snd_soc_component_update_bits(component, hd2_scale_reg,
1281 					      CDC_WSA_RX_PATH_HD2_ALPHA_MASK,
1282 					      0);
1283 	}
1284 }
1285 
1286 static int wsa_macro_config_compander(struct snd_soc_component *component,
1287 				      int comp, int event)
1288 {
1289 	u16 comp_ctl0_reg, rx_path_cfg0_reg;
1290 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1291 
1292 	if (!wsa->comp_enabled[comp])
1293 		return 0;
1294 
1295 	comp_ctl0_reg = CDC_WSA_COMPANDER0_CTL0 +
1296 					(comp * WSA_MACRO_RX_COMP_OFFSET);
1297 	rx_path_cfg0_reg = CDC_WSA_RX0_RX_PATH_CFG0 +
1298 					(comp * WSA_MACRO_RX_PATH_OFFSET);
1299 
1300 	if (SND_SOC_DAPM_EVENT_ON(event)) {
1301 		/* Enable Compander Clock */
1302 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1303 					      CDC_WSA_COMPANDER_CLK_EN_MASK,
1304 					      CDC_WSA_COMPANDER_CLK_ENABLE);
1305 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1306 					      CDC_WSA_COMPANDER_SOFT_RST_MASK,
1307 					      CDC_WSA_COMPANDER_SOFT_RST_ENABLE);
1308 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1309 					      CDC_WSA_COMPANDER_SOFT_RST_MASK,
1310 					      0);
1311 		snd_soc_component_update_bits(component, rx_path_cfg0_reg,
1312 					      CDC_WSA_RX_PATH_COMP_EN_MASK,
1313 					      CDC_WSA_RX_PATH_COMP_ENABLE);
1314 	}
1315 
1316 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
1317 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1318 					      CDC_WSA_COMPANDER_HALT_MASK,
1319 					      CDC_WSA_COMPANDER_HALT);
1320 		snd_soc_component_update_bits(component, rx_path_cfg0_reg,
1321 					      CDC_WSA_RX_PATH_COMP_EN_MASK, 0);
1322 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1323 					      CDC_WSA_COMPANDER_SOFT_RST_MASK,
1324 					      CDC_WSA_COMPANDER_SOFT_RST_ENABLE);
1325 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1326 					      CDC_WSA_COMPANDER_SOFT_RST_MASK,
1327 					      0);
1328 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1329 					      CDC_WSA_COMPANDER_CLK_EN_MASK, 0);
1330 		snd_soc_component_update_bits(component, comp_ctl0_reg,
1331 					      CDC_WSA_COMPANDER_HALT_MASK, 0);
1332 	}
1333 
1334 	return 0;
1335 }
1336 
1337 static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component,
1338 					 struct wsa_macro *wsa,
1339 					 int path,
1340 					 bool enable)
1341 {
1342 	u16 softclip_clk_reg = CDC_WSA_SOFTCLIP0_CRC +
1343 			(path * WSA_MACRO_RX_SOFTCLIP_OFFSET);
1344 	u8 softclip_mux_mask = (1 << path);
1345 	u8 softclip_mux_value = (1 << path);
1346 
1347 	if (enable) {
1348 		if (wsa->softclip_clk_users[path] == 0) {
1349 			snd_soc_component_update_bits(component,
1350 						softclip_clk_reg,
1351 						CDC_WSA_SOFTCLIP_CLK_EN_MASK,
1352 						CDC_WSA_SOFTCLIP_CLK_ENABLE);
1353 			snd_soc_component_update_bits(component,
1354 				CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0,
1355 				softclip_mux_mask, softclip_mux_value);
1356 		}
1357 		wsa->softclip_clk_users[path]++;
1358 	} else {
1359 		wsa->softclip_clk_users[path]--;
1360 		if (wsa->softclip_clk_users[path] == 0) {
1361 			snd_soc_component_update_bits(component,
1362 						softclip_clk_reg,
1363 						CDC_WSA_SOFTCLIP_CLK_EN_MASK,
1364 						0);
1365 			snd_soc_component_update_bits(component,
1366 				CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0,
1367 				softclip_mux_mask, 0x00);
1368 		}
1369 	}
1370 }
1371 
1372 static int wsa_macro_config_softclip(struct snd_soc_component *component,
1373 				     int path, int event)
1374 {
1375 	u16 softclip_ctrl_reg;
1376 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1377 	int softclip_path = 0;
1378 
1379 	if (path == WSA_MACRO_COMP1)
1380 		softclip_path = WSA_MACRO_SOFTCLIP0;
1381 	else if (path == WSA_MACRO_COMP2)
1382 		softclip_path = WSA_MACRO_SOFTCLIP1;
1383 
1384 	if (!wsa->is_softclip_on[softclip_path])
1385 		return 0;
1386 
1387 	softclip_ctrl_reg = CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL +
1388 				(softclip_path * WSA_MACRO_RX_SOFTCLIP_OFFSET);
1389 
1390 	if (SND_SOC_DAPM_EVENT_ON(event)) {
1391 		/* Enable Softclip clock and mux */
1392 		wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
1393 					      true);
1394 		/* Enable Softclip control */
1395 		snd_soc_component_update_bits(component, softclip_ctrl_reg,
1396 					      CDC_WSA_SOFTCLIP_EN_MASK,
1397 					      CDC_WSA_SOFTCLIP_ENABLE);
1398 	}
1399 
1400 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
1401 		snd_soc_component_update_bits(component, softclip_ctrl_reg,
1402 					      CDC_WSA_SOFTCLIP_EN_MASK, 0);
1403 		wsa_macro_enable_softclip_clk(component, wsa, softclip_path,
1404 					      false);
1405 	}
1406 
1407 	return 0;
1408 }
1409 
1410 static bool wsa_macro_adie_lb(struct snd_soc_component *component,
1411 			      int interp_idx)
1412 {
1413 	u16 int_mux_cfg0,  int_mux_cfg1;
1414 	u8 int_n_inp0, int_n_inp1, int_n_inp2;
1415 
1416 	int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8;
1417 	int_mux_cfg1 = int_mux_cfg0 + 4;
1418 
1419 	int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0,
1420 						  CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK);
1421 	if (int_n_inp0 == INTn_1_INP_SEL_DEC0 ||
1422 		int_n_inp0 == INTn_1_INP_SEL_DEC1)
1423 		return true;
1424 
1425 	int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0,
1426 						  CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK);
1427 	if (int_n_inp1 == INTn_1_INP_SEL_DEC0 ||
1428 		int_n_inp1 == INTn_1_INP_SEL_DEC1)
1429 		return true;
1430 
1431 	int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1,
1432 						  CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK);
1433 	if (int_n_inp2 == INTn_1_INP_SEL_DEC0 ||
1434 		int_n_inp2 == INTn_1_INP_SEL_DEC1)
1435 		return true;
1436 
1437 	return false;
1438 }
1439 
1440 static int wsa_macro_enable_main_path(struct snd_soc_dapm_widget *w,
1441 				      struct snd_kcontrol *kcontrol,
1442 				      int event)
1443 {
1444 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1445 	u16 reg;
1446 
1447 	reg = CDC_WSA_RX0_RX_PATH_CTL + WSA_MACRO_RX_PATH_OFFSET * w->shift;
1448 	switch (event) {
1449 	case SND_SOC_DAPM_PRE_PMU:
1450 		if (wsa_macro_adie_lb(component, w->shift)) {
1451 			snd_soc_component_update_bits(component, reg,
1452 					     CDC_WSA_RX_PATH_CLK_EN_MASK,
1453 					     CDC_WSA_RX_PATH_CLK_ENABLE);
1454 		}
1455 		break;
1456 	default:
1457 		break;
1458 	}
1459 	return 0;
1460 }
1461 
1462 static int wsa_macro_interp_get_primary_reg(u16 reg, u16 *ind)
1463 {
1464 	u16 prim_int_reg = 0;
1465 
1466 	switch (reg) {
1467 	case CDC_WSA_RX0_RX_PATH_CTL:
1468 	case CDC_WSA_RX0_RX_PATH_MIX_CTL:
1469 		prim_int_reg = CDC_WSA_RX0_RX_PATH_CTL;
1470 		*ind = 0;
1471 		break;
1472 	case CDC_WSA_RX1_RX_PATH_CTL:
1473 	case CDC_WSA_RX1_RX_PATH_MIX_CTL:
1474 		prim_int_reg = CDC_WSA_RX1_RX_PATH_CTL;
1475 		*ind = 1;
1476 		break;
1477 	}
1478 
1479 	return prim_int_reg;
1480 }
1481 
1482 static int wsa_macro_enable_prim_interpolator(struct snd_soc_component *component,
1483 					      u16 reg, int event)
1484 {
1485 	u16 prim_int_reg;
1486 	u16 ind = 0;
1487 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1488 
1489 	prim_int_reg = wsa_macro_interp_get_primary_reg(reg, &ind);
1490 
1491 	switch (event) {
1492 	case SND_SOC_DAPM_PRE_PMU:
1493 		wsa->prim_int_users[ind]++;
1494 		if (wsa->prim_int_users[ind] == 1) {
1495 			snd_soc_component_update_bits(component,
1496 						      prim_int_reg + WSA_MACRO_RX_PATH_CFG3_OFFSET,
1497 						      CDC_WSA_RX_DC_DCOEFF_MASK,
1498 						      0x3);
1499 			snd_soc_component_update_bits(component, prim_int_reg,
1500 					CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK,
1501 					CDC_WSA_RX_PATH_PGA_MUTE_ENABLE);
1502 			wsa_macro_hd2_control(component, prim_int_reg, event);
1503 			snd_soc_component_update_bits(component,
1504 				prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET,
1505 				CDC_WSA_RX_DSMDEM_CLK_EN_MASK,
1506 				CDC_WSA_RX_DSMDEM_CLK_ENABLE);
1507 		}
1508 		if ((reg != prim_int_reg) &&
1509 		    ((snd_soc_component_read(
1510 				component, prim_int_reg)) & 0x10))
1511 			snd_soc_component_update_bits(component, reg,
1512 					0x10, 0x10);
1513 		break;
1514 	case SND_SOC_DAPM_POST_PMD:
1515 		wsa->prim_int_users[ind]--;
1516 		if (wsa->prim_int_users[ind] == 0) {
1517 			snd_soc_component_update_bits(component,
1518 				prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET,
1519 				CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 0);
1520 			wsa_macro_hd2_control(component, prim_int_reg, event);
1521 		}
1522 		break;
1523 	}
1524 
1525 	return 0;
1526 }
1527 
1528 static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component,
1529 					  struct wsa_macro *wsa,
1530 					  int event, int gain_reg)
1531 {
1532 	int comp_gain_offset, val;
1533 
1534 	switch (wsa->spkr_mode) {
1535 	/* Compander gain in WSA_MACRO_SPKR_MODE1 case is 12 dB */
1536 	case WSA_MACRO_SPKR_MODE_1:
1537 		comp_gain_offset = -12;
1538 		break;
1539 	/* Default case compander gain is 15 dB */
1540 	default:
1541 		comp_gain_offset = -15;
1542 		break;
1543 	}
1544 
1545 	switch (event) {
1546 	case SND_SOC_DAPM_POST_PMU:
1547 		/* Apply ear spkr gain only if compander is enabled */
1548 		if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
1549 		    (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) &&
1550 		    (wsa->ear_spkr_gain != 0)) {
1551 			/* For example, val is -8(-12+5-1) for 4dB of gain */
1552 			val = comp_gain_offset + wsa->ear_spkr_gain - 1;
1553 			snd_soc_component_write(component, gain_reg, val);
1554 		}
1555 		break;
1556 	case SND_SOC_DAPM_POST_PMD:
1557 		/*
1558 		 * Reset RX0 volume to 0 dB if compander is enabled and
1559 		 * ear_spkr_gain is non-zero.
1560 		 */
1561 		if (wsa->comp_enabled[WSA_MACRO_COMP1] &&
1562 		    (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) &&
1563 		    (wsa->ear_spkr_gain != 0)) {
1564 			snd_soc_component_write(component, gain_reg, 0x0);
1565 		}
1566 		break;
1567 	}
1568 
1569 	return 0;
1570 }
1571 
1572 static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w,
1573 					 struct snd_kcontrol *kcontrol,
1574 					 int event)
1575 {
1576 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1577 	u16 gain_reg;
1578 	u16 reg;
1579 	int val;
1580 	int offset_val = 0;
1581 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1582 
1583 	if (w->shift == WSA_MACRO_COMP1) {
1584 		reg = CDC_WSA_RX0_RX_PATH_CTL;
1585 		gain_reg = CDC_WSA_RX0_RX_VOL_CTL;
1586 	} else if (w->shift == WSA_MACRO_COMP2) {
1587 		reg = CDC_WSA_RX1_RX_PATH_CTL;
1588 		gain_reg = CDC_WSA_RX1_RX_VOL_CTL;
1589 	}
1590 
1591 	switch (event) {
1592 	case SND_SOC_DAPM_PRE_PMU:
1593 		/* Reset if needed */
1594 		wsa_macro_enable_prim_interpolator(component, reg, event);
1595 		break;
1596 	case SND_SOC_DAPM_POST_PMU:
1597 		wsa_macro_config_compander(component, w->shift, event);
1598 		wsa_macro_config_softclip(component, w->shift, event);
1599 		/* apply gain after int clk is enabled */
1600 		if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
1601 		    (wsa->comp_enabled[WSA_MACRO_COMP1] ||
1602 		     wsa->comp_enabled[WSA_MACRO_COMP2])) {
1603 			snd_soc_component_update_bits(component,
1604 					CDC_WSA_RX0_RX_PATH_SEC1,
1605 					CDC_WSA_RX_PGA_HALF_DB_MASK,
1606 					CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1607 			snd_soc_component_update_bits(component,
1608 					CDC_WSA_RX0_RX_PATH_MIX_SEC0,
1609 					CDC_WSA_RX_PGA_HALF_DB_MASK,
1610 					CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1611 			snd_soc_component_update_bits(component,
1612 					CDC_WSA_RX1_RX_PATH_SEC1,
1613 					CDC_WSA_RX_PGA_HALF_DB_MASK,
1614 					CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1615 			snd_soc_component_update_bits(component,
1616 					CDC_WSA_RX1_RX_PATH_MIX_SEC0,
1617 					CDC_WSA_RX_PGA_HALF_DB_MASK,
1618 					CDC_WSA_RX_PGA_HALF_DB_ENABLE);
1619 			offset_val = -2;
1620 		}
1621 		val = snd_soc_component_read(component, gain_reg);
1622 		val += offset_val;
1623 		snd_soc_component_write(component, gain_reg, val);
1624 		wsa_macro_config_ear_spkr_gain(component, wsa,
1625 						event, gain_reg);
1626 		break;
1627 	case SND_SOC_DAPM_POST_PMD:
1628 		wsa_macro_config_compander(component, w->shift, event);
1629 		wsa_macro_config_softclip(component, w->shift, event);
1630 		wsa_macro_enable_prim_interpolator(component, reg, event);
1631 		if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) &&
1632 		    (wsa->comp_enabled[WSA_MACRO_COMP1] ||
1633 		     wsa->comp_enabled[WSA_MACRO_COMP2])) {
1634 			snd_soc_component_update_bits(component,
1635 					CDC_WSA_RX0_RX_PATH_SEC1,
1636 					CDC_WSA_RX_PGA_HALF_DB_MASK,
1637 					CDC_WSA_RX_PGA_HALF_DB_DISABLE);
1638 			snd_soc_component_update_bits(component,
1639 					CDC_WSA_RX0_RX_PATH_MIX_SEC0,
1640 					CDC_WSA_RX_PGA_HALF_DB_MASK,
1641 					CDC_WSA_RX_PGA_HALF_DB_DISABLE);
1642 			snd_soc_component_update_bits(component,
1643 					CDC_WSA_RX1_RX_PATH_SEC1,
1644 					CDC_WSA_RX_PGA_HALF_DB_MASK,
1645 					CDC_WSA_RX_PGA_HALF_DB_DISABLE);
1646 			snd_soc_component_update_bits(component,
1647 					CDC_WSA_RX1_RX_PATH_MIX_SEC0,
1648 					CDC_WSA_RX_PGA_HALF_DB_MASK,
1649 					CDC_WSA_RX_PGA_HALF_DB_DISABLE);
1650 			offset_val = 2;
1651 			val = snd_soc_component_read(component, gain_reg);
1652 			val += offset_val;
1653 			snd_soc_component_write(component, gain_reg, val);
1654 		}
1655 		wsa_macro_config_ear_spkr_gain(component, wsa,
1656 						event, gain_reg);
1657 		break;
1658 	}
1659 
1660 	return 0;
1661 }
1662 
1663 static int wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w,
1664 				     struct snd_kcontrol *kcontrol,
1665 				     int event)
1666 {
1667 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1668 	u16 boost_path_ctl, boost_path_cfg1;
1669 	u16 reg, reg_mix;
1670 
1671 	if (!strcmp(w->name, "WSA_RX INT0 CHAIN")) {
1672 		boost_path_ctl = CDC_WSA_BOOST0_BOOST_PATH_CTL;
1673 		boost_path_cfg1 = CDC_WSA_RX0_RX_PATH_CFG1;
1674 		reg = CDC_WSA_RX0_RX_PATH_CTL;
1675 		reg_mix = CDC_WSA_RX0_RX_PATH_MIX_CTL;
1676 	} else if (!strcmp(w->name, "WSA_RX INT1 CHAIN")) {
1677 		boost_path_ctl = CDC_WSA_BOOST1_BOOST_PATH_CTL;
1678 		boost_path_cfg1 = CDC_WSA_RX1_RX_PATH_CFG1;
1679 		reg = CDC_WSA_RX1_RX_PATH_CTL;
1680 		reg_mix = CDC_WSA_RX1_RX_PATH_MIX_CTL;
1681 	}
1682 
1683 	switch (event) {
1684 	case SND_SOC_DAPM_PRE_PMU:
1685 		snd_soc_component_update_bits(component, boost_path_cfg1,
1686 					      CDC_WSA_RX_PATH_SMART_BST_EN_MASK,
1687 					      CDC_WSA_RX_PATH_SMART_BST_ENABLE);
1688 		snd_soc_component_update_bits(component, boost_path_ctl,
1689 					      CDC_WSA_BOOST_PATH_CLK_EN_MASK,
1690 					      CDC_WSA_BOOST_PATH_CLK_ENABLE);
1691 		if ((snd_soc_component_read(component, reg_mix)) & 0x10)
1692 			snd_soc_component_update_bits(component, reg_mix,
1693 						0x10, 0x00);
1694 		break;
1695 	case SND_SOC_DAPM_POST_PMU:
1696 		snd_soc_component_update_bits(component, reg, 0x10, 0x00);
1697 		break;
1698 	case SND_SOC_DAPM_POST_PMD:
1699 		snd_soc_component_update_bits(component, boost_path_ctl,
1700 					      CDC_WSA_BOOST_PATH_CLK_EN_MASK,
1701 					      CDC_WSA_BOOST_PATH_CLK_DISABLE);
1702 		snd_soc_component_update_bits(component, boost_path_cfg1,
1703 					      CDC_WSA_RX_PATH_SMART_BST_EN_MASK,
1704 					      CDC_WSA_RX_PATH_SMART_BST_DISABLE);
1705 		break;
1706 	}
1707 
1708 	return 0;
1709 }
1710 
1711 static int wsa_macro_enable_echo(struct snd_soc_dapm_widget *w,
1712 				 struct snd_kcontrol *kcontrol,
1713 				 int event)
1714 {
1715 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1716 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1717 	u16 val, ec_tx, ec_hq_reg;
1718 
1719 	val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0);
1720 
1721 	switch (w->shift) {
1722 	case WSA_MACRO_EC0_MUX:
1723 		val = val & CDC_WSA_RX_MIX_TX0_SEL_MASK;
1724 		ec_tx = val - 1;
1725 		break;
1726 	case WSA_MACRO_EC1_MUX:
1727 		val = val & CDC_WSA_RX_MIX_TX1_SEL_MASK;
1728 		ec_tx = (val >> CDC_WSA_RX_MIX_TX1_SEL_SHFT) - 1;
1729 		break;
1730 	default:
1731 		dev_err(component->dev,	"%s: Invalid shift %u\n",
1732 			__func__, w->shift);
1733 		return -EINVAL;
1734 	}
1735 
1736 	if (wsa->ec_hq[ec_tx]) {
1737 		ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL +	0x40 * ec_tx;
1738 		snd_soc_component_update_bits(component, ec_hq_reg,
1739 					     CDC_WSA_EC_HQ_EC_CLK_EN_MASK,
1740 					     CDC_WSA_EC_HQ_EC_CLK_ENABLE);
1741 		ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 + 0x40 * ec_tx;
1742 		/* default set to 48k */
1743 		snd_soc_component_update_bits(component, ec_hq_reg,
1744 				      CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK,
1745 				      CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K);
1746 	}
1747 
1748 	return 0;
1749 }
1750 
1751 static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol,
1752 			       struct snd_ctl_elem_value *ucontrol)
1753 {
1754 
1755 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1756 	int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
1757 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1758 
1759 	ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx];
1760 
1761 	return 0;
1762 }
1763 
1764 static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol,
1765 			       struct snd_ctl_elem_value *ucontrol)
1766 {
1767 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1768 	int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
1769 	int value = ucontrol->value.integer.value[0];
1770 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1771 
1772 	wsa->ec_hq[ec_tx] = value;
1773 
1774 	return 0;
1775 }
1776 
1777 static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol,
1778 				   struct snd_ctl_elem_value *ucontrol)
1779 {
1780 
1781 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1782 	int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
1783 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1784 
1785 	ucontrol->value.integer.value[0] = wsa->comp_enabled[comp];
1786 	return 0;
1787 }
1788 
1789 static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol,
1790 				   struct snd_ctl_elem_value *ucontrol)
1791 {
1792 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1793 	int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
1794 	int value = ucontrol->value.integer.value[0];
1795 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1796 
1797 	wsa->comp_enabled[comp] = value;
1798 
1799 	return 0;
1800 }
1801 
1802 static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol,
1803 					  struct snd_ctl_elem_value *ucontrol)
1804 {
1805 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1806 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1807 
1808 	ucontrol->value.integer.value[0] = wsa->ear_spkr_gain;
1809 
1810 	return 0;
1811 }
1812 
1813 static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol,
1814 					  struct snd_ctl_elem_value *ucontrol)
1815 {
1816 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1817 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1818 
1819 	wsa->ear_spkr_gain =  ucontrol->value.integer.value[0];
1820 
1821 	return 0;
1822 }
1823 
1824 static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol,
1825 				struct snd_ctl_elem_value *ucontrol)
1826 {
1827 	struct snd_soc_dapm_widget *widget =
1828 		snd_soc_dapm_kcontrol_widget(kcontrol);
1829 	struct snd_soc_component *component =
1830 				snd_soc_dapm_to_component(widget->dapm);
1831 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1832 
1833 	ucontrol->value.integer.value[0] =
1834 			wsa->rx_port_value[widget->shift];
1835 	return 0;
1836 }
1837 
1838 static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol,
1839 				struct snd_ctl_elem_value *ucontrol)
1840 {
1841 	struct snd_soc_dapm_widget *widget =
1842 		snd_soc_dapm_kcontrol_widget(kcontrol);
1843 	struct snd_soc_component *component =
1844 				snd_soc_dapm_to_component(widget->dapm);
1845 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1846 	struct snd_soc_dapm_update *update = NULL;
1847 	u32 rx_port_value = ucontrol->value.integer.value[0];
1848 	u32 bit_input;
1849 	u32 aif_rst;
1850 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1851 
1852 	aif_rst = wsa->rx_port_value[widget->shift];
1853 	if (!rx_port_value) {
1854 		if (aif_rst == 0) {
1855 			dev_err(component->dev, "%s: AIF reset already\n", __func__);
1856 			return 0;
1857 		}
1858 		if (aif_rst >= WSA_MACRO_RX_MAX) {
1859 			dev_err(component->dev, "%s: Invalid AIF reset\n", __func__);
1860 			return 0;
1861 		}
1862 	}
1863 	wsa->rx_port_value[widget->shift] = rx_port_value;
1864 
1865 	bit_input = widget->shift;
1866 
1867 	switch (rx_port_value) {
1868 	case 0:
1869 		if (wsa->active_ch_cnt[aif_rst]) {
1870 			clear_bit(bit_input,
1871 				  &wsa->active_ch_mask[aif_rst]);
1872 			wsa->active_ch_cnt[aif_rst]--;
1873 		}
1874 		break;
1875 	case 1:
1876 	case 2:
1877 		set_bit(bit_input,
1878 			&wsa->active_ch_mask[rx_port_value]);
1879 		wsa->active_ch_cnt[rx_port_value]++;
1880 		break;
1881 	default:
1882 		dev_err(component->dev,
1883 			"%s: Invalid AIF_ID for WSA RX MUX %d\n",
1884 			__func__, rx_port_value);
1885 		return -EINVAL;
1886 	}
1887 
1888 	snd_soc_dapm_mux_update_power(widget->dapm, kcontrol,
1889 					rx_port_value, e, update);
1890 	return 0;
1891 }
1892 
1893 static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol,
1894 					  struct snd_ctl_elem_value *ucontrol)
1895 {
1896 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1897 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1898 	int path = ((struct soc_mixer_control *)kcontrol->private_value)->shift;
1899 
1900 	ucontrol->value.integer.value[0] = wsa->is_softclip_on[path];
1901 
1902 	return 0;
1903 }
1904 
1905 static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol,
1906 					  struct snd_ctl_elem_value *ucontrol)
1907 {
1908 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1909 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1910 	int path = ((struct soc_mixer_control *) kcontrol->private_value)->shift;
1911 
1912 	wsa->is_softclip_on[path] =  ucontrol->value.integer.value[0];
1913 
1914 	return 0;
1915 }
1916 
1917 static const struct snd_kcontrol_new wsa_macro_snd_controls[] = {
1918 	SOC_ENUM_EXT("EAR SPKR PA Gain", wsa_macro_ear_spkr_pa_gain_enum,
1919 		     wsa_macro_ear_spkr_pa_gain_get,
1920 		     wsa_macro_ear_spkr_pa_gain_put),
1921 	SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM,
1922 			WSA_MACRO_SOFTCLIP0, 1, 0,
1923 			wsa_macro_soft_clip_enable_get,
1924 			wsa_macro_soft_clip_enable_put),
1925 	SOC_SINGLE_EXT("WSA_Softclip1 Enable", SND_SOC_NOPM,
1926 			WSA_MACRO_SOFTCLIP1, 1, 0,
1927 			wsa_macro_soft_clip_enable_get,
1928 			wsa_macro_soft_clip_enable_put),
1929 
1930 	SOC_SINGLE_S8_TLV("WSA_RX0 Digital Volume", CDC_WSA_RX0_RX_VOL_CTL,
1931 			  -84, 40, digital_gain),
1932 	SOC_SINGLE_S8_TLV("WSA_RX1 Digital Volume", CDC_WSA_RX1_RX_VOL_CTL,
1933 			  -84, 40, digital_gain),
1934 
1935 	SOC_SINGLE("WSA_RX0 Digital Mute", CDC_WSA_RX0_RX_PATH_CTL, 4, 1, 0),
1936 	SOC_SINGLE("WSA_RX1 Digital Mute", CDC_WSA_RX1_RX_PATH_CTL, 4, 1, 0),
1937 	SOC_SINGLE("WSA_RX0_MIX Digital Mute", CDC_WSA_RX0_RX_PATH_MIX_CTL, 4,
1938 		   1, 0),
1939 	SOC_SINGLE("WSA_RX1_MIX Digital Mute", CDC_WSA_RX1_RX_PATH_MIX_CTL, 4,
1940 		   1, 0),
1941 	SOC_SINGLE_EXT("WSA_COMP1 Switch", SND_SOC_NOPM, WSA_MACRO_COMP1, 1, 0,
1942 		       wsa_macro_get_compander, wsa_macro_set_compander),
1943 	SOC_SINGLE_EXT("WSA_COMP2 Switch", SND_SOC_NOPM, WSA_MACRO_COMP2, 1, 0,
1944 		       wsa_macro_get_compander, wsa_macro_set_compander),
1945 	SOC_SINGLE_EXT("WSA_RX0 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX0, 1, 0,
1946 		       wsa_macro_get_ec_hq, wsa_macro_set_ec_hq),
1947 	SOC_SINGLE_EXT("WSA_RX1 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX1, 1, 0,
1948 		       wsa_macro_get_ec_hq, wsa_macro_set_ec_hq),
1949 };
1950 
1951 static const struct soc_enum rx_mux_enum =
1952 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_mux_text), rx_mux_text);
1953 
1954 static const struct snd_kcontrol_new rx_mux[WSA_MACRO_RX_MAX] = {
1955 	SOC_DAPM_ENUM_EXT("WSA RX0 Mux", rx_mux_enum,
1956 			  wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
1957 	SOC_DAPM_ENUM_EXT("WSA RX1 Mux", rx_mux_enum,
1958 			  wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
1959 	SOC_DAPM_ENUM_EXT("WSA RX_MIX0 Mux", rx_mux_enum,
1960 			  wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
1961 	SOC_DAPM_ENUM_EXT("WSA RX_MIX1 Mux", rx_mux_enum,
1962 			  wsa_macro_rx_mux_get, wsa_macro_rx_mux_put),
1963 };
1964 
1965 static int wsa_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol,
1966 				       struct snd_ctl_elem_value *ucontrol)
1967 {
1968 	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
1969 	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
1970 	struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1971 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1972 	u32 spk_tx_id = mixer->shift;
1973 	u32 dai_id = widget->shift;
1974 
1975 	if (test_bit(spk_tx_id, &wsa->active_ch_mask[dai_id]))
1976 		ucontrol->value.integer.value[0] = 1;
1977 	else
1978 		ucontrol->value.integer.value[0] = 0;
1979 
1980 	return 0;
1981 }
1982 
1983 static int wsa_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol,
1984 				       struct snd_ctl_elem_value *ucontrol)
1985 {
1986 	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
1987 	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
1988 	struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1989 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1990 	u32 enable = ucontrol->value.integer.value[0];
1991 	u32 spk_tx_id = mixer->shift;
1992 
1993 	if (enable) {
1994 		if (spk_tx_id == WSA_MACRO_TX0 &&
1995 			!test_bit(WSA_MACRO_TX0,
1996 				&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
1997 			set_bit(WSA_MACRO_TX0,
1998 				&wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
1999 			wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++;
2000 		}
2001 		if (spk_tx_id == WSA_MACRO_TX1 &&
2002 			!test_bit(WSA_MACRO_TX1,
2003 				&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
2004 			set_bit(WSA_MACRO_TX1,
2005 				&wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
2006 			wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++;
2007 		}
2008 	} else {
2009 		if (spk_tx_id == WSA_MACRO_TX0 &&
2010 			test_bit(WSA_MACRO_TX0,
2011 				&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
2012 			clear_bit(WSA_MACRO_TX0,
2013 				&wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
2014 			wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--;
2015 		}
2016 		if (spk_tx_id == WSA_MACRO_TX1 &&
2017 			test_bit(WSA_MACRO_TX1,
2018 				&wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
2019 			clear_bit(WSA_MACRO_TX1,
2020 				&wsa->active_ch_mask[WSA_MACRO_AIF_VI]);
2021 			wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--;
2022 		}
2023 	}
2024 	snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL);
2025 
2026 	return 0;
2027 }
2028 
2029 static const struct snd_kcontrol_new aif_vi_mixer[] = {
2030 	SOC_SINGLE_EXT("WSA_SPKR_VI_1", SND_SOC_NOPM, WSA_MACRO_TX0, 1, 0,
2031 			wsa_macro_vi_feed_mixer_get,
2032 			wsa_macro_vi_feed_mixer_put),
2033 	SOC_SINGLE_EXT("WSA_SPKR_VI_2", SND_SOC_NOPM, WSA_MACRO_TX1, 1, 0,
2034 			wsa_macro_vi_feed_mixer_get,
2035 			wsa_macro_vi_feed_mixer_put),
2036 };
2037 
2038 static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = {
2039 	SND_SOC_DAPM_AIF_IN("WSA AIF1 PB", "WSA_AIF1 Playback", 0,
2040 			    SND_SOC_NOPM, 0, 0),
2041 	SND_SOC_DAPM_AIF_IN("WSA AIF_MIX1 PB", "WSA_AIF_MIX1 Playback", 0,
2042 			    SND_SOC_NOPM, 0, 0),
2043 
2044 	SND_SOC_DAPM_AIF_OUT_E("WSA AIF_VI", "WSA_AIF_VI Capture", 0,
2045 			       SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0,
2046 			       wsa_macro_enable_vi_feedback,
2047 			       SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
2048 	SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0,
2049 			     SND_SOC_NOPM, 0, 0),
2050 
2051 	SND_SOC_DAPM_MIXER("WSA_AIF_VI Mixer", SND_SOC_NOPM, WSA_MACRO_AIF_VI,
2052 			   0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)),
2053 	SND_SOC_DAPM_MUX_E("WSA RX_MIX EC0_MUX", SND_SOC_NOPM,
2054 			   WSA_MACRO_EC0_MUX, 0,
2055 			   &rx_mix_ec0_mux, wsa_macro_enable_echo,
2056 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2057 	SND_SOC_DAPM_MUX_E("WSA RX_MIX EC1_MUX", SND_SOC_NOPM,
2058 			   WSA_MACRO_EC1_MUX, 0,
2059 			   &rx_mix_ec1_mux, wsa_macro_enable_echo,
2060 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2061 
2062 	SND_SOC_DAPM_MUX("WSA RX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX0, 0,
2063 			 &rx_mux[WSA_MACRO_RX0]),
2064 	SND_SOC_DAPM_MUX("WSA RX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX1, 0,
2065 			 &rx_mux[WSA_MACRO_RX1]),
2066 	SND_SOC_DAPM_MUX("WSA RX_MIX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 0,
2067 			 &rx_mux[WSA_MACRO_RX_MIX0]),
2068 	SND_SOC_DAPM_MUX("WSA RX_MIX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 0,
2069 			 &rx_mux[WSA_MACRO_RX_MIX1]),
2070 
2071 	SND_SOC_DAPM_MIXER("WSA RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2072 	SND_SOC_DAPM_MIXER("WSA RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2073 	SND_SOC_DAPM_MIXER("WSA RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0),
2074 	SND_SOC_DAPM_MIXER("WSA RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
2075 
2076 	SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, &rx0_prim_inp0_mux),
2077 	SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, &rx0_prim_inp1_mux),
2078 	SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, &rx0_prim_inp2_mux),
2079 	SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX0,
2080 			   0, &rx0_mix_mux, wsa_macro_enable_mix_path,
2081 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2082 	SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, &rx1_prim_inp0_mux),
2083 	SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, &rx1_prim_inp1_mux),
2084 	SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, &rx1_prim_inp2_mux),
2085 	SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX1,
2086 			   0, &rx1_mix_mux, wsa_macro_enable_mix_path,
2087 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2088 
2089 	SND_SOC_DAPM_MIXER_E("WSA_RX INT0 MIX", SND_SOC_NOPM, 0, 0, NULL, 0,
2090 			     wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU),
2091 	SND_SOC_DAPM_MIXER_E("WSA_RX INT1 MIX", SND_SOC_NOPM, 1, 0, NULL, 0,
2092 			     wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU),
2093 
2094 	SND_SOC_DAPM_MIXER("WSA_RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2095 	SND_SOC_DAPM_MIXER("WSA_RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2096 
2097 	SND_SOC_DAPM_MUX("WSA_RX0 INT0 SIDETONE MIX", CDC_WSA_RX0_RX_PATH_CFG1,
2098 			 4, 0, &rx0_sidetone_mix_mux),
2099 
2100 	SND_SOC_DAPM_INPUT("WSA SRC0_INP"),
2101 	SND_SOC_DAPM_INPUT("WSA_TX DEC0_INP"),
2102 	SND_SOC_DAPM_INPUT("WSA_TX DEC1_INP"),
2103 
2104 	SND_SOC_DAPM_MIXER_E("WSA_RX INT0 INTERP", SND_SOC_NOPM,
2105 			     WSA_MACRO_COMP1, 0, NULL, 0,
2106 			     wsa_macro_enable_interpolator,
2107 			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2108 			     SND_SOC_DAPM_POST_PMD),
2109 
2110 	SND_SOC_DAPM_MIXER_E("WSA_RX INT1 INTERP", SND_SOC_NOPM,
2111 			     WSA_MACRO_COMP2, 0, NULL, 0,
2112 			     wsa_macro_enable_interpolator,
2113 			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2114 			     SND_SOC_DAPM_POST_PMD),
2115 
2116 	SND_SOC_DAPM_MIXER_E("WSA_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0,
2117 			     NULL, 0, wsa_macro_spk_boost_event,
2118 			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2119 			     SND_SOC_DAPM_POST_PMD),
2120 
2121 	SND_SOC_DAPM_MIXER_E("WSA_RX INT1 CHAIN", SND_SOC_NOPM, 0, 0,
2122 			     NULL, 0, wsa_macro_spk_boost_event,
2123 			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2124 			     SND_SOC_DAPM_POST_PMD),
2125 
2126 	SND_SOC_DAPM_INPUT("VIINPUT_WSA"),
2127 	SND_SOC_DAPM_OUTPUT("WSA_SPK1 OUT"),
2128 	SND_SOC_DAPM_OUTPUT("WSA_SPK2 OUT"),
2129 
2130 	SND_SOC_DAPM_SUPPLY("WSA_RX0_CLK", CDC_WSA_RX0_RX_PATH_CTL, 5, 0, NULL, 0),
2131 	SND_SOC_DAPM_SUPPLY("WSA_RX1_CLK", CDC_WSA_RX1_RX_PATH_CTL, 5, 0, NULL, 0),
2132 	SND_SOC_DAPM_SUPPLY("WSA_RX_MIX0_CLK", CDC_WSA_RX0_RX_PATH_MIX_CTL, 5, 0, NULL, 0),
2133 	SND_SOC_DAPM_SUPPLY("WSA_RX_MIX1_CLK", CDC_WSA_RX1_RX_PATH_MIX_CTL, 5, 0, NULL, 0),
2134 	SND_SOC_DAPM_SUPPLY_S("WSA_MCLK", 0, SND_SOC_NOPM, 0, 0,
2135 			      wsa_macro_mclk_event,
2136 			      SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2137 };
2138 
2139 static const struct snd_soc_dapm_route wsa_audio_map[] = {
2140 	/* VI Feedback */
2141 	{"WSA_AIF_VI Mixer", "WSA_SPKR_VI_1", "VIINPUT_WSA"},
2142 	{"WSA_AIF_VI Mixer", "WSA_SPKR_VI_2", "VIINPUT_WSA"},
2143 	{"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"},
2144 	{"WSA AIF_VI", NULL, "WSA_MCLK"},
2145 
2146 	{"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
2147 	{"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"},
2148 	{"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
2149 	{"WSA RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"},
2150 	{"WSA AIF_ECHO", NULL, "WSA RX_MIX EC0_MUX"},
2151 	{"WSA AIF_ECHO", NULL, "WSA RX_MIX EC1_MUX"},
2152 	{"WSA AIF_ECHO", NULL, "WSA_MCLK"},
2153 
2154 	{"WSA AIF1 PB", NULL, "WSA_MCLK"},
2155 	{"WSA AIF_MIX1 PB", NULL, "WSA_MCLK"},
2156 
2157 	{"WSA RX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
2158 	{"WSA RX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
2159 	{"WSA RX_MIX0 MUX", "AIF1_PB", "WSA AIF1 PB"},
2160 	{"WSA RX_MIX1 MUX", "AIF1_PB", "WSA AIF1 PB"},
2161 
2162 	{"WSA RX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2163 	{"WSA RX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2164 	{"WSA RX_MIX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2165 	{"WSA RX_MIX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"},
2166 
2167 	{"WSA RX0", NULL, "WSA RX0 MUX"},
2168 	{"WSA RX1", NULL, "WSA RX1 MUX"},
2169 	{"WSA RX_MIX0", NULL, "WSA RX_MIX0 MUX"},
2170 	{"WSA RX_MIX1", NULL, "WSA RX_MIX1 MUX"},
2171 
2172 	{"WSA RX0", NULL, "WSA_RX0_CLK"},
2173 	{"WSA RX1", NULL, "WSA_RX1_CLK"},
2174 	{"WSA RX_MIX0", NULL, "WSA_RX_MIX0_CLK"},
2175 	{"WSA RX_MIX1", NULL, "WSA_RX_MIX1_CLK"},
2176 
2177 	{"WSA_RX0 INP0", "RX0", "WSA RX0"},
2178 	{"WSA_RX0 INP0", "RX1", "WSA RX1"},
2179 	{"WSA_RX0 INP0", "RX_MIX0", "WSA RX_MIX0"},
2180 	{"WSA_RX0 INP0", "RX_MIX1", "WSA RX_MIX1"},
2181 	{"WSA_RX0 INP0", "DEC0", "WSA_TX DEC0_INP"},
2182 	{"WSA_RX0 INP0", "DEC1", "WSA_TX DEC1_INP"},
2183 	{"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP0"},
2184 
2185 	{"WSA_RX0 INP1", "RX0", "WSA RX0"},
2186 	{"WSA_RX0 INP1", "RX1", "WSA RX1"},
2187 	{"WSA_RX0 INP1", "RX_MIX0", "WSA RX_MIX0"},
2188 	{"WSA_RX0 INP1", "RX_MIX1", "WSA RX_MIX1"},
2189 	{"WSA_RX0 INP1", "DEC0", "WSA_TX DEC0_INP"},
2190 	{"WSA_RX0 INP1", "DEC1", "WSA_TX DEC1_INP"},
2191 	{"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP1"},
2192 
2193 	{"WSA_RX0 INP2", "RX0", "WSA RX0"},
2194 	{"WSA_RX0 INP2", "RX1", "WSA RX1"},
2195 	{"WSA_RX0 INP2", "RX_MIX0", "WSA RX_MIX0"},
2196 	{"WSA_RX0 INP2", "RX_MIX1", "WSA RX_MIX1"},
2197 	{"WSA_RX0 INP2", "DEC0", "WSA_TX DEC0_INP"},
2198 	{"WSA_RX0 INP2", "DEC1", "WSA_TX DEC1_INP"},
2199 	{"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP2"},
2200 
2201 	{"WSA_RX0 MIX INP", "RX0", "WSA RX0"},
2202 	{"WSA_RX0 MIX INP", "RX1", "WSA RX1"},
2203 	{"WSA_RX0 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
2204 	{"WSA_RX0 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
2205 	{"WSA_RX INT0 SEC MIX", NULL, "WSA_RX0 MIX INP"},
2206 
2207 	{"WSA_RX INT0 SEC MIX", NULL, "WSA_RX INT0 MIX"},
2208 	{"WSA_RX INT0 INTERP", NULL, "WSA_RX INT0 SEC MIX"},
2209 	{"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"},
2210 	{"WSA_RX INT0 INTERP", NULL, "WSA_RX0 INT0 SIDETONE MIX"},
2211 	{"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 INTERP"},
2212 
2213 	{"WSA_SPK1 OUT", NULL, "WSA_RX INT0 CHAIN"},
2214 	{"WSA_SPK1 OUT", NULL, "WSA_MCLK"},
2215 
2216 	{"WSA_RX1 INP0", "RX0", "WSA RX0"},
2217 	{"WSA_RX1 INP0", "RX1", "WSA RX1"},
2218 	{"WSA_RX1 INP0", "RX_MIX0", "WSA RX_MIX0"},
2219 	{"WSA_RX1 INP0", "RX_MIX1", "WSA RX_MIX1"},
2220 	{"WSA_RX1 INP0", "DEC0", "WSA_TX DEC0_INP"},
2221 	{"WSA_RX1 INP0", "DEC1", "WSA_TX DEC1_INP"},
2222 	{"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP0"},
2223 
2224 	{"WSA_RX1 INP1", "RX0", "WSA RX0"},
2225 	{"WSA_RX1 INP1", "RX1", "WSA RX1"},
2226 	{"WSA_RX1 INP1", "RX_MIX0", "WSA RX_MIX0"},
2227 	{"WSA_RX1 INP1", "RX_MIX1", "WSA RX_MIX1"},
2228 	{"WSA_RX1 INP1", "DEC0", "WSA_TX DEC0_INP"},
2229 	{"WSA_RX1 INP1", "DEC1", "WSA_TX DEC1_INP"},
2230 	{"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP1"},
2231 
2232 	{"WSA_RX1 INP2", "RX0", "WSA RX0"},
2233 	{"WSA_RX1 INP2", "RX1", "WSA RX1"},
2234 	{"WSA_RX1 INP2", "RX_MIX0", "WSA RX_MIX0"},
2235 	{"WSA_RX1 INP2", "RX_MIX1", "WSA RX_MIX1"},
2236 	{"WSA_RX1 INP2", "DEC0", "WSA_TX DEC0_INP"},
2237 	{"WSA_RX1 INP2", "DEC1", "WSA_TX DEC1_INP"},
2238 	{"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP2"},
2239 
2240 	{"WSA_RX1 MIX INP", "RX0", "WSA RX0"},
2241 	{"WSA_RX1 MIX INP", "RX1", "WSA RX1"},
2242 	{"WSA_RX1 MIX INP", "RX_MIX0", "WSA RX_MIX0"},
2243 	{"WSA_RX1 MIX INP", "RX_MIX1", "WSA RX_MIX1"},
2244 	{"WSA_RX INT1 SEC MIX", NULL, "WSA_RX1 MIX INP"},
2245 
2246 	{"WSA_RX INT1 SEC MIX", NULL, "WSA_RX INT1 MIX"},
2247 	{"WSA_RX INT1 INTERP", NULL, "WSA_RX INT1 SEC MIX"},
2248 
2249 	{"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 INTERP"},
2250 	{"WSA_SPK2 OUT", NULL, "WSA_RX INT1 CHAIN"},
2251 	{"WSA_SPK2 OUT", NULL, "WSA_MCLK"},
2252 };
2253 
2254 static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable)
2255 {
2256 	struct regmap *regmap = wsa->regmap;
2257 
2258 	if (enable) {
2259 		wsa_macro_mclk_enable(wsa, true);
2260 
2261 		/* reset swr ip */
2262 		if (wsa->reset_swr)
2263 			regmap_update_bits(regmap,
2264 					   CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2265 					   CDC_WSA_SWR_RST_EN_MASK,
2266 					   CDC_WSA_SWR_RST_ENABLE);
2267 
2268 		regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2269 				   CDC_WSA_SWR_CLK_EN_MASK,
2270 				   CDC_WSA_SWR_CLK_ENABLE);
2271 
2272 		/* Bring out of reset */
2273 		if (wsa->reset_swr)
2274 			regmap_update_bits(regmap,
2275 					   CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2276 					   CDC_WSA_SWR_RST_EN_MASK,
2277 					   CDC_WSA_SWR_RST_DISABLE);
2278 		wsa->reset_swr = false;
2279 	} else {
2280 		regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL,
2281 				   CDC_WSA_SWR_CLK_EN_MASK, 0);
2282 		wsa_macro_mclk_enable(wsa, false);
2283 	}
2284 
2285 	return 0;
2286 }
2287 
2288 static int wsa_macro_component_probe(struct snd_soc_component *comp)
2289 {
2290 	struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp);
2291 
2292 	snd_soc_component_init_regmap(comp, wsa->regmap);
2293 
2294 	wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB;
2295 
2296 	/* set SPKR rate to FS_2P4_3P072 */
2297 	snd_soc_component_update_bits(comp, CDC_WSA_RX0_RX_PATH_CFG1,
2298 				CDC_WSA_RX_PATH_SPKR_RATE_MASK,
2299 				CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);
2300 
2301 	snd_soc_component_update_bits(comp, CDC_WSA_RX1_RX_PATH_CFG1,
2302 				CDC_WSA_RX_PATH_SPKR_RATE_MASK,
2303 				CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072);
2304 
2305 	wsa_macro_set_spkr_mode(comp, WSA_MACRO_SPKR_MODE_1);
2306 
2307 	return 0;
2308 }
2309 
2310 static int swclk_gate_enable(struct clk_hw *hw)
2311 {
2312 	return wsa_swrm_clock(to_wsa_macro(hw), true);
2313 }
2314 
2315 static void swclk_gate_disable(struct clk_hw *hw)
2316 {
2317 	wsa_swrm_clock(to_wsa_macro(hw), false);
2318 }
2319 
2320 static int swclk_gate_is_enabled(struct clk_hw *hw)
2321 {
2322 	struct wsa_macro *wsa = to_wsa_macro(hw);
2323 	int ret, val;
2324 
2325 	regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val);
2326 	ret = val & BIT(0);
2327 
2328 	return ret;
2329 }
2330 
2331 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2332 				       unsigned long parent_rate)
2333 {
2334 	return parent_rate / 2;
2335 }
2336 
2337 static const struct clk_ops swclk_gate_ops = {
2338 	.prepare = swclk_gate_enable,
2339 	.unprepare = swclk_gate_disable,
2340 	.is_enabled = swclk_gate_is_enabled,
2341 	.recalc_rate = swclk_recalc_rate,
2342 };
2343 
2344 static int wsa_macro_register_mclk_output(struct wsa_macro *wsa)
2345 {
2346 	struct device *dev = wsa->dev;
2347 	const char *parent_clk_name;
2348 	const char *clk_name = "mclk";
2349 	struct clk_hw *hw;
2350 	struct clk_init_data init;
2351 	int ret;
2352 
2353 	parent_clk_name = __clk_get_name(wsa->clks[2].clk);
2354 
2355 	init.name = clk_name;
2356 	init.ops = &swclk_gate_ops;
2357 	init.flags = 0;
2358 	init.parent_names = &parent_clk_name;
2359 	init.num_parents = 1;
2360 	wsa->hw.init = &init;
2361 	hw = &wsa->hw;
2362 	ret = clk_hw_register(wsa->dev, hw);
2363 	if (ret)
2364 		return ret;
2365 
2366 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
2367 }
2368 
2369 static const struct snd_soc_component_driver wsa_macro_component_drv = {
2370 	.name = "WSA MACRO",
2371 	.probe = wsa_macro_component_probe,
2372 	.controls = wsa_macro_snd_controls,
2373 	.num_controls = ARRAY_SIZE(wsa_macro_snd_controls),
2374 	.dapm_widgets = wsa_macro_dapm_widgets,
2375 	.num_dapm_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets),
2376 	.dapm_routes = wsa_audio_map,
2377 	.num_dapm_routes = ARRAY_SIZE(wsa_audio_map),
2378 };
2379 
2380 static int wsa_macro_probe(struct platform_device *pdev)
2381 {
2382 	struct device *dev = &pdev->dev;
2383 	struct wsa_macro *wsa;
2384 	void __iomem *base;
2385 	int ret;
2386 
2387 	wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL);
2388 	if (!wsa)
2389 		return -ENOMEM;
2390 
2391 	wsa->clks[0].id = "macro";
2392 	wsa->clks[1].id = "dcodec";
2393 	wsa->clks[2].id = "mclk";
2394 	wsa->clks[3].id = "npl";
2395 	wsa->clks[4].id = "fsgen";
2396 
2397 	ret = devm_clk_bulk_get(dev, WSA_NUM_CLKS_MAX, wsa->clks);
2398 	if (ret) {
2399 		dev_err(dev, "Error getting WSA Clocks (%d)\n", ret);
2400 		return ret;
2401 	}
2402 
2403 	base = devm_platform_ioremap_resource(pdev, 0);
2404 	if (IS_ERR(base))
2405 		return PTR_ERR(base);
2406 
2407 	wsa->regmap = devm_regmap_init_mmio(dev, base, &wsa_regmap_config);
2408 
2409 	dev_set_drvdata(dev, wsa);
2410 
2411 	wsa->reset_swr = true;
2412 	wsa->dev = dev;
2413 
2414 	/* set MCLK and NPL rates */
2415 	clk_set_rate(wsa->clks[2].clk, WSA_MACRO_MCLK_FREQ);
2416 	clk_set_rate(wsa->clks[3].clk, WSA_MACRO_MCLK_FREQ);
2417 
2418 	ret = clk_bulk_prepare_enable(WSA_NUM_CLKS_MAX, wsa->clks);
2419 	if (ret)
2420 		return ret;
2421 
2422 	wsa_macro_register_mclk_output(wsa);
2423 
2424 	ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv,
2425 					      wsa_macro_dai,
2426 					      ARRAY_SIZE(wsa_macro_dai));
2427 	if (ret)
2428 		goto err;
2429 
2430 	return ret;
2431 err:
2432 	clk_bulk_disable_unprepare(WSA_NUM_CLKS_MAX, wsa->clks);
2433 
2434 	return ret;
2435 
2436 }
2437 
2438 static int wsa_macro_remove(struct platform_device *pdev)
2439 {
2440 	struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev);
2441 
2442 	clk_bulk_disable_unprepare(WSA_NUM_CLKS_MAX, wsa->clks);
2443 
2444 	return 0;
2445 }
2446 
2447 static const struct of_device_id wsa_macro_dt_match[] = {
2448 	{.compatible = "qcom,sm8250-lpass-wsa-macro"},
2449 	{}
2450 };
2451 MODULE_DEVICE_TABLE(of, wsa_macro_dt_match);
2452 
2453 static struct platform_driver wsa_macro_driver = {
2454 	.driver = {
2455 		.name = "wsa_macro",
2456 		.of_match_table = wsa_macro_dt_match,
2457 	},
2458 	.probe = wsa_macro_probe,
2459 	.remove = wsa_macro_remove,
2460 };
2461 
2462 module_platform_driver(wsa_macro_driver);
2463 MODULE_DESCRIPTION("WSA macro driver");
2464 MODULE_LICENSE("GPL");
2465