1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/module.h> 5 #include <linux/init.h> 6 #include <linux/io.h> 7 #include <linux/platform_device.h> 8 #include <linux/clk.h> 9 #include <linux/of_clk.h> 10 #include <linux/clk-provider.h> 11 #include <sound/soc.h> 12 #include <sound/soc-dapm.h> 13 #include <linux/of_platform.h> 14 #include <sound/tlv.h> 15 #include "lpass-wsa-macro.h" 16 17 #define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 18 #define CDC_WSA_MCLK_EN_MASK BIT(0) 19 #define CDC_WSA_MCLK_ENABLE BIT(0) 20 #define CDC_WSA_MCLK_DISABLE 0 21 #define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 22 #define CDC_WSA_FS_CNT_EN_MASK BIT(0) 23 #define CDC_WSA_FS_CNT_ENABLE BIT(0) 24 #define CDC_WSA_FS_CNT_DISABLE 0 25 #define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL (0x0008) 26 #define CDC_WSA_SWR_CLK_EN_MASK BIT(0) 27 #define CDC_WSA_SWR_CLK_ENABLE BIT(0) 28 #define CDC_WSA_SWR_RST_EN_MASK BIT(1) 29 #define CDC_WSA_SWR_RST_ENABLE BIT(1) 30 #define CDC_WSA_SWR_RST_DISABLE 0 31 #define CDC_WSA_TOP_TOP_CFG0 (0x0080) 32 #define CDC_WSA_TOP_TOP_CFG1 (0x0084) 33 #define CDC_WSA_TOP_FREQ_MCLK (0x0088) 34 #define CDC_WSA_TOP_DEBUG_BUS_SEL (0x008C) 35 #define CDC_WSA_TOP_DEBUG_EN0 (0x0090) 36 #define CDC_WSA_TOP_DEBUG_EN1 (0x0094) 37 #define CDC_WSA_TOP_DEBUG_DSM_LB (0x0098) 38 #define CDC_WSA_TOP_RX_I2S_CTL (0x009C) 39 #define CDC_WSA_TOP_TX_I2S_CTL (0x00A0) 40 #define CDC_WSA_TOP_I2S_CLK (0x00A4) 41 #define CDC_WSA_TOP_I2S_RESET (0x00A8) 42 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 (0x0100) 43 #define CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(2, 0) 44 #define CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(5, 3) 45 #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 (0x0104) 46 #define CDC_WSA_RX_INTX_2_SEL_MASK GENMASK(2, 0) 47 #define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(5, 3) 48 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 (0x0108) 49 #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 (0x010C) 50 #define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 (0x0110) 51 #define CDC_WSA_RX_MIX_TX1_SEL_MASK GENMASK(5, 3) 52 #define CDC_WSA_RX_MIX_TX1_SEL_SHFT 3 53 #define CDC_WSA_RX_MIX_TX0_SEL_MASK GENMASK(2, 0) 54 #define CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (0x0114) 55 #define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (0x0118) 56 #define CDC_WSA_TX0_SPKR_PROT_PATH_CTL (0x0244) 57 #define CDC_WSA_TX_SPKR_PROT_RESET_MASK BIT(5) 58 #define CDC_WSA_TX_SPKR_PROT_RESET BIT(5) 59 #define CDC_WSA_TX_SPKR_PROT_NO_RESET 0 60 #define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK BIT(4) 61 #define CDC_WSA_TX_SPKR_PROT_CLK_ENABLE BIT(4) 62 #define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0 63 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0) 64 #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K 0 65 #define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (0x0248) 66 #define CDC_WSA_TX1_SPKR_PROT_PATH_CTL (0x0264) 67 #define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (0x0268) 68 #define CDC_WSA_TX2_SPKR_PROT_PATH_CTL (0x0284) 69 #define CDC_WSA_TX2_SPKR_PROT_PATH_CFG0 (0x0288) 70 #define CDC_WSA_TX3_SPKR_PROT_PATH_CTL (0x02A4) 71 #define CDC_WSA_TX3_SPKR_PROT_PATH_CFG0 (0x02A8) 72 #define CDC_WSA_INTR_CTRL_CFG (0x0340) 73 #define CDC_WSA_INTR_CTRL_CLR_COMMIT (0x0344) 74 #define CDC_WSA_INTR_CTRL_PIN1_MASK0 (0x0360) 75 #define CDC_WSA_INTR_CTRL_PIN1_STATUS0 (0x0368) 76 #define CDC_WSA_INTR_CTRL_PIN1_CLEAR0 (0x0370) 77 #define CDC_WSA_INTR_CTRL_PIN2_MASK0 (0x0380) 78 #define CDC_WSA_INTR_CTRL_PIN2_STATUS0 (0x0388) 79 #define CDC_WSA_INTR_CTRL_PIN2_CLEAR0 (0x0390) 80 #define CDC_WSA_INTR_CTRL_LEVEL0 (0x03C0) 81 #define CDC_WSA_INTR_CTRL_BYPASS0 (0x03C8) 82 #define CDC_WSA_INTR_CTRL_SET0 (0x03D0) 83 #define CDC_WSA_RX0_RX_PATH_CTL (0x0400) 84 #define CDC_WSA_RX_PATH_CLK_EN_MASK BIT(5) 85 #define CDC_WSA_RX_PATH_CLK_ENABLE BIT(5) 86 #define CDC_WSA_RX_PATH_CLK_DISABLE 0 87 #define CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK BIT(4) 88 #define CDC_WSA_RX_PATH_PGA_MUTE_ENABLE BIT(4) 89 #define CDC_WSA_RX_PATH_PGA_MUTE_DISABLE 0 90 #define CDC_WSA_RX0_RX_PATH_CFG0 (0x0404) 91 #define CDC_WSA_RX_PATH_COMP_EN_MASK BIT(1) 92 #define CDC_WSA_RX_PATH_COMP_ENABLE BIT(1) 93 #define CDC_WSA_RX_PATH_HD2_EN_MASK BIT(2) 94 #define CDC_WSA_RX_PATH_HD2_ENABLE BIT(2) 95 #define CDC_WSA_RX_PATH_SPKR_RATE_MASK BIT(3) 96 #define CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072 BIT(3) 97 #define CDC_WSA_RX0_RX_PATH_CFG1 (0x0408) 98 #define CDC_WSA_RX_PATH_SMART_BST_EN_MASK BIT(0) 99 #define CDC_WSA_RX_PATH_SMART_BST_ENABLE BIT(0) 100 #define CDC_WSA_RX_PATH_SMART_BST_DISABLE 0 101 #define CDC_WSA_RX0_RX_PATH_CFG2 (0x040C) 102 #define CDC_WSA_RX0_RX_PATH_CFG3 (0x0410) 103 #define CDC_WSA_RX_DC_DCOEFF_MASK GENMASK(1, 0) 104 #define CDC_WSA_RX0_RX_VOL_CTL (0x0414) 105 #define CDC_WSA_RX0_RX_PATH_MIX_CTL (0x0418) 106 #define CDC_WSA_RX_PATH_MIX_CLK_EN_MASK BIT(5) 107 #define CDC_WSA_RX_PATH_MIX_CLK_ENABLE BIT(5) 108 #define CDC_WSA_RX_PATH_MIX_CLK_DISABLE 0 109 #define CDC_WSA_RX0_RX_PATH_MIX_CFG (0x041C) 110 #define CDC_WSA_RX0_RX_VOL_MIX_CTL (0x0420) 111 #define CDC_WSA_RX0_RX_PATH_SEC0 (0x0424) 112 #define CDC_WSA_RX0_RX_PATH_SEC1 (0x0428) 113 #define CDC_WSA_RX_PGA_HALF_DB_MASK BIT(0) 114 #define CDC_WSA_RX_PGA_HALF_DB_ENABLE BIT(0) 115 #define CDC_WSA_RX_PGA_HALF_DB_DISABLE 0 116 #define CDC_WSA_RX0_RX_PATH_SEC2 (0x042C) 117 #define CDC_WSA_RX0_RX_PATH_SEC3 (0x0430) 118 #define CDC_WSA_RX_PATH_HD2_SCALE_MASK GENMASK(1, 0) 119 #define CDC_WSA_RX_PATH_HD2_ALPHA_MASK GENMASK(5, 2) 120 #define CDC_WSA_RX0_RX_PATH_SEC5 (0x0438) 121 #define CDC_WSA_RX0_RX_PATH_SEC6 (0x043C) 122 #define CDC_WSA_RX0_RX_PATH_SEC7 (0x0440) 123 #define CDC_WSA_RX0_RX_PATH_MIX_SEC0 (0x0444) 124 #define CDC_WSA_RX0_RX_PATH_MIX_SEC1 (0x0448) 125 #define CDC_WSA_RX0_RX_PATH_DSMDEM_CTL (0x044C) 126 #define CDC_WSA_RX_DSMDEM_CLK_EN_MASK BIT(0) 127 #define CDC_WSA_RX_DSMDEM_CLK_ENABLE BIT(0) 128 #define CDC_WSA_RX1_RX_PATH_CTL (0x0480) 129 #define CDC_WSA_RX1_RX_PATH_CFG0 (0x0484) 130 #define CDC_WSA_RX1_RX_PATH_CFG1 (0x0488) 131 #define CDC_WSA_RX1_RX_PATH_CFG2 (0x048C) 132 #define CDC_WSA_RX1_RX_PATH_CFG3 (0x0490) 133 #define CDC_WSA_RX1_RX_VOL_CTL (0x0494) 134 #define CDC_WSA_RX1_RX_PATH_MIX_CTL (0x0498) 135 #define CDC_WSA_RX1_RX_PATH_MIX_CFG (0x049C) 136 #define CDC_WSA_RX1_RX_VOL_MIX_CTL (0x04A0) 137 #define CDC_WSA_RX1_RX_PATH_SEC0 (0x04A4) 138 #define CDC_WSA_RX1_RX_PATH_SEC1 (0x04A8) 139 #define CDC_WSA_RX1_RX_PATH_SEC2 (0x04AC) 140 #define CDC_WSA_RX1_RX_PATH_SEC3 (0x04B0) 141 #define CDC_WSA_RX1_RX_PATH_SEC5 (0x04B8) 142 #define CDC_WSA_RX1_RX_PATH_SEC6 (0x04BC) 143 #define CDC_WSA_RX1_RX_PATH_SEC7 (0x04C0) 144 #define CDC_WSA_RX1_RX_PATH_MIX_SEC0 (0x04C4) 145 #define CDC_WSA_RX1_RX_PATH_MIX_SEC1 (0x04C8) 146 #define CDC_WSA_RX1_RX_PATH_DSMDEM_CTL (0x04CC) 147 #define CDC_WSA_BOOST0_BOOST_PATH_CTL (0x0500) 148 #define CDC_WSA_BOOST_PATH_CLK_EN_MASK BIT(4) 149 #define CDC_WSA_BOOST_PATH_CLK_ENABLE BIT(4) 150 #define CDC_WSA_BOOST_PATH_CLK_DISABLE 0 151 #define CDC_WSA_BOOST0_BOOST_CTL (0x0504) 152 #define CDC_WSA_BOOST0_BOOST_CFG1 (0x0508) 153 #define CDC_WSA_BOOST0_BOOST_CFG2 (0x050C) 154 #define CDC_WSA_BOOST1_BOOST_PATH_CTL (0x0540) 155 #define CDC_WSA_BOOST1_BOOST_CTL (0x0544) 156 #define CDC_WSA_BOOST1_BOOST_CFG1 (0x0548) 157 #define CDC_WSA_BOOST1_BOOST_CFG2 (0x054C) 158 #define CDC_WSA_COMPANDER0_CTL0 (0x0580) 159 #define CDC_WSA_COMPANDER_CLK_EN_MASK BIT(0) 160 #define CDC_WSA_COMPANDER_CLK_ENABLE BIT(0) 161 #define CDC_WSA_COMPANDER_SOFT_RST_MASK BIT(1) 162 #define CDC_WSA_COMPANDER_SOFT_RST_ENABLE BIT(1) 163 #define CDC_WSA_COMPANDER_HALT_MASK BIT(2) 164 #define CDC_WSA_COMPANDER_HALT BIT(2) 165 #define CDC_WSA_COMPANDER0_CTL1 (0x0584) 166 #define CDC_WSA_COMPANDER0_CTL2 (0x0588) 167 #define CDC_WSA_COMPANDER0_CTL3 (0x058C) 168 #define CDC_WSA_COMPANDER0_CTL4 (0x0590) 169 #define CDC_WSA_COMPANDER0_CTL5 (0x0594) 170 #define CDC_WSA_COMPANDER0_CTL6 (0x0598) 171 #define CDC_WSA_COMPANDER0_CTL7 (0x059C) 172 #define CDC_WSA_COMPANDER1_CTL0 (0x05C0) 173 #define CDC_WSA_COMPANDER1_CTL1 (0x05C4) 174 #define CDC_WSA_COMPANDER1_CTL2 (0x05C8) 175 #define CDC_WSA_COMPANDER1_CTL3 (0x05CC) 176 #define CDC_WSA_COMPANDER1_CTL4 (0x05D0) 177 #define CDC_WSA_COMPANDER1_CTL5 (0x05D4) 178 #define CDC_WSA_COMPANDER1_CTL6 (0x05D8) 179 #define CDC_WSA_COMPANDER1_CTL7 (0x05DC) 180 #define CDC_WSA_SOFTCLIP0_CRC (0x0600) 181 #define CDC_WSA_SOFTCLIP_CLK_EN_MASK BIT(0) 182 #define CDC_WSA_SOFTCLIP_CLK_ENABLE BIT(0) 183 #define CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (0x0604) 184 #define CDC_WSA_SOFTCLIP_EN_MASK BIT(0) 185 #define CDC_WSA_SOFTCLIP_ENABLE BIT(0) 186 #define CDC_WSA_SOFTCLIP1_CRC (0x0640) 187 #define CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (0x0644) 188 #define CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL (0x0680) 189 #define CDC_WSA_EC_HQ_EC_CLK_EN_MASK BIT(0) 190 #define CDC_WSA_EC_HQ_EC_CLK_ENABLE BIT(0) 191 #define CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 (0x0684) 192 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK GENMASK(4, 1) 193 #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K BIT(3) 194 #define CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL (0x06C0) 195 #define CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 (0x06C4) 196 #define CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL (0x0700) 197 #define CDC_WSA_SPLINE_ASRC0_CTL0 (0x0704) 198 #define CDC_WSA_SPLINE_ASRC0_CTL1 (0x0708) 199 #define CDC_WSA_SPLINE_ASRC0_FIFO_CTL (0x070C) 200 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB (0x0710) 201 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB (0x0714) 202 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB (0x0718) 203 #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB (0x071C) 204 #define CDC_WSA_SPLINE_ASRC0_STATUS_FIFO (0x0720) 205 #define CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL (0x0740) 206 #define CDC_WSA_SPLINE_ASRC1_CTL0 (0x0744) 207 #define CDC_WSA_SPLINE_ASRC1_CTL1 (0x0748) 208 #define CDC_WSA_SPLINE_ASRC1_FIFO_CTL (0x074C) 209 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB (0x0750) 210 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB (0x0754) 211 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB (0x0758) 212 #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB (0x075C) 213 #define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO (0x0760) 214 #define WSA_MAX_OFFSET (0x0760) 215 216 #define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 217 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 218 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 219 #define WSA_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\ 220 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 221 #define WSA_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 222 SNDRV_PCM_FMTBIT_S24_LE |\ 223 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 224 225 #define WSA_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 226 SNDRV_PCM_RATE_48000) 227 #define WSA_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 228 SNDRV_PCM_FMTBIT_S24_LE |\ 229 SNDRV_PCM_FMTBIT_S24_3LE) 230 231 #define NUM_INTERPOLATORS 2 232 #define WSA_NUM_CLKS_MAX 5 233 #define WSA_MACRO_MCLK_FREQ 19200000 234 #define WSA_MACRO_MUX_INP_MASK2 0x38 235 #define WSA_MACRO_MUX_CFG_OFFSET 0x8 236 #define WSA_MACRO_MUX_CFG1_OFFSET 0x4 237 #define WSA_MACRO_RX_COMP_OFFSET 0x40 238 #define WSA_MACRO_RX_SOFTCLIP_OFFSET 0x40 239 #define WSA_MACRO_RX_PATH_OFFSET 0x80 240 #define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10 241 #define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C 242 #define WSA_MACRO_FS_RATE_MASK 0x0F 243 #define WSA_MACRO_EC_MIX_TX0_MASK 0x03 244 #define WSA_MACRO_EC_MIX_TX1_MASK 0x18 245 #define WSA_MACRO_MAX_DMA_CH_PER_PORT 0x2 246 247 enum { 248 WSA_MACRO_GAIN_OFFSET_M1P5_DB, 249 WSA_MACRO_GAIN_OFFSET_0_DB, 250 }; 251 enum { 252 WSA_MACRO_RX0 = 0, 253 WSA_MACRO_RX1, 254 WSA_MACRO_RX_MIX, 255 WSA_MACRO_RX_MIX0 = WSA_MACRO_RX_MIX, 256 WSA_MACRO_RX_MIX1, 257 WSA_MACRO_RX_MAX, 258 }; 259 260 enum { 261 WSA_MACRO_TX0 = 0, 262 WSA_MACRO_TX1, 263 WSA_MACRO_TX_MAX, 264 }; 265 266 enum { 267 WSA_MACRO_EC0_MUX = 0, 268 WSA_MACRO_EC1_MUX, 269 WSA_MACRO_EC_MUX_MAX, 270 }; 271 272 enum { 273 WSA_MACRO_COMP1, /* SPK_L */ 274 WSA_MACRO_COMP2, /* SPK_R */ 275 WSA_MACRO_COMP_MAX 276 }; 277 278 enum { 279 WSA_MACRO_SOFTCLIP0, /* RX0 */ 280 WSA_MACRO_SOFTCLIP1, /* RX1 */ 281 WSA_MACRO_SOFTCLIP_MAX 282 }; 283 284 enum { 285 INTn_1_INP_SEL_ZERO = 0, 286 INTn_1_INP_SEL_RX0, 287 INTn_1_INP_SEL_RX1, 288 INTn_1_INP_SEL_RX2, 289 INTn_1_INP_SEL_RX3, 290 INTn_1_INP_SEL_DEC0, 291 INTn_1_INP_SEL_DEC1, 292 }; 293 294 enum { 295 INTn_2_INP_SEL_ZERO = 0, 296 INTn_2_INP_SEL_RX0, 297 INTn_2_INP_SEL_RX1, 298 INTn_2_INP_SEL_RX2, 299 INTn_2_INP_SEL_RX3, 300 }; 301 302 struct interp_sample_rate { 303 int sample_rate; 304 int rate_val; 305 }; 306 307 static struct interp_sample_rate int_prim_sample_rate_val[] = { 308 {8000, 0x0}, /* 8K */ 309 {16000, 0x1}, /* 16K */ 310 {24000, -EINVAL},/* 24K */ 311 {32000, 0x3}, /* 32K */ 312 {48000, 0x4}, /* 48K */ 313 {96000, 0x5}, /* 96K */ 314 {192000, 0x6}, /* 192K */ 315 {384000, 0x7}, /* 384K */ 316 {44100, 0x8}, /* 44.1K */ 317 }; 318 319 static struct interp_sample_rate int_mix_sample_rate_val[] = { 320 {48000, 0x4}, /* 48K */ 321 {96000, 0x5}, /* 96K */ 322 {192000, 0x6}, /* 192K */ 323 }; 324 325 enum { 326 WSA_MACRO_AIF_INVALID = 0, 327 WSA_MACRO_AIF1_PB, 328 WSA_MACRO_AIF_MIX1_PB, 329 WSA_MACRO_AIF_VI, 330 WSA_MACRO_AIF_ECHO, 331 WSA_MACRO_MAX_DAIS, 332 }; 333 334 struct wsa_macro { 335 struct device *dev; 336 int comp_enabled[WSA_MACRO_COMP_MAX]; 337 int ec_hq[WSA_MACRO_RX1 + 1]; 338 u16 prim_int_users[WSA_MACRO_RX1 + 1]; 339 u16 wsa_mclk_users; 340 bool reset_swr; 341 unsigned long active_ch_mask[WSA_MACRO_MAX_DAIS]; 342 unsigned long active_ch_cnt[WSA_MACRO_MAX_DAIS]; 343 int rx_port_value[WSA_MACRO_RX_MAX]; 344 int ear_spkr_gain; 345 int spkr_gain_offset; 346 int spkr_mode; 347 int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX]; 348 int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX]; 349 struct regmap *regmap; 350 struct clk_bulk_data clks[WSA_NUM_CLKS_MAX]; 351 struct clk_hw hw; 352 }; 353 #define to_wsa_macro(_hw) container_of(_hw, struct wsa_macro, hw) 354 355 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 356 357 static const char *const rx_text[] = { 358 "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "DEC0", "DEC1" 359 }; 360 361 static const char *const rx_mix_text[] = { 362 "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1" 363 }; 364 365 static const char *const rx_mix_ec_text[] = { 366 "ZERO", "RX_MIX_TX0", "RX_MIX_TX1" 367 }; 368 369 static const char *const rx_mux_text[] = { 370 "ZERO", "AIF1_PB", "AIF_MIX1_PB" 371 }; 372 373 static const char *const rx_sidetone_mix_text[] = { 374 "ZERO", "SRC0" 375 }; 376 377 static const char * const wsa_macro_ear_spkr_pa_gain_text[] = { 378 "G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB", 379 "G_4_DB", "G_5_DB", "G_6_DB" 380 }; 381 382 static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum, 383 wsa_macro_ear_spkr_pa_gain_text); 384 385 /* RX INT0 */ 386 static const struct soc_enum rx0_prim_inp0_chain_enum = 387 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 388 0, 7, rx_text); 389 390 static const struct soc_enum rx0_prim_inp1_chain_enum = 391 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 392 3, 7, rx_text); 393 394 static const struct soc_enum rx0_prim_inp2_chain_enum = 395 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 396 3, 7, rx_text); 397 398 static const struct soc_enum rx0_mix_chain_enum = 399 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 400 0, 5, rx_mix_text); 401 402 static const struct soc_enum rx0_sidetone_mix_enum = 403 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text); 404 405 static const struct snd_kcontrol_new rx0_prim_inp0_mux = 406 SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum); 407 408 static const struct snd_kcontrol_new rx0_prim_inp1_mux = 409 SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum); 410 411 static const struct snd_kcontrol_new rx0_prim_inp2_mux = 412 SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum); 413 414 static const struct snd_kcontrol_new rx0_mix_mux = 415 SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum); 416 417 static const struct snd_kcontrol_new rx0_sidetone_mix_mux = 418 SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum); 419 420 /* RX INT1 */ 421 static const struct soc_enum rx1_prim_inp0_chain_enum = 422 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 423 0, 7, rx_text); 424 425 static const struct soc_enum rx1_prim_inp1_chain_enum = 426 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 427 3, 7, rx_text); 428 429 static const struct soc_enum rx1_prim_inp2_chain_enum = 430 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 431 3, 7, rx_text); 432 433 static const struct soc_enum rx1_mix_chain_enum = 434 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 435 0, 5, rx_mix_text); 436 437 static const struct snd_kcontrol_new rx1_prim_inp0_mux = 438 SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum); 439 440 static const struct snd_kcontrol_new rx1_prim_inp1_mux = 441 SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum); 442 443 static const struct snd_kcontrol_new rx1_prim_inp2_mux = 444 SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum); 445 446 static const struct snd_kcontrol_new rx1_mix_mux = 447 SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum); 448 449 static const struct soc_enum rx_mix_ec0_enum = 450 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 451 0, 3, rx_mix_ec_text); 452 453 static const struct soc_enum rx_mix_ec1_enum = 454 SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 455 3, 3, rx_mix_ec_text); 456 457 static const struct snd_kcontrol_new rx_mix_ec0_mux = 458 SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum); 459 460 static const struct snd_kcontrol_new rx_mix_ec1_mux = 461 SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum); 462 463 static const struct reg_default wsa_defaults[] = { 464 /* WSA Macro */ 465 { CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, 466 { CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, 467 { CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 468 { CDC_WSA_TOP_TOP_CFG0, 0x00}, 469 { CDC_WSA_TOP_TOP_CFG1, 0x00}, 470 { CDC_WSA_TOP_FREQ_MCLK, 0x00}, 471 { CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00}, 472 { CDC_WSA_TOP_DEBUG_EN0, 0x00}, 473 { CDC_WSA_TOP_DEBUG_EN1, 0x00}, 474 { CDC_WSA_TOP_DEBUG_DSM_LB, 0x88}, 475 { CDC_WSA_TOP_RX_I2S_CTL, 0x0C}, 476 { CDC_WSA_TOP_TX_I2S_CTL, 0x0C}, 477 { CDC_WSA_TOP_I2S_CLK, 0x02}, 478 { CDC_WSA_TOP_I2S_RESET, 0x00}, 479 { CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00}, 480 { CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00}, 481 { CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00}, 482 { CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00}, 483 { CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00}, 484 { CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00}, 485 { CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00}, 486 { CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02}, 487 { CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00}, 488 { CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02}, 489 { CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00}, 490 { CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02}, 491 { CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00}, 492 { CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02}, 493 { CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00}, 494 { CDC_WSA_INTR_CTRL_CFG, 0x00}, 495 { CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00}, 496 { CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF}, 497 { CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00}, 498 { CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00}, 499 { CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF}, 500 { CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00}, 501 { CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00}, 502 { CDC_WSA_INTR_CTRL_LEVEL0, 0x00}, 503 { CDC_WSA_INTR_CTRL_BYPASS0, 0x00}, 504 { CDC_WSA_INTR_CTRL_SET0, 0x00}, 505 { CDC_WSA_RX0_RX_PATH_CTL, 0x04}, 506 { CDC_WSA_RX0_RX_PATH_CFG0, 0x00}, 507 { CDC_WSA_RX0_RX_PATH_CFG1, 0x64}, 508 { CDC_WSA_RX0_RX_PATH_CFG2, 0x8F}, 509 { CDC_WSA_RX0_RX_PATH_CFG3, 0x00}, 510 { CDC_WSA_RX0_RX_VOL_CTL, 0x00}, 511 { CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04}, 512 { CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E}, 513 { CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00}, 514 { CDC_WSA_RX0_RX_PATH_SEC0, 0x04}, 515 { CDC_WSA_RX0_RX_PATH_SEC1, 0x08}, 516 { CDC_WSA_RX0_RX_PATH_SEC2, 0x00}, 517 { CDC_WSA_RX0_RX_PATH_SEC3, 0x00}, 518 { CDC_WSA_RX0_RX_PATH_SEC5, 0x00}, 519 { CDC_WSA_RX0_RX_PATH_SEC6, 0x00}, 520 { CDC_WSA_RX0_RX_PATH_SEC7, 0x00}, 521 { CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08}, 522 { CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00}, 523 { CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00}, 524 { CDC_WSA_RX1_RX_PATH_CFG0, 0x00}, 525 { CDC_WSA_RX1_RX_PATH_CFG1, 0x64}, 526 { CDC_WSA_RX1_RX_PATH_CFG2, 0x8F}, 527 { CDC_WSA_RX1_RX_PATH_CFG3, 0x00}, 528 { CDC_WSA_RX1_RX_VOL_CTL, 0x00}, 529 { CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04}, 530 { CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E}, 531 { CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00}, 532 { CDC_WSA_RX1_RX_PATH_SEC0, 0x04}, 533 { CDC_WSA_RX1_RX_PATH_SEC1, 0x08}, 534 { CDC_WSA_RX1_RX_PATH_SEC2, 0x00}, 535 { CDC_WSA_RX1_RX_PATH_SEC3, 0x00}, 536 { CDC_WSA_RX1_RX_PATH_SEC5, 0x00}, 537 { CDC_WSA_RX1_RX_PATH_SEC6, 0x00}, 538 { CDC_WSA_RX1_RX_PATH_SEC7, 0x00}, 539 { CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08}, 540 { CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00}, 541 { CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00}, 542 { CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00}, 543 { CDC_WSA_BOOST0_BOOST_CTL, 0xD0}, 544 { CDC_WSA_BOOST0_BOOST_CFG1, 0x89}, 545 { CDC_WSA_BOOST0_BOOST_CFG2, 0x04}, 546 { CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00}, 547 { CDC_WSA_BOOST1_BOOST_CTL, 0xD0}, 548 { CDC_WSA_BOOST1_BOOST_CFG1, 0x89}, 549 { CDC_WSA_BOOST1_BOOST_CFG2, 0x04}, 550 { CDC_WSA_COMPANDER0_CTL0, 0x60}, 551 { CDC_WSA_COMPANDER0_CTL1, 0xDB}, 552 { CDC_WSA_COMPANDER0_CTL2, 0xFF}, 553 { CDC_WSA_COMPANDER0_CTL3, 0x35}, 554 { CDC_WSA_COMPANDER0_CTL4, 0xFF}, 555 { CDC_WSA_COMPANDER0_CTL5, 0x00}, 556 { CDC_WSA_COMPANDER0_CTL6, 0x01}, 557 { CDC_WSA_COMPANDER0_CTL7, 0x28}, 558 { CDC_WSA_COMPANDER1_CTL0, 0x60}, 559 { CDC_WSA_COMPANDER1_CTL1, 0xDB}, 560 { CDC_WSA_COMPANDER1_CTL2, 0xFF}, 561 { CDC_WSA_COMPANDER1_CTL3, 0x35}, 562 { CDC_WSA_COMPANDER1_CTL4, 0xFF}, 563 { CDC_WSA_COMPANDER1_CTL5, 0x00}, 564 { CDC_WSA_COMPANDER1_CTL6, 0x01}, 565 { CDC_WSA_COMPANDER1_CTL7, 0x28}, 566 { CDC_WSA_SOFTCLIP0_CRC, 0x00}, 567 { CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38}, 568 { CDC_WSA_SOFTCLIP1_CRC, 0x00}, 569 { CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38}, 570 { CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00}, 571 { CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01}, 572 { CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00}, 573 { CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01}, 574 { CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00}, 575 { CDC_WSA_SPLINE_ASRC0_CTL0, 0x00}, 576 { CDC_WSA_SPLINE_ASRC0_CTL1, 0x00}, 577 { CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8}, 578 { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00}, 579 { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00}, 580 { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00}, 581 { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00}, 582 { CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00}, 583 { CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00}, 584 { CDC_WSA_SPLINE_ASRC1_CTL0, 0x00}, 585 { CDC_WSA_SPLINE_ASRC1_CTL1, 0x00}, 586 { CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8}, 587 { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00}, 588 { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00}, 589 { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00}, 590 { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00}, 591 { CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00}, 592 }; 593 594 static bool wsa_is_wronly_register(struct device *dev, 595 unsigned int reg) 596 { 597 switch (reg) { 598 case CDC_WSA_INTR_CTRL_CLR_COMMIT: 599 case CDC_WSA_INTR_CTRL_PIN1_CLEAR0: 600 case CDC_WSA_INTR_CTRL_PIN2_CLEAR0: 601 return true; 602 } 603 604 return false; 605 } 606 607 static bool wsa_is_rw_register(struct device *dev, unsigned int reg) 608 { 609 switch (reg) { 610 case CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL: 611 case CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL: 612 case CDC_WSA_CLK_RST_CTRL_SWR_CONTROL: 613 case CDC_WSA_TOP_TOP_CFG0: 614 case CDC_WSA_TOP_TOP_CFG1: 615 case CDC_WSA_TOP_FREQ_MCLK: 616 case CDC_WSA_TOP_DEBUG_BUS_SEL: 617 case CDC_WSA_TOP_DEBUG_EN0: 618 case CDC_WSA_TOP_DEBUG_EN1: 619 case CDC_WSA_TOP_DEBUG_DSM_LB: 620 case CDC_WSA_TOP_RX_I2S_CTL: 621 case CDC_WSA_TOP_TX_I2S_CTL: 622 case CDC_WSA_TOP_I2S_CLK: 623 case CDC_WSA_TOP_I2S_RESET: 624 case CDC_WSA_RX_INP_MUX_RX_INT0_CFG0: 625 case CDC_WSA_RX_INP_MUX_RX_INT0_CFG1: 626 case CDC_WSA_RX_INP_MUX_RX_INT1_CFG0: 627 case CDC_WSA_RX_INP_MUX_RX_INT1_CFG1: 628 case CDC_WSA_RX_INP_MUX_RX_MIX_CFG0: 629 case CDC_WSA_RX_INP_MUX_RX_EC_CFG0: 630 case CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0: 631 case CDC_WSA_TX0_SPKR_PROT_PATH_CTL: 632 case CDC_WSA_TX0_SPKR_PROT_PATH_CFG0: 633 case CDC_WSA_TX1_SPKR_PROT_PATH_CTL: 634 case CDC_WSA_TX1_SPKR_PROT_PATH_CFG0: 635 case CDC_WSA_TX2_SPKR_PROT_PATH_CTL: 636 case CDC_WSA_TX2_SPKR_PROT_PATH_CFG0: 637 case CDC_WSA_TX3_SPKR_PROT_PATH_CTL: 638 case CDC_WSA_TX3_SPKR_PROT_PATH_CFG0: 639 case CDC_WSA_INTR_CTRL_CFG: 640 case CDC_WSA_INTR_CTRL_PIN1_MASK0: 641 case CDC_WSA_INTR_CTRL_PIN2_MASK0: 642 case CDC_WSA_INTR_CTRL_LEVEL0: 643 case CDC_WSA_INTR_CTRL_BYPASS0: 644 case CDC_WSA_INTR_CTRL_SET0: 645 case CDC_WSA_RX0_RX_PATH_CTL: 646 case CDC_WSA_RX0_RX_PATH_CFG0: 647 case CDC_WSA_RX0_RX_PATH_CFG1: 648 case CDC_WSA_RX0_RX_PATH_CFG2: 649 case CDC_WSA_RX0_RX_PATH_CFG3: 650 case CDC_WSA_RX0_RX_VOL_CTL: 651 case CDC_WSA_RX0_RX_PATH_MIX_CTL: 652 case CDC_WSA_RX0_RX_PATH_MIX_CFG: 653 case CDC_WSA_RX0_RX_VOL_MIX_CTL: 654 case CDC_WSA_RX0_RX_PATH_SEC0: 655 case CDC_WSA_RX0_RX_PATH_SEC1: 656 case CDC_WSA_RX0_RX_PATH_SEC2: 657 case CDC_WSA_RX0_RX_PATH_SEC3: 658 case CDC_WSA_RX0_RX_PATH_SEC5: 659 case CDC_WSA_RX0_RX_PATH_SEC6: 660 case CDC_WSA_RX0_RX_PATH_SEC7: 661 case CDC_WSA_RX0_RX_PATH_MIX_SEC0: 662 case CDC_WSA_RX0_RX_PATH_MIX_SEC1: 663 case CDC_WSA_RX0_RX_PATH_DSMDEM_CTL: 664 case CDC_WSA_RX1_RX_PATH_CTL: 665 case CDC_WSA_RX1_RX_PATH_CFG0: 666 case CDC_WSA_RX1_RX_PATH_CFG1: 667 case CDC_WSA_RX1_RX_PATH_CFG2: 668 case CDC_WSA_RX1_RX_PATH_CFG3: 669 case CDC_WSA_RX1_RX_VOL_CTL: 670 case CDC_WSA_RX1_RX_PATH_MIX_CTL: 671 case CDC_WSA_RX1_RX_PATH_MIX_CFG: 672 case CDC_WSA_RX1_RX_VOL_MIX_CTL: 673 case CDC_WSA_RX1_RX_PATH_SEC0: 674 case CDC_WSA_RX1_RX_PATH_SEC1: 675 case CDC_WSA_RX1_RX_PATH_SEC2: 676 case CDC_WSA_RX1_RX_PATH_SEC3: 677 case CDC_WSA_RX1_RX_PATH_SEC5: 678 case CDC_WSA_RX1_RX_PATH_SEC6: 679 case CDC_WSA_RX1_RX_PATH_SEC7: 680 case CDC_WSA_RX1_RX_PATH_MIX_SEC0: 681 case CDC_WSA_RX1_RX_PATH_MIX_SEC1: 682 case CDC_WSA_RX1_RX_PATH_DSMDEM_CTL: 683 case CDC_WSA_BOOST0_BOOST_PATH_CTL: 684 case CDC_WSA_BOOST0_BOOST_CTL: 685 case CDC_WSA_BOOST0_BOOST_CFG1: 686 case CDC_WSA_BOOST0_BOOST_CFG2: 687 case CDC_WSA_BOOST1_BOOST_PATH_CTL: 688 case CDC_WSA_BOOST1_BOOST_CTL: 689 case CDC_WSA_BOOST1_BOOST_CFG1: 690 case CDC_WSA_BOOST1_BOOST_CFG2: 691 case CDC_WSA_COMPANDER0_CTL0: 692 case CDC_WSA_COMPANDER0_CTL1: 693 case CDC_WSA_COMPANDER0_CTL2: 694 case CDC_WSA_COMPANDER0_CTL3: 695 case CDC_WSA_COMPANDER0_CTL4: 696 case CDC_WSA_COMPANDER0_CTL5: 697 case CDC_WSA_COMPANDER0_CTL7: 698 case CDC_WSA_COMPANDER1_CTL0: 699 case CDC_WSA_COMPANDER1_CTL1: 700 case CDC_WSA_COMPANDER1_CTL2: 701 case CDC_WSA_COMPANDER1_CTL3: 702 case CDC_WSA_COMPANDER1_CTL4: 703 case CDC_WSA_COMPANDER1_CTL5: 704 case CDC_WSA_COMPANDER1_CTL7: 705 case CDC_WSA_SOFTCLIP0_CRC: 706 case CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL: 707 case CDC_WSA_SOFTCLIP1_CRC: 708 case CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL: 709 case CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL: 710 case CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0: 711 case CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL: 712 case CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0: 713 case CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL: 714 case CDC_WSA_SPLINE_ASRC0_CTL0: 715 case CDC_WSA_SPLINE_ASRC0_CTL1: 716 case CDC_WSA_SPLINE_ASRC0_FIFO_CTL: 717 case CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL: 718 case CDC_WSA_SPLINE_ASRC1_CTL0: 719 case CDC_WSA_SPLINE_ASRC1_CTL1: 720 case CDC_WSA_SPLINE_ASRC1_FIFO_CTL: 721 return true; 722 } 723 724 return false; 725 } 726 727 static bool wsa_is_writeable_register(struct device *dev, unsigned int reg) 728 { 729 bool ret; 730 731 ret = wsa_is_rw_register(dev, reg); 732 if (!ret) 733 return wsa_is_wronly_register(dev, reg); 734 735 return ret; 736 } 737 738 static bool wsa_is_readable_register(struct device *dev, unsigned int reg) 739 { 740 switch (reg) { 741 case CDC_WSA_INTR_CTRL_CLR_COMMIT: 742 case CDC_WSA_INTR_CTRL_PIN1_CLEAR0: 743 case CDC_WSA_INTR_CTRL_PIN2_CLEAR0: 744 case CDC_WSA_INTR_CTRL_PIN1_STATUS0: 745 case CDC_WSA_INTR_CTRL_PIN2_STATUS0: 746 case CDC_WSA_COMPANDER0_CTL6: 747 case CDC_WSA_COMPANDER1_CTL6: 748 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: 749 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: 750 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: 751 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB: 752 case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO: 753 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB: 754 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB: 755 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB: 756 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB: 757 case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO: 758 return true; 759 } 760 761 return wsa_is_rw_register(dev, reg); 762 } 763 764 static bool wsa_is_volatile_register(struct device *dev, unsigned int reg) 765 { 766 /* Update volatile list for rx/tx macros */ 767 switch (reg) { 768 case CDC_WSA_INTR_CTRL_PIN1_STATUS0: 769 case CDC_WSA_INTR_CTRL_PIN2_STATUS0: 770 case CDC_WSA_COMPANDER0_CTL6: 771 case CDC_WSA_COMPANDER1_CTL6: 772 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: 773 case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: 774 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: 775 case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB: 776 case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO: 777 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB: 778 case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB: 779 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB: 780 case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB: 781 case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO: 782 return true; 783 } 784 return false; 785 } 786 787 static const struct regmap_config wsa_regmap_config = { 788 .name = "wsa_macro", 789 .reg_bits = 16, 790 .val_bits = 32, /* 8 but with 32 bit read/write */ 791 .reg_stride = 4, 792 .cache_type = REGCACHE_FLAT, 793 .reg_defaults = wsa_defaults, 794 .num_reg_defaults = ARRAY_SIZE(wsa_defaults), 795 .max_register = WSA_MAX_OFFSET, 796 .writeable_reg = wsa_is_writeable_register, 797 .volatile_reg = wsa_is_volatile_register, 798 .readable_reg = wsa_is_readable_register, 799 }; 800 801 /** 802 * wsa_macro_set_spkr_mode - Configures speaker compander and smartboost 803 * settings based on speaker mode. 804 * 805 * @component: codec instance 806 * @mode: Indicates speaker configuration mode. 807 * 808 * Returns 0 on success or -EINVAL on error. 809 */ 810 int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode) 811 { 812 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 813 814 wsa->spkr_mode = mode; 815 816 switch (mode) { 817 case WSA_MACRO_SPKR_MODE_1: 818 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00); 819 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00); 820 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00); 821 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00); 822 snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44); 823 snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44); 824 break; 825 default: 826 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80); 827 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80); 828 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01); 829 snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01); 830 snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58); 831 snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58); 832 break; 833 } 834 return 0; 835 } 836 EXPORT_SYMBOL(wsa_macro_set_spkr_mode); 837 838 static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, 839 u8 int_prim_fs_rate_reg_val, 840 u32 sample_rate) 841 { 842 u8 int_1_mix1_inp; 843 u32 j, port; 844 u16 int_mux_cfg0, int_mux_cfg1; 845 u16 int_fs_reg; 846 u8 inp0_sel, inp1_sel, inp2_sel; 847 struct snd_soc_component *component = dai->component; 848 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 849 850 for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) { 851 int_1_mix1_inp = port; 852 if ((int_1_mix1_inp < WSA_MACRO_RX0) || (int_1_mix1_inp > WSA_MACRO_RX_MIX1)) { 853 dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n", 854 __func__, dai->id); 855 return -EINVAL; 856 } 857 858 int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0; 859 860 /* 861 * Loop through all interpolator MUX inputs and find out 862 * to which interpolator input, the cdc_dma rx port 863 * is connected 864 */ 865 for (j = 0; j < NUM_INTERPOLATORS; j++) { 866 int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET; 867 inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0, 868 CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK); 869 inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0, 870 CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK); 871 inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1, 872 CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK); 873 874 if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 875 (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 876 (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) { 877 int_fs_reg = CDC_WSA_RX0_RX_PATH_CTL + 878 WSA_MACRO_RX_PATH_OFFSET * j; 879 /* sample_rate is in Hz */ 880 snd_soc_component_update_bits(component, int_fs_reg, 881 WSA_MACRO_FS_RATE_MASK, 882 int_prim_fs_rate_reg_val); 883 } 884 int_mux_cfg0 += WSA_MACRO_MUX_CFG_OFFSET; 885 } 886 } 887 888 return 0; 889 } 890 891 static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, 892 u8 int_mix_fs_rate_reg_val, 893 u32 sample_rate) 894 { 895 u8 int_2_inp; 896 u32 j, port; 897 u16 int_mux_cfg1, int_fs_reg; 898 u8 int_mux_cfg1_val; 899 struct snd_soc_component *component = dai->component; 900 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 901 902 for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) { 903 int_2_inp = port; 904 if ((int_2_inp < WSA_MACRO_RX0) || (int_2_inp > WSA_MACRO_RX_MIX1)) { 905 dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n", 906 __func__, dai->id); 907 return -EINVAL; 908 } 909 910 int_mux_cfg1 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG1; 911 for (j = 0; j < NUM_INTERPOLATORS; j++) { 912 int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1, 913 CDC_WSA_RX_INTX_2_SEL_MASK); 914 915 if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) { 916 int_fs_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL + 917 WSA_MACRO_RX_PATH_OFFSET * j; 918 919 snd_soc_component_update_bits(component, 920 int_fs_reg, 921 WSA_MACRO_FS_RATE_MASK, 922 int_mix_fs_rate_reg_val); 923 } 924 int_mux_cfg1 += WSA_MACRO_MUX_CFG_OFFSET; 925 } 926 } 927 return 0; 928 } 929 930 static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai, 931 u32 sample_rate) 932 { 933 int rate_val = 0; 934 int i, ret; 935 936 /* set mixing path rate */ 937 for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) { 938 if (sample_rate == int_mix_sample_rate_val[i].sample_rate) { 939 rate_val = int_mix_sample_rate_val[i].rate_val; 940 break; 941 } 942 } 943 if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) || (rate_val < 0)) 944 goto prim_rate; 945 946 ret = wsa_macro_set_mix_interpolator_rate(dai, (u8) rate_val, sample_rate); 947 prim_rate: 948 /* set primary path sample rate */ 949 for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) { 950 if (sample_rate == int_prim_sample_rate_val[i].sample_rate) { 951 rate_val = int_prim_sample_rate_val[i].rate_val; 952 break; 953 } 954 } 955 if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) || (rate_val < 0)) 956 return -EINVAL; 957 958 ret = wsa_macro_set_prim_interpolator_rate(dai, (u8) rate_val, sample_rate); 959 960 return ret; 961 } 962 963 static int wsa_macro_hw_params(struct snd_pcm_substream *substream, 964 struct snd_pcm_hw_params *params, 965 struct snd_soc_dai *dai) 966 { 967 struct snd_soc_component *component = dai->component; 968 int ret; 969 970 switch (substream->stream) { 971 case SNDRV_PCM_STREAM_PLAYBACK: 972 ret = wsa_macro_set_interpolator_rate(dai, params_rate(params)); 973 if (ret) { 974 dev_err(component->dev, 975 "%s: cannot set sample rate: %u\n", 976 __func__, params_rate(params)); 977 return ret; 978 } 979 break; 980 default: 981 break; 982 } 983 return 0; 984 } 985 986 static int wsa_macro_get_channel_map(struct snd_soc_dai *dai, 987 unsigned int *tx_num, unsigned int *tx_slot, 988 unsigned int *rx_num, unsigned int *rx_slot) 989 { 990 struct snd_soc_component *component = dai->component; 991 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 992 u16 val, mask = 0, cnt = 0, temp; 993 994 switch (dai->id) { 995 case WSA_MACRO_AIF_VI: 996 *tx_slot = wsa->active_ch_mask[dai->id]; 997 *tx_num = wsa->active_ch_cnt[dai->id]; 998 break; 999 case WSA_MACRO_AIF1_PB: 1000 case WSA_MACRO_AIF_MIX1_PB: 1001 for_each_set_bit(temp, &wsa->active_ch_mask[dai->id], 1002 WSA_MACRO_RX_MAX) { 1003 mask |= (1 << temp); 1004 if (++cnt == WSA_MACRO_MAX_DMA_CH_PER_PORT) 1005 break; 1006 } 1007 if (mask & 0x0C) 1008 mask = mask >> 0x2; 1009 *rx_slot = mask; 1010 *rx_num = cnt; 1011 break; 1012 case WSA_MACRO_AIF_ECHO: 1013 val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0); 1014 if (val & WSA_MACRO_EC_MIX_TX1_MASK) { 1015 mask |= 0x2; 1016 cnt++; 1017 } 1018 if (val & WSA_MACRO_EC_MIX_TX0_MASK) { 1019 mask |= 0x1; 1020 cnt++; 1021 } 1022 *tx_slot = mask; 1023 *tx_num = cnt; 1024 break; 1025 default: 1026 dev_err(component->dev, "%s: Invalid AIF\n", __func__); 1027 break; 1028 } 1029 return 0; 1030 } 1031 1032 static struct snd_soc_dai_ops wsa_macro_dai_ops = { 1033 .hw_params = wsa_macro_hw_params, 1034 .get_channel_map = wsa_macro_get_channel_map, 1035 }; 1036 1037 static struct snd_soc_dai_driver wsa_macro_dai[] = { 1038 { 1039 .name = "wsa_macro_rx1", 1040 .id = WSA_MACRO_AIF1_PB, 1041 .playback = { 1042 .stream_name = "WSA_AIF1 Playback", 1043 .rates = WSA_MACRO_RX_RATES, 1044 .formats = WSA_MACRO_RX_FORMATS, 1045 .rate_max = 384000, 1046 .rate_min = 8000, 1047 .channels_min = 1, 1048 .channels_max = 2, 1049 }, 1050 .ops = &wsa_macro_dai_ops, 1051 }, 1052 { 1053 .name = "wsa_macro_rx_mix", 1054 .id = WSA_MACRO_AIF_MIX1_PB, 1055 .playback = { 1056 .stream_name = "WSA_AIF_MIX1 Playback", 1057 .rates = WSA_MACRO_RX_MIX_RATES, 1058 .formats = WSA_MACRO_RX_FORMATS, 1059 .rate_max = 192000, 1060 .rate_min = 48000, 1061 .channels_min = 1, 1062 .channels_max = 2, 1063 }, 1064 .ops = &wsa_macro_dai_ops, 1065 }, 1066 { 1067 .name = "wsa_macro_vifeedback", 1068 .id = WSA_MACRO_AIF_VI, 1069 .capture = { 1070 .stream_name = "WSA_AIF_VI Capture", 1071 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000, 1072 .formats = WSA_MACRO_RX_FORMATS, 1073 .rate_max = 48000, 1074 .rate_min = 8000, 1075 .channels_min = 1, 1076 .channels_max = 4, 1077 }, 1078 .ops = &wsa_macro_dai_ops, 1079 }, 1080 { 1081 .name = "wsa_macro_echo", 1082 .id = WSA_MACRO_AIF_ECHO, 1083 .capture = { 1084 .stream_name = "WSA_AIF_ECHO Capture", 1085 .rates = WSA_MACRO_ECHO_RATES, 1086 .formats = WSA_MACRO_ECHO_FORMATS, 1087 .rate_max = 48000, 1088 .rate_min = 8000, 1089 .channels_min = 1, 1090 .channels_max = 2, 1091 }, 1092 .ops = &wsa_macro_dai_ops, 1093 }, 1094 }; 1095 1096 static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable) 1097 { 1098 struct regmap *regmap = wsa->regmap; 1099 1100 if (mclk_enable) { 1101 if (wsa->wsa_mclk_users == 0) { 1102 regcache_mark_dirty(regmap); 1103 regcache_sync(regmap); 1104 /* 9.6MHz MCLK, set value 0x00 if other frequency */ 1105 regmap_update_bits(regmap, CDC_WSA_TOP_FREQ_MCLK, 0x01, 0x01); 1106 regmap_update_bits(regmap, 1107 CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 1108 CDC_WSA_MCLK_EN_MASK, 1109 CDC_WSA_MCLK_ENABLE); 1110 regmap_update_bits(regmap, 1111 CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 1112 CDC_WSA_FS_CNT_EN_MASK, 1113 CDC_WSA_FS_CNT_ENABLE); 1114 } 1115 wsa->wsa_mclk_users++; 1116 } else { 1117 if (wsa->wsa_mclk_users <= 0) { 1118 dev_err(wsa->dev, "clock already disabled\n"); 1119 wsa->wsa_mclk_users = 0; 1120 return; 1121 } 1122 wsa->wsa_mclk_users--; 1123 if (wsa->wsa_mclk_users == 0) { 1124 regmap_update_bits(regmap, 1125 CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 1126 CDC_WSA_FS_CNT_EN_MASK, 1127 CDC_WSA_FS_CNT_DISABLE); 1128 regmap_update_bits(regmap, 1129 CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 1130 CDC_WSA_MCLK_EN_MASK, 1131 CDC_WSA_MCLK_DISABLE); 1132 } 1133 } 1134 } 1135 1136 static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w, 1137 struct snd_kcontrol *kcontrol, int event) 1138 { 1139 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1140 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1141 1142 wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU); 1143 return 0; 1144 } 1145 1146 static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w, 1147 struct snd_kcontrol *kcontrol, 1148 int event) 1149 { 1150 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1151 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1152 u32 tx_reg0, tx_reg1; 1153 1154 if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 1155 tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL; 1156 tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL; 1157 } else if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 1158 tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL; 1159 tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL; 1160 } 1161 1162 switch (event) { 1163 case SND_SOC_DAPM_POST_PMU: 1164 /* Enable V&I sensing */ 1165 snd_soc_component_update_bits(component, tx_reg0, 1166 CDC_WSA_TX_SPKR_PROT_RESET_MASK, 1167 CDC_WSA_TX_SPKR_PROT_RESET); 1168 snd_soc_component_update_bits(component, tx_reg1, 1169 CDC_WSA_TX_SPKR_PROT_RESET_MASK, 1170 CDC_WSA_TX_SPKR_PROT_RESET); 1171 snd_soc_component_update_bits(component, tx_reg0, 1172 CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK, 1173 CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K); 1174 snd_soc_component_update_bits(component, tx_reg1, 1175 CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK, 1176 CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K); 1177 snd_soc_component_update_bits(component, tx_reg0, 1178 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 1179 CDC_WSA_TX_SPKR_PROT_CLK_ENABLE); 1180 snd_soc_component_update_bits(component, tx_reg1, 1181 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 1182 CDC_WSA_TX_SPKR_PROT_CLK_ENABLE); 1183 snd_soc_component_update_bits(component, tx_reg0, 1184 CDC_WSA_TX_SPKR_PROT_RESET_MASK, 1185 CDC_WSA_TX_SPKR_PROT_NO_RESET); 1186 snd_soc_component_update_bits(component, tx_reg1, 1187 CDC_WSA_TX_SPKR_PROT_RESET_MASK, 1188 CDC_WSA_TX_SPKR_PROT_NO_RESET); 1189 break; 1190 case SND_SOC_DAPM_POST_PMD: 1191 /* Disable V&I sensing */ 1192 snd_soc_component_update_bits(component, tx_reg0, 1193 CDC_WSA_TX_SPKR_PROT_RESET_MASK, 1194 CDC_WSA_TX_SPKR_PROT_RESET); 1195 snd_soc_component_update_bits(component, tx_reg1, 1196 CDC_WSA_TX_SPKR_PROT_RESET_MASK, 1197 CDC_WSA_TX_SPKR_PROT_RESET); 1198 snd_soc_component_update_bits(component, tx_reg0, 1199 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 1200 CDC_WSA_TX_SPKR_PROT_CLK_DISABLE); 1201 snd_soc_component_update_bits(component, tx_reg1, 1202 CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 1203 CDC_WSA_TX_SPKR_PROT_CLK_DISABLE); 1204 break; 1205 } 1206 1207 return 0; 1208 } 1209 1210 static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w, 1211 struct snd_kcontrol *kcontrol, int event) 1212 { 1213 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1214 u16 gain_reg; 1215 int val; 1216 1217 switch (w->reg) { 1218 case CDC_WSA_RX0_RX_PATH_MIX_CTL: 1219 gain_reg = CDC_WSA_RX0_RX_VOL_MIX_CTL; 1220 break; 1221 case CDC_WSA_RX1_RX_PATH_MIX_CTL: 1222 gain_reg = CDC_WSA_RX1_RX_VOL_MIX_CTL; 1223 break; 1224 default: 1225 return 0; 1226 } 1227 1228 switch (event) { 1229 case SND_SOC_DAPM_POST_PMU: 1230 val = snd_soc_component_read(component, gain_reg); 1231 snd_soc_component_write(component, gain_reg, val); 1232 break; 1233 case SND_SOC_DAPM_POST_PMD: 1234 snd_soc_component_update_bits(component, w->reg, 1235 CDC_WSA_RX_PATH_MIX_CLK_EN_MASK, 1236 CDC_WSA_RX_PATH_MIX_CLK_DISABLE); 1237 break; 1238 } 1239 1240 return 0; 1241 } 1242 1243 static void wsa_macro_hd2_control(struct snd_soc_component *component, 1244 u16 reg, int event) 1245 { 1246 u16 hd2_scale_reg; 1247 u16 hd2_enable_reg; 1248 1249 if (reg == CDC_WSA_RX0_RX_PATH_CTL) { 1250 hd2_scale_reg = CDC_WSA_RX0_RX_PATH_SEC3; 1251 hd2_enable_reg = CDC_WSA_RX0_RX_PATH_CFG0; 1252 } 1253 if (reg == CDC_WSA_RX1_RX_PATH_CTL) { 1254 hd2_scale_reg = CDC_WSA_RX1_RX_PATH_SEC3; 1255 hd2_enable_reg = CDC_WSA_RX1_RX_PATH_CFG0; 1256 } 1257 1258 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 1259 snd_soc_component_update_bits(component, hd2_scale_reg, 1260 CDC_WSA_RX_PATH_HD2_ALPHA_MASK, 1261 0x10); 1262 snd_soc_component_update_bits(component, hd2_scale_reg, 1263 CDC_WSA_RX_PATH_HD2_SCALE_MASK, 1264 0x1); 1265 snd_soc_component_update_bits(component, hd2_enable_reg, 1266 CDC_WSA_RX_PATH_HD2_EN_MASK, 1267 CDC_WSA_RX_PATH_HD2_ENABLE); 1268 } 1269 1270 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 1271 snd_soc_component_update_bits(component, hd2_enable_reg, 1272 CDC_WSA_RX_PATH_HD2_EN_MASK, 0); 1273 snd_soc_component_update_bits(component, hd2_scale_reg, 1274 CDC_WSA_RX_PATH_HD2_SCALE_MASK, 1275 0); 1276 snd_soc_component_update_bits(component, hd2_scale_reg, 1277 CDC_WSA_RX_PATH_HD2_ALPHA_MASK, 1278 0); 1279 } 1280 } 1281 1282 static int wsa_macro_config_compander(struct snd_soc_component *component, 1283 int comp, int event) 1284 { 1285 u16 comp_ctl0_reg, rx_path_cfg0_reg; 1286 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1287 1288 if (!wsa->comp_enabled[comp]) 1289 return 0; 1290 1291 comp_ctl0_reg = CDC_WSA_COMPANDER0_CTL0 + 1292 (comp * WSA_MACRO_RX_COMP_OFFSET); 1293 rx_path_cfg0_reg = CDC_WSA_RX0_RX_PATH_CFG0 + 1294 (comp * WSA_MACRO_RX_PATH_OFFSET); 1295 1296 if (SND_SOC_DAPM_EVENT_ON(event)) { 1297 /* Enable Compander Clock */ 1298 snd_soc_component_update_bits(component, comp_ctl0_reg, 1299 CDC_WSA_COMPANDER_CLK_EN_MASK, 1300 CDC_WSA_COMPANDER_CLK_ENABLE); 1301 snd_soc_component_update_bits(component, comp_ctl0_reg, 1302 CDC_WSA_COMPANDER_SOFT_RST_MASK, 1303 CDC_WSA_COMPANDER_SOFT_RST_ENABLE); 1304 snd_soc_component_update_bits(component, comp_ctl0_reg, 1305 CDC_WSA_COMPANDER_SOFT_RST_MASK, 1306 0); 1307 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 1308 CDC_WSA_RX_PATH_COMP_EN_MASK, 1309 CDC_WSA_RX_PATH_COMP_ENABLE); 1310 } 1311 1312 if (SND_SOC_DAPM_EVENT_OFF(event)) { 1313 snd_soc_component_update_bits(component, comp_ctl0_reg, 1314 CDC_WSA_COMPANDER_HALT_MASK, 1315 CDC_WSA_COMPANDER_HALT); 1316 snd_soc_component_update_bits(component, rx_path_cfg0_reg, 1317 CDC_WSA_RX_PATH_COMP_EN_MASK, 0); 1318 snd_soc_component_update_bits(component, comp_ctl0_reg, 1319 CDC_WSA_COMPANDER_SOFT_RST_MASK, 1320 CDC_WSA_COMPANDER_SOFT_RST_ENABLE); 1321 snd_soc_component_update_bits(component, comp_ctl0_reg, 1322 CDC_WSA_COMPANDER_SOFT_RST_MASK, 1323 0); 1324 snd_soc_component_update_bits(component, comp_ctl0_reg, 1325 CDC_WSA_COMPANDER_CLK_EN_MASK, 0); 1326 snd_soc_component_update_bits(component, comp_ctl0_reg, 1327 CDC_WSA_COMPANDER_HALT_MASK, 0); 1328 } 1329 1330 return 0; 1331 } 1332 1333 static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component, 1334 struct wsa_macro *wsa, 1335 int path, 1336 bool enable) 1337 { 1338 u16 softclip_clk_reg = CDC_WSA_SOFTCLIP0_CRC + 1339 (path * WSA_MACRO_RX_SOFTCLIP_OFFSET); 1340 u8 softclip_mux_mask = (1 << path); 1341 u8 softclip_mux_value = (1 << path); 1342 1343 if (enable) { 1344 if (wsa->softclip_clk_users[path] == 0) { 1345 snd_soc_component_update_bits(component, 1346 softclip_clk_reg, 1347 CDC_WSA_SOFTCLIP_CLK_EN_MASK, 1348 CDC_WSA_SOFTCLIP_CLK_ENABLE); 1349 snd_soc_component_update_bits(component, 1350 CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 1351 softclip_mux_mask, softclip_mux_value); 1352 } 1353 wsa->softclip_clk_users[path]++; 1354 } else { 1355 wsa->softclip_clk_users[path]--; 1356 if (wsa->softclip_clk_users[path] == 0) { 1357 snd_soc_component_update_bits(component, 1358 softclip_clk_reg, 1359 CDC_WSA_SOFTCLIP_CLK_EN_MASK, 1360 0); 1361 snd_soc_component_update_bits(component, 1362 CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 1363 softclip_mux_mask, 0x00); 1364 } 1365 } 1366 } 1367 1368 static int wsa_macro_config_softclip(struct snd_soc_component *component, 1369 int path, int event) 1370 { 1371 u16 softclip_ctrl_reg; 1372 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1373 int softclip_path = 0; 1374 1375 if (path == WSA_MACRO_COMP1) 1376 softclip_path = WSA_MACRO_SOFTCLIP0; 1377 else if (path == WSA_MACRO_COMP2) 1378 softclip_path = WSA_MACRO_SOFTCLIP1; 1379 1380 if (!wsa->is_softclip_on[softclip_path]) 1381 return 0; 1382 1383 softclip_ctrl_reg = CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL + 1384 (softclip_path * WSA_MACRO_RX_SOFTCLIP_OFFSET); 1385 1386 if (SND_SOC_DAPM_EVENT_ON(event)) { 1387 /* Enable Softclip clock and mux */ 1388 wsa_macro_enable_softclip_clk(component, wsa, softclip_path, 1389 true); 1390 /* Enable Softclip control */ 1391 snd_soc_component_update_bits(component, softclip_ctrl_reg, 1392 CDC_WSA_SOFTCLIP_EN_MASK, 1393 CDC_WSA_SOFTCLIP_ENABLE); 1394 } 1395 1396 if (SND_SOC_DAPM_EVENT_OFF(event)) { 1397 snd_soc_component_update_bits(component, softclip_ctrl_reg, 1398 CDC_WSA_SOFTCLIP_EN_MASK, 0); 1399 wsa_macro_enable_softclip_clk(component, wsa, softclip_path, 1400 false); 1401 } 1402 1403 return 0; 1404 } 1405 1406 static bool wsa_macro_adie_lb(struct snd_soc_component *component, 1407 int interp_idx) 1408 { 1409 u16 int_mux_cfg0, int_mux_cfg1; 1410 u8 int_n_inp0, int_n_inp1, int_n_inp2; 1411 1412 int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8; 1413 int_mux_cfg1 = int_mux_cfg0 + 4; 1414 1415 int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0, 1416 CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK); 1417 if (int_n_inp0 == INTn_1_INP_SEL_DEC0 || 1418 int_n_inp0 == INTn_1_INP_SEL_DEC1) 1419 return true; 1420 1421 int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0, 1422 CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK); 1423 if (int_n_inp1 == INTn_1_INP_SEL_DEC0 || 1424 int_n_inp1 == INTn_1_INP_SEL_DEC1) 1425 return true; 1426 1427 int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1, 1428 CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK); 1429 if (int_n_inp2 == INTn_1_INP_SEL_DEC0 || 1430 int_n_inp2 == INTn_1_INP_SEL_DEC1) 1431 return true; 1432 1433 return false; 1434 } 1435 1436 static int wsa_macro_enable_main_path(struct snd_soc_dapm_widget *w, 1437 struct snd_kcontrol *kcontrol, 1438 int event) 1439 { 1440 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1441 u16 reg; 1442 1443 reg = CDC_WSA_RX0_RX_PATH_CTL + WSA_MACRO_RX_PATH_OFFSET * w->shift; 1444 switch (event) { 1445 case SND_SOC_DAPM_PRE_PMU: 1446 if (wsa_macro_adie_lb(component, w->shift)) { 1447 snd_soc_component_update_bits(component, reg, 1448 CDC_WSA_RX_PATH_CLK_EN_MASK, 1449 CDC_WSA_RX_PATH_CLK_ENABLE); 1450 } 1451 break; 1452 default: 1453 break; 1454 } 1455 return 0; 1456 } 1457 1458 static int wsa_macro_interp_get_primary_reg(u16 reg, u16 *ind) 1459 { 1460 u16 prim_int_reg = 0; 1461 1462 switch (reg) { 1463 case CDC_WSA_RX0_RX_PATH_CTL: 1464 case CDC_WSA_RX0_RX_PATH_MIX_CTL: 1465 prim_int_reg = CDC_WSA_RX0_RX_PATH_CTL; 1466 *ind = 0; 1467 break; 1468 case CDC_WSA_RX1_RX_PATH_CTL: 1469 case CDC_WSA_RX1_RX_PATH_MIX_CTL: 1470 prim_int_reg = CDC_WSA_RX1_RX_PATH_CTL; 1471 *ind = 1; 1472 break; 1473 } 1474 1475 return prim_int_reg; 1476 } 1477 1478 static int wsa_macro_enable_prim_interpolator(struct snd_soc_component *component, 1479 u16 reg, int event) 1480 { 1481 u16 prim_int_reg; 1482 u16 ind = 0; 1483 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1484 1485 prim_int_reg = wsa_macro_interp_get_primary_reg(reg, &ind); 1486 1487 switch (event) { 1488 case SND_SOC_DAPM_PRE_PMU: 1489 wsa->prim_int_users[ind]++; 1490 if (wsa->prim_int_users[ind] == 1) { 1491 snd_soc_component_update_bits(component, 1492 prim_int_reg + WSA_MACRO_RX_PATH_CFG3_OFFSET, 1493 CDC_WSA_RX_DC_DCOEFF_MASK, 1494 0x3); 1495 snd_soc_component_update_bits(component, prim_int_reg, 1496 CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK, 1497 CDC_WSA_RX_PATH_PGA_MUTE_ENABLE); 1498 wsa_macro_hd2_control(component, prim_int_reg, event); 1499 snd_soc_component_update_bits(component, 1500 prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET, 1501 CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 1502 CDC_WSA_RX_DSMDEM_CLK_ENABLE); 1503 } 1504 if ((reg != prim_int_reg) && 1505 ((snd_soc_component_read( 1506 component, prim_int_reg)) & 0x10)) 1507 snd_soc_component_update_bits(component, reg, 1508 0x10, 0x10); 1509 break; 1510 case SND_SOC_DAPM_POST_PMD: 1511 wsa->prim_int_users[ind]--; 1512 if (wsa->prim_int_users[ind] == 0) { 1513 snd_soc_component_update_bits(component, 1514 prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET, 1515 CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 0); 1516 wsa_macro_hd2_control(component, prim_int_reg, event); 1517 } 1518 break; 1519 } 1520 1521 return 0; 1522 } 1523 1524 static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component, 1525 struct wsa_macro *wsa, 1526 int event, int gain_reg) 1527 { 1528 int comp_gain_offset, val; 1529 1530 switch (wsa->spkr_mode) { 1531 /* Compander gain in WSA_MACRO_SPKR_MODE1 case is 12 dB */ 1532 case WSA_MACRO_SPKR_MODE_1: 1533 comp_gain_offset = -12; 1534 break; 1535 /* Default case compander gain is 15 dB */ 1536 default: 1537 comp_gain_offset = -15; 1538 break; 1539 } 1540 1541 switch (event) { 1542 case SND_SOC_DAPM_POST_PMU: 1543 /* Apply ear spkr gain only if compander is enabled */ 1544 if (wsa->comp_enabled[WSA_MACRO_COMP1] && 1545 (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) && 1546 (wsa->ear_spkr_gain != 0)) { 1547 /* For example, val is -8(-12+5-1) for 4dB of gain */ 1548 val = comp_gain_offset + wsa->ear_spkr_gain - 1; 1549 snd_soc_component_write(component, gain_reg, val); 1550 } 1551 break; 1552 case SND_SOC_DAPM_POST_PMD: 1553 /* 1554 * Reset RX0 volume to 0 dB if compander is enabled and 1555 * ear_spkr_gain is non-zero. 1556 */ 1557 if (wsa->comp_enabled[WSA_MACRO_COMP1] && 1558 (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) && 1559 (wsa->ear_spkr_gain != 0)) { 1560 snd_soc_component_write(component, gain_reg, 0x0); 1561 } 1562 break; 1563 } 1564 1565 return 0; 1566 } 1567 1568 static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w, 1569 struct snd_kcontrol *kcontrol, 1570 int event) 1571 { 1572 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1573 u16 gain_reg; 1574 u16 reg; 1575 int val; 1576 int offset_val = 0; 1577 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1578 1579 if (w->shift == WSA_MACRO_COMP1) { 1580 reg = CDC_WSA_RX0_RX_PATH_CTL; 1581 gain_reg = CDC_WSA_RX0_RX_VOL_CTL; 1582 } else if (w->shift == WSA_MACRO_COMP2) { 1583 reg = CDC_WSA_RX1_RX_PATH_CTL; 1584 gain_reg = CDC_WSA_RX1_RX_VOL_CTL; 1585 } 1586 1587 switch (event) { 1588 case SND_SOC_DAPM_PRE_PMU: 1589 /* Reset if needed */ 1590 wsa_macro_enable_prim_interpolator(component, reg, event); 1591 break; 1592 case SND_SOC_DAPM_POST_PMU: 1593 wsa_macro_config_compander(component, w->shift, event); 1594 wsa_macro_config_softclip(component, w->shift, event); 1595 /* apply gain after int clk is enabled */ 1596 if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) && 1597 (wsa->comp_enabled[WSA_MACRO_COMP1] || 1598 wsa->comp_enabled[WSA_MACRO_COMP2])) { 1599 snd_soc_component_update_bits(component, 1600 CDC_WSA_RX0_RX_PATH_SEC1, 1601 CDC_WSA_RX_PGA_HALF_DB_MASK, 1602 CDC_WSA_RX_PGA_HALF_DB_ENABLE); 1603 snd_soc_component_update_bits(component, 1604 CDC_WSA_RX0_RX_PATH_MIX_SEC0, 1605 CDC_WSA_RX_PGA_HALF_DB_MASK, 1606 CDC_WSA_RX_PGA_HALF_DB_ENABLE); 1607 snd_soc_component_update_bits(component, 1608 CDC_WSA_RX1_RX_PATH_SEC1, 1609 CDC_WSA_RX_PGA_HALF_DB_MASK, 1610 CDC_WSA_RX_PGA_HALF_DB_ENABLE); 1611 snd_soc_component_update_bits(component, 1612 CDC_WSA_RX1_RX_PATH_MIX_SEC0, 1613 CDC_WSA_RX_PGA_HALF_DB_MASK, 1614 CDC_WSA_RX_PGA_HALF_DB_ENABLE); 1615 offset_val = -2; 1616 } 1617 val = snd_soc_component_read(component, gain_reg); 1618 val += offset_val; 1619 snd_soc_component_write(component, gain_reg, val); 1620 wsa_macro_config_ear_spkr_gain(component, wsa, 1621 event, gain_reg); 1622 break; 1623 case SND_SOC_DAPM_POST_PMD: 1624 wsa_macro_config_compander(component, w->shift, event); 1625 wsa_macro_config_softclip(component, w->shift, event); 1626 wsa_macro_enable_prim_interpolator(component, reg, event); 1627 if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) && 1628 (wsa->comp_enabled[WSA_MACRO_COMP1] || 1629 wsa->comp_enabled[WSA_MACRO_COMP2])) { 1630 snd_soc_component_update_bits(component, 1631 CDC_WSA_RX0_RX_PATH_SEC1, 1632 CDC_WSA_RX_PGA_HALF_DB_MASK, 1633 CDC_WSA_RX_PGA_HALF_DB_DISABLE); 1634 snd_soc_component_update_bits(component, 1635 CDC_WSA_RX0_RX_PATH_MIX_SEC0, 1636 CDC_WSA_RX_PGA_HALF_DB_MASK, 1637 CDC_WSA_RX_PGA_HALF_DB_DISABLE); 1638 snd_soc_component_update_bits(component, 1639 CDC_WSA_RX1_RX_PATH_SEC1, 1640 CDC_WSA_RX_PGA_HALF_DB_MASK, 1641 CDC_WSA_RX_PGA_HALF_DB_DISABLE); 1642 snd_soc_component_update_bits(component, 1643 CDC_WSA_RX1_RX_PATH_MIX_SEC0, 1644 CDC_WSA_RX_PGA_HALF_DB_MASK, 1645 CDC_WSA_RX_PGA_HALF_DB_DISABLE); 1646 offset_val = 2; 1647 val = snd_soc_component_read(component, gain_reg); 1648 val += offset_val; 1649 snd_soc_component_write(component, gain_reg, val); 1650 } 1651 wsa_macro_config_ear_spkr_gain(component, wsa, 1652 event, gain_reg); 1653 break; 1654 } 1655 1656 return 0; 1657 } 1658 1659 static int wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w, 1660 struct snd_kcontrol *kcontrol, 1661 int event) 1662 { 1663 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1664 u16 boost_path_ctl, boost_path_cfg1; 1665 u16 reg, reg_mix; 1666 1667 if (!strcmp(w->name, "WSA_RX INT0 CHAIN")) { 1668 boost_path_ctl = CDC_WSA_BOOST0_BOOST_PATH_CTL; 1669 boost_path_cfg1 = CDC_WSA_RX0_RX_PATH_CFG1; 1670 reg = CDC_WSA_RX0_RX_PATH_CTL; 1671 reg_mix = CDC_WSA_RX0_RX_PATH_MIX_CTL; 1672 } else if (!strcmp(w->name, "WSA_RX INT1 CHAIN")) { 1673 boost_path_ctl = CDC_WSA_BOOST1_BOOST_PATH_CTL; 1674 boost_path_cfg1 = CDC_WSA_RX1_RX_PATH_CFG1; 1675 reg = CDC_WSA_RX1_RX_PATH_CTL; 1676 reg_mix = CDC_WSA_RX1_RX_PATH_MIX_CTL; 1677 } 1678 1679 switch (event) { 1680 case SND_SOC_DAPM_PRE_PMU: 1681 snd_soc_component_update_bits(component, boost_path_cfg1, 1682 CDC_WSA_RX_PATH_SMART_BST_EN_MASK, 1683 CDC_WSA_RX_PATH_SMART_BST_ENABLE); 1684 snd_soc_component_update_bits(component, boost_path_ctl, 1685 CDC_WSA_BOOST_PATH_CLK_EN_MASK, 1686 CDC_WSA_BOOST_PATH_CLK_ENABLE); 1687 if ((snd_soc_component_read(component, reg_mix)) & 0x10) 1688 snd_soc_component_update_bits(component, reg_mix, 1689 0x10, 0x00); 1690 break; 1691 case SND_SOC_DAPM_POST_PMU: 1692 snd_soc_component_update_bits(component, reg, 0x10, 0x00); 1693 break; 1694 case SND_SOC_DAPM_POST_PMD: 1695 snd_soc_component_update_bits(component, boost_path_ctl, 1696 CDC_WSA_BOOST_PATH_CLK_EN_MASK, 1697 CDC_WSA_BOOST_PATH_CLK_DISABLE); 1698 snd_soc_component_update_bits(component, boost_path_cfg1, 1699 CDC_WSA_RX_PATH_SMART_BST_EN_MASK, 1700 CDC_WSA_RX_PATH_SMART_BST_DISABLE); 1701 break; 1702 } 1703 1704 return 0; 1705 } 1706 1707 static int wsa_macro_enable_echo(struct snd_soc_dapm_widget *w, 1708 struct snd_kcontrol *kcontrol, 1709 int event) 1710 { 1711 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1712 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1713 u16 val, ec_tx, ec_hq_reg; 1714 1715 val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0); 1716 1717 switch (w->shift) { 1718 case WSA_MACRO_EC0_MUX: 1719 val = val & CDC_WSA_RX_MIX_TX0_SEL_MASK; 1720 ec_tx = val - 1; 1721 break; 1722 case WSA_MACRO_EC1_MUX: 1723 val = val & CDC_WSA_RX_MIX_TX1_SEL_MASK; 1724 ec_tx = (val >> CDC_WSA_RX_MIX_TX1_SEL_SHFT) - 1; 1725 break; 1726 } 1727 1728 if (wsa->ec_hq[ec_tx]) { 1729 ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL + 0x40 * ec_tx; 1730 snd_soc_component_update_bits(component, ec_hq_reg, 1731 CDC_WSA_EC_HQ_EC_CLK_EN_MASK, 1732 CDC_WSA_EC_HQ_EC_CLK_ENABLE); 1733 ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 + 0x40 * ec_tx; 1734 /* default set to 48k */ 1735 snd_soc_component_update_bits(component, ec_hq_reg, 1736 CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK, 1737 CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K); 1738 } 1739 1740 return 0; 1741 } 1742 1743 static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol, 1744 struct snd_ctl_elem_value *ucontrol) 1745 { 1746 1747 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1748 int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1749 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1750 1751 ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx]; 1752 1753 return 0; 1754 } 1755 1756 static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol, 1757 struct snd_ctl_elem_value *ucontrol) 1758 { 1759 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1760 int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1761 int value = ucontrol->value.integer.value[0]; 1762 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1763 1764 wsa->ec_hq[ec_tx] = value; 1765 1766 return 0; 1767 } 1768 1769 static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol, 1770 struct snd_ctl_elem_value *ucontrol) 1771 { 1772 1773 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1774 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1775 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1776 1777 ucontrol->value.integer.value[0] = wsa->comp_enabled[comp]; 1778 return 0; 1779 } 1780 1781 static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol, 1782 struct snd_ctl_elem_value *ucontrol) 1783 { 1784 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1785 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1786 int value = ucontrol->value.integer.value[0]; 1787 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1788 1789 wsa->comp_enabled[comp] = value; 1790 1791 return 0; 1792 } 1793 1794 static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol, 1795 struct snd_ctl_elem_value *ucontrol) 1796 { 1797 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1798 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1799 1800 ucontrol->value.integer.value[0] = wsa->ear_spkr_gain; 1801 1802 return 0; 1803 } 1804 1805 static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol, 1806 struct snd_ctl_elem_value *ucontrol) 1807 { 1808 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1809 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1810 1811 wsa->ear_spkr_gain = ucontrol->value.integer.value[0]; 1812 1813 return 0; 1814 } 1815 1816 static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol, 1817 struct snd_ctl_elem_value *ucontrol) 1818 { 1819 struct snd_soc_dapm_widget *widget = 1820 snd_soc_dapm_kcontrol_widget(kcontrol); 1821 struct snd_soc_component *component = 1822 snd_soc_dapm_to_component(widget->dapm); 1823 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1824 1825 ucontrol->value.integer.value[0] = 1826 wsa->rx_port_value[widget->shift]; 1827 return 0; 1828 } 1829 1830 static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol, 1831 struct snd_ctl_elem_value *ucontrol) 1832 { 1833 struct snd_soc_dapm_widget *widget = 1834 snd_soc_dapm_kcontrol_widget(kcontrol); 1835 struct snd_soc_component *component = 1836 snd_soc_dapm_to_component(widget->dapm); 1837 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 1838 struct snd_soc_dapm_update *update = NULL; 1839 u32 rx_port_value = ucontrol->value.integer.value[0]; 1840 u32 bit_input; 1841 u32 aif_rst; 1842 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1843 1844 aif_rst = wsa->rx_port_value[widget->shift]; 1845 if (!rx_port_value) { 1846 if (aif_rst == 0) { 1847 dev_err(component->dev, "%s: AIF reset already\n", __func__); 1848 return 0; 1849 } 1850 if (aif_rst >= WSA_MACRO_RX_MAX) { 1851 dev_err(component->dev, "%s: Invalid AIF reset\n", __func__); 1852 return 0; 1853 } 1854 } 1855 wsa->rx_port_value[widget->shift] = rx_port_value; 1856 1857 bit_input = widget->shift; 1858 1859 switch (rx_port_value) { 1860 case 0: 1861 if (wsa->active_ch_cnt[aif_rst]) { 1862 clear_bit(bit_input, 1863 &wsa->active_ch_mask[aif_rst]); 1864 wsa->active_ch_cnt[aif_rst]--; 1865 } 1866 break; 1867 case 1: 1868 case 2: 1869 set_bit(bit_input, 1870 &wsa->active_ch_mask[rx_port_value]); 1871 wsa->active_ch_cnt[rx_port_value]++; 1872 break; 1873 default: 1874 dev_err(component->dev, 1875 "%s: Invalid AIF_ID for WSA RX MUX %d\n", 1876 __func__, rx_port_value); 1877 return -EINVAL; 1878 } 1879 1880 snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, 1881 rx_port_value, e, update); 1882 return 0; 1883 } 1884 1885 static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, 1886 struct snd_ctl_elem_value *ucontrol) 1887 { 1888 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1889 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1890 int path = ((struct soc_mixer_control *)kcontrol->private_value)->shift; 1891 1892 ucontrol->value.integer.value[0] = wsa->is_softclip_on[path]; 1893 1894 return 0; 1895 } 1896 1897 static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, 1898 struct snd_ctl_elem_value *ucontrol) 1899 { 1900 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1901 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1902 int path = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1903 1904 wsa->is_softclip_on[path] = ucontrol->value.integer.value[0]; 1905 1906 return 0; 1907 } 1908 1909 static const struct snd_kcontrol_new wsa_macro_snd_controls[] = { 1910 SOC_ENUM_EXT("EAR SPKR PA Gain", wsa_macro_ear_spkr_pa_gain_enum, 1911 wsa_macro_ear_spkr_pa_gain_get, 1912 wsa_macro_ear_spkr_pa_gain_put), 1913 SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM, 1914 WSA_MACRO_SOFTCLIP0, 1, 0, 1915 wsa_macro_soft_clip_enable_get, 1916 wsa_macro_soft_clip_enable_put), 1917 SOC_SINGLE_EXT("WSA_Softclip1 Enable", SND_SOC_NOPM, 1918 WSA_MACRO_SOFTCLIP1, 1, 0, 1919 wsa_macro_soft_clip_enable_get, 1920 wsa_macro_soft_clip_enable_put), 1921 1922 SOC_SINGLE_S8_TLV("WSA_RX0 Digital Volume", CDC_WSA_RX0_RX_VOL_CTL, 1923 -84, 40, digital_gain), 1924 SOC_SINGLE_S8_TLV("WSA_RX1 Digital Volume", CDC_WSA_RX1_RX_VOL_CTL, 1925 -84, 40, digital_gain), 1926 1927 SOC_SINGLE("WSA_RX0 Digital Mute", CDC_WSA_RX0_RX_PATH_CTL, 4, 1, 0), 1928 SOC_SINGLE("WSA_RX1 Digital Mute", CDC_WSA_RX1_RX_PATH_CTL, 4, 1, 0), 1929 SOC_SINGLE("WSA_RX0_MIX Digital Mute", CDC_WSA_RX0_RX_PATH_MIX_CTL, 4, 1930 1, 0), 1931 SOC_SINGLE("WSA_RX1_MIX Digital Mute", CDC_WSA_RX1_RX_PATH_MIX_CTL, 4, 1932 1, 0), 1933 SOC_SINGLE_EXT("WSA_COMP1 Switch", SND_SOC_NOPM, WSA_MACRO_COMP1, 1, 0, 1934 wsa_macro_get_compander, wsa_macro_set_compander), 1935 SOC_SINGLE_EXT("WSA_COMP2 Switch", SND_SOC_NOPM, WSA_MACRO_COMP2, 1, 0, 1936 wsa_macro_get_compander, wsa_macro_set_compander), 1937 SOC_SINGLE_EXT("WSA_RX0 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX0, 1, 0, 1938 wsa_macro_get_ec_hq, wsa_macro_set_ec_hq), 1939 SOC_SINGLE_EXT("WSA_RX1 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX1, 1, 0, 1940 wsa_macro_get_ec_hq, wsa_macro_set_ec_hq), 1941 }; 1942 1943 static const struct soc_enum rx_mux_enum = 1944 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_mux_text), rx_mux_text); 1945 1946 static const struct snd_kcontrol_new rx_mux[WSA_MACRO_RX_MAX] = { 1947 SOC_DAPM_ENUM_EXT("WSA RX0 Mux", rx_mux_enum, 1948 wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 1949 SOC_DAPM_ENUM_EXT("WSA RX1 Mux", rx_mux_enum, 1950 wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 1951 SOC_DAPM_ENUM_EXT("WSA RX_MIX0 Mux", rx_mux_enum, 1952 wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 1953 SOC_DAPM_ENUM_EXT("WSA RX_MIX1 Mux", rx_mux_enum, 1954 wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 1955 }; 1956 1957 static int wsa_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol, 1958 struct snd_ctl_elem_value *ucontrol) 1959 { 1960 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 1961 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 1962 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1963 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1964 u32 spk_tx_id = mixer->shift; 1965 u32 dai_id = widget->shift; 1966 1967 if (test_bit(spk_tx_id, &wsa->active_ch_mask[dai_id])) 1968 ucontrol->value.integer.value[0] = 1; 1969 else 1970 ucontrol->value.integer.value[0] = 0; 1971 1972 return 0; 1973 } 1974 1975 static int wsa_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol, 1976 struct snd_ctl_elem_value *ucontrol) 1977 { 1978 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 1979 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 1980 struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 1981 struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1982 u32 enable = ucontrol->value.integer.value[0]; 1983 u32 spk_tx_id = mixer->shift; 1984 1985 if (enable) { 1986 if (spk_tx_id == WSA_MACRO_TX0 && 1987 !test_bit(WSA_MACRO_TX0, 1988 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 1989 set_bit(WSA_MACRO_TX0, 1990 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 1991 wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++; 1992 } 1993 if (spk_tx_id == WSA_MACRO_TX1 && 1994 !test_bit(WSA_MACRO_TX1, 1995 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 1996 set_bit(WSA_MACRO_TX1, 1997 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 1998 wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++; 1999 } 2000 } else { 2001 if (spk_tx_id == WSA_MACRO_TX0 && 2002 test_bit(WSA_MACRO_TX0, 2003 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 2004 clear_bit(WSA_MACRO_TX0, 2005 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 2006 wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--; 2007 } 2008 if (spk_tx_id == WSA_MACRO_TX1 && 2009 test_bit(WSA_MACRO_TX1, 2010 &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 2011 clear_bit(WSA_MACRO_TX1, 2012 &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 2013 wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--; 2014 } 2015 } 2016 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL); 2017 2018 return 0; 2019 } 2020 2021 static const struct snd_kcontrol_new aif_vi_mixer[] = { 2022 SOC_SINGLE_EXT("WSA_SPKR_VI_1", SND_SOC_NOPM, WSA_MACRO_TX0, 1, 0, 2023 wsa_macro_vi_feed_mixer_get, 2024 wsa_macro_vi_feed_mixer_put), 2025 SOC_SINGLE_EXT("WSA_SPKR_VI_2", SND_SOC_NOPM, WSA_MACRO_TX1, 1, 0, 2026 wsa_macro_vi_feed_mixer_get, 2027 wsa_macro_vi_feed_mixer_put), 2028 }; 2029 2030 static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = { 2031 SND_SOC_DAPM_AIF_IN("WSA AIF1 PB", "WSA_AIF1 Playback", 0, 2032 SND_SOC_NOPM, 0, 0), 2033 SND_SOC_DAPM_AIF_IN("WSA AIF_MIX1 PB", "WSA_AIF_MIX1 Playback", 0, 2034 SND_SOC_NOPM, 0, 0), 2035 2036 SND_SOC_DAPM_AIF_OUT_E("WSA AIF_VI", "WSA_AIF_VI Capture", 0, 2037 SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0, 2038 wsa_macro_enable_vi_feedback, 2039 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 2040 SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0, 2041 SND_SOC_NOPM, 0, 0), 2042 2043 SND_SOC_DAPM_MIXER("WSA_AIF_VI Mixer", SND_SOC_NOPM, WSA_MACRO_AIF_VI, 2044 0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)), 2045 SND_SOC_DAPM_MUX_E("WSA RX_MIX EC0_MUX", SND_SOC_NOPM, 2046 WSA_MACRO_EC0_MUX, 0, 2047 &rx_mix_ec0_mux, wsa_macro_enable_echo, 2048 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2049 SND_SOC_DAPM_MUX_E("WSA RX_MIX EC1_MUX", SND_SOC_NOPM, 2050 WSA_MACRO_EC1_MUX, 0, 2051 &rx_mix_ec1_mux, wsa_macro_enable_echo, 2052 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2053 2054 SND_SOC_DAPM_MUX("WSA RX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX0, 0, 2055 &rx_mux[WSA_MACRO_RX0]), 2056 SND_SOC_DAPM_MUX("WSA RX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX1, 0, 2057 &rx_mux[WSA_MACRO_RX1]), 2058 SND_SOC_DAPM_MUX("WSA RX_MIX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 0, 2059 &rx_mux[WSA_MACRO_RX_MIX0]), 2060 SND_SOC_DAPM_MUX("WSA RX_MIX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 0, 2061 &rx_mux[WSA_MACRO_RX_MIX1]), 2062 2063 SND_SOC_DAPM_MIXER("WSA RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 2064 SND_SOC_DAPM_MIXER("WSA RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 2065 SND_SOC_DAPM_MIXER("WSA RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0), 2066 SND_SOC_DAPM_MIXER("WSA RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 2067 2068 SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, &rx0_prim_inp0_mux), 2069 SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, &rx0_prim_inp1_mux), 2070 SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, &rx0_prim_inp2_mux), 2071 SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", CDC_WSA_RX0_RX_PATH_MIX_CTL, 2072 0, 0, &rx0_mix_mux, wsa_macro_enable_mix_path, 2073 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2074 SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, &rx1_prim_inp0_mux), 2075 SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, &rx1_prim_inp1_mux), 2076 SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, &rx1_prim_inp2_mux), 2077 SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", CDC_WSA_RX1_RX_PATH_MIX_CTL, 2078 0, 0, &rx1_mix_mux, wsa_macro_enable_mix_path, 2079 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2080 2081 SND_SOC_DAPM_MIXER_E("WSA_RX INT0 MIX", SND_SOC_NOPM, 0, 0, NULL, 0, 2082 wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU), 2083 SND_SOC_DAPM_MIXER_E("WSA_RX INT1 MIX", SND_SOC_NOPM, 1, 0, NULL, 0, 2084 wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU), 2085 2086 SND_SOC_DAPM_MIXER("WSA_RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2087 SND_SOC_DAPM_MIXER("WSA_RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 2088 2089 SND_SOC_DAPM_MUX("WSA_RX0 INT0 SIDETONE MIX", CDC_WSA_RX0_RX_PATH_CFG1, 2090 4, 0, &rx0_sidetone_mix_mux), 2091 2092 SND_SOC_DAPM_INPUT("WSA SRC0_INP"), 2093 SND_SOC_DAPM_INPUT("WSA_TX DEC0_INP"), 2094 SND_SOC_DAPM_INPUT("WSA_TX DEC1_INP"), 2095 2096 SND_SOC_DAPM_MIXER_E("WSA_RX INT0 INTERP", SND_SOC_NOPM, 2097 WSA_MACRO_COMP1, 0, NULL, 0, 2098 wsa_macro_enable_interpolator, 2099 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2100 SND_SOC_DAPM_POST_PMD), 2101 2102 SND_SOC_DAPM_MIXER_E("WSA_RX INT1 INTERP", SND_SOC_NOPM, 2103 WSA_MACRO_COMP2, 0, NULL, 0, 2104 wsa_macro_enable_interpolator, 2105 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2106 SND_SOC_DAPM_POST_PMD), 2107 2108 SND_SOC_DAPM_MIXER_E("WSA_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0, 2109 NULL, 0, wsa_macro_spk_boost_event, 2110 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2111 SND_SOC_DAPM_POST_PMD), 2112 2113 SND_SOC_DAPM_MIXER_E("WSA_RX INT1 CHAIN", SND_SOC_NOPM, 0, 0, 2114 NULL, 0, wsa_macro_spk_boost_event, 2115 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 2116 SND_SOC_DAPM_POST_PMD), 2117 2118 SND_SOC_DAPM_INPUT("VIINPUT_WSA"), 2119 SND_SOC_DAPM_OUTPUT("WSA_SPK1 OUT"), 2120 SND_SOC_DAPM_OUTPUT("WSA_SPK2 OUT"), 2121 2122 SND_SOC_DAPM_SUPPLY("WSA_RX0_CLK", CDC_WSA_RX0_RX_PATH_CTL, 5, 0, NULL, 0), 2123 SND_SOC_DAPM_SUPPLY("WSA_RX1_CLK", CDC_WSA_RX1_RX_PATH_CTL, 5, 0, NULL, 0), 2124 SND_SOC_DAPM_SUPPLY("WSA_RX_MIX0_CLK", CDC_WSA_RX0_RX_PATH_MIX_CTL, 5, 0, NULL, 0), 2125 SND_SOC_DAPM_SUPPLY("WSA_RX_MIX1_CLK", CDC_WSA_RX1_RX_PATH_MIX_CTL, 5, 0, NULL, 0), 2126 SND_SOC_DAPM_SUPPLY_S("WSA_MCLK", 0, SND_SOC_NOPM, 0, 0, 2127 wsa_macro_mclk_event, 2128 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 2129 }; 2130 2131 static const struct snd_soc_dapm_route wsa_audio_map[] = { 2132 /* VI Feedback */ 2133 {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_1", "VIINPUT_WSA"}, 2134 {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_2", "VIINPUT_WSA"}, 2135 {"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"}, 2136 {"WSA AIF_VI", NULL, "WSA_MCLK"}, 2137 2138 {"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"}, 2139 {"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"}, 2140 {"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"}, 2141 {"WSA RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"}, 2142 {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC0_MUX"}, 2143 {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC1_MUX"}, 2144 {"WSA AIF_ECHO", NULL, "WSA_MCLK"}, 2145 2146 {"WSA AIF1 PB", NULL, "WSA_MCLK"}, 2147 {"WSA AIF_MIX1 PB", NULL, "WSA_MCLK"}, 2148 2149 {"WSA RX0 MUX", "AIF1_PB", "WSA AIF1 PB"}, 2150 {"WSA RX1 MUX", "AIF1_PB", "WSA AIF1 PB"}, 2151 {"WSA RX_MIX0 MUX", "AIF1_PB", "WSA AIF1 PB"}, 2152 {"WSA RX_MIX1 MUX", "AIF1_PB", "WSA AIF1 PB"}, 2153 2154 {"WSA RX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 2155 {"WSA RX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 2156 {"WSA RX_MIX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 2157 {"WSA RX_MIX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 2158 2159 {"WSA RX0", NULL, "WSA RX0 MUX"}, 2160 {"WSA RX1", NULL, "WSA RX1 MUX"}, 2161 {"WSA RX_MIX0", NULL, "WSA RX_MIX0 MUX"}, 2162 {"WSA RX_MIX1", NULL, "WSA RX_MIX1 MUX"}, 2163 2164 {"WSA RX0", NULL, "WSA_RX0_CLK"}, 2165 {"WSA RX1", NULL, "WSA_RX1_CLK"}, 2166 {"WSA RX_MIX0", NULL, "WSA_RX_MIX0_CLK"}, 2167 {"WSA RX_MIX1", NULL, "WSA_RX_MIX1_CLK"}, 2168 2169 {"WSA_RX0 INP0", "RX0", "WSA RX0"}, 2170 {"WSA_RX0 INP0", "RX1", "WSA RX1"}, 2171 {"WSA_RX0 INP0", "RX_MIX0", "WSA RX_MIX0"}, 2172 {"WSA_RX0 INP0", "RX_MIX1", "WSA RX_MIX1"}, 2173 {"WSA_RX0 INP0", "DEC0", "WSA_TX DEC0_INP"}, 2174 {"WSA_RX0 INP0", "DEC1", "WSA_TX DEC1_INP"}, 2175 {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP0"}, 2176 2177 {"WSA_RX0 INP1", "RX0", "WSA RX0"}, 2178 {"WSA_RX0 INP1", "RX1", "WSA RX1"}, 2179 {"WSA_RX0 INP1", "RX_MIX0", "WSA RX_MIX0"}, 2180 {"WSA_RX0 INP1", "RX_MIX1", "WSA RX_MIX1"}, 2181 {"WSA_RX0 INP1", "DEC0", "WSA_TX DEC0_INP"}, 2182 {"WSA_RX0 INP1", "DEC1", "WSA_TX DEC1_INP"}, 2183 {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP1"}, 2184 2185 {"WSA_RX0 INP2", "RX0", "WSA RX0"}, 2186 {"WSA_RX0 INP2", "RX1", "WSA RX1"}, 2187 {"WSA_RX0 INP2", "RX_MIX0", "WSA RX_MIX0"}, 2188 {"WSA_RX0 INP2", "RX_MIX1", "WSA RX_MIX1"}, 2189 {"WSA_RX0 INP2", "DEC0", "WSA_TX DEC0_INP"}, 2190 {"WSA_RX0 INP2", "DEC1", "WSA_TX DEC1_INP"}, 2191 {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP2"}, 2192 2193 {"WSA_RX0 MIX INP", "RX0", "WSA RX0"}, 2194 {"WSA_RX0 MIX INP", "RX1", "WSA RX1"}, 2195 {"WSA_RX0 MIX INP", "RX_MIX0", "WSA RX_MIX0"}, 2196 {"WSA_RX0 MIX INP", "RX_MIX1", "WSA RX_MIX1"}, 2197 {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX0 MIX INP"}, 2198 2199 {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX INT0 MIX"}, 2200 {"WSA_RX INT0 INTERP", NULL, "WSA_RX INT0 SEC MIX"}, 2201 {"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"}, 2202 {"WSA_RX INT0 INTERP", NULL, "WSA_RX0 INT0 SIDETONE MIX"}, 2203 {"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 INTERP"}, 2204 2205 {"WSA_SPK1 OUT", NULL, "WSA_RX INT0 CHAIN"}, 2206 {"WSA_SPK1 OUT", NULL, "WSA_MCLK"}, 2207 2208 {"WSA_RX1 INP0", "RX0", "WSA RX0"}, 2209 {"WSA_RX1 INP0", "RX1", "WSA RX1"}, 2210 {"WSA_RX1 INP0", "RX_MIX0", "WSA RX_MIX0"}, 2211 {"WSA_RX1 INP0", "RX_MIX1", "WSA RX_MIX1"}, 2212 {"WSA_RX1 INP0", "DEC0", "WSA_TX DEC0_INP"}, 2213 {"WSA_RX1 INP0", "DEC1", "WSA_TX DEC1_INP"}, 2214 {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP0"}, 2215 2216 {"WSA_RX1 INP1", "RX0", "WSA RX0"}, 2217 {"WSA_RX1 INP1", "RX1", "WSA RX1"}, 2218 {"WSA_RX1 INP1", "RX_MIX0", "WSA RX_MIX0"}, 2219 {"WSA_RX1 INP1", "RX_MIX1", "WSA RX_MIX1"}, 2220 {"WSA_RX1 INP1", "DEC0", "WSA_TX DEC0_INP"}, 2221 {"WSA_RX1 INP1", "DEC1", "WSA_TX DEC1_INP"}, 2222 {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP1"}, 2223 2224 {"WSA_RX1 INP2", "RX0", "WSA RX0"}, 2225 {"WSA_RX1 INP2", "RX1", "WSA RX1"}, 2226 {"WSA_RX1 INP2", "RX_MIX0", "WSA RX_MIX0"}, 2227 {"WSA_RX1 INP2", "RX_MIX1", "WSA RX_MIX1"}, 2228 {"WSA_RX1 INP2", "DEC0", "WSA_TX DEC0_INP"}, 2229 {"WSA_RX1 INP2", "DEC1", "WSA_TX DEC1_INP"}, 2230 {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP2"}, 2231 2232 {"WSA_RX1 MIX INP", "RX0", "WSA RX0"}, 2233 {"WSA_RX1 MIX INP", "RX1", "WSA RX1"}, 2234 {"WSA_RX1 MIX INP", "RX_MIX0", "WSA RX_MIX0"}, 2235 {"WSA_RX1 MIX INP", "RX_MIX1", "WSA RX_MIX1"}, 2236 {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX1 MIX INP"}, 2237 2238 {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX INT1 MIX"}, 2239 {"WSA_RX INT1 INTERP", NULL, "WSA_RX INT1 SEC MIX"}, 2240 2241 {"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 INTERP"}, 2242 {"WSA_SPK2 OUT", NULL, "WSA_RX INT1 CHAIN"}, 2243 {"WSA_SPK2 OUT", NULL, "WSA_MCLK"}, 2244 }; 2245 2246 static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable) 2247 { 2248 struct regmap *regmap = wsa->regmap; 2249 2250 if (enable) { 2251 wsa_macro_mclk_enable(wsa, true); 2252 2253 /* reset swr ip */ 2254 if (wsa->reset_swr) 2255 regmap_update_bits(regmap, 2256 CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2257 CDC_WSA_SWR_RST_EN_MASK, 2258 CDC_WSA_SWR_RST_ENABLE); 2259 2260 regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2261 CDC_WSA_SWR_CLK_EN_MASK, 2262 CDC_WSA_SWR_CLK_ENABLE); 2263 2264 /* Bring out of reset */ 2265 if (wsa->reset_swr) 2266 regmap_update_bits(regmap, 2267 CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2268 CDC_WSA_SWR_RST_EN_MASK, 2269 CDC_WSA_SWR_RST_DISABLE); 2270 wsa->reset_swr = false; 2271 } else { 2272 regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2273 CDC_WSA_SWR_CLK_EN_MASK, 0); 2274 wsa_macro_mclk_enable(wsa, false); 2275 } 2276 2277 return 0; 2278 } 2279 2280 static int wsa_macro_component_probe(struct snd_soc_component *comp) 2281 { 2282 struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp); 2283 2284 snd_soc_component_init_regmap(comp, wsa->regmap); 2285 2286 wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB; 2287 2288 /* set SPKR rate to FS_2P4_3P072 */ 2289 snd_soc_component_update_bits(comp, CDC_WSA_RX0_RX_PATH_CFG1, 2290 CDC_WSA_RX_PATH_SPKR_RATE_MASK, 2291 CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072); 2292 2293 snd_soc_component_update_bits(comp, CDC_WSA_RX1_RX_PATH_CFG1, 2294 CDC_WSA_RX_PATH_SPKR_RATE_MASK, 2295 CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072); 2296 2297 wsa_macro_set_spkr_mode(comp, WSA_MACRO_SPKR_MODE_1); 2298 2299 return 0; 2300 } 2301 2302 static int swclk_gate_enable(struct clk_hw *hw) 2303 { 2304 return wsa_swrm_clock(to_wsa_macro(hw), true); 2305 } 2306 2307 static void swclk_gate_disable(struct clk_hw *hw) 2308 { 2309 wsa_swrm_clock(to_wsa_macro(hw), false); 2310 } 2311 2312 static int swclk_gate_is_enabled(struct clk_hw *hw) 2313 { 2314 struct wsa_macro *wsa = to_wsa_macro(hw); 2315 int ret, val; 2316 2317 regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val); 2318 ret = val & BIT(0); 2319 2320 return ret; 2321 } 2322 2323 static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2324 unsigned long parent_rate) 2325 { 2326 return parent_rate / 2; 2327 } 2328 2329 static const struct clk_ops swclk_gate_ops = { 2330 .prepare = swclk_gate_enable, 2331 .unprepare = swclk_gate_disable, 2332 .is_enabled = swclk_gate_is_enabled, 2333 .recalc_rate = swclk_recalc_rate, 2334 }; 2335 2336 static struct clk *wsa_macro_register_mclk_output(struct wsa_macro *wsa) 2337 { 2338 struct device *dev = wsa->dev; 2339 struct device_node *np = dev->of_node; 2340 const char *parent_clk_name; 2341 const char *clk_name = "mclk"; 2342 struct clk_hw *hw; 2343 struct clk_init_data init; 2344 int ret; 2345 2346 parent_clk_name = __clk_get_name(wsa->clks[2].clk); 2347 2348 init.name = clk_name; 2349 init.ops = &swclk_gate_ops; 2350 init.flags = 0; 2351 init.parent_names = &parent_clk_name; 2352 init.num_parents = 1; 2353 wsa->hw.init = &init; 2354 hw = &wsa->hw; 2355 ret = clk_hw_register(wsa->dev, hw); 2356 if (ret) 2357 return ERR_PTR(ret); 2358 2359 of_clk_add_provider(np, of_clk_src_simple_get, hw->clk); 2360 2361 return NULL; 2362 } 2363 2364 static const struct snd_soc_component_driver wsa_macro_component_drv = { 2365 .name = "WSA MACRO", 2366 .probe = wsa_macro_component_probe, 2367 .controls = wsa_macro_snd_controls, 2368 .num_controls = ARRAY_SIZE(wsa_macro_snd_controls), 2369 .dapm_widgets = wsa_macro_dapm_widgets, 2370 .num_dapm_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets), 2371 .dapm_routes = wsa_audio_map, 2372 .num_dapm_routes = ARRAY_SIZE(wsa_audio_map), 2373 }; 2374 2375 static int wsa_macro_probe(struct platform_device *pdev) 2376 { 2377 struct device *dev = &pdev->dev; 2378 struct wsa_macro *wsa; 2379 void __iomem *base; 2380 int ret; 2381 2382 wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL); 2383 if (!wsa) 2384 return -ENOMEM; 2385 2386 wsa->clks[0].id = "macro"; 2387 wsa->clks[1].id = "dcodec"; 2388 wsa->clks[2].id = "mclk"; 2389 wsa->clks[3].id = "npl"; 2390 wsa->clks[4].id = "fsgen"; 2391 2392 ret = devm_clk_bulk_get(dev, WSA_NUM_CLKS_MAX, wsa->clks); 2393 if (ret) { 2394 dev_err(dev, "Error getting WSA Clocks (%d)\n", ret); 2395 return ret; 2396 } 2397 2398 base = devm_platform_ioremap_resource(pdev, 0); 2399 if (IS_ERR(base)) 2400 return PTR_ERR(base); 2401 2402 wsa->regmap = devm_regmap_init_mmio(dev, base, &wsa_regmap_config); 2403 2404 dev_set_drvdata(dev, wsa); 2405 2406 wsa->reset_swr = true; 2407 wsa->dev = dev; 2408 2409 /* set MCLK and NPL rates */ 2410 clk_set_rate(wsa->clks[2].clk, WSA_MACRO_MCLK_FREQ); 2411 clk_set_rate(wsa->clks[3].clk, WSA_MACRO_MCLK_FREQ); 2412 2413 ret = clk_bulk_prepare_enable(WSA_NUM_CLKS_MAX, wsa->clks); 2414 if (ret) 2415 return ret; 2416 2417 wsa_macro_register_mclk_output(wsa); 2418 2419 ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv, 2420 wsa_macro_dai, 2421 ARRAY_SIZE(wsa_macro_dai)); 2422 if (ret) 2423 goto err; 2424 2425 return ret; 2426 err: 2427 clk_bulk_disable_unprepare(WSA_NUM_CLKS_MAX, wsa->clks); 2428 2429 return ret; 2430 2431 } 2432 2433 static int wsa_macro_remove(struct platform_device *pdev) 2434 { 2435 struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev); 2436 2437 of_clk_del_provider(pdev->dev.of_node); 2438 2439 clk_bulk_disable_unprepare(WSA_NUM_CLKS_MAX, wsa->clks); 2440 2441 return 0; 2442 } 2443 2444 static const struct of_device_id wsa_macro_dt_match[] = { 2445 {.compatible = "qcom,sm8250-lpass-wsa-macro"}, 2446 {} 2447 }; 2448 MODULE_DEVICE_TABLE(of, wsa_macro_dt_match); 2449 2450 static struct platform_driver wsa_macro_driver = { 2451 .driver = { 2452 .name = "wsa_macro", 2453 .of_match_table = wsa_macro_dt_match, 2454 }, 2455 .probe = wsa_macro_probe, 2456 .remove = wsa_macro_remove, 2457 }; 2458 2459 module_platform_driver(wsa_macro_driver); 2460 MODULE_DESCRIPTION("WSA macro driver"); 2461 MODULE_LICENSE("GPL"); 2462