1809bcbceSSrinivas Kandagatla // SPDX-License-Identifier: GPL-2.0-only 2809bcbceSSrinivas Kandagatla // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3809bcbceSSrinivas Kandagatla 4809bcbceSSrinivas Kandagatla #include <linux/module.h> 5809bcbceSSrinivas Kandagatla #include <linux/init.h> 6809bcbceSSrinivas Kandagatla #include <linux/io.h> 7809bcbceSSrinivas Kandagatla #include <linux/platform_device.h> 8809bcbceSSrinivas Kandagatla #include <linux/clk.h> 9809bcbceSSrinivas Kandagatla #include <linux/of_clk.h> 10809bcbceSSrinivas Kandagatla #include <linux/clk-provider.h> 11809bcbceSSrinivas Kandagatla #include <sound/soc.h> 12809bcbceSSrinivas Kandagatla #include <sound/soc-dapm.h> 13809bcbceSSrinivas Kandagatla #include <linux/of_platform.h> 14809bcbceSSrinivas Kandagatla #include <sound/tlv.h> 15809bcbceSSrinivas Kandagatla #include "lpass-wsa-macro.h" 16809bcbceSSrinivas Kandagatla 17809bcbceSSrinivas Kandagatla #define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 18809bcbceSSrinivas Kandagatla #define CDC_WSA_MCLK_EN_MASK BIT(0) 19809bcbceSSrinivas Kandagatla #define CDC_WSA_MCLK_ENABLE BIT(0) 20809bcbceSSrinivas Kandagatla #define CDC_WSA_MCLK_DISABLE 0 21809bcbceSSrinivas Kandagatla #define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 22809bcbceSSrinivas Kandagatla #define CDC_WSA_FS_CNT_EN_MASK BIT(0) 23809bcbceSSrinivas Kandagatla #define CDC_WSA_FS_CNT_ENABLE BIT(0) 24809bcbceSSrinivas Kandagatla #define CDC_WSA_FS_CNT_DISABLE 0 25809bcbceSSrinivas Kandagatla #define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL (0x0008) 26809bcbceSSrinivas Kandagatla #define CDC_WSA_SWR_CLK_EN_MASK BIT(0) 27809bcbceSSrinivas Kandagatla #define CDC_WSA_SWR_CLK_ENABLE BIT(0) 28809bcbceSSrinivas Kandagatla #define CDC_WSA_SWR_RST_EN_MASK BIT(1) 29809bcbceSSrinivas Kandagatla #define CDC_WSA_SWR_RST_ENABLE BIT(1) 30809bcbceSSrinivas Kandagatla #define CDC_WSA_SWR_RST_DISABLE 0 31809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_TOP_CFG0 (0x0080) 32809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_TOP_CFG1 (0x0084) 33809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_FREQ_MCLK (0x0088) 34809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_DEBUG_BUS_SEL (0x008C) 35809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_DEBUG_EN0 (0x0090) 36809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_DEBUG_EN1 (0x0094) 37809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_DEBUG_DSM_LB (0x0098) 38809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_RX_I2S_CTL (0x009C) 39809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_TX_I2S_CTL (0x00A0) 40809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_I2S_CLK (0x00A4) 41809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_I2S_RESET (0x00A8) 42809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 (0x0100) 43*7db4c4cdSSrinivas Kandagatla #define CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(2, 0) 44*7db4c4cdSSrinivas Kandagatla #define CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(5, 3) 45809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 (0x0104) 46*7db4c4cdSSrinivas Kandagatla #define CDC_WSA_RX_INTX_2_SEL_MASK GENMASK(2, 0) 47*7db4c4cdSSrinivas Kandagatla #define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(5, 3) 48809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 (0x0108) 49809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 (0x010C) 50809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 (0x0110) 51809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_MIX_TX1_SEL_MASK GENMASK(5, 3) 52809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_MIX_TX1_SEL_SHFT 3 53809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_MIX_TX0_SEL_MASK GENMASK(2, 0) 54809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (0x0114) 55809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (0x0118) 56809bcbceSSrinivas Kandagatla #define CDC_WSA_TX0_SPKR_PROT_PATH_CTL (0x0244) 57809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_RESET_MASK BIT(5) 58809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_RESET BIT(5) 59809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_NO_RESET 0 60809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK BIT(4) 61809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_CLK_ENABLE BIT(4) 62809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0 63809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0) 64809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K 0 65809bcbceSSrinivas Kandagatla #define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (0x0248) 66809bcbceSSrinivas Kandagatla #define CDC_WSA_TX1_SPKR_PROT_PATH_CTL (0x0264) 67809bcbceSSrinivas Kandagatla #define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (0x0268) 68809bcbceSSrinivas Kandagatla #define CDC_WSA_TX2_SPKR_PROT_PATH_CTL (0x0284) 69809bcbceSSrinivas Kandagatla #define CDC_WSA_TX2_SPKR_PROT_PATH_CFG0 (0x0288) 70809bcbceSSrinivas Kandagatla #define CDC_WSA_TX3_SPKR_PROT_PATH_CTL (0x02A4) 71809bcbceSSrinivas Kandagatla #define CDC_WSA_TX3_SPKR_PROT_PATH_CFG0 (0x02A8) 72809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_CFG (0x0340) 73809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_CLR_COMMIT (0x0344) 74809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_PIN1_MASK0 (0x0360) 75809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_PIN1_STATUS0 (0x0368) 76809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_PIN1_CLEAR0 (0x0370) 77809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_PIN2_MASK0 (0x0380) 78809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_PIN2_STATUS0 (0x0388) 79809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_PIN2_CLEAR0 (0x0390) 80809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_LEVEL0 (0x03C0) 81809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_BYPASS0 (0x03C8) 82809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_SET0 (0x03D0) 83809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_CTL (0x0400) 84809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_CLK_EN_MASK BIT(5) 85809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_CLK_ENABLE BIT(5) 86809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_CLK_DISABLE 0 87809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK BIT(4) 88809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_PGA_MUTE_ENABLE BIT(4) 89809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_PGA_MUTE_DISABLE 0 90809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_CFG0 (0x0404) 91809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_COMP_EN_MASK BIT(1) 92809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_COMP_ENABLE BIT(1) 93809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_HD2_EN_MASK BIT(2) 94809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_HD2_ENABLE BIT(2) 95809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_SPKR_RATE_MASK BIT(3) 96809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072 BIT(3) 97809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_CFG1 (0x0408) 98809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_SMART_BST_EN_MASK BIT(0) 99809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_SMART_BST_ENABLE BIT(0) 100809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_SMART_BST_DISABLE 0 101809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_CFG2 (0x040C) 102809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_CFG3 (0x0410) 103809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_DC_DCOEFF_MASK GENMASK(1, 0) 104809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_VOL_CTL (0x0414) 105809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_MIX_CTL (0x0418) 106809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_MIX_CLK_EN_MASK BIT(5) 107809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_MIX_CLK_ENABLE BIT(5) 108809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_MIX_CLK_DISABLE 0 109809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_MIX_CFG (0x041C) 110809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_VOL_MIX_CTL (0x0420) 111809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC0 (0x0424) 112809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC1 (0x0428) 113809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PGA_HALF_DB_MASK BIT(0) 114809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PGA_HALF_DB_ENABLE BIT(0) 115809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PGA_HALF_DB_DISABLE 0 116809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC2 (0x042C) 117809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC3 (0x0430) 118809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_HD2_SCALE_MASK GENMASK(1, 0) 119809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_HD2_ALPHA_MASK GENMASK(5, 2) 120809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC5 (0x0438) 121809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC6 (0x043C) 122809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC7 (0x0440) 123809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_MIX_SEC0 (0x0444) 124809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_MIX_SEC1 (0x0448) 125809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_DSMDEM_CTL (0x044C) 126809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_DSMDEM_CLK_EN_MASK BIT(0) 127809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_DSMDEM_CLK_ENABLE BIT(0) 128809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_CTL (0x0480) 129809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_CFG0 (0x0484) 130809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_CFG1 (0x0488) 131809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_CFG2 (0x048C) 132809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_CFG3 (0x0490) 133809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_VOL_CTL (0x0494) 134809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_MIX_CTL (0x0498) 135809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_MIX_CFG (0x049C) 136809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_VOL_MIX_CTL (0x04A0) 137809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC0 (0x04A4) 138809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC1 (0x04A8) 139809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC2 (0x04AC) 140809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC3 (0x04B0) 141809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC5 (0x04B8) 142809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC6 (0x04BC) 143809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC7 (0x04C0) 144809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_MIX_SEC0 (0x04C4) 145809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_MIX_SEC1 (0x04C8) 146809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_DSMDEM_CTL (0x04CC) 147809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST0_BOOST_PATH_CTL (0x0500) 148809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST_PATH_CLK_EN_MASK BIT(4) 149809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST_PATH_CLK_ENABLE BIT(4) 150809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST_PATH_CLK_DISABLE 0 151809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST0_BOOST_CTL (0x0504) 152809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST0_BOOST_CFG1 (0x0508) 153809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST0_BOOST_CFG2 (0x050C) 154809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST1_BOOST_PATH_CTL (0x0540) 155809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST1_BOOST_CTL (0x0544) 156809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST1_BOOST_CFG1 (0x0548) 157809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST1_BOOST_CFG2 (0x054C) 158809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL0 (0x0580) 159809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER_CLK_EN_MASK BIT(0) 160809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER_CLK_ENABLE BIT(0) 161809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER_SOFT_RST_MASK BIT(1) 162809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER_SOFT_RST_ENABLE BIT(1) 163809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER_HALT_MASK BIT(2) 164809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER_HALT BIT(2) 165809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL1 (0x0584) 166809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL2 (0x0588) 167809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL3 (0x058C) 168809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL4 (0x0590) 169809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL5 (0x0594) 170809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL6 (0x0598) 171809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL7 (0x059C) 172809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL0 (0x05C0) 173809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL1 (0x05C4) 174809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL2 (0x05C8) 175809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL3 (0x05CC) 176809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL4 (0x05D0) 177809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL5 (0x05D4) 178809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL6 (0x05D8) 179809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL7 (0x05DC) 180809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP0_CRC (0x0600) 181809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP_CLK_EN_MASK BIT(0) 182809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP_CLK_ENABLE BIT(0) 183809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (0x0604) 184809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP_EN_MASK BIT(0) 185809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP_ENABLE BIT(0) 186809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP1_CRC (0x0640) 187809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (0x0644) 188809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL (0x0680) 189809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ_EC_CLK_EN_MASK BIT(0) 190809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ_EC_CLK_ENABLE BIT(0) 191809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 (0x0684) 192809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK GENMASK(4, 1) 193809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K BIT(3) 194809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL (0x06C0) 195809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 (0x06C4) 196809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL (0x0700) 197809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_CTL0 (0x0704) 198809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_CTL1 (0x0708) 199809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_FIFO_CTL (0x070C) 200809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB (0x0710) 201809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB (0x0714) 202809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB (0x0718) 203809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB (0x071C) 204809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_STATUS_FIFO (0x0720) 205809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL (0x0740) 206809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_CTL0 (0x0744) 207809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_CTL1 (0x0748) 208809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_FIFO_CTL (0x074C) 209809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB (0x0750) 210809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB (0x0754) 211809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB (0x0758) 212809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB (0x075C) 213809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO (0x0760) 214809bcbceSSrinivas Kandagatla #define WSA_MAX_OFFSET (0x0760) 215809bcbceSSrinivas Kandagatla 216809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 217809bcbceSSrinivas Kandagatla SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 218809bcbceSSrinivas Kandagatla SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 219809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\ 220809bcbceSSrinivas Kandagatla SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 221809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 222809bcbceSSrinivas Kandagatla SNDRV_PCM_FMTBIT_S24_LE |\ 223809bcbceSSrinivas Kandagatla SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 224809bcbceSSrinivas Kandagatla 225809bcbceSSrinivas Kandagatla #define WSA_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 226809bcbceSSrinivas Kandagatla SNDRV_PCM_RATE_48000) 227809bcbceSSrinivas Kandagatla #define WSA_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 228809bcbceSSrinivas Kandagatla SNDRV_PCM_FMTBIT_S24_LE |\ 229809bcbceSSrinivas Kandagatla SNDRV_PCM_FMTBIT_S24_3LE) 230809bcbceSSrinivas Kandagatla 231809bcbceSSrinivas Kandagatla #define NUM_INTERPOLATORS 2 232809bcbceSSrinivas Kandagatla #define WSA_NUM_CLKS_MAX 5 233809bcbceSSrinivas Kandagatla #define WSA_MACRO_MCLK_FREQ 19200000 234809bcbceSSrinivas Kandagatla #define WSA_MACRO_MUX_INP_MASK2 0x38 235809bcbceSSrinivas Kandagatla #define WSA_MACRO_MUX_CFG_OFFSET 0x8 236809bcbceSSrinivas Kandagatla #define WSA_MACRO_MUX_CFG1_OFFSET 0x4 237809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_COMP_OFFSET 0x40 238809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_SOFTCLIP_OFFSET 0x40 239809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_PATH_OFFSET 0x80 240809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10 241809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C 242809bcbceSSrinivas Kandagatla #define WSA_MACRO_FS_RATE_MASK 0x0F 243809bcbceSSrinivas Kandagatla #define WSA_MACRO_EC_MIX_TX0_MASK 0x03 244809bcbceSSrinivas Kandagatla #define WSA_MACRO_EC_MIX_TX1_MASK 0x18 245809bcbceSSrinivas Kandagatla #define WSA_MACRO_MAX_DMA_CH_PER_PORT 0x2 246809bcbceSSrinivas Kandagatla 247809bcbceSSrinivas Kandagatla enum { 248809bcbceSSrinivas Kandagatla WSA_MACRO_GAIN_OFFSET_M1P5_DB, 249809bcbceSSrinivas Kandagatla WSA_MACRO_GAIN_OFFSET_0_DB, 250809bcbceSSrinivas Kandagatla }; 251809bcbceSSrinivas Kandagatla enum { 252809bcbceSSrinivas Kandagatla WSA_MACRO_RX0 = 0, 253809bcbceSSrinivas Kandagatla WSA_MACRO_RX1, 254809bcbceSSrinivas Kandagatla WSA_MACRO_RX_MIX, 255809bcbceSSrinivas Kandagatla WSA_MACRO_RX_MIX0 = WSA_MACRO_RX_MIX, 256809bcbceSSrinivas Kandagatla WSA_MACRO_RX_MIX1, 257809bcbceSSrinivas Kandagatla WSA_MACRO_RX_MAX, 258809bcbceSSrinivas Kandagatla }; 259809bcbceSSrinivas Kandagatla 260809bcbceSSrinivas Kandagatla enum { 261809bcbceSSrinivas Kandagatla WSA_MACRO_TX0 = 0, 262809bcbceSSrinivas Kandagatla WSA_MACRO_TX1, 263809bcbceSSrinivas Kandagatla WSA_MACRO_TX_MAX, 264809bcbceSSrinivas Kandagatla }; 265809bcbceSSrinivas Kandagatla 266809bcbceSSrinivas Kandagatla enum { 267809bcbceSSrinivas Kandagatla WSA_MACRO_EC0_MUX = 0, 268809bcbceSSrinivas Kandagatla WSA_MACRO_EC1_MUX, 269809bcbceSSrinivas Kandagatla WSA_MACRO_EC_MUX_MAX, 270809bcbceSSrinivas Kandagatla }; 271809bcbceSSrinivas Kandagatla 272809bcbceSSrinivas Kandagatla enum { 273809bcbceSSrinivas Kandagatla WSA_MACRO_COMP1, /* SPK_L */ 274809bcbceSSrinivas Kandagatla WSA_MACRO_COMP2, /* SPK_R */ 275809bcbceSSrinivas Kandagatla WSA_MACRO_COMP_MAX 276809bcbceSSrinivas Kandagatla }; 277809bcbceSSrinivas Kandagatla 278809bcbceSSrinivas Kandagatla enum { 279809bcbceSSrinivas Kandagatla WSA_MACRO_SOFTCLIP0, /* RX0 */ 280809bcbceSSrinivas Kandagatla WSA_MACRO_SOFTCLIP1, /* RX1 */ 281809bcbceSSrinivas Kandagatla WSA_MACRO_SOFTCLIP_MAX 282809bcbceSSrinivas Kandagatla }; 283809bcbceSSrinivas Kandagatla 284809bcbceSSrinivas Kandagatla enum { 285809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_ZERO = 0, 286809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_RX0, 287809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_RX1, 288809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_RX2, 289809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_RX3, 290809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_DEC0, 291809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_DEC1, 292809bcbceSSrinivas Kandagatla }; 293809bcbceSSrinivas Kandagatla 294809bcbceSSrinivas Kandagatla enum { 295809bcbceSSrinivas Kandagatla INTn_2_INP_SEL_ZERO = 0, 296809bcbceSSrinivas Kandagatla INTn_2_INP_SEL_RX0, 297809bcbceSSrinivas Kandagatla INTn_2_INP_SEL_RX1, 298809bcbceSSrinivas Kandagatla INTn_2_INP_SEL_RX2, 299809bcbceSSrinivas Kandagatla INTn_2_INP_SEL_RX3, 300809bcbceSSrinivas Kandagatla }; 301809bcbceSSrinivas Kandagatla 302809bcbceSSrinivas Kandagatla struct interp_sample_rate { 303809bcbceSSrinivas Kandagatla int sample_rate; 304809bcbceSSrinivas Kandagatla int rate_val; 305809bcbceSSrinivas Kandagatla }; 306809bcbceSSrinivas Kandagatla 307809bcbceSSrinivas Kandagatla static struct interp_sample_rate int_prim_sample_rate_val[] = { 308809bcbceSSrinivas Kandagatla {8000, 0x0}, /* 8K */ 309809bcbceSSrinivas Kandagatla {16000, 0x1}, /* 16K */ 310809bcbceSSrinivas Kandagatla {24000, -EINVAL},/* 24K */ 311809bcbceSSrinivas Kandagatla {32000, 0x3}, /* 32K */ 312809bcbceSSrinivas Kandagatla {48000, 0x4}, /* 48K */ 313809bcbceSSrinivas Kandagatla {96000, 0x5}, /* 96K */ 314809bcbceSSrinivas Kandagatla {192000, 0x6}, /* 192K */ 315809bcbceSSrinivas Kandagatla {384000, 0x7}, /* 384K */ 316809bcbceSSrinivas Kandagatla {44100, 0x8}, /* 44.1K */ 317809bcbceSSrinivas Kandagatla }; 318809bcbceSSrinivas Kandagatla 319809bcbceSSrinivas Kandagatla static struct interp_sample_rate int_mix_sample_rate_val[] = { 320809bcbceSSrinivas Kandagatla {48000, 0x4}, /* 48K */ 321809bcbceSSrinivas Kandagatla {96000, 0x5}, /* 96K */ 322809bcbceSSrinivas Kandagatla {192000, 0x6}, /* 192K */ 323809bcbceSSrinivas Kandagatla }; 324809bcbceSSrinivas Kandagatla 325809bcbceSSrinivas Kandagatla enum { 326809bcbceSSrinivas Kandagatla WSA_MACRO_AIF_INVALID = 0, 327809bcbceSSrinivas Kandagatla WSA_MACRO_AIF1_PB, 328809bcbceSSrinivas Kandagatla WSA_MACRO_AIF_MIX1_PB, 329809bcbceSSrinivas Kandagatla WSA_MACRO_AIF_VI, 330809bcbceSSrinivas Kandagatla WSA_MACRO_AIF_ECHO, 331809bcbceSSrinivas Kandagatla WSA_MACRO_MAX_DAIS, 332809bcbceSSrinivas Kandagatla }; 333809bcbceSSrinivas Kandagatla 334809bcbceSSrinivas Kandagatla struct wsa_macro { 335809bcbceSSrinivas Kandagatla struct device *dev; 336809bcbceSSrinivas Kandagatla int comp_enabled[WSA_MACRO_COMP_MAX]; 337809bcbceSSrinivas Kandagatla int ec_hq[WSA_MACRO_RX1 + 1]; 338809bcbceSSrinivas Kandagatla u16 prim_int_users[WSA_MACRO_RX1 + 1]; 339809bcbceSSrinivas Kandagatla u16 wsa_mclk_users; 340809bcbceSSrinivas Kandagatla bool reset_swr; 341809bcbceSSrinivas Kandagatla unsigned long active_ch_mask[WSA_MACRO_MAX_DAIS]; 342809bcbceSSrinivas Kandagatla unsigned long active_ch_cnt[WSA_MACRO_MAX_DAIS]; 343809bcbceSSrinivas Kandagatla int rx_port_value[WSA_MACRO_RX_MAX]; 344809bcbceSSrinivas Kandagatla int ear_spkr_gain; 345809bcbceSSrinivas Kandagatla int spkr_gain_offset; 346809bcbceSSrinivas Kandagatla int spkr_mode; 347809bcbceSSrinivas Kandagatla int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX]; 348809bcbceSSrinivas Kandagatla int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX]; 349809bcbceSSrinivas Kandagatla struct regmap *regmap; 350809bcbceSSrinivas Kandagatla struct clk_bulk_data clks[WSA_NUM_CLKS_MAX]; 351809bcbceSSrinivas Kandagatla struct clk_hw hw; 352809bcbceSSrinivas Kandagatla }; 353809bcbceSSrinivas Kandagatla #define to_wsa_macro(_hw) container_of(_hw, struct wsa_macro, hw) 354809bcbceSSrinivas Kandagatla 355809bcbceSSrinivas Kandagatla static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 356809bcbceSSrinivas Kandagatla 3572c4066e5SSrinivas Kandagatla static const char *const rx_text[] = { 3582c4066e5SSrinivas Kandagatla "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "DEC0", "DEC1" 3592c4066e5SSrinivas Kandagatla }; 3602c4066e5SSrinivas Kandagatla 3612c4066e5SSrinivas Kandagatla static const char *const rx_mix_text[] = { 3622c4066e5SSrinivas Kandagatla "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1" 3632c4066e5SSrinivas Kandagatla }; 3642c4066e5SSrinivas Kandagatla 3652c4066e5SSrinivas Kandagatla static const char *const rx_mix_ec_text[] = { 3662c4066e5SSrinivas Kandagatla "ZERO", "RX_MIX_TX0", "RX_MIX_TX1" 3672c4066e5SSrinivas Kandagatla }; 3682c4066e5SSrinivas Kandagatla 3692c4066e5SSrinivas Kandagatla static const char *const rx_mux_text[] = { 3702c4066e5SSrinivas Kandagatla "ZERO", "AIF1_PB", "AIF_MIX1_PB" 3712c4066e5SSrinivas Kandagatla }; 3722c4066e5SSrinivas Kandagatla 3732c4066e5SSrinivas Kandagatla static const char *const rx_sidetone_mix_text[] = { 3742c4066e5SSrinivas Kandagatla "ZERO", "SRC0" 3752c4066e5SSrinivas Kandagatla }; 3762c4066e5SSrinivas Kandagatla 377809bcbceSSrinivas Kandagatla static const char * const wsa_macro_ear_spkr_pa_gain_text[] = { 378809bcbceSSrinivas Kandagatla "G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB", 379809bcbceSSrinivas Kandagatla "G_4_DB", "G_5_DB", "G_6_DB" 380809bcbceSSrinivas Kandagatla }; 381809bcbceSSrinivas Kandagatla 382809bcbceSSrinivas Kandagatla static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum, 383809bcbceSSrinivas Kandagatla wsa_macro_ear_spkr_pa_gain_text); 384809bcbceSSrinivas Kandagatla 3852c4066e5SSrinivas Kandagatla /* RX INT0 */ 3862c4066e5SSrinivas Kandagatla static const struct soc_enum rx0_prim_inp0_chain_enum = 3872c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 3882c4066e5SSrinivas Kandagatla 0, 7, rx_text); 3892c4066e5SSrinivas Kandagatla 3902c4066e5SSrinivas Kandagatla static const struct soc_enum rx0_prim_inp1_chain_enum = 3912c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 3922c4066e5SSrinivas Kandagatla 3, 7, rx_text); 3932c4066e5SSrinivas Kandagatla 3942c4066e5SSrinivas Kandagatla static const struct soc_enum rx0_prim_inp2_chain_enum = 3952c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 3962c4066e5SSrinivas Kandagatla 3, 7, rx_text); 3972c4066e5SSrinivas Kandagatla 3982c4066e5SSrinivas Kandagatla static const struct soc_enum rx0_mix_chain_enum = 3992c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 4002c4066e5SSrinivas Kandagatla 0, 5, rx_mix_text); 4012c4066e5SSrinivas Kandagatla 4022c4066e5SSrinivas Kandagatla static const struct soc_enum rx0_sidetone_mix_enum = 4032c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text); 4042c4066e5SSrinivas Kandagatla 4052c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx0_prim_inp0_mux = 4062c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum); 4072c4066e5SSrinivas Kandagatla 4082c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx0_prim_inp1_mux = 4092c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum); 4102c4066e5SSrinivas Kandagatla 4112c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx0_prim_inp2_mux = 4122c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum); 4132c4066e5SSrinivas Kandagatla 4142c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx0_mix_mux = 4152c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum); 4162c4066e5SSrinivas Kandagatla 4172c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx0_sidetone_mix_mux = 4182c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum); 4192c4066e5SSrinivas Kandagatla 4202c4066e5SSrinivas Kandagatla /* RX INT1 */ 4212c4066e5SSrinivas Kandagatla static const struct soc_enum rx1_prim_inp0_chain_enum = 4222c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 4232c4066e5SSrinivas Kandagatla 0, 7, rx_text); 4242c4066e5SSrinivas Kandagatla 4252c4066e5SSrinivas Kandagatla static const struct soc_enum rx1_prim_inp1_chain_enum = 4262c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 4272c4066e5SSrinivas Kandagatla 3, 7, rx_text); 4282c4066e5SSrinivas Kandagatla 4292c4066e5SSrinivas Kandagatla static const struct soc_enum rx1_prim_inp2_chain_enum = 4302c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 4312c4066e5SSrinivas Kandagatla 3, 7, rx_text); 4322c4066e5SSrinivas Kandagatla 4332c4066e5SSrinivas Kandagatla static const struct soc_enum rx1_mix_chain_enum = 4342c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 4352c4066e5SSrinivas Kandagatla 0, 5, rx_mix_text); 4362c4066e5SSrinivas Kandagatla 4372c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx1_prim_inp0_mux = 4382c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum); 4392c4066e5SSrinivas Kandagatla 4402c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx1_prim_inp1_mux = 4412c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum); 4422c4066e5SSrinivas Kandagatla 4432c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx1_prim_inp2_mux = 4442c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum); 4452c4066e5SSrinivas Kandagatla 4462c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx1_mix_mux = 4472c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum); 4482c4066e5SSrinivas Kandagatla 4492c4066e5SSrinivas Kandagatla static const struct soc_enum rx_mix_ec0_enum = 4502c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 4512c4066e5SSrinivas Kandagatla 0, 3, rx_mix_ec_text); 4522c4066e5SSrinivas Kandagatla 4532c4066e5SSrinivas Kandagatla static const struct soc_enum rx_mix_ec1_enum = 4542c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 4552c4066e5SSrinivas Kandagatla 3, 3, rx_mix_ec_text); 4562c4066e5SSrinivas Kandagatla 4572c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx_mix_ec0_mux = 4582c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum); 4592c4066e5SSrinivas Kandagatla 4602c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx_mix_ec1_mux = 4612c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum); 4622c4066e5SSrinivas Kandagatla 463809bcbceSSrinivas Kandagatla static const struct reg_default wsa_defaults[] = { 464809bcbceSSrinivas Kandagatla /* WSA Macro */ 465809bcbceSSrinivas Kandagatla { CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, 466809bcbceSSrinivas Kandagatla { CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, 467809bcbceSSrinivas Kandagatla { CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 468809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_TOP_CFG0, 0x00}, 469809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_TOP_CFG1, 0x00}, 470809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_FREQ_MCLK, 0x00}, 471809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00}, 472809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_DEBUG_EN0, 0x00}, 473809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_DEBUG_EN1, 0x00}, 474809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_DEBUG_DSM_LB, 0x88}, 475809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_RX_I2S_CTL, 0x0C}, 476809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_TX_I2S_CTL, 0x0C}, 477809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_I2S_CLK, 0x02}, 478809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_I2S_RESET, 0x00}, 479809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00}, 480809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00}, 481809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00}, 482809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00}, 483809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00}, 484809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00}, 485809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00}, 486809bcbceSSrinivas Kandagatla { CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02}, 487809bcbceSSrinivas Kandagatla { CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00}, 488809bcbceSSrinivas Kandagatla { CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02}, 489809bcbceSSrinivas Kandagatla { CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00}, 490809bcbceSSrinivas Kandagatla { CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02}, 491809bcbceSSrinivas Kandagatla { CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00}, 492809bcbceSSrinivas Kandagatla { CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02}, 493809bcbceSSrinivas Kandagatla { CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00}, 494809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_CFG, 0x00}, 495809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00}, 496809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF}, 497809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00}, 498809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00}, 499809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF}, 500809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00}, 501809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00}, 502809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_LEVEL0, 0x00}, 503809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_BYPASS0, 0x00}, 504809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_SET0, 0x00}, 505809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_CTL, 0x04}, 506809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_CFG0, 0x00}, 507809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_CFG1, 0x64}, 508809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_CFG2, 0x8F}, 509809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_CFG3, 0x00}, 510809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_VOL_CTL, 0x00}, 511809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04}, 512809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E}, 513809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00}, 514809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC0, 0x04}, 515809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC1, 0x08}, 516809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC2, 0x00}, 517809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC3, 0x00}, 518809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC5, 0x00}, 519809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC6, 0x00}, 520809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC7, 0x00}, 521809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08}, 522809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00}, 523809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00}, 524809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_CFG0, 0x00}, 525809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_CFG1, 0x64}, 526809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_CFG2, 0x8F}, 527809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_CFG3, 0x00}, 528809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_VOL_CTL, 0x00}, 529809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04}, 530809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E}, 531809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00}, 532809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC0, 0x04}, 533809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC1, 0x08}, 534809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC2, 0x00}, 535809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC3, 0x00}, 536809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC5, 0x00}, 537809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC6, 0x00}, 538809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC7, 0x00}, 539809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08}, 540809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00}, 541809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00}, 542809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00}, 543809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST0_BOOST_CTL, 0xD0}, 544809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST0_BOOST_CFG1, 0x89}, 545809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST0_BOOST_CFG2, 0x04}, 546809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00}, 547809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST1_BOOST_CTL, 0xD0}, 548809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST1_BOOST_CFG1, 0x89}, 549809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST1_BOOST_CFG2, 0x04}, 550809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL0, 0x60}, 551809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL1, 0xDB}, 552809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL2, 0xFF}, 553809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL3, 0x35}, 554809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL4, 0xFF}, 555809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL5, 0x00}, 556809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL6, 0x01}, 557809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL7, 0x28}, 558809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL0, 0x60}, 559809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL1, 0xDB}, 560809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL2, 0xFF}, 561809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL3, 0x35}, 562809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL4, 0xFF}, 563809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL5, 0x00}, 564809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL6, 0x01}, 565809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL7, 0x28}, 566809bcbceSSrinivas Kandagatla { CDC_WSA_SOFTCLIP0_CRC, 0x00}, 567809bcbceSSrinivas Kandagatla { CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38}, 568809bcbceSSrinivas Kandagatla { CDC_WSA_SOFTCLIP1_CRC, 0x00}, 569809bcbceSSrinivas Kandagatla { CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38}, 570809bcbceSSrinivas Kandagatla { CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00}, 571809bcbceSSrinivas Kandagatla { CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01}, 572809bcbceSSrinivas Kandagatla { CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00}, 573809bcbceSSrinivas Kandagatla { CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01}, 574809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00}, 575809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_CTL0, 0x00}, 576809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_CTL1, 0x00}, 577809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8}, 578809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00}, 579809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00}, 580809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00}, 581809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00}, 582809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00}, 583809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00}, 584809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_CTL0, 0x00}, 585809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_CTL1, 0x00}, 586809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8}, 587809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00}, 588809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00}, 589809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00}, 590809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00}, 591809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00}, 592809bcbceSSrinivas Kandagatla }; 593809bcbceSSrinivas Kandagatla 594809bcbceSSrinivas Kandagatla static bool wsa_is_wronly_register(struct device *dev, 595809bcbceSSrinivas Kandagatla unsigned int reg) 596809bcbceSSrinivas Kandagatla { 597809bcbceSSrinivas Kandagatla switch (reg) { 598809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_CLR_COMMIT: 599809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN1_CLEAR0: 600809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN2_CLEAR0: 601809bcbceSSrinivas Kandagatla return true; 602809bcbceSSrinivas Kandagatla } 603809bcbceSSrinivas Kandagatla 604809bcbceSSrinivas Kandagatla return false; 605809bcbceSSrinivas Kandagatla } 606809bcbceSSrinivas Kandagatla 607809bcbceSSrinivas Kandagatla static bool wsa_is_rw_register(struct device *dev, unsigned int reg) 608809bcbceSSrinivas Kandagatla { 609809bcbceSSrinivas Kandagatla switch (reg) { 610809bcbceSSrinivas Kandagatla case CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL: 611809bcbceSSrinivas Kandagatla case CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL: 612809bcbceSSrinivas Kandagatla case CDC_WSA_CLK_RST_CTRL_SWR_CONTROL: 613809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_TOP_CFG0: 614809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_TOP_CFG1: 615809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_FREQ_MCLK: 616809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_DEBUG_BUS_SEL: 617809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_DEBUG_EN0: 618809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_DEBUG_EN1: 619809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_DEBUG_DSM_LB: 620809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_RX_I2S_CTL: 621809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_TX_I2S_CTL: 622809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_I2S_CLK: 623809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_I2S_RESET: 624809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_RX_INT0_CFG0: 625809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_RX_INT0_CFG1: 626809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_RX_INT1_CFG0: 627809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_RX_INT1_CFG1: 628809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_RX_MIX_CFG0: 629809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_RX_EC_CFG0: 630809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0: 631809bcbceSSrinivas Kandagatla case CDC_WSA_TX0_SPKR_PROT_PATH_CTL: 632809bcbceSSrinivas Kandagatla case CDC_WSA_TX0_SPKR_PROT_PATH_CFG0: 633809bcbceSSrinivas Kandagatla case CDC_WSA_TX1_SPKR_PROT_PATH_CTL: 634809bcbceSSrinivas Kandagatla case CDC_WSA_TX1_SPKR_PROT_PATH_CFG0: 635809bcbceSSrinivas Kandagatla case CDC_WSA_TX2_SPKR_PROT_PATH_CTL: 636809bcbceSSrinivas Kandagatla case CDC_WSA_TX2_SPKR_PROT_PATH_CFG0: 637809bcbceSSrinivas Kandagatla case CDC_WSA_TX3_SPKR_PROT_PATH_CTL: 638809bcbceSSrinivas Kandagatla case CDC_WSA_TX3_SPKR_PROT_PATH_CFG0: 639809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_CFG: 640809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN1_MASK0: 641809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN2_MASK0: 642809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_LEVEL0: 643809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_BYPASS0: 644809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_SET0: 645809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_CTL: 646809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_CFG0: 647809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_CFG1: 648809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_CFG2: 649809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_CFG3: 650809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_VOL_CTL: 651809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_MIX_CTL: 652809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_MIX_CFG: 653809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_VOL_MIX_CTL: 654809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC0: 655809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC1: 656809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC2: 657809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC3: 658809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC5: 659809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC6: 660809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC7: 661809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_MIX_SEC0: 662809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_MIX_SEC1: 663809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_DSMDEM_CTL: 664809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_CTL: 665809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_CFG0: 666809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_CFG1: 667809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_CFG2: 668809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_CFG3: 669809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_VOL_CTL: 670809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_MIX_CTL: 671809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_MIX_CFG: 672809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_VOL_MIX_CTL: 673809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC0: 674809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC1: 675809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC2: 676809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC3: 677809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC5: 678809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC6: 679809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC7: 680809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_MIX_SEC0: 681809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_MIX_SEC1: 682809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_DSMDEM_CTL: 683809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST0_BOOST_PATH_CTL: 684809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST0_BOOST_CTL: 685809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST0_BOOST_CFG1: 686809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST0_BOOST_CFG2: 687809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST1_BOOST_PATH_CTL: 688809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST1_BOOST_CTL: 689809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST1_BOOST_CFG1: 690809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST1_BOOST_CFG2: 691809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL0: 692809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL1: 693809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL2: 694809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL3: 695809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL4: 696809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL5: 697809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL7: 698809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL0: 699809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL1: 700809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL2: 701809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL3: 702809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL4: 703809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL5: 704809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL7: 705809bcbceSSrinivas Kandagatla case CDC_WSA_SOFTCLIP0_CRC: 706809bcbceSSrinivas Kandagatla case CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL: 707809bcbceSSrinivas Kandagatla case CDC_WSA_SOFTCLIP1_CRC: 708809bcbceSSrinivas Kandagatla case CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL: 709809bcbceSSrinivas Kandagatla case CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL: 710809bcbceSSrinivas Kandagatla case CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0: 711809bcbceSSrinivas Kandagatla case CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL: 712809bcbceSSrinivas Kandagatla case CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0: 713809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL: 714809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_CTL0: 715809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_CTL1: 716809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_FIFO_CTL: 717809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL: 718809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_CTL0: 719809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_CTL1: 720809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_FIFO_CTL: 721809bcbceSSrinivas Kandagatla return true; 722809bcbceSSrinivas Kandagatla } 723809bcbceSSrinivas Kandagatla 724809bcbceSSrinivas Kandagatla return false; 725809bcbceSSrinivas Kandagatla } 726809bcbceSSrinivas Kandagatla 727809bcbceSSrinivas Kandagatla static bool wsa_is_writeable_register(struct device *dev, unsigned int reg) 728809bcbceSSrinivas Kandagatla { 729809bcbceSSrinivas Kandagatla bool ret; 730809bcbceSSrinivas Kandagatla 731809bcbceSSrinivas Kandagatla ret = wsa_is_rw_register(dev, reg); 732809bcbceSSrinivas Kandagatla if (!ret) 733809bcbceSSrinivas Kandagatla return wsa_is_wronly_register(dev, reg); 734809bcbceSSrinivas Kandagatla 735809bcbceSSrinivas Kandagatla return ret; 736809bcbceSSrinivas Kandagatla } 737809bcbceSSrinivas Kandagatla 738809bcbceSSrinivas Kandagatla static bool wsa_is_readable_register(struct device *dev, unsigned int reg) 739809bcbceSSrinivas Kandagatla { 740809bcbceSSrinivas Kandagatla switch (reg) { 741809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_CLR_COMMIT: 742809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN1_CLEAR0: 743809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN2_CLEAR0: 744809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN1_STATUS0: 745809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN2_STATUS0: 746809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL6: 747809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL6: 748809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: 749809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: 750809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: 751809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB: 752809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO: 753809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB: 754809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB: 755809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB: 756809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB: 757809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO: 758809bcbceSSrinivas Kandagatla return true; 759809bcbceSSrinivas Kandagatla } 760809bcbceSSrinivas Kandagatla 761809bcbceSSrinivas Kandagatla return wsa_is_rw_register(dev, reg); 762809bcbceSSrinivas Kandagatla } 763809bcbceSSrinivas Kandagatla 764809bcbceSSrinivas Kandagatla static bool wsa_is_volatile_register(struct device *dev, unsigned int reg) 765809bcbceSSrinivas Kandagatla { 766809bcbceSSrinivas Kandagatla /* Update volatile list for rx/tx macros */ 767809bcbceSSrinivas Kandagatla switch (reg) { 768809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN1_STATUS0: 769809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN2_STATUS0: 770809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL6: 771809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL6: 772809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: 773809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: 774809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: 775809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB: 776809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO: 777809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB: 778809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB: 779809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB: 780809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB: 781809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO: 782809bcbceSSrinivas Kandagatla return true; 783809bcbceSSrinivas Kandagatla } 784809bcbceSSrinivas Kandagatla return false; 785809bcbceSSrinivas Kandagatla } 786809bcbceSSrinivas Kandagatla 787809bcbceSSrinivas Kandagatla static const struct regmap_config wsa_regmap_config = { 788809bcbceSSrinivas Kandagatla .name = "wsa_macro", 789809bcbceSSrinivas Kandagatla .reg_bits = 16, 790809bcbceSSrinivas Kandagatla .val_bits = 32, /* 8 but with 32 bit read/write */ 791809bcbceSSrinivas Kandagatla .reg_stride = 4, 792809bcbceSSrinivas Kandagatla .cache_type = REGCACHE_FLAT, 793809bcbceSSrinivas Kandagatla .reg_defaults = wsa_defaults, 794809bcbceSSrinivas Kandagatla .num_reg_defaults = ARRAY_SIZE(wsa_defaults), 795809bcbceSSrinivas Kandagatla .max_register = WSA_MAX_OFFSET, 796809bcbceSSrinivas Kandagatla .writeable_reg = wsa_is_writeable_register, 797809bcbceSSrinivas Kandagatla .volatile_reg = wsa_is_volatile_register, 798809bcbceSSrinivas Kandagatla .readable_reg = wsa_is_readable_register, 799809bcbceSSrinivas Kandagatla }; 800809bcbceSSrinivas Kandagatla 801809bcbceSSrinivas Kandagatla /** 802809bcbceSSrinivas Kandagatla * wsa_macro_set_spkr_mode - Configures speaker compander and smartboost 803809bcbceSSrinivas Kandagatla * settings based on speaker mode. 804809bcbceSSrinivas Kandagatla * 805809bcbceSSrinivas Kandagatla * @component: codec instance 806809bcbceSSrinivas Kandagatla * @mode: Indicates speaker configuration mode. 807809bcbceSSrinivas Kandagatla * 808809bcbceSSrinivas Kandagatla * Returns 0 on success or -EINVAL on error. 809809bcbceSSrinivas Kandagatla */ 810809bcbceSSrinivas Kandagatla int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode) 811809bcbceSSrinivas Kandagatla { 812809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 813809bcbceSSrinivas Kandagatla 814809bcbceSSrinivas Kandagatla wsa->spkr_mode = mode; 815809bcbceSSrinivas Kandagatla 816809bcbceSSrinivas Kandagatla switch (mode) { 817809bcbceSSrinivas Kandagatla case WSA_MACRO_SPKR_MODE_1: 818809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00); 819809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00); 820809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00); 821809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00); 822809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44); 823809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44); 824809bcbceSSrinivas Kandagatla break; 825809bcbceSSrinivas Kandagatla default: 826809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80); 827809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80); 828809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01); 829809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01); 830809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58); 831809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58); 832809bcbceSSrinivas Kandagatla break; 833809bcbceSSrinivas Kandagatla } 834809bcbceSSrinivas Kandagatla return 0; 835809bcbceSSrinivas Kandagatla } 836809bcbceSSrinivas Kandagatla EXPORT_SYMBOL(wsa_macro_set_spkr_mode); 837809bcbceSSrinivas Kandagatla 838809bcbceSSrinivas Kandagatla static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, 839809bcbceSSrinivas Kandagatla u8 int_prim_fs_rate_reg_val, 840809bcbceSSrinivas Kandagatla u32 sample_rate) 841809bcbceSSrinivas Kandagatla { 842809bcbceSSrinivas Kandagatla u8 int_1_mix1_inp; 843809bcbceSSrinivas Kandagatla u32 j, port; 844809bcbceSSrinivas Kandagatla u16 int_mux_cfg0, int_mux_cfg1; 845809bcbceSSrinivas Kandagatla u16 int_fs_reg; 846809bcbceSSrinivas Kandagatla u8 inp0_sel, inp1_sel, inp2_sel; 847809bcbceSSrinivas Kandagatla struct snd_soc_component *component = dai->component; 848809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 849809bcbceSSrinivas Kandagatla 850809bcbceSSrinivas Kandagatla for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) { 851809bcbceSSrinivas Kandagatla int_1_mix1_inp = port; 852809bcbceSSrinivas Kandagatla if ((int_1_mix1_inp < WSA_MACRO_RX0) || (int_1_mix1_inp > WSA_MACRO_RX_MIX1)) { 853809bcbceSSrinivas Kandagatla dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n", 854809bcbceSSrinivas Kandagatla __func__, dai->id); 855809bcbceSSrinivas Kandagatla return -EINVAL; 856809bcbceSSrinivas Kandagatla } 857809bcbceSSrinivas Kandagatla 858809bcbceSSrinivas Kandagatla int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0; 859809bcbceSSrinivas Kandagatla 860809bcbceSSrinivas Kandagatla /* 861809bcbceSSrinivas Kandagatla * Loop through all interpolator MUX inputs and find out 862809bcbceSSrinivas Kandagatla * to which interpolator input, the cdc_dma rx port 863809bcbceSSrinivas Kandagatla * is connected 864809bcbceSSrinivas Kandagatla */ 865809bcbceSSrinivas Kandagatla for (j = 0; j < NUM_INTERPOLATORS; j++) { 866809bcbceSSrinivas Kandagatla int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET; 867*7db4c4cdSSrinivas Kandagatla inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0, 868*7db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK); 869*7db4c4cdSSrinivas Kandagatla inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0, 870*7db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK); 871*7db4c4cdSSrinivas Kandagatla inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1, 872*7db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK); 873*7db4c4cdSSrinivas Kandagatla 874809bcbceSSrinivas Kandagatla if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 875809bcbceSSrinivas Kandagatla (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 876809bcbceSSrinivas Kandagatla (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) { 877809bcbceSSrinivas Kandagatla int_fs_reg = CDC_WSA_RX0_RX_PATH_CTL + 878809bcbceSSrinivas Kandagatla WSA_MACRO_RX_PATH_OFFSET * j; 879809bcbceSSrinivas Kandagatla /* sample_rate is in Hz */ 880809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, int_fs_reg, 881809bcbceSSrinivas Kandagatla WSA_MACRO_FS_RATE_MASK, 882809bcbceSSrinivas Kandagatla int_prim_fs_rate_reg_val); 883809bcbceSSrinivas Kandagatla } 884809bcbceSSrinivas Kandagatla int_mux_cfg0 += WSA_MACRO_MUX_CFG_OFFSET; 885809bcbceSSrinivas Kandagatla } 886809bcbceSSrinivas Kandagatla } 887809bcbceSSrinivas Kandagatla 888809bcbceSSrinivas Kandagatla return 0; 889809bcbceSSrinivas Kandagatla } 890809bcbceSSrinivas Kandagatla 891809bcbceSSrinivas Kandagatla static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, 892809bcbceSSrinivas Kandagatla u8 int_mix_fs_rate_reg_val, 893809bcbceSSrinivas Kandagatla u32 sample_rate) 894809bcbceSSrinivas Kandagatla { 895809bcbceSSrinivas Kandagatla u8 int_2_inp; 896809bcbceSSrinivas Kandagatla u32 j, port; 897809bcbceSSrinivas Kandagatla u16 int_mux_cfg1, int_fs_reg; 898809bcbceSSrinivas Kandagatla u8 int_mux_cfg1_val; 899809bcbceSSrinivas Kandagatla struct snd_soc_component *component = dai->component; 900809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 901809bcbceSSrinivas Kandagatla 902809bcbceSSrinivas Kandagatla for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) { 903809bcbceSSrinivas Kandagatla int_2_inp = port; 904809bcbceSSrinivas Kandagatla if ((int_2_inp < WSA_MACRO_RX0) || (int_2_inp > WSA_MACRO_RX_MIX1)) { 905809bcbceSSrinivas Kandagatla dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n", 906809bcbceSSrinivas Kandagatla __func__, dai->id); 907809bcbceSSrinivas Kandagatla return -EINVAL; 908809bcbceSSrinivas Kandagatla } 909809bcbceSSrinivas Kandagatla 910809bcbceSSrinivas Kandagatla int_mux_cfg1 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG1; 911809bcbceSSrinivas Kandagatla for (j = 0; j < NUM_INTERPOLATORS; j++) { 912*7db4c4cdSSrinivas Kandagatla int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1, 913*7db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_2_SEL_MASK); 914*7db4c4cdSSrinivas Kandagatla 915809bcbceSSrinivas Kandagatla if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) { 916809bcbceSSrinivas Kandagatla int_fs_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL + 917809bcbceSSrinivas Kandagatla WSA_MACRO_RX_PATH_OFFSET * j; 918809bcbceSSrinivas Kandagatla 919809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, 920809bcbceSSrinivas Kandagatla int_fs_reg, 921809bcbceSSrinivas Kandagatla WSA_MACRO_FS_RATE_MASK, 922809bcbceSSrinivas Kandagatla int_mix_fs_rate_reg_val); 923809bcbceSSrinivas Kandagatla } 924809bcbceSSrinivas Kandagatla int_mux_cfg1 += WSA_MACRO_MUX_CFG_OFFSET; 925809bcbceSSrinivas Kandagatla } 926809bcbceSSrinivas Kandagatla } 927809bcbceSSrinivas Kandagatla return 0; 928809bcbceSSrinivas Kandagatla } 929809bcbceSSrinivas Kandagatla 930809bcbceSSrinivas Kandagatla static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai, 931809bcbceSSrinivas Kandagatla u32 sample_rate) 932809bcbceSSrinivas Kandagatla { 933809bcbceSSrinivas Kandagatla int rate_val = 0; 934809bcbceSSrinivas Kandagatla int i, ret; 935809bcbceSSrinivas Kandagatla 936809bcbceSSrinivas Kandagatla /* set mixing path rate */ 937809bcbceSSrinivas Kandagatla for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) { 938809bcbceSSrinivas Kandagatla if (sample_rate == int_mix_sample_rate_val[i].sample_rate) { 939809bcbceSSrinivas Kandagatla rate_val = int_mix_sample_rate_val[i].rate_val; 940809bcbceSSrinivas Kandagatla break; 941809bcbceSSrinivas Kandagatla } 942809bcbceSSrinivas Kandagatla } 943809bcbceSSrinivas Kandagatla if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) || (rate_val < 0)) 944809bcbceSSrinivas Kandagatla goto prim_rate; 945809bcbceSSrinivas Kandagatla 946809bcbceSSrinivas Kandagatla ret = wsa_macro_set_mix_interpolator_rate(dai, (u8) rate_val, sample_rate); 947809bcbceSSrinivas Kandagatla prim_rate: 948809bcbceSSrinivas Kandagatla /* set primary path sample rate */ 949809bcbceSSrinivas Kandagatla for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) { 950809bcbceSSrinivas Kandagatla if (sample_rate == int_prim_sample_rate_val[i].sample_rate) { 951809bcbceSSrinivas Kandagatla rate_val = int_prim_sample_rate_val[i].rate_val; 952809bcbceSSrinivas Kandagatla break; 953809bcbceSSrinivas Kandagatla } 954809bcbceSSrinivas Kandagatla } 955809bcbceSSrinivas Kandagatla if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) || (rate_val < 0)) 956809bcbceSSrinivas Kandagatla return -EINVAL; 957809bcbceSSrinivas Kandagatla 958809bcbceSSrinivas Kandagatla ret = wsa_macro_set_prim_interpolator_rate(dai, (u8) rate_val, sample_rate); 959809bcbceSSrinivas Kandagatla 960809bcbceSSrinivas Kandagatla return ret; 961809bcbceSSrinivas Kandagatla } 962809bcbceSSrinivas Kandagatla 963809bcbceSSrinivas Kandagatla static int wsa_macro_hw_params(struct snd_pcm_substream *substream, 964809bcbceSSrinivas Kandagatla struct snd_pcm_hw_params *params, 965809bcbceSSrinivas Kandagatla struct snd_soc_dai *dai) 966809bcbceSSrinivas Kandagatla { 967809bcbceSSrinivas Kandagatla struct snd_soc_component *component = dai->component; 968809bcbceSSrinivas Kandagatla int ret; 969809bcbceSSrinivas Kandagatla 970809bcbceSSrinivas Kandagatla switch (substream->stream) { 971809bcbceSSrinivas Kandagatla case SNDRV_PCM_STREAM_PLAYBACK: 972809bcbceSSrinivas Kandagatla ret = wsa_macro_set_interpolator_rate(dai, params_rate(params)); 973809bcbceSSrinivas Kandagatla if (ret) { 974809bcbceSSrinivas Kandagatla dev_err(component->dev, 975809bcbceSSrinivas Kandagatla "%s: cannot set sample rate: %u\n", 976809bcbceSSrinivas Kandagatla __func__, params_rate(params)); 977809bcbceSSrinivas Kandagatla return ret; 978809bcbceSSrinivas Kandagatla } 979809bcbceSSrinivas Kandagatla break; 980809bcbceSSrinivas Kandagatla default: 981809bcbceSSrinivas Kandagatla break; 982809bcbceSSrinivas Kandagatla } 983809bcbceSSrinivas Kandagatla return 0; 984809bcbceSSrinivas Kandagatla } 985809bcbceSSrinivas Kandagatla 986809bcbceSSrinivas Kandagatla static int wsa_macro_get_channel_map(struct snd_soc_dai *dai, 987809bcbceSSrinivas Kandagatla unsigned int *tx_num, unsigned int *tx_slot, 988809bcbceSSrinivas Kandagatla unsigned int *rx_num, unsigned int *rx_slot) 989809bcbceSSrinivas Kandagatla { 990809bcbceSSrinivas Kandagatla struct snd_soc_component *component = dai->component; 991809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 992809bcbceSSrinivas Kandagatla u16 val, mask = 0, cnt = 0, temp; 993809bcbceSSrinivas Kandagatla 994809bcbceSSrinivas Kandagatla switch (dai->id) { 995809bcbceSSrinivas Kandagatla case WSA_MACRO_AIF_VI: 996809bcbceSSrinivas Kandagatla *tx_slot = wsa->active_ch_mask[dai->id]; 997809bcbceSSrinivas Kandagatla *tx_num = wsa->active_ch_cnt[dai->id]; 998809bcbceSSrinivas Kandagatla break; 999809bcbceSSrinivas Kandagatla case WSA_MACRO_AIF1_PB: 1000809bcbceSSrinivas Kandagatla case WSA_MACRO_AIF_MIX1_PB: 1001809bcbceSSrinivas Kandagatla for_each_set_bit(temp, &wsa->active_ch_mask[dai->id], 1002809bcbceSSrinivas Kandagatla WSA_MACRO_RX_MAX) { 1003809bcbceSSrinivas Kandagatla mask |= (1 << temp); 1004809bcbceSSrinivas Kandagatla if (++cnt == WSA_MACRO_MAX_DMA_CH_PER_PORT) 1005809bcbceSSrinivas Kandagatla break; 1006809bcbceSSrinivas Kandagatla } 1007809bcbceSSrinivas Kandagatla if (mask & 0x0C) 1008809bcbceSSrinivas Kandagatla mask = mask >> 0x2; 1009809bcbceSSrinivas Kandagatla *rx_slot = mask; 1010809bcbceSSrinivas Kandagatla *rx_num = cnt; 1011809bcbceSSrinivas Kandagatla break; 1012809bcbceSSrinivas Kandagatla case WSA_MACRO_AIF_ECHO: 1013809bcbceSSrinivas Kandagatla val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0); 1014809bcbceSSrinivas Kandagatla if (val & WSA_MACRO_EC_MIX_TX1_MASK) { 1015809bcbceSSrinivas Kandagatla mask |= 0x2; 1016809bcbceSSrinivas Kandagatla cnt++; 1017809bcbceSSrinivas Kandagatla } 1018809bcbceSSrinivas Kandagatla if (val & WSA_MACRO_EC_MIX_TX0_MASK) { 1019809bcbceSSrinivas Kandagatla mask |= 0x1; 1020809bcbceSSrinivas Kandagatla cnt++; 1021809bcbceSSrinivas Kandagatla } 1022809bcbceSSrinivas Kandagatla *tx_slot = mask; 1023809bcbceSSrinivas Kandagatla *tx_num = cnt; 1024809bcbceSSrinivas Kandagatla break; 1025809bcbceSSrinivas Kandagatla default: 1026809bcbceSSrinivas Kandagatla dev_err(component->dev, "%s: Invalid AIF\n", __func__); 1027809bcbceSSrinivas Kandagatla break; 1028809bcbceSSrinivas Kandagatla } 1029809bcbceSSrinivas Kandagatla return 0; 1030809bcbceSSrinivas Kandagatla } 1031809bcbceSSrinivas Kandagatla 1032809bcbceSSrinivas Kandagatla static struct snd_soc_dai_ops wsa_macro_dai_ops = { 1033809bcbceSSrinivas Kandagatla .hw_params = wsa_macro_hw_params, 1034809bcbceSSrinivas Kandagatla .get_channel_map = wsa_macro_get_channel_map, 1035809bcbceSSrinivas Kandagatla }; 1036809bcbceSSrinivas Kandagatla 1037809bcbceSSrinivas Kandagatla static struct snd_soc_dai_driver wsa_macro_dai[] = { 1038809bcbceSSrinivas Kandagatla { 1039809bcbceSSrinivas Kandagatla .name = "wsa_macro_rx1", 1040809bcbceSSrinivas Kandagatla .id = WSA_MACRO_AIF1_PB, 1041809bcbceSSrinivas Kandagatla .playback = { 1042809bcbceSSrinivas Kandagatla .stream_name = "WSA_AIF1 Playback", 1043809bcbceSSrinivas Kandagatla .rates = WSA_MACRO_RX_RATES, 1044809bcbceSSrinivas Kandagatla .formats = WSA_MACRO_RX_FORMATS, 1045809bcbceSSrinivas Kandagatla .rate_max = 384000, 1046809bcbceSSrinivas Kandagatla .rate_min = 8000, 1047809bcbceSSrinivas Kandagatla .channels_min = 1, 1048809bcbceSSrinivas Kandagatla .channels_max = 2, 1049809bcbceSSrinivas Kandagatla }, 1050809bcbceSSrinivas Kandagatla .ops = &wsa_macro_dai_ops, 1051809bcbceSSrinivas Kandagatla }, 1052809bcbceSSrinivas Kandagatla { 1053809bcbceSSrinivas Kandagatla .name = "wsa_macro_rx_mix", 1054809bcbceSSrinivas Kandagatla .id = WSA_MACRO_AIF_MIX1_PB, 1055809bcbceSSrinivas Kandagatla .playback = { 1056809bcbceSSrinivas Kandagatla .stream_name = "WSA_AIF_MIX1 Playback", 1057809bcbceSSrinivas Kandagatla .rates = WSA_MACRO_RX_MIX_RATES, 1058809bcbceSSrinivas Kandagatla .formats = WSA_MACRO_RX_FORMATS, 1059809bcbceSSrinivas Kandagatla .rate_max = 192000, 1060809bcbceSSrinivas Kandagatla .rate_min = 48000, 1061809bcbceSSrinivas Kandagatla .channels_min = 1, 1062809bcbceSSrinivas Kandagatla .channels_max = 2, 1063809bcbceSSrinivas Kandagatla }, 1064809bcbceSSrinivas Kandagatla .ops = &wsa_macro_dai_ops, 1065809bcbceSSrinivas Kandagatla }, 1066809bcbceSSrinivas Kandagatla { 1067809bcbceSSrinivas Kandagatla .name = "wsa_macro_vifeedback", 1068809bcbceSSrinivas Kandagatla .id = WSA_MACRO_AIF_VI, 1069809bcbceSSrinivas Kandagatla .capture = { 1070809bcbceSSrinivas Kandagatla .stream_name = "WSA_AIF_VI Capture", 1071809bcbceSSrinivas Kandagatla .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000, 1072809bcbceSSrinivas Kandagatla .formats = WSA_MACRO_RX_FORMATS, 1073809bcbceSSrinivas Kandagatla .rate_max = 48000, 1074809bcbceSSrinivas Kandagatla .rate_min = 8000, 1075809bcbceSSrinivas Kandagatla .channels_min = 1, 1076809bcbceSSrinivas Kandagatla .channels_max = 4, 1077809bcbceSSrinivas Kandagatla }, 1078809bcbceSSrinivas Kandagatla .ops = &wsa_macro_dai_ops, 1079809bcbceSSrinivas Kandagatla }, 1080809bcbceSSrinivas Kandagatla { 1081809bcbceSSrinivas Kandagatla .name = "wsa_macro_echo", 1082809bcbceSSrinivas Kandagatla .id = WSA_MACRO_AIF_ECHO, 1083809bcbceSSrinivas Kandagatla .capture = { 1084809bcbceSSrinivas Kandagatla .stream_name = "WSA_AIF_ECHO Capture", 1085809bcbceSSrinivas Kandagatla .rates = WSA_MACRO_ECHO_RATES, 1086809bcbceSSrinivas Kandagatla .formats = WSA_MACRO_ECHO_FORMATS, 1087809bcbceSSrinivas Kandagatla .rate_max = 48000, 1088809bcbceSSrinivas Kandagatla .rate_min = 8000, 1089809bcbceSSrinivas Kandagatla .channels_min = 1, 1090809bcbceSSrinivas Kandagatla .channels_max = 2, 1091809bcbceSSrinivas Kandagatla }, 1092809bcbceSSrinivas Kandagatla .ops = &wsa_macro_dai_ops, 1093809bcbceSSrinivas Kandagatla }, 1094809bcbceSSrinivas Kandagatla }; 1095809bcbceSSrinivas Kandagatla 1096809bcbceSSrinivas Kandagatla static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable) 1097809bcbceSSrinivas Kandagatla { 1098809bcbceSSrinivas Kandagatla struct regmap *regmap = wsa->regmap; 1099809bcbceSSrinivas Kandagatla 1100809bcbceSSrinivas Kandagatla if (mclk_enable) { 1101809bcbceSSrinivas Kandagatla if (wsa->wsa_mclk_users == 0) { 1102809bcbceSSrinivas Kandagatla regcache_mark_dirty(regmap); 1103809bcbceSSrinivas Kandagatla regcache_sync(regmap); 1104809bcbceSSrinivas Kandagatla /* 9.6MHz MCLK, set value 0x00 if other frequency */ 1105809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, CDC_WSA_TOP_FREQ_MCLK, 0x01, 0x01); 1106809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, 1107809bcbceSSrinivas Kandagatla CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 1108809bcbceSSrinivas Kandagatla CDC_WSA_MCLK_EN_MASK, 1109809bcbceSSrinivas Kandagatla CDC_WSA_MCLK_ENABLE); 1110809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, 1111809bcbceSSrinivas Kandagatla CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 1112809bcbceSSrinivas Kandagatla CDC_WSA_FS_CNT_EN_MASK, 1113809bcbceSSrinivas Kandagatla CDC_WSA_FS_CNT_ENABLE); 1114809bcbceSSrinivas Kandagatla } 1115809bcbceSSrinivas Kandagatla wsa->wsa_mclk_users++; 1116809bcbceSSrinivas Kandagatla } else { 1117809bcbceSSrinivas Kandagatla if (wsa->wsa_mclk_users <= 0) { 1118809bcbceSSrinivas Kandagatla dev_err(wsa->dev, "clock already disabled\n"); 1119809bcbceSSrinivas Kandagatla wsa->wsa_mclk_users = 0; 1120809bcbceSSrinivas Kandagatla return; 1121809bcbceSSrinivas Kandagatla } 1122809bcbceSSrinivas Kandagatla wsa->wsa_mclk_users--; 1123809bcbceSSrinivas Kandagatla if (wsa->wsa_mclk_users == 0) { 1124809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, 1125809bcbceSSrinivas Kandagatla CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 1126809bcbceSSrinivas Kandagatla CDC_WSA_FS_CNT_EN_MASK, 1127809bcbceSSrinivas Kandagatla CDC_WSA_FS_CNT_DISABLE); 1128809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, 1129809bcbceSSrinivas Kandagatla CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 1130809bcbceSSrinivas Kandagatla CDC_WSA_MCLK_EN_MASK, 1131809bcbceSSrinivas Kandagatla CDC_WSA_MCLK_DISABLE); 1132809bcbceSSrinivas Kandagatla } 1133809bcbceSSrinivas Kandagatla } 1134809bcbceSSrinivas Kandagatla } 1135809bcbceSSrinivas Kandagatla 11362c4066e5SSrinivas Kandagatla static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w, 11372c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, int event) 11382c4066e5SSrinivas Kandagatla { 11392c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 11402c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 11412c4066e5SSrinivas Kandagatla 11422c4066e5SSrinivas Kandagatla wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU); 11432c4066e5SSrinivas Kandagatla return 0; 11442c4066e5SSrinivas Kandagatla } 11452c4066e5SSrinivas Kandagatla 11462c4066e5SSrinivas Kandagatla static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w, 11472c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, 11482c4066e5SSrinivas Kandagatla int event) 11492c4066e5SSrinivas Kandagatla { 11502c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 11512c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 11522c4066e5SSrinivas Kandagatla u32 tx_reg0, tx_reg1; 11532c4066e5SSrinivas Kandagatla 11542c4066e5SSrinivas Kandagatla if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 11552c4066e5SSrinivas Kandagatla tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL; 11562c4066e5SSrinivas Kandagatla tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL; 11572c4066e5SSrinivas Kandagatla } else if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 11582c4066e5SSrinivas Kandagatla tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL; 11592c4066e5SSrinivas Kandagatla tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL; 11602c4066e5SSrinivas Kandagatla } 11612c4066e5SSrinivas Kandagatla 11622c4066e5SSrinivas Kandagatla switch (event) { 11632c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMU: 11642c4066e5SSrinivas Kandagatla /* Enable V&I sensing */ 11652c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg0, 11662c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET_MASK, 11672c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET); 11682c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg1, 11692c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET_MASK, 11702c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET); 11712c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg0, 11722c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK, 11732c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K); 11742c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg1, 11752c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK, 11762c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K); 11772c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg0, 11782c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 11792c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_ENABLE); 11802c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg1, 11812c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 11822c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_ENABLE); 11832c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg0, 11842c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET_MASK, 11852c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_NO_RESET); 11862c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg1, 11872c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET_MASK, 11882c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_NO_RESET); 11892c4066e5SSrinivas Kandagatla break; 11902c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMD: 11912c4066e5SSrinivas Kandagatla /* Disable V&I sensing */ 11922c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg0, 11932c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET_MASK, 11942c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET); 11952c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg1, 11962c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET_MASK, 11972c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET); 11982c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg0, 11992c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 12002c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_DISABLE); 12012c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg1, 12022c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 12032c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_DISABLE); 12042c4066e5SSrinivas Kandagatla break; 12052c4066e5SSrinivas Kandagatla } 12062c4066e5SSrinivas Kandagatla 12072c4066e5SSrinivas Kandagatla return 0; 12082c4066e5SSrinivas Kandagatla } 12092c4066e5SSrinivas Kandagatla 12102c4066e5SSrinivas Kandagatla static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w, 12112c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, int event) 12122c4066e5SSrinivas Kandagatla { 12132c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 12142c4066e5SSrinivas Kandagatla u16 gain_reg; 12152c4066e5SSrinivas Kandagatla int val; 12162c4066e5SSrinivas Kandagatla 12172c4066e5SSrinivas Kandagatla switch (w->reg) { 12182c4066e5SSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_MIX_CTL: 12192c4066e5SSrinivas Kandagatla gain_reg = CDC_WSA_RX0_RX_VOL_MIX_CTL; 12202c4066e5SSrinivas Kandagatla break; 12212c4066e5SSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_MIX_CTL: 12222c4066e5SSrinivas Kandagatla gain_reg = CDC_WSA_RX1_RX_VOL_MIX_CTL; 12232c4066e5SSrinivas Kandagatla break; 12242c4066e5SSrinivas Kandagatla default: 12252c4066e5SSrinivas Kandagatla return 0; 12262c4066e5SSrinivas Kandagatla } 12272c4066e5SSrinivas Kandagatla 12282c4066e5SSrinivas Kandagatla switch (event) { 12292c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMU: 12302c4066e5SSrinivas Kandagatla val = snd_soc_component_read(component, gain_reg); 12312c4066e5SSrinivas Kandagatla snd_soc_component_write(component, gain_reg, val); 12322c4066e5SSrinivas Kandagatla break; 12332c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMD: 12342c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, w->reg, 12352c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_MIX_CLK_EN_MASK, 12362c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_MIX_CLK_DISABLE); 12372c4066e5SSrinivas Kandagatla break; 12382c4066e5SSrinivas Kandagatla } 12392c4066e5SSrinivas Kandagatla 12402c4066e5SSrinivas Kandagatla return 0; 12412c4066e5SSrinivas Kandagatla } 12422c4066e5SSrinivas Kandagatla 12432c4066e5SSrinivas Kandagatla static void wsa_macro_hd2_control(struct snd_soc_component *component, 12442c4066e5SSrinivas Kandagatla u16 reg, int event) 12452c4066e5SSrinivas Kandagatla { 12462c4066e5SSrinivas Kandagatla u16 hd2_scale_reg; 12472c4066e5SSrinivas Kandagatla u16 hd2_enable_reg; 12482c4066e5SSrinivas Kandagatla 12492c4066e5SSrinivas Kandagatla if (reg == CDC_WSA_RX0_RX_PATH_CTL) { 12502c4066e5SSrinivas Kandagatla hd2_scale_reg = CDC_WSA_RX0_RX_PATH_SEC3; 12512c4066e5SSrinivas Kandagatla hd2_enable_reg = CDC_WSA_RX0_RX_PATH_CFG0; 12522c4066e5SSrinivas Kandagatla } 12532c4066e5SSrinivas Kandagatla if (reg == CDC_WSA_RX1_RX_PATH_CTL) { 12542c4066e5SSrinivas Kandagatla hd2_scale_reg = CDC_WSA_RX1_RX_PATH_SEC3; 12552c4066e5SSrinivas Kandagatla hd2_enable_reg = CDC_WSA_RX1_RX_PATH_CFG0; 12562c4066e5SSrinivas Kandagatla } 12572c4066e5SSrinivas Kandagatla 12582c4066e5SSrinivas Kandagatla if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 12592c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, hd2_scale_reg, 12602c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_ALPHA_MASK, 12612c4066e5SSrinivas Kandagatla 0x10); 12622c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, hd2_scale_reg, 12632c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_SCALE_MASK, 12642c4066e5SSrinivas Kandagatla 0x1); 12652c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, hd2_enable_reg, 12662c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_EN_MASK, 12672c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_ENABLE); 12682c4066e5SSrinivas Kandagatla } 12692c4066e5SSrinivas Kandagatla 12702c4066e5SSrinivas Kandagatla if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 12712c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, hd2_enable_reg, 12722c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_EN_MASK, 0); 12732c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, hd2_scale_reg, 12742c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_SCALE_MASK, 12752c4066e5SSrinivas Kandagatla 0); 12762c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, hd2_scale_reg, 12772c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_ALPHA_MASK, 12782c4066e5SSrinivas Kandagatla 0); 12792c4066e5SSrinivas Kandagatla } 12802c4066e5SSrinivas Kandagatla } 12812c4066e5SSrinivas Kandagatla 12822c4066e5SSrinivas Kandagatla static int wsa_macro_config_compander(struct snd_soc_component *component, 12832c4066e5SSrinivas Kandagatla int comp, int event) 12842c4066e5SSrinivas Kandagatla { 12852c4066e5SSrinivas Kandagatla u16 comp_ctl0_reg, rx_path_cfg0_reg; 12862c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 12872c4066e5SSrinivas Kandagatla 12882c4066e5SSrinivas Kandagatla if (!wsa->comp_enabled[comp]) 12892c4066e5SSrinivas Kandagatla return 0; 12902c4066e5SSrinivas Kandagatla 12912c4066e5SSrinivas Kandagatla comp_ctl0_reg = CDC_WSA_COMPANDER0_CTL0 + 12922c4066e5SSrinivas Kandagatla (comp * WSA_MACRO_RX_COMP_OFFSET); 12932c4066e5SSrinivas Kandagatla rx_path_cfg0_reg = CDC_WSA_RX0_RX_PATH_CFG0 + 12942c4066e5SSrinivas Kandagatla (comp * WSA_MACRO_RX_PATH_OFFSET); 12952c4066e5SSrinivas Kandagatla 12962c4066e5SSrinivas Kandagatla if (SND_SOC_DAPM_EVENT_ON(event)) { 12972c4066e5SSrinivas Kandagatla /* Enable Compander Clock */ 12982c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 12992c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_CLK_EN_MASK, 13002c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_CLK_ENABLE); 13012c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13022c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_SOFT_RST_MASK, 13032c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_SOFT_RST_ENABLE); 13042c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13052c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_SOFT_RST_MASK, 13062c4066e5SSrinivas Kandagatla 0); 13072c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, rx_path_cfg0_reg, 13082c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_COMP_EN_MASK, 13092c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_COMP_ENABLE); 13102c4066e5SSrinivas Kandagatla } 13112c4066e5SSrinivas Kandagatla 13122c4066e5SSrinivas Kandagatla if (SND_SOC_DAPM_EVENT_OFF(event)) { 13132c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13142c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_HALT_MASK, 13152c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_HALT); 13162c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, rx_path_cfg0_reg, 13172c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_COMP_EN_MASK, 0); 13182c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13192c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_SOFT_RST_MASK, 13202c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_SOFT_RST_ENABLE); 13212c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13222c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_SOFT_RST_MASK, 13232c4066e5SSrinivas Kandagatla 0); 13242c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13252c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_CLK_EN_MASK, 0); 13262c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13272c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_HALT_MASK, 0); 13282c4066e5SSrinivas Kandagatla } 13292c4066e5SSrinivas Kandagatla 13302c4066e5SSrinivas Kandagatla return 0; 13312c4066e5SSrinivas Kandagatla } 13322c4066e5SSrinivas Kandagatla 13332c4066e5SSrinivas Kandagatla static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component, 13342c4066e5SSrinivas Kandagatla struct wsa_macro *wsa, 13352c4066e5SSrinivas Kandagatla int path, 13362c4066e5SSrinivas Kandagatla bool enable) 13372c4066e5SSrinivas Kandagatla { 13382c4066e5SSrinivas Kandagatla u16 softclip_clk_reg = CDC_WSA_SOFTCLIP0_CRC + 13392c4066e5SSrinivas Kandagatla (path * WSA_MACRO_RX_SOFTCLIP_OFFSET); 13402c4066e5SSrinivas Kandagatla u8 softclip_mux_mask = (1 << path); 13412c4066e5SSrinivas Kandagatla u8 softclip_mux_value = (1 << path); 13422c4066e5SSrinivas Kandagatla 13432c4066e5SSrinivas Kandagatla if (enable) { 13442c4066e5SSrinivas Kandagatla if (wsa->softclip_clk_users[path] == 0) { 13452c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 13462c4066e5SSrinivas Kandagatla softclip_clk_reg, 13472c4066e5SSrinivas Kandagatla CDC_WSA_SOFTCLIP_CLK_EN_MASK, 13482c4066e5SSrinivas Kandagatla CDC_WSA_SOFTCLIP_CLK_ENABLE); 13492c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 13502c4066e5SSrinivas Kandagatla CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 13512c4066e5SSrinivas Kandagatla softclip_mux_mask, softclip_mux_value); 13522c4066e5SSrinivas Kandagatla } 13532c4066e5SSrinivas Kandagatla wsa->softclip_clk_users[path]++; 13542c4066e5SSrinivas Kandagatla } else { 13552c4066e5SSrinivas Kandagatla wsa->softclip_clk_users[path]--; 13562c4066e5SSrinivas Kandagatla if (wsa->softclip_clk_users[path] == 0) { 13572c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 13582c4066e5SSrinivas Kandagatla softclip_clk_reg, 13592c4066e5SSrinivas Kandagatla CDC_WSA_SOFTCLIP_CLK_EN_MASK, 13602c4066e5SSrinivas Kandagatla 0); 13612c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 13622c4066e5SSrinivas Kandagatla CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 13632c4066e5SSrinivas Kandagatla softclip_mux_mask, 0x00); 13642c4066e5SSrinivas Kandagatla } 13652c4066e5SSrinivas Kandagatla } 13662c4066e5SSrinivas Kandagatla } 13672c4066e5SSrinivas Kandagatla 13682c4066e5SSrinivas Kandagatla static int wsa_macro_config_softclip(struct snd_soc_component *component, 13692c4066e5SSrinivas Kandagatla int path, int event) 13702c4066e5SSrinivas Kandagatla { 13712c4066e5SSrinivas Kandagatla u16 softclip_ctrl_reg; 13722c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 13732c4066e5SSrinivas Kandagatla int softclip_path = 0; 13742c4066e5SSrinivas Kandagatla 13752c4066e5SSrinivas Kandagatla if (path == WSA_MACRO_COMP1) 13762c4066e5SSrinivas Kandagatla softclip_path = WSA_MACRO_SOFTCLIP0; 13772c4066e5SSrinivas Kandagatla else if (path == WSA_MACRO_COMP2) 13782c4066e5SSrinivas Kandagatla softclip_path = WSA_MACRO_SOFTCLIP1; 13792c4066e5SSrinivas Kandagatla 13802c4066e5SSrinivas Kandagatla if (!wsa->is_softclip_on[softclip_path]) 13812c4066e5SSrinivas Kandagatla return 0; 13822c4066e5SSrinivas Kandagatla 13832c4066e5SSrinivas Kandagatla softclip_ctrl_reg = CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL + 13842c4066e5SSrinivas Kandagatla (softclip_path * WSA_MACRO_RX_SOFTCLIP_OFFSET); 13852c4066e5SSrinivas Kandagatla 13862c4066e5SSrinivas Kandagatla if (SND_SOC_DAPM_EVENT_ON(event)) { 13872c4066e5SSrinivas Kandagatla /* Enable Softclip clock and mux */ 13882c4066e5SSrinivas Kandagatla wsa_macro_enable_softclip_clk(component, wsa, softclip_path, 13892c4066e5SSrinivas Kandagatla true); 13902c4066e5SSrinivas Kandagatla /* Enable Softclip control */ 13912c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, softclip_ctrl_reg, 13922c4066e5SSrinivas Kandagatla CDC_WSA_SOFTCLIP_EN_MASK, 13932c4066e5SSrinivas Kandagatla CDC_WSA_SOFTCLIP_ENABLE); 13942c4066e5SSrinivas Kandagatla } 13952c4066e5SSrinivas Kandagatla 13962c4066e5SSrinivas Kandagatla if (SND_SOC_DAPM_EVENT_OFF(event)) { 13972c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, softclip_ctrl_reg, 13982c4066e5SSrinivas Kandagatla CDC_WSA_SOFTCLIP_EN_MASK, 0); 13992c4066e5SSrinivas Kandagatla wsa_macro_enable_softclip_clk(component, wsa, softclip_path, 14002c4066e5SSrinivas Kandagatla false); 14012c4066e5SSrinivas Kandagatla } 14022c4066e5SSrinivas Kandagatla 14032c4066e5SSrinivas Kandagatla return 0; 14042c4066e5SSrinivas Kandagatla } 14052c4066e5SSrinivas Kandagatla 14062c4066e5SSrinivas Kandagatla static bool wsa_macro_adie_lb(struct snd_soc_component *component, 14072c4066e5SSrinivas Kandagatla int interp_idx) 14082c4066e5SSrinivas Kandagatla { 14092c4066e5SSrinivas Kandagatla u16 int_mux_cfg0, int_mux_cfg1; 14102c4066e5SSrinivas Kandagatla u8 int_n_inp0, int_n_inp1, int_n_inp2; 14112c4066e5SSrinivas Kandagatla 14122c4066e5SSrinivas Kandagatla int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8; 14132c4066e5SSrinivas Kandagatla int_mux_cfg1 = int_mux_cfg0 + 4; 14142c4066e5SSrinivas Kandagatla 1415*7db4c4cdSSrinivas Kandagatla int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0, 1416*7db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK); 14172c4066e5SSrinivas Kandagatla if (int_n_inp0 == INTn_1_INP_SEL_DEC0 || 14182c4066e5SSrinivas Kandagatla int_n_inp0 == INTn_1_INP_SEL_DEC1) 14192c4066e5SSrinivas Kandagatla return true; 14202c4066e5SSrinivas Kandagatla 1421*7db4c4cdSSrinivas Kandagatla int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0, 1422*7db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK); 14232c4066e5SSrinivas Kandagatla if (int_n_inp1 == INTn_1_INP_SEL_DEC0 || 14242c4066e5SSrinivas Kandagatla int_n_inp1 == INTn_1_INP_SEL_DEC1) 14252c4066e5SSrinivas Kandagatla return true; 14262c4066e5SSrinivas Kandagatla 1427*7db4c4cdSSrinivas Kandagatla int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1, 1428*7db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK); 14292c4066e5SSrinivas Kandagatla if (int_n_inp2 == INTn_1_INP_SEL_DEC0 || 14302c4066e5SSrinivas Kandagatla int_n_inp2 == INTn_1_INP_SEL_DEC1) 14312c4066e5SSrinivas Kandagatla return true; 14322c4066e5SSrinivas Kandagatla 14332c4066e5SSrinivas Kandagatla return false; 14342c4066e5SSrinivas Kandagatla } 14352c4066e5SSrinivas Kandagatla 14362c4066e5SSrinivas Kandagatla static int wsa_macro_enable_main_path(struct snd_soc_dapm_widget *w, 14372c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, 14382c4066e5SSrinivas Kandagatla int event) 14392c4066e5SSrinivas Kandagatla { 14402c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 14412c4066e5SSrinivas Kandagatla u16 reg; 14422c4066e5SSrinivas Kandagatla 14432c4066e5SSrinivas Kandagatla reg = CDC_WSA_RX0_RX_PATH_CTL + WSA_MACRO_RX_PATH_OFFSET * w->shift; 14442c4066e5SSrinivas Kandagatla switch (event) { 14452c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_PRE_PMU: 14462c4066e5SSrinivas Kandagatla if (wsa_macro_adie_lb(component, w->shift)) { 14472c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, reg, 14482c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_CLK_EN_MASK, 14492c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_CLK_ENABLE); 14502c4066e5SSrinivas Kandagatla } 14512c4066e5SSrinivas Kandagatla break; 14522c4066e5SSrinivas Kandagatla default: 14532c4066e5SSrinivas Kandagatla break; 14542c4066e5SSrinivas Kandagatla } 14552c4066e5SSrinivas Kandagatla return 0; 14562c4066e5SSrinivas Kandagatla } 14572c4066e5SSrinivas Kandagatla 14582c4066e5SSrinivas Kandagatla static int wsa_macro_interp_get_primary_reg(u16 reg, u16 *ind) 14592c4066e5SSrinivas Kandagatla { 14602c4066e5SSrinivas Kandagatla u16 prim_int_reg = 0; 14612c4066e5SSrinivas Kandagatla 14622c4066e5SSrinivas Kandagatla switch (reg) { 14632c4066e5SSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_CTL: 14642c4066e5SSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_MIX_CTL: 14652c4066e5SSrinivas Kandagatla prim_int_reg = CDC_WSA_RX0_RX_PATH_CTL; 14662c4066e5SSrinivas Kandagatla *ind = 0; 14672c4066e5SSrinivas Kandagatla break; 14682c4066e5SSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_CTL: 14692c4066e5SSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_MIX_CTL: 14702c4066e5SSrinivas Kandagatla prim_int_reg = CDC_WSA_RX1_RX_PATH_CTL; 14712c4066e5SSrinivas Kandagatla *ind = 1; 14722c4066e5SSrinivas Kandagatla break; 14732c4066e5SSrinivas Kandagatla } 14742c4066e5SSrinivas Kandagatla 14752c4066e5SSrinivas Kandagatla return prim_int_reg; 14762c4066e5SSrinivas Kandagatla } 14772c4066e5SSrinivas Kandagatla 14782c4066e5SSrinivas Kandagatla static int wsa_macro_enable_prim_interpolator(struct snd_soc_component *component, 14792c4066e5SSrinivas Kandagatla u16 reg, int event) 14802c4066e5SSrinivas Kandagatla { 14812c4066e5SSrinivas Kandagatla u16 prim_int_reg; 14822c4066e5SSrinivas Kandagatla u16 ind = 0; 14832c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 14842c4066e5SSrinivas Kandagatla 14852c4066e5SSrinivas Kandagatla prim_int_reg = wsa_macro_interp_get_primary_reg(reg, &ind); 14862c4066e5SSrinivas Kandagatla 14872c4066e5SSrinivas Kandagatla switch (event) { 14882c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_PRE_PMU: 14892c4066e5SSrinivas Kandagatla wsa->prim_int_users[ind]++; 14902c4066e5SSrinivas Kandagatla if (wsa->prim_int_users[ind] == 1) { 14912c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 14922c4066e5SSrinivas Kandagatla prim_int_reg + WSA_MACRO_RX_PATH_CFG3_OFFSET, 14932c4066e5SSrinivas Kandagatla CDC_WSA_RX_DC_DCOEFF_MASK, 14942c4066e5SSrinivas Kandagatla 0x3); 14952c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, prim_int_reg, 14962c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK, 14972c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_PGA_MUTE_ENABLE); 14982c4066e5SSrinivas Kandagatla wsa_macro_hd2_control(component, prim_int_reg, event); 14992c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 15002c4066e5SSrinivas Kandagatla prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET, 15012c4066e5SSrinivas Kandagatla CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 15022c4066e5SSrinivas Kandagatla CDC_WSA_RX_DSMDEM_CLK_ENABLE); 15032c4066e5SSrinivas Kandagatla } 15042c4066e5SSrinivas Kandagatla if ((reg != prim_int_reg) && 15052c4066e5SSrinivas Kandagatla ((snd_soc_component_read( 15062c4066e5SSrinivas Kandagatla component, prim_int_reg)) & 0x10)) 15072c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, reg, 15082c4066e5SSrinivas Kandagatla 0x10, 0x10); 15092c4066e5SSrinivas Kandagatla break; 15102c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMD: 15112c4066e5SSrinivas Kandagatla wsa->prim_int_users[ind]--; 15122c4066e5SSrinivas Kandagatla if (wsa->prim_int_users[ind] == 0) { 15132c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 15142c4066e5SSrinivas Kandagatla prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET, 15152c4066e5SSrinivas Kandagatla CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 0); 15162c4066e5SSrinivas Kandagatla wsa_macro_hd2_control(component, prim_int_reg, event); 15172c4066e5SSrinivas Kandagatla } 15182c4066e5SSrinivas Kandagatla break; 15192c4066e5SSrinivas Kandagatla } 15202c4066e5SSrinivas Kandagatla 15212c4066e5SSrinivas Kandagatla return 0; 15222c4066e5SSrinivas Kandagatla } 15232c4066e5SSrinivas Kandagatla 15242c4066e5SSrinivas Kandagatla static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component, 15252c4066e5SSrinivas Kandagatla struct wsa_macro *wsa, 15262c4066e5SSrinivas Kandagatla int event, int gain_reg) 15272c4066e5SSrinivas Kandagatla { 15282c4066e5SSrinivas Kandagatla int comp_gain_offset, val; 15292c4066e5SSrinivas Kandagatla 15302c4066e5SSrinivas Kandagatla switch (wsa->spkr_mode) { 15312c4066e5SSrinivas Kandagatla /* Compander gain in WSA_MACRO_SPKR_MODE1 case is 12 dB */ 15322c4066e5SSrinivas Kandagatla case WSA_MACRO_SPKR_MODE_1: 15332c4066e5SSrinivas Kandagatla comp_gain_offset = -12; 15342c4066e5SSrinivas Kandagatla break; 15352c4066e5SSrinivas Kandagatla /* Default case compander gain is 15 dB */ 15362c4066e5SSrinivas Kandagatla default: 15372c4066e5SSrinivas Kandagatla comp_gain_offset = -15; 15382c4066e5SSrinivas Kandagatla break; 15392c4066e5SSrinivas Kandagatla } 15402c4066e5SSrinivas Kandagatla 15412c4066e5SSrinivas Kandagatla switch (event) { 15422c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMU: 15432c4066e5SSrinivas Kandagatla /* Apply ear spkr gain only if compander is enabled */ 15442c4066e5SSrinivas Kandagatla if (wsa->comp_enabled[WSA_MACRO_COMP1] && 15452c4066e5SSrinivas Kandagatla (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) && 15462c4066e5SSrinivas Kandagatla (wsa->ear_spkr_gain != 0)) { 15472c4066e5SSrinivas Kandagatla /* For example, val is -8(-12+5-1) for 4dB of gain */ 15482c4066e5SSrinivas Kandagatla val = comp_gain_offset + wsa->ear_spkr_gain - 1; 15492c4066e5SSrinivas Kandagatla snd_soc_component_write(component, gain_reg, val); 15502c4066e5SSrinivas Kandagatla } 15512c4066e5SSrinivas Kandagatla break; 15522c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMD: 15532c4066e5SSrinivas Kandagatla /* 15542c4066e5SSrinivas Kandagatla * Reset RX0 volume to 0 dB if compander is enabled and 15552c4066e5SSrinivas Kandagatla * ear_spkr_gain is non-zero. 15562c4066e5SSrinivas Kandagatla */ 15572c4066e5SSrinivas Kandagatla if (wsa->comp_enabled[WSA_MACRO_COMP1] && 15582c4066e5SSrinivas Kandagatla (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) && 15592c4066e5SSrinivas Kandagatla (wsa->ear_spkr_gain != 0)) { 15602c4066e5SSrinivas Kandagatla snd_soc_component_write(component, gain_reg, 0x0); 15612c4066e5SSrinivas Kandagatla } 15622c4066e5SSrinivas Kandagatla break; 15632c4066e5SSrinivas Kandagatla } 15642c4066e5SSrinivas Kandagatla 15652c4066e5SSrinivas Kandagatla return 0; 15662c4066e5SSrinivas Kandagatla } 15672c4066e5SSrinivas Kandagatla 15682c4066e5SSrinivas Kandagatla static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w, 15692c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, 15702c4066e5SSrinivas Kandagatla int event) 15712c4066e5SSrinivas Kandagatla { 15722c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 15732c4066e5SSrinivas Kandagatla u16 gain_reg; 15742c4066e5SSrinivas Kandagatla u16 reg; 15752c4066e5SSrinivas Kandagatla int val; 15762c4066e5SSrinivas Kandagatla int offset_val = 0; 15772c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 15782c4066e5SSrinivas Kandagatla 15792c4066e5SSrinivas Kandagatla if (w->shift == WSA_MACRO_COMP1) { 15802c4066e5SSrinivas Kandagatla reg = CDC_WSA_RX0_RX_PATH_CTL; 15812c4066e5SSrinivas Kandagatla gain_reg = CDC_WSA_RX0_RX_VOL_CTL; 15822c4066e5SSrinivas Kandagatla } else if (w->shift == WSA_MACRO_COMP2) { 15832c4066e5SSrinivas Kandagatla reg = CDC_WSA_RX1_RX_PATH_CTL; 15842c4066e5SSrinivas Kandagatla gain_reg = CDC_WSA_RX1_RX_VOL_CTL; 15852c4066e5SSrinivas Kandagatla } 15862c4066e5SSrinivas Kandagatla 15872c4066e5SSrinivas Kandagatla switch (event) { 15882c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_PRE_PMU: 15892c4066e5SSrinivas Kandagatla /* Reset if needed */ 15902c4066e5SSrinivas Kandagatla wsa_macro_enable_prim_interpolator(component, reg, event); 15912c4066e5SSrinivas Kandagatla break; 15922c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMU: 15932c4066e5SSrinivas Kandagatla wsa_macro_config_compander(component, w->shift, event); 15942c4066e5SSrinivas Kandagatla wsa_macro_config_softclip(component, w->shift, event); 15952c4066e5SSrinivas Kandagatla /* apply gain after int clk is enabled */ 15962c4066e5SSrinivas Kandagatla if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) && 15972c4066e5SSrinivas Kandagatla (wsa->comp_enabled[WSA_MACRO_COMP1] || 15982c4066e5SSrinivas Kandagatla wsa->comp_enabled[WSA_MACRO_COMP2])) { 15992c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16002c4066e5SSrinivas Kandagatla CDC_WSA_RX0_RX_PATH_SEC1, 16012c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16022c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_ENABLE); 16032c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16042c4066e5SSrinivas Kandagatla CDC_WSA_RX0_RX_PATH_MIX_SEC0, 16052c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16062c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_ENABLE); 16072c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16082c4066e5SSrinivas Kandagatla CDC_WSA_RX1_RX_PATH_SEC1, 16092c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16102c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_ENABLE); 16112c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16122c4066e5SSrinivas Kandagatla CDC_WSA_RX1_RX_PATH_MIX_SEC0, 16132c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16142c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_ENABLE); 16152c4066e5SSrinivas Kandagatla offset_val = -2; 16162c4066e5SSrinivas Kandagatla } 16172c4066e5SSrinivas Kandagatla val = snd_soc_component_read(component, gain_reg); 16182c4066e5SSrinivas Kandagatla val += offset_val; 16192c4066e5SSrinivas Kandagatla snd_soc_component_write(component, gain_reg, val); 16202c4066e5SSrinivas Kandagatla wsa_macro_config_ear_spkr_gain(component, wsa, 16212c4066e5SSrinivas Kandagatla event, gain_reg); 16222c4066e5SSrinivas Kandagatla break; 16232c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMD: 16242c4066e5SSrinivas Kandagatla wsa_macro_config_compander(component, w->shift, event); 16252c4066e5SSrinivas Kandagatla wsa_macro_config_softclip(component, w->shift, event); 16262c4066e5SSrinivas Kandagatla wsa_macro_enable_prim_interpolator(component, reg, event); 16272c4066e5SSrinivas Kandagatla if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) && 16282c4066e5SSrinivas Kandagatla (wsa->comp_enabled[WSA_MACRO_COMP1] || 16292c4066e5SSrinivas Kandagatla wsa->comp_enabled[WSA_MACRO_COMP2])) { 16302c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16312c4066e5SSrinivas Kandagatla CDC_WSA_RX0_RX_PATH_SEC1, 16322c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16332c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_DISABLE); 16342c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16352c4066e5SSrinivas Kandagatla CDC_WSA_RX0_RX_PATH_MIX_SEC0, 16362c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16372c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_DISABLE); 16382c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16392c4066e5SSrinivas Kandagatla CDC_WSA_RX1_RX_PATH_SEC1, 16402c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16412c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_DISABLE); 16422c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16432c4066e5SSrinivas Kandagatla CDC_WSA_RX1_RX_PATH_MIX_SEC0, 16442c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16452c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_DISABLE); 16462c4066e5SSrinivas Kandagatla offset_val = 2; 16472c4066e5SSrinivas Kandagatla val = snd_soc_component_read(component, gain_reg); 16482c4066e5SSrinivas Kandagatla val += offset_val; 16492c4066e5SSrinivas Kandagatla snd_soc_component_write(component, gain_reg, val); 16502c4066e5SSrinivas Kandagatla } 16512c4066e5SSrinivas Kandagatla wsa_macro_config_ear_spkr_gain(component, wsa, 16522c4066e5SSrinivas Kandagatla event, gain_reg); 16532c4066e5SSrinivas Kandagatla break; 16542c4066e5SSrinivas Kandagatla } 16552c4066e5SSrinivas Kandagatla 16562c4066e5SSrinivas Kandagatla return 0; 16572c4066e5SSrinivas Kandagatla } 16582c4066e5SSrinivas Kandagatla 16592c4066e5SSrinivas Kandagatla static int wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w, 16602c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, 16612c4066e5SSrinivas Kandagatla int event) 16622c4066e5SSrinivas Kandagatla { 16632c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 16642c4066e5SSrinivas Kandagatla u16 boost_path_ctl, boost_path_cfg1; 16652c4066e5SSrinivas Kandagatla u16 reg, reg_mix; 16662c4066e5SSrinivas Kandagatla 16672c4066e5SSrinivas Kandagatla if (!strcmp(w->name, "WSA_RX INT0 CHAIN")) { 16682c4066e5SSrinivas Kandagatla boost_path_ctl = CDC_WSA_BOOST0_BOOST_PATH_CTL; 16692c4066e5SSrinivas Kandagatla boost_path_cfg1 = CDC_WSA_RX0_RX_PATH_CFG1; 16702c4066e5SSrinivas Kandagatla reg = CDC_WSA_RX0_RX_PATH_CTL; 16712c4066e5SSrinivas Kandagatla reg_mix = CDC_WSA_RX0_RX_PATH_MIX_CTL; 16722c4066e5SSrinivas Kandagatla } else if (!strcmp(w->name, "WSA_RX INT1 CHAIN")) { 16732c4066e5SSrinivas Kandagatla boost_path_ctl = CDC_WSA_BOOST1_BOOST_PATH_CTL; 16742c4066e5SSrinivas Kandagatla boost_path_cfg1 = CDC_WSA_RX1_RX_PATH_CFG1; 16752c4066e5SSrinivas Kandagatla reg = CDC_WSA_RX1_RX_PATH_CTL; 16762c4066e5SSrinivas Kandagatla reg_mix = CDC_WSA_RX1_RX_PATH_MIX_CTL; 16772c4066e5SSrinivas Kandagatla } 16782c4066e5SSrinivas Kandagatla 16792c4066e5SSrinivas Kandagatla switch (event) { 16802c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_PRE_PMU: 16812c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, boost_path_cfg1, 16822c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_SMART_BST_EN_MASK, 16832c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_SMART_BST_ENABLE); 16842c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, boost_path_ctl, 16852c4066e5SSrinivas Kandagatla CDC_WSA_BOOST_PATH_CLK_EN_MASK, 16862c4066e5SSrinivas Kandagatla CDC_WSA_BOOST_PATH_CLK_ENABLE); 16872c4066e5SSrinivas Kandagatla if ((snd_soc_component_read(component, reg_mix)) & 0x10) 16882c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, reg_mix, 16892c4066e5SSrinivas Kandagatla 0x10, 0x00); 16902c4066e5SSrinivas Kandagatla break; 16912c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMU: 16922c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, reg, 0x10, 0x00); 16932c4066e5SSrinivas Kandagatla break; 16942c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMD: 16952c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, boost_path_ctl, 16962c4066e5SSrinivas Kandagatla CDC_WSA_BOOST_PATH_CLK_EN_MASK, 16972c4066e5SSrinivas Kandagatla CDC_WSA_BOOST_PATH_CLK_DISABLE); 16982c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, boost_path_cfg1, 16992c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_SMART_BST_EN_MASK, 17002c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_SMART_BST_DISABLE); 17012c4066e5SSrinivas Kandagatla break; 17022c4066e5SSrinivas Kandagatla } 17032c4066e5SSrinivas Kandagatla 17042c4066e5SSrinivas Kandagatla return 0; 17052c4066e5SSrinivas Kandagatla } 17062c4066e5SSrinivas Kandagatla 17072c4066e5SSrinivas Kandagatla static int wsa_macro_enable_echo(struct snd_soc_dapm_widget *w, 17082c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, 17092c4066e5SSrinivas Kandagatla int event) 17102c4066e5SSrinivas Kandagatla { 17112c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 17122c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 17132c4066e5SSrinivas Kandagatla u16 val, ec_tx, ec_hq_reg; 17142c4066e5SSrinivas Kandagatla 17152c4066e5SSrinivas Kandagatla val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0); 17162c4066e5SSrinivas Kandagatla 17172c4066e5SSrinivas Kandagatla switch (w->shift) { 17182c4066e5SSrinivas Kandagatla case WSA_MACRO_EC0_MUX: 17192c4066e5SSrinivas Kandagatla val = val & CDC_WSA_RX_MIX_TX0_SEL_MASK; 17202c4066e5SSrinivas Kandagatla ec_tx = val - 1; 17212c4066e5SSrinivas Kandagatla break; 17222c4066e5SSrinivas Kandagatla case WSA_MACRO_EC1_MUX: 17232c4066e5SSrinivas Kandagatla val = val & CDC_WSA_RX_MIX_TX1_SEL_MASK; 17242c4066e5SSrinivas Kandagatla ec_tx = (val >> CDC_WSA_RX_MIX_TX1_SEL_SHFT) - 1; 17252c4066e5SSrinivas Kandagatla break; 17262c4066e5SSrinivas Kandagatla } 17272c4066e5SSrinivas Kandagatla 17282c4066e5SSrinivas Kandagatla if (wsa->ec_hq[ec_tx]) { 17292c4066e5SSrinivas Kandagatla ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL + 0x40 * ec_tx; 17302c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, ec_hq_reg, 17312c4066e5SSrinivas Kandagatla CDC_WSA_EC_HQ_EC_CLK_EN_MASK, 17322c4066e5SSrinivas Kandagatla CDC_WSA_EC_HQ_EC_CLK_ENABLE); 17332c4066e5SSrinivas Kandagatla ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 + 0x40 * ec_tx; 17342c4066e5SSrinivas Kandagatla /* default set to 48k */ 17352c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, ec_hq_reg, 17362c4066e5SSrinivas Kandagatla CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK, 17372c4066e5SSrinivas Kandagatla CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K); 17382c4066e5SSrinivas Kandagatla } 17392c4066e5SSrinivas Kandagatla 17402c4066e5SSrinivas Kandagatla return 0; 17412c4066e5SSrinivas Kandagatla } 17422c4066e5SSrinivas Kandagatla 1743809bcbceSSrinivas Kandagatla static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol, 1744809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1745809bcbceSSrinivas Kandagatla { 1746809bcbceSSrinivas Kandagatla 1747809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1748809bcbceSSrinivas Kandagatla int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1749809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1750809bcbceSSrinivas Kandagatla 1751809bcbceSSrinivas Kandagatla ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx]; 1752809bcbceSSrinivas Kandagatla 1753809bcbceSSrinivas Kandagatla return 0; 1754809bcbceSSrinivas Kandagatla } 1755809bcbceSSrinivas Kandagatla 1756809bcbceSSrinivas Kandagatla static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol, 1757809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1758809bcbceSSrinivas Kandagatla { 1759809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1760809bcbceSSrinivas Kandagatla int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1761809bcbceSSrinivas Kandagatla int value = ucontrol->value.integer.value[0]; 1762809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1763809bcbceSSrinivas Kandagatla 1764809bcbceSSrinivas Kandagatla wsa->ec_hq[ec_tx] = value; 1765809bcbceSSrinivas Kandagatla 1766809bcbceSSrinivas Kandagatla return 0; 1767809bcbceSSrinivas Kandagatla } 1768809bcbceSSrinivas Kandagatla 1769809bcbceSSrinivas Kandagatla static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol, 1770809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1771809bcbceSSrinivas Kandagatla { 1772809bcbceSSrinivas Kandagatla 1773809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1774809bcbceSSrinivas Kandagatla int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1775809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1776809bcbceSSrinivas Kandagatla 1777809bcbceSSrinivas Kandagatla ucontrol->value.integer.value[0] = wsa->comp_enabled[comp]; 1778809bcbceSSrinivas Kandagatla return 0; 1779809bcbceSSrinivas Kandagatla } 1780809bcbceSSrinivas Kandagatla 1781809bcbceSSrinivas Kandagatla static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol, 1782809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1783809bcbceSSrinivas Kandagatla { 1784809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1785809bcbceSSrinivas Kandagatla int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1786809bcbceSSrinivas Kandagatla int value = ucontrol->value.integer.value[0]; 1787809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1788809bcbceSSrinivas Kandagatla 1789809bcbceSSrinivas Kandagatla wsa->comp_enabled[comp] = value; 1790809bcbceSSrinivas Kandagatla 1791809bcbceSSrinivas Kandagatla return 0; 1792809bcbceSSrinivas Kandagatla } 1793809bcbceSSrinivas Kandagatla 1794809bcbceSSrinivas Kandagatla static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol, 1795809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1796809bcbceSSrinivas Kandagatla { 1797809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1798809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1799809bcbceSSrinivas Kandagatla 1800809bcbceSSrinivas Kandagatla ucontrol->value.integer.value[0] = wsa->ear_spkr_gain; 1801809bcbceSSrinivas Kandagatla 1802809bcbceSSrinivas Kandagatla return 0; 1803809bcbceSSrinivas Kandagatla } 1804809bcbceSSrinivas Kandagatla 1805809bcbceSSrinivas Kandagatla static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol, 1806809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1807809bcbceSSrinivas Kandagatla { 1808809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1809809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1810809bcbceSSrinivas Kandagatla 1811809bcbceSSrinivas Kandagatla wsa->ear_spkr_gain = ucontrol->value.integer.value[0]; 1812809bcbceSSrinivas Kandagatla 1813809bcbceSSrinivas Kandagatla return 0; 1814809bcbceSSrinivas Kandagatla } 1815809bcbceSSrinivas Kandagatla 18162c4066e5SSrinivas Kandagatla static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol, 18172c4066e5SSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 18182c4066e5SSrinivas Kandagatla { 18192c4066e5SSrinivas Kandagatla struct snd_soc_dapm_widget *widget = 18202c4066e5SSrinivas Kandagatla snd_soc_dapm_kcontrol_widget(kcontrol); 18212c4066e5SSrinivas Kandagatla struct snd_soc_component *component = 18222c4066e5SSrinivas Kandagatla snd_soc_dapm_to_component(widget->dapm); 18232c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 18242c4066e5SSrinivas Kandagatla 18252c4066e5SSrinivas Kandagatla ucontrol->value.integer.value[0] = 18262c4066e5SSrinivas Kandagatla wsa->rx_port_value[widget->shift]; 18272c4066e5SSrinivas Kandagatla return 0; 18282c4066e5SSrinivas Kandagatla } 18292c4066e5SSrinivas Kandagatla 18302c4066e5SSrinivas Kandagatla static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol, 18312c4066e5SSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 18322c4066e5SSrinivas Kandagatla { 18332c4066e5SSrinivas Kandagatla struct snd_soc_dapm_widget *widget = 18342c4066e5SSrinivas Kandagatla snd_soc_dapm_kcontrol_widget(kcontrol); 18352c4066e5SSrinivas Kandagatla struct snd_soc_component *component = 18362c4066e5SSrinivas Kandagatla snd_soc_dapm_to_component(widget->dapm); 18372c4066e5SSrinivas Kandagatla struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 18382c4066e5SSrinivas Kandagatla struct snd_soc_dapm_update *update = NULL; 18392c4066e5SSrinivas Kandagatla u32 rx_port_value = ucontrol->value.integer.value[0]; 18402c4066e5SSrinivas Kandagatla u32 bit_input; 18412c4066e5SSrinivas Kandagatla u32 aif_rst; 18422c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 18432c4066e5SSrinivas Kandagatla 18442c4066e5SSrinivas Kandagatla aif_rst = wsa->rx_port_value[widget->shift]; 18452c4066e5SSrinivas Kandagatla if (!rx_port_value) { 18462c4066e5SSrinivas Kandagatla if (aif_rst == 0) { 18472c4066e5SSrinivas Kandagatla dev_err(component->dev, "%s: AIF reset already\n", __func__); 18482c4066e5SSrinivas Kandagatla return 0; 18492c4066e5SSrinivas Kandagatla } 18502c4066e5SSrinivas Kandagatla if (aif_rst >= WSA_MACRO_RX_MAX) { 18512c4066e5SSrinivas Kandagatla dev_err(component->dev, "%s: Invalid AIF reset\n", __func__); 18522c4066e5SSrinivas Kandagatla return 0; 18532c4066e5SSrinivas Kandagatla } 18542c4066e5SSrinivas Kandagatla } 18552c4066e5SSrinivas Kandagatla wsa->rx_port_value[widget->shift] = rx_port_value; 18562c4066e5SSrinivas Kandagatla 18572c4066e5SSrinivas Kandagatla bit_input = widget->shift; 18582c4066e5SSrinivas Kandagatla 18592c4066e5SSrinivas Kandagatla switch (rx_port_value) { 18602c4066e5SSrinivas Kandagatla case 0: 18612c4066e5SSrinivas Kandagatla if (wsa->active_ch_cnt[aif_rst]) { 18622c4066e5SSrinivas Kandagatla clear_bit(bit_input, 18632c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[aif_rst]); 18642c4066e5SSrinivas Kandagatla wsa->active_ch_cnt[aif_rst]--; 18652c4066e5SSrinivas Kandagatla } 18662c4066e5SSrinivas Kandagatla break; 18672c4066e5SSrinivas Kandagatla case 1: 18682c4066e5SSrinivas Kandagatla case 2: 18692c4066e5SSrinivas Kandagatla set_bit(bit_input, 18702c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[rx_port_value]); 18712c4066e5SSrinivas Kandagatla wsa->active_ch_cnt[rx_port_value]++; 18722c4066e5SSrinivas Kandagatla break; 18732c4066e5SSrinivas Kandagatla default: 18742c4066e5SSrinivas Kandagatla dev_err(component->dev, 18752c4066e5SSrinivas Kandagatla "%s: Invalid AIF_ID for WSA RX MUX %d\n", 18762c4066e5SSrinivas Kandagatla __func__, rx_port_value); 18772c4066e5SSrinivas Kandagatla return -EINVAL; 18782c4066e5SSrinivas Kandagatla } 18792c4066e5SSrinivas Kandagatla 18802c4066e5SSrinivas Kandagatla snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, 18812c4066e5SSrinivas Kandagatla rx_port_value, e, update); 18822c4066e5SSrinivas Kandagatla return 0; 18832c4066e5SSrinivas Kandagatla } 18842c4066e5SSrinivas Kandagatla 1885809bcbceSSrinivas Kandagatla static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, 1886809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1887809bcbceSSrinivas Kandagatla { 1888809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1889809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1890809bcbceSSrinivas Kandagatla int path = ((struct soc_mixer_control *)kcontrol->private_value)->shift; 1891809bcbceSSrinivas Kandagatla 1892809bcbceSSrinivas Kandagatla ucontrol->value.integer.value[0] = wsa->is_softclip_on[path]; 1893809bcbceSSrinivas Kandagatla 1894809bcbceSSrinivas Kandagatla return 0; 1895809bcbceSSrinivas Kandagatla } 1896809bcbceSSrinivas Kandagatla 1897809bcbceSSrinivas Kandagatla static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, 1898809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1899809bcbceSSrinivas Kandagatla { 1900809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1901809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1902809bcbceSSrinivas Kandagatla int path = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1903809bcbceSSrinivas Kandagatla 1904809bcbceSSrinivas Kandagatla wsa->is_softclip_on[path] = ucontrol->value.integer.value[0]; 1905809bcbceSSrinivas Kandagatla 1906809bcbceSSrinivas Kandagatla return 0; 1907809bcbceSSrinivas Kandagatla } 1908809bcbceSSrinivas Kandagatla 1909809bcbceSSrinivas Kandagatla static const struct snd_kcontrol_new wsa_macro_snd_controls[] = { 1910809bcbceSSrinivas Kandagatla SOC_ENUM_EXT("EAR SPKR PA Gain", wsa_macro_ear_spkr_pa_gain_enum, 1911809bcbceSSrinivas Kandagatla wsa_macro_ear_spkr_pa_gain_get, 1912809bcbceSSrinivas Kandagatla wsa_macro_ear_spkr_pa_gain_put), 1913809bcbceSSrinivas Kandagatla SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM, 1914809bcbceSSrinivas Kandagatla WSA_MACRO_SOFTCLIP0, 1, 0, 1915809bcbceSSrinivas Kandagatla wsa_macro_soft_clip_enable_get, 1916809bcbceSSrinivas Kandagatla wsa_macro_soft_clip_enable_put), 1917809bcbceSSrinivas Kandagatla SOC_SINGLE_EXT("WSA_Softclip1 Enable", SND_SOC_NOPM, 1918809bcbceSSrinivas Kandagatla WSA_MACRO_SOFTCLIP1, 1, 0, 1919809bcbceSSrinivas Kandagatla wsa_macro_soft_clip_enable_get, 1920809bcbceSSrinivas Kandagatla wsa_macro_soft_clip_enable_put), 1921809bcbceSSrinivas Kandagatla 1922809bcbceSSrinivas Kandagatla SOC_SINGLE_S8_TLV("WSA_RX0 Digital Volume", CDC_WSA_RX0_RX_VOL_CTL, 1923809bcbceSSrinivas Kandagatla -84, 40, digital_gain), 1924809bcbceSSrinivas Kandagatla SOC_SINGLE_S8_TLV("WSA_RX1 Digital Volume", CDC_WSA_RX1_RX_VOL_CTL, 1925809bcbceSSrinivas Kandagatla -84, 40, digital_gain), 1926809bcbceSSrinivas Kandagatla 1927809bcbceSSrinivas Kandagatla SOC_SINGLE("WSA_RX0 Digital Mute", CDC_WSA_RX0_RX_PATH_CTL, 4, 1, 0), 1928809bcbceSSrinivas Kandagatla SOC_SINGLE("WSA_RX1 Digital Mute", CDC_WSA_RX1_RX_PATH_CTL, 4, 1, 0), 1929809bcbceSSrinivas Kandagatla SOC_SINGLE("WSA_RX0_MIX Digital Mute", CDC_WSA_RX0_RX_PATH_MIX_CTL, 4, 1930809bcbceSSrinivas Kandagatla 1, 0), 1931809bcbceSSrinivas Kandagatla SOC_SINGLE("WSA_RX1_MIX Digital Mute", CDC_WSA_RX1_RX_PATH_MIX_CTL, 4, 1932809bcbceSSrinivas Kandagatla 1, 0), 1933809bcbceSSrinivas Kandagatla SOC_SINGLE_EXT("WSA_COMP1 Switch", SND_SOC_NOPM, WSA_MACRO_COMP1, 1, 0, 1934809bcbceSSrinivas Kandagatla wsa_macro_get_compander, wsa_macro_set_compander), 1935809bcbceSSrinivas Kandagatla SOC_SINGLE_EXT("WSA_COMP2 Switch", SND_SOC_NOPM, WSA_MACRO_COMP2, 1, 0, 1936809bcbceSSrinivas Kandagatla wsa_macro_get_compander, wsa_macro_set_compander), 1937809bcbceSSrinivas Kandagatla SOC_SINGLE_EXT("WSA_RX0 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX0, 1, 0, 1938809bcbceSSrinivas Kandagatla wsa_macro_get_ec_hq, wsa_macro_set_ec_hq), 1939809bcbceSSrinivas Kandagatla SOC_SINGLE_EXT("WSA_RX1 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX1, 1, 0, 1940809bcbceSSrinivas Kandagatla wsa_macro_get_ec_hq, wsa_macro_set_ec_hq), 1941809bcbceSSrinivas Kandagatla }; 1942809bcbceSSrinivas Kandagatla 19432c4066e5SSrinivas Kandagatla static const struct soc_enum rx_mux_enum = 19442c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_mux_text), rx_mux_text); 19452c4066e5SSrinivas Kandagatla 19462c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx_mux[WSA_MACRO_RX_MAX] = { 19472c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM_EXT("WSA RX0 Mux", rx_mux_enum, 19482c4066e5SSrinivas Kandagatla wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 19492c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM_EXT("WSA RX1 Mux", rx_mux_enum, 19502c4066e5SSrinivas Kandagatla wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 19512c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM_EXT("WSA RX_MIX0 Mux", rx_mux_enum, 19522c4066e5SSrinivas Kandagatla wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 19532c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM_EXT("WSA RX_MIX1 Mux", rx_mux_enum, 19542c4066e5SSrinivas Kandagatla wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 19552c4066e5SSrinivas Kandagatla }; 19562c4066e5SSrinivas Kandagatla 19572c4066e5SSrinivas Kandagatla static int wsa_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol, 19582c4066e5SSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 19592c4066e5SSrinivas Kandagatla { 19602c4066e5SSrinivas Kandagatla struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 19612c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 19622c4066e5SSrinivas Kandagatla struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 19632c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 19642c4066e5SSrinivas Kandagatla u32 spk_tx_id = mixer->shift; 19652c4066e5SSrinivas Kandagatla u32 dai_id = widget->shift; 19662c4066e5SSrinivas Kandagatla 19672c4066e5SSrinivas Kandagatla if (test_bit(spk_tx_id, &wsa->active_ch_mask[dai_id])) 19682c4066e5SSrinivas Kandagatla ucontrol->value.integer.value[0] = 1; 19692c4066e5SSrinivas Kandagatla else 19702c4066e5SSrinivas Kandagatla ucontrol->value.integer.value[0] = 0; 19712c4066e5SSrinivas Kandagatla 19722c4066e5SSrinivas Kandagatla return 0; 19732c4066e5SSrinivas Kandagatla } 19742c4066e5SSrinivas Kandagatla 19752c4066e5SSrinivas Kandagatla static int wsa_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol, 19762c4066e5SSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 19772c4066e5SSrinivas Kandagatla { 19782c4066e5SSrinivas Kandagatla struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 19792c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 19802c4066e5SSrinivas Kandagatla struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 19812c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 19822c4066e5SSrinivas Kandagatla u32 enable = ucontrol->value.integer.value[0]; 19832c4066e5SSrinivas Kandagatla u32 spk_tx_id = mixer->shift; 19842c4066e5SSrinivas Kandagatla 19852c4066e5SSrinivas Kandagatla if (enable) { 19862c4066e5SSrinivas Kandagatla if (spk_tx_id == WSA_MACRO_TX0 && 19872c4066e5SSrinivas Kandagatla !test_bit(WSA_MACRO_TX0, 19882c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 19892c4066e5SSrinivas Kandagatla set_bit(WSA_MACRO_TX0, 19902c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 19912c4066e5SSrinivas Kandagatla wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++; 19922c4066e5SSrinivas Kandagatla } 19932c4066e5SSrinivas Kandagatla if (spk_tx_id == WSA_MACRO_TX1 && 19942c4066e5SSrinivas Kandagatla !test_bit(WSA_MACRO_TX1, 19952c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 19962c4066e5SSrinivas Kandagatla set_bit(WSA_MACRO_TX1, 19972c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 19982c4066e5SSrinivas Kandagatla wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++; 19992c4066e5SSrinivas Kandagatla } 20002c4066e5SSrinivas Kandagatla } else { 20012c4066e5SSrinivas Kandagatla if (spk_tx_id == WSA_MACRO_TX0 && 20022c4066e5SSrinivas Kandagatla test_bit(WSA_MACRO_TX0, 20032c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 20042c4066e5SSrinivas Kandagatla clear_bit(WSA_MACRO_TX0, 20052c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 20062c4066e5SSrinivas Kandagatla wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--; 20072c4066e5SSrinivas Kandagatla } 20082c4066e5SSrinivas Kandagatla if (spk_tx_id == WSA_MACRO_TX1 && 20092c4066e5SSrinivas Kandagatla test_bit(WSA_MACRO_TX1, 20102c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 20112c4066e5SSrinivas Kandagatla clear_bit(WSA_MACRO_TX1, 20122c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 20132c4066e5SSrinivas Kandagatla wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--; 20142c4066e5SSrinivas Kandagatla } 20152c4066e5SSrinivas Kandagatla } 20162c4066e5SSrinivas Kandagatla snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL); 20172c4066e5SSrinivas Kandagatla 20182c4066e5SSrinivas Kandagatla return 0; 20192c4066e5SSrinivas Kandagatla } 20202c4066e5SSrinivas Kandagatla 20212c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new aif_vi_mixer[] = { 20222c4066e5SSrinivas Kandagatla SOC_SINGLE_EXT("WSA_SPKR_VI_1", SND_SOC_NOPM, WSA_MACRO_TX0, 1, 0, 20232c4066e5SSrinivas Kandagatla wsa_macro_vi_feed_mixer_get, 20242c4066e5SSrinivas Kandagatla wsa_macro_vi_feed_mixer_put), 20252c4066e5SSrinivas Kandagatla SOC_SINGLE_EXT("WSA_SPKR_VI_2", SND_SOC_NOPM, WSA_MACRO_TX1, 1, 0, 20262c4066e5SSrinivas Kandagatla wsa_macro_vi_feed_mixer_get, 20272c4066e5SSrinivas Kandagatla wsa_macro_vi_feed_mixer_put), 20282c4066e5SSrinivas Kandagatla }; 20292c4066e5SSrinivas Kandagatla 20302c4066e5SSrinivas Kandagatla static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = { 20312c4066e5SSrinivas Kandagatla SND_SOC_DAPM_AIF_IN("WSA AIF1 PB", "WSA_AIF1 Playback", 0, 20322c4066e5SSrinivas Kandagatla SND_SOC_NOPM, 0, 0), 20332c4066e5SSrinivas Kandagatla SND_SOC_DAPM_AIF_IN("WSA AIF_MIX1 PB", "WSA_AIF_MIX1 Playback", 0, 20342c4066e5SSrinivas Kandagatla SND_SOC_NOPM, 0, 0), 20352c4066e5SSrinivas Kandagatla 20362c4066e5SSrinivas Kandagatla SND_SOC_DAPM_AIF_OUT_E("WSA AIF_VI", "WSA_AIF_VI Capture", 0, 20372c4066e5SSrinivas Kandagatla SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0, 20382c4066e5SSrinivas Kandagatla wsa_macro_enable_vi_feedback, 20392c4066e5SSrinivas Kandagatla SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 20402c4066e5SSrinivas Kandagatla SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0, 20412c4066e5SSrinivas Kandagatla SND_SOC_NOPM, 0, 0), 20422c4066e5SSrinivas Kandagatla 20432c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA_AIF_VI Mixer", SND_SOC_NOPM, WSA_MACRO_AIF_VI, 20442c4066e5SSrinivas Kandagatla 0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)), 20452c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX_E("WSA RX_MIX EC0_MUX", SND_SOC_NOPM, 20462c4066e5SSrinivas Kandagatla WSA_MACRO_EC0_MUX, 0, 20472c4066e5SSrinivas Kandagatla &rx_mix_ec0_mux, wsa_macro_enable_echo, 20482c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 20492c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX_E("WSA RX_MIX EC1_MUX", SND_SOC_NOPM, 20502c4066e5SSrinivas Kandagatla WSA_MACRO_EC1_MUX, 0, 20512c4066e5SSrinivas Kandagatla &rx_mix_ec1_mux, wsa_macro_enable_echo, 20522c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 20532c4066e5SSrinivas Kandagatla 20542c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA RX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX0, 0, 20552c4066e5SSrinivas Kandagatla &rx_mux[WSA_MACRO_RX0]), 20562c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA RX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX1, 0, 20572c4066e5SSrinivas Kandagatla &rx_mux[WSA_MACRO_RX1]), 20582c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA RX_MIX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 0, 20592c4066e5SSrinivas Kandagatla &rx_mux[WSA_MACRO_RX_MIX0]), 20602c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA RX_MIX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 0, 20612c4066e5SSrinivas Kandagatla &rx_mux[WSA_MACRO_RX_MIX1]), 20622c4066e5SSrinivas Kandagatla 20632c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 20642c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 20652c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0), 20662c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 20672c4066e5SSrinivas Kandagatla 20682c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, &rx0_prim_inp0_mux), 20692c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, &rx0_prim_inp1_mux), 20702c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, &rx0_prim_inp2_mux), 20712c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", CDC_WSA_RX0_RX_PATH_MIX_CTL, 20722c4066e5SSrinivas Kandagatla 0, 0, &rx0_mix_mux, wsa_macro_enable_mix_path, 20732c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 20742c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, &rx1_prim_inp0_mux), 20752c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, &rx1_prim_inp1_mux), 20762c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, &rx1_prim_inp2_mux), 20772c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", CDC_WSA_RX1_RX_PATH_MIX_CTL, 20782c4066e5SSrinivas Kandagatla 0, 0, &rx1_mix_mux, wsa_macro_enable_mix_path, 20792c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 20802c4066e5SSrinivas Kandagatla 20812c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER_E("WSA_RX INT0 MIX", SND_SOC_NOPM, 0, 0, NULL, 0, 20822c4066e5SSrinivas Kandagatla wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU), 20832c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER_E("WSA_RX INT1 MIX", SND_SOC_NOPM, 1, 0, NULL, 0, 20842c4066e5SSrinivas Kandagatla wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU), 20852c4066e5SSrinivas Kandagatla 20862c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA_RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 20872c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA_RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 20882c4066e5SSrinivas Kandagatla 20892c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX0 INT0 SIDETONE MIX", CDC_WSA_RX0_RX_PATH_CFG1, 20902c4066e5SSrinivas Kandagatla 4, 0, &rx0_sidetone_mix_mux), 20912c4066e5SSrinivas Kandagatla 20922c4066e5SSrinivas Kandagatla SND_SOC_DAPM_INPUT("WSA SRC0_INP"), 20932c4066e5SSrinivas Kandagatla SND_SOC_DAPM_INPUT("WSA_TX DEC0_INP"), 20942c4066e5SSrinivas Kandagatla SND_SOC_DAPM_INPUT("WSA_TX DEC1_INP"), 20952c4066e5SSrinivas Kandagatla 20962c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER_E("WSA_RX INT0 INTERP", SND_SOC_NOPM, 20972c4066e5SSrinivas Kandagatla WSA_MACRO_COMP1, 0, NULL, 0, 20982c4066e5SSrinivas Kandagatla wsa_macro_enable_interpolator, 20992c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 21002c4066e5SSrinivas Kandagatla SND_SOC_DAPM_POST_PMD), 21012c4066e5SSrinivas Kandagatla 21022c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER_E("WSA_RX INT1 INTERP", SND_SOC_NOPM, 21032c4066e5SSrinivas Kandagatla WSA_MACRO_COMP2, 0, NULL, 0, 21042c4066e5SSrinivas Kandagatla wsa_macro_enable_interpolator, 21052c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 21062c4066e5SSrinivas Kandagatla SND_SOC_DAPM_POST_PMD), 21072c4066e5SSrinivas Kandagatla 21082c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER_E("WSA_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0, 21092c4066e5SSrinivas Kandagatla NULL, 0, wsa_macro_spk_boost_event, 21102c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 21112c4066e5SSrinivas Kandagatla SND_SOC_DAPM_POST_PMD), 21122c4066e5SSrinivas Kandagatla 21132c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER_E("WSA_RX INT1 CHAIN", SND_SOC_NOPM, 0, 0, 21142c4066e5SSrinivas Kandagatla NULL, 0, wsa_macro_spk_boost_event, 21152c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 21162c4066e5SSrinivas Kandagatla SND_SOC_DAPM_POST_PMD), 21172c4066e5SSrinivas Kandagatla 21182c4066e5SSrinivas Kandagatla SND_SOC_DAPM_INPUT("VIINPUT_WSA"), 21192c4066e5SSrinivas Kandagatla SND_SOC_DAPM_OUTPUT("WSA_SPK1 OUT"), 21202c4066e5SSrinivas Kandagatla SND_SOC_DAPM_OUTPUT("WSA_SPK2 OUT"), 21212c4066e5SSrinivas Kandagatla 21222c4066e5SSrinivas Kandagatla SND_SOC_DAPM_SUPPLY("WSA_RX0_CLK", CDC_WSA_RX0_RX_PATH_CTL, 5, 0, NULL, 0), 21232c4066e5SSrinivas Kandagatla SND_SOC_DAPM_SUPPLY("WSA_RX1_CLK", CDC_WSA_RX1_RX_PATH_CTL, 5, 0, NULL, 0), 21242c4066e5SSrinivas Kandagatla SND_SOC_DAPM_SUPPLY("WSA_RX_MIX0_CLK", CDC_WSA_RX0_RX_PATH_MIX_CTL, 5, 0, NULL, 0), 21252c4066e5SSrinivas Kandagatla SND_SOC_DAPM_SUPPLY("WSA_RX_MIX1_CLK", CDC_WSA_RX1_RX_PATH_MIX_CTL, 5, 0, NULL, 0), 21262c4066e5SSrinivas Kandagatla SND_SOC_DAPM_SUPPLY_S("WSA_MCLK", 0, SND_SOC_NOPM, 0, 0, 21272c4066e5SSrinivas Kandagatla wsa_macro_mclk_event, 21282c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 21292c4066e5SSrinivas Kandagatla }; 21302c4066e5SSrinivas Kandagatla 21312c4066e5SSrinivas Kandagatla static const struct snd_soc_dapm_route wsa_audio_map[] = { 21322c4066e5SSrinivas Kandagatla /* VI Feedback */ 21332c4066e5SSrinivas Kandagatla {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_1", "VIINPUT_WSA"}, 21342c4066e5SSrinivas Kandagatla {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_2", "VIINPUT_WSA"}, 21352c4066e5SSrinivas Kandagatla {"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"}, 21362c4066e5SSrinivas Kandagatla {"WSA AIF_VI", NULL, "WSA_MCLK"}, 21372c4066e5SSrinivas Kandagatla 21382c4066e5SSrinivas Kandagatla {"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"}, 21392c4066e5SSrinivas Kandagatla {"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"}, 21402c4066e5SSrinivas Kandagatla {"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"}, 21412c4066e5SSrinivas Kandagatla {"WSA RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"}, 21422c4066e5SSrinivas Kandagatla {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC0_MUX"}, 21432c4066e5SSrinivas Kandagatla {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC1_MUX"}, 21442c4066e5SSrinivas Kandagatla {"WSA AIF_ECHO", NULL, "WSA_MCLK"}, 21452c4066e5SSrinivas Kandagatla 21462c4066e5SSrinivas Kandagatla {"WSA AIF1 PB", NULL, "WSA_MCLK"}, 21472c4066e5SSrinivas Kandagatla {"WSA AIF_MIX1 PB", NULL, "WSA_MCLK"}, 21482c4066e5SSrinivas Kandagatla 21492c4066e5SSrinivas Kandagatla {"WSA RX0 MUX", "AIF1_PB", "WSA AIF1 PB"}, 21502c4066e5SSrinivas Kandagatla {"WSA RX1 MUX", "AIF1_PB", "WSA AIF1 PB"}, 21512c4066e5SSrinivas Kandagatla {"WSA RX_MIX0 MUX", "AIF1_PB", "WSA AIF1 PB"}, 21522c4066e5SSrinivas Kandagatla {"WSA RX_MIX1 MUX", "AIF1_PB", "WSA AIF1 PB"}, 21532c4066e5SSrinivas Kandagatla 21542c4066e5SSrinivas Kandagatla {"WSA RX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 21552c4066e5SSrinivas Kandagatla {"WSA RX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 21562c4066e5SSrinivas Kandagatla {"WSA RX_MIX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 21572c4066e5SSrinivas Kandagatla {"WSA RX_MIX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 21582c4066e5SSrinivas Kandagatla 21592c4066e5SSrinivas Kandagatla {"WSA RX0", NULL, "WSA RX0 MUX"}, 21602c4066e5SSrinivas Kandagatla {"WSA RX1", NULL, "WSA RX1 MUX"}, 21612c4066e5SSrinivas Kandagatla {"WSA RX_MIX0", NULL, "WSA RX_MIX0 MUX"}, 21622c4066e5SSrinivas Kandagatla {"WSA RX_MIX1", NULL, "WSA RX_MIX1 MUX"}, 21632c4066e5SSrinivas Kandagatla 21642c4066e5SSrinivas Kandagatla {"WSA RX0", NULL, "WSA_RX0_CLK"}, 21652c4066e5SSrinivas Kandagatla {"WSA RX1", NULL, "WSA_RX1_CLK"}, 21662c4066e5SSrinivas Kandagatla {"WSA RX_MIX0", NULL, "WSA_RX_MIX0_CLK"}, 21672c4066e5SSrinivas Kandagatla {"WSA RX_MIX1", NULL, "WSA_RX_MIX1_CLK"}, 21682c4066e5SSrinivas Kandagatla 21692c4066e5SSrinivas Kandagatla {"WSA_RX0 INP0", "RX0", "WSA RX0"}, 21702c4066e5SSrinivas Kandagatla {"WSA_RX0 INP0", "RX1", "WSA RX1"}, 21712c4066e5SSrinivas Kandagatla {"WSA_RX0 INP0", "RX_MIX0", "WSA RX_MIX0"}, 21722c4066e5SSrinivas Kandagatla {"WSA_RX0 INP0", "RX_MIX1", "WSA RX_MIX1"}, 21732c4066e5SSrinivas Kandagatla {"WSA_RX0 INP0", "DEC0", "WSA_TX DEC0_INP"}, 21742c4066e5SSrinivas Kandagatla {"WSA_RX0 INP0", "DEC1", "WSA_TX DEC1_INP"}, 21752c4066e5SSrinivas Kandagatla {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP0"}, 21762c4066e5SSrinivas Kandagatla 21772c4066e5SSrinivas Kandagatla {"WSA_RX0 INP1", "RX0", "WSA RX0"}, 21782c4066e5SSrinivas Kandagatla {"WSA_RX0 INP1", "RX1", "WSA RX1"}, 21792c4066e5SSrinivas Kandagatla {"WSA_RX0 INP1", "RX_MIX0", "WSA RX_MIX0"}, 21802c4066e5SSrinivas Kandagatla {"WSA_RX0 INP1", "RX_MIX1", "WSA RX_MIX1"}, 21812c4066e5SSrinivas Kandagatla {"WSA_RX0 INP1", "DEC0", "WSA_TX DEC0_INP"}, 21822c4066e5SSrinivas Kandagatla {"WSA_RX0 INP1", "DEC1", "WSA_TX DEC1_INP"}, 21832c4066e5SSrinivas Kandagatla {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP1"}, 21842c4066e5SSrinivas Kandagatla 21852c4066e5SSrinivas Kandagatla {"WSA_RX0 INP2", "RX0", "WSA RX0"}, 21862c4066e5SSrinivas Kandagatla {"WSA_RX0 INP2", "RX1", "WSA RX1"}, 21872c4066e5SSrinivas Kandagatla {"WSA_RX0 INP2", "RX_MIX0", "WSA RX_MIX0"}, 21882c4066e5SSrinivas Kandagatla {"WSA_RX0 INP2", "RX_MIX1", "WSA RX_MIX1"}, 21892c4066e5SSrinivas Kandagatla {"WSA_RX0 INP2", "DEC0", "WSA_TX DEC0_INP"}, 21902c4066e5SSrinivas Kandagatla {"WSA_RX0 INP2", "DEC1", "WSA_TX DEC1_INP"}, 21912c4066e5SSrinivas Kandagatla {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP2"}, 21922c4066e5SSrinivas Kandagatla 21932c4066e5SSrinivas Kandagatla {"WSA_RX0 MIX INP", "RX0", "WSA RX0"}, 21942c4066e5SSrinivas Kandagatla {"WSA_RX0 MIX INP", "RX1", "WSA RX1"}, 21952c4066e5SSrinivas Kandagatla {"WSA_RX0 MIX INP", "RX_MIX0", "WSA RX_MIX0"}, 21962c4066e5SSrinivas Kandagatla {"WSA_RX0 MIX INP", "RX_MIX1", "WSA RX_MIX1"}, 21972c4066e5SSrinivas Kandagatla {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX0 MIX INP"}, 21982c4066e5SSrinivas Kandagatla 21992c4066e5SSrinivas Kandagatla {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX INT0 MIX"}, 22002c4066e5SSrinivas Kandagatla {"WSA_RX INT0 INTERP", NULL, "WSA_RX INT0 SEC MIX"}, 22012c4066e5SSrinivas Kandagatla {"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"}, 22022c4066e5SSrinivas Kandagatla {"WSA_RX INT0 INTERP", NULL, "WSA_RX0 INT0 SIDETONE MIX"}, 22032c4066e5SSrinivas Kandagatla {"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 INTERP"}, 22042c4066e5SSrinivas Kandagatla 22052c4066e5SSrinivas Kandagatla {"WSA_SPK1 OUT", NULL, "WSA_RX INT0 CHAIN"}, 22062c4066e5SSrinivas Kandagatla {"WSA_SPK1 OUT", NULL, "WSA_MCLK"}, 22072c4066e5SSrinivas Kandagatla 22082c4066e5SSrinivas Kandagatla {"WSA_RX1 INP0", "RX0", "WSA RX0"}, 22092c4066e5SSrinivas Kandagatla {"WSA_RX1 INP0", "RX1", "WSA RX1"}, 22102c4066e5SSrinivas Kandagatla {"WSA_RX1 INP0", "RX_MIX0", "WSA RX_MIX0"}, 22112c4066e5SSrinivas Kandagatla {"WSA_RX1 INP0", "RX_MIX1", "WSA RX_MIX1"}, 22122c4066e5SSrinivas Kandagatla {"WSA_RX1 INP0", "DEC0", "WSA_TX DEC0_INP"}, 22132c4066e5SSrinivas Kandagatla {"WSA_RX1 INP0", "DEC1", "WSA_TX DEC1_INP"}, 22142c4066e5SSrinivas Kandagatla {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP0"}, 22152c4066e5SSrinivas Kandagatla 22162c4066e5SSrinivas Kandagatla {"WSA_RX1 INP1", "RX0", "WSA RX0"}, 22172c4066e5SSrinivas Kandagatla {"WSA_RX1 INP1", "RX1", "WSA RX1"}, 22182c4066e5SSrinivas Kandagatla {"WSA_RX1 INP1", "RX_MIX0", "WSA RX_MIX0"}, 22192c4066e5SSrinivas Kandagatla {"WSA_RX1 INP1", "RX_MIX1", "WSA RX_MIX1"}, 22202c4066e5SSrinivas Kandagatla {"WSA_RX1 INP1", "DEC0", "WSA_TX DEC0_INP"}, 22212c4066e5SSrinivas Kandagatla {"WSA_RX1 INP1", "DEC1", "WSA_TX DEC1_INP"}, 22222c4066e5SSrinivas Kandagatla {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP1"}, 22232c4066e5SSrinivas Kandagatla 22242c4066e5SSrinivas Kandagatla {"WSA_RX1 INP2", "RX0", "WSA RX0"}, 22252c4066e5SSrinivas Kandagatla {"WSA_RX1 INP2", "RX1", "WSA RX1"}, 22262c4066e5SSrinivas Kandagatla {"WSA_RX1 INP2", "RX_MIX0", "WSA RX_MIX0"}, 22272c4066e5SSrinivas Kandagatla {"WSA_RX1 INP2", "RX_MIX1", "WSA RX_MIX1"}, 22282c4066e5SSrinivas Kandagatla {"WSA_RX1 INP2", "DEC0", "WSA_TX DEC0_INP"}, 22292c4066e5SSrinivas Kandagatla {"WSA_RX1 INP2", "DEC1", "WSA_TX DEC1_INP"}, 22302c4066e5SSrinivas Kandagatla {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP2"}, 22312c4066e5SSrinivas Kandagatla 22322c4066e5SSrinivas Kandagatla {"WSA_RX1 MIX INP", "RX0", "WSA RX0"}, 22332c4066e5SSrinivas Kandagatla {"WSA_RX1 MIX INP", "RX1", "WSA RX1"}, 22342c4066e5SSrinivas Kandagatla {"WSA_RX1 MIX INP", "RX_MIX0", "WSA RX_MIX0"}, 22352c4066e5SSrinivas Kandagatla {"WSA_RX1 MIX INP", "RX_MIX1", "WSA RX_MIX1"}, 22362c4066e5SSrinivas Kandagatla {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX1 MIX INP"}, 22372c4066e5SSrinivas Kandagatla 22382c4066e5SSrinivas Kandagatla {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX INT1 MIX"}, 22392c4066e5SSrinivas Kandagatla {"WSA_RX INT1 INTERP", NULL, "WSA_RX INT1 SEC MIX"}, 22402c4066e5SSrinivas Kandagatla 22412c4066e5SSrinivas Kandagatla {"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 INTERP"}, 22422c4066e5SSrinivas Kandagatla {"WSA_SPK2 OUT", NULL, "WSA_RX INT1 CHAIN"}, 22432c4066e5SSrinivas Kandagatla {"WSA_SPK2 OUT", NULL, "WSA_MCLK"}, 22442c4066e5SSrinivas Kandagatla }; 22452c4066e5SSrinivas Kandagatla 2246809bcbceSSrinivas Kandagatla static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable) 2247809bcbceSSrinivas Kandagatla { 2248809bcbceSSrinivas Kandagatla struct regmap *regmap = wsa->regmap; 2249809bcbceSSrinivas Kandagatla 2250809bcbceSSrinivas Kandagatla if (enable) { 2251809bcbceSSrinivas Kandagatla wsa_macro_mclk_enable(wsa, true); 2252809bcbceSSrinivas Kandagatla 2253809bcbceSSrinivas Kandagatla /* reset swr ip */ 2254809bcbceSSrinivas Kandagatla if (wsa->reset_swr) 2255809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, 2256809bcbceSSrinivas Kandagatla CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2257809bcbceSSrinivas Kandagatla CDC_WSA_SWR_RST_EN_MASK, 2258809bcbceSSrinivas Kandagatla CDC_WSA_SWR_RST_ENABLE); 2259809bcbceSSrinivas Kandagatla 2260809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2261809bcbceSSrinivas Kandagatla CDC_WSA_SWR_CLK_EN_MASK, 2262809bcbceSSrinivas Kandagatla CDC_WSA_SWR_CLK_ENABLE); 2263809bcbceSSrinivas Kandagatla 2264809bcbceSSrinivas Kandagatla /* Bring out of reset */ 2265809bcbceSSrinivas Kandagatla if (wsa->reset_swr) 2266809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, 2267809bcbceSSrinivas Kandagatla CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2268809bcbceSSrinivas Kandagatla CDC_WSA_SWR_RST_EN_MASK, 2269809bcbceSSrinivas Kandagatla CDC_WSA_SWR_RST_DISABLE); 2270809bcbceSSrinivas Kandagatla wsa->reset_swr = false; 2271809bcbceSSrinivas Kandagatla } else { 2272809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2273809bcbceSSrinivas Kandagatla CDC_WSA_SWR_CLK_EN_MASK, 0); 2274809bcbceSSrinivas Kandagatla wsa_macro_mclk_enable(wsa, false); 2275809bcbceSSrinivas Kandagatla } 2276809bcbceSSrinivas Kandagatla 2277809bcbceSSrinivas Kandagatla return 0; 2278809bcbceSSrinivas Kandagatla } 2279809bcbceSSrinivas Kandagatla 2280809bcbceSSrinivas Kandagatla static int wsa_macro_component_probe(struct snd_soc_component *comp) 2281809bcbceSSrinivas Kandagatla { 2282809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp); 2283809bcbceSSrinivas Kandagatla 2284809bcbceSSrinivas Kandagatla snd_soc_component_init_regmap(comp, wsa->regmap); 2285809bcbceSSrinivas Kandagatla 2286809bcbceSSrinivas Kandagatla wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB; 2287809bcbceSSrinivas Kandagatla 2288809bcbceSSrinivas Kandagatla /* set SPKR rate to FS_2P4_3P072 */ 2289809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(comp, CDC_WSA_RX0_RX_PATH_CFG1, 2290809bcbceSSrinivas Kandagatla CDC_WSA_RX_PATH_SPKR_RATE_MASK, 2291809bcbceSSrinivas Kandagatla CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072); 2292809bcbceSSrinivas Kandagatla 2293809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(comp, CDC_WSA_RX1_RX_PATH_CFG1, 2294809bcbceSSrinivas Kandagatla CDC_WSA_RX_PATH_SPKR_RATE_MASK, 2295809bcbceSSrinivas Kandagatla CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072); 2296809bcbceSSrinivas Kandagatla 2297809bcbceSSrinivas Kandagatla wsa_macro_set_spkr_mode(comp, WSA_MACRO_SPKR_MODE_1); 2298809bcbceSSrinivas Kandagatla 2299809bcbceSSrinivas Kandagatla return 0; 2300809bcbceSSrinivas Kandagatla } 2301809bcbceSSrinivas Kandagatla 2302809bcbceSSrinivas Kandagatla static int swclk_gate_enable(struct clk_hw *hw) 2303809bcbceSSrinivas Kandagatla { 2304809bcbceSSrinivas Kandagatla return wsa_swrm_clock(to_wsa_macro(hw), true); 2305809bcbceSSrinivas Kandagatla } 2306809bcbceSSrinivas Kandagatla 2307809bcbceSSrinivas Kandagatla static void swclk_gate_disable(struct clk_hw *hw) 2308809bcbceSSrinivas Kandagatla { 2309809bcbceSSrinivas Kandagatla wsa_swrm_clock(to_wsa_macro(hw), false); 2310809bcbceSSrinivas Kandagatla } 2311809bcbceSSrinivas Kandagatla 2312809bcbceSSrinivas Kandagatla static int swclk_gate_is_enabled(struct clk_hw *hw) 2313809bcbceSSrinivas Kandagatla { 2314809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = to_wsa_macro(hw); 2315809bcbceSSrinivas Kandagatla int ret, val; 2316809bcbceSSrinivas Kandagatla 2317809bcbceSSrinivas Kandagatla regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val); 2318809bcbceSSrinivas Kandagatla ret = val & BIT(0); 2319809bcbceSSrinivas Kandagatla 2320809bcbceSSrinivas Kandagatla return ret; 2321809bcbceSSrinivas Kandagatla } 2322809bcbceSSrinivas Kandagatla 2323809bcbceSSrinivas Kandagatla static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2324809bcbceSSrinivas Kandagatla unsigned long parent_rate) 2325809bcbceSSrinivas Kandagatla { 2326809bcbceSSrinivas Kandagatla return parent_rate / 2; 2327809bcbceSSrinivas Kandagatla } 2328809bcbceSSrinivas Kandagatla 2329809bcbceSSrinivas Kandagatla static const struct clk_ops swclk_gate_ops = { 2330809bcbceSSrinivas Kandagatla .prepare = swclk_gate_enable, 2331809bcbceSSrinivas Kandagatla .unprepare = swclk_gate_disable, 2332809bcbceSSrinivas Kandagatla .is_enabled = swclk_gate_is_enabled, 2333809bcbceSSrinivas Kandagatla .recalc_rate = swclk_recalc_rate, 2334809bcbceSSrinivas Kandagatla }; 2335809bcbceSSrinivas Kandagatla 2336809bcbceSSrinivas Kandagatla static struct clk *wsa_macro_register_mclk_output(struct wsa_macro *wsa) 2337809bcbceSSrinivas Kandagatla { 2338809bcbceSSrinivas Kandagatla struct device *dev = wsa->dev; 2339809bcbceSSrinivas Kandagatla struct device_node *np = dev->of_node; 2340809bcbceSSrinivas Kandagatla const char *parent_clk_name; 2341809bcbceSSrinivas Kandagatla const char *clk_name = "mclk"; 2342809bcbceSSrinivas Kandagatla struct clk_hw *hw; 2343809bcbceSSrinivas Kandagatla struct clk_init_data init; 2344809bcbceSSrinivas Kandagatla int ret; 2345809bcbceSSrinivas Kandagatla 2346809bcbceSSrinivas Kandagatla parent_clk_name = __clk_get_name(wsa->clks[2].clk); 2347809bcbceSSrinivas Kandagatla 2348809bcbceSSrinivas Kandagatla init.name = clk_name; 2349809bcbceSSrinivas Kandagatla init.ops = &swclk_gate_ops; 2350809bcbceSSrinivas Kandagatla init.flags = 0; 2351809bcbceSSrinivas Kandagatla init.parent_names = &parent_clk_name; 2352809bcbceSSrinivas Kandagatla init.num_parents = 1; 2353809bcbceSSrinivas Kandagatla wsa->hw.init = &init; 2354809bcbceSSrinivas Kandagatla hw = &wsa->hw; 2355809bcbceSSrinivas Kandagatla ret = clk_hw_register(wsa->dev, hw); 2356809bcbceSSrinivas Kandagatla if (ret) 2357809bcbceSSrinivas Kandagatla return ERR_PTR(ret); 2358809bcbceSSrinivas Kandagatla 2359809bcbceSSrinivas Kandagatla of_clk_add_provider(np, of_clk_src_simple_get, hw->clk); 2360809bcbceSSrinivas Kandagatla 2361809bcbceSSrinivas Kandagatla return NULL; 2362809bcbceSSrinivas Kandagatla } 2363809bcbceSSrinivas Kandagatla 2364809bcbceSSrinivas Kandagatla static const struct snd_soc_component_driver wsa_macro_component_drv = { 2365809bcbceSSrinivas Kandagatla .name = "WSA MACRO", 2366809bcbceSSrinivas Kandagatla .probe = wsa_macro_component_probe, 2367809bcbceSSrinivas Kandagatla .controls = wsa_macro_snd_controls, 2368809bcbceSSrinivas Kandagatla .num_controls = ARRAY_SIZE(wsa_macro_snd_controls), 23692c4066e5SSrinivas Kandagatla .dapm_widgets = wsa_macro_dapm_widgets, 23702c4066e5SSrinivas Kandagatla .num_dapm_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets), 23712c4066e5SSrinivas Kandagatla .dapm_routes = wsa_audio_map, 23722c4066e5SSrinivas Kandagatla .num_dapm_routes = ARRAY_SIZE(wsa_audio_map), 2373809bcbceSSrinivas Kandagatla }; 2374809bcbceSSrinivas Kandagatla 2375809bcbceSSrinivas Kandagatla static int wsa_macro_probe(struct platform_device *pdev) 2376809bcbceSSrinivas Kandagatla { 2377809bcbceSSrinivas Kandagatla struct device *dev = &pdev->dev; 2378809bcbceSSrinivas Kandagatla struct wsa_macro *wsa; 2379809bcbceSSrinivas Kandagatla void __iomem *base; 2380809bcbceSSrinivas Kandagatla int ret; 2381809bcbceSSrinivas Kandagatla 2382809bcbceSSrinivas Kandagatla wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL); 2383809bcbceSSrinivas Kandagatla if (!wsa) 2384809bcbceSSrinivas Kandagatla return -ENOMEM; 2385809bcbceSSrinivas Kandagatla 2386809bcbceSSrinivas Kandagatla wsa->clks[0].id = "macro"; 2387809bcbceSSrinivas Kandagatla wsa->clks[1].id = "dcodec"; 2388809bcbceSSrinivas Kandagatla wsa->clks[2].id = "mclk"; 2389809bcbceSSrinivas Kandagatla wsa->clks[3].id = "npl"; 2390809bcbceSSrinivas Kandagatla wsa->clks[4].id = "fsgen"; 2391809bcbceSSrinivas Kandagatla 2392809bcbceSSrinivas Kandagatla ret = devm_clk_bulk_get(dev, WSA_NUM_CLKS_MAX, wsa->clks); 2393809bcbceSSrinivas Kandagatla if (ret) { 2394809bcbceSSrinivas Kandagatla dev_err(dev, "Error getting WSA Clocks (%d)\n", ret); 2395809bcbceSSrinivas Kandagatla return ret; 2396809bcbceSSrinivas Kandagatla } 2397809bcbceSSrinivas Kandagatla 2398809bcbceSSrinivas Kandagatla base = devm_platform_ioremap_resource(pdev, 0); 2399809bcbceSSrinivas Kandagatla if (IS_ERR(base)) 2400809bcbceSSrinivas Kandagatla return PTR_ERR(base); 2401809bcbceSSrinivas Kandagatla 2402809bcbceSSrinivas Kandagatla wsa->regmap = devm_regmap_init_mmio(dev, base, &wsa_regmap_config); 2403809bcbceSSrinivas Kandagatla 2404809bcbceSSrinivas Kandagatla dev_set_drvdata(dev, wsa); 2405809bcbceSSrinivas Kandagatla 2406809bcbceSSrinivas Kandagatla wsa->reset_swr = true; 2407809bcbceSSrinivas Kandagatla wsa->dev = dev; 2408809bcbceSSrinivas Kandagatla 2409809bcbceSSrinivas Kandagatla /* set MCLK and NPL rates */ 2410809bcbceSSrinivas Kandagatla clk_set_rate(wsa->clks[2].clk, WSA_MACRO_MCLK_FREQ); 2411809bcbceSSrinivas Kandagatla clk_set_rate(wsa->clks[3].clk, WSA_MACRO_MCLK_FREQ); 2412809bcbceSSrinivas Kandagatla 2413809bcbceSSrinivas Kandagatla ret = clk_bulk_prepare_enable(WSA_NUM_CLKS_MAX, wsa->clks); 2414809bcbceSSrinivas Kandagatla if (ret) 2415809bcbceSSrinivas Kandagatla return ret; 2416809bcbceSSrinivas Kandagatla 2417809bcbceSSrinivas Kandagatla wsa_macro_register_mclk_output(wsa); 2418809bcbceSSrinivas Kandagatla 2419809bcbceSSrinivas Kandagatla ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv, 2420809bcbceSSrinivas Kandagatla wsa_macro_dai, 2421809bcbceSSrinivas Kandagatla ARRAY_SIZE(wsa_macro_dai)); 2422809bcbceSSrinivas Kandagatla if (ret) 2423809bcbceSSrinivas Kandagatla goto err; 2424809bcbceSSrinivas Kandagatla 2425809bcbceSSrinivas Kandagatla return ret; 2426809bcbceSSrinivas Kandagatla err: 2427809bcbceSSrinivas Kandagatla clk_bulk_disable_unprepare(WSA_NUM_CLKS_MAX, wsa->clks); 2428809bcbceSSrinivas Kandagatla 2429809bcbceSSrinivas Kandagatla return ret; 2430809bcbceSSrinivas Kandagatla 2431809bcbceSSrinivas Kandagatla } 2432809bcbceSSrinivas Kandagatla 2433809bcbceSSrinivas Kandagatla static int wsa_macro_remove(struct platform_device *pdev) 2434809bcbceSSrinivas Kandagatla { 2435809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev); 2436809bcbceSSrinivas Kandagatla 2437809bcbceSSrinivas Kandagatla of_clk_del_provider(pdev->dev.of_node); 2438809bcbceSSrinivas Kandagatla 2439809bcbceSSrinivas Kandagatla clk_bulk_disable_unprepare(WSA_NUM_CLKS_MAX, wsa->clks); 2440809bcbceSSrinivas Kandagatla 2441809bcbceSSrinivas Kandagatla return 0; 2442809bcbceSSrinivas Kandagatla } 2443809bcbceSSrinivas Kandagatla 2444809bcbceSSrinivas Kandagatla static const struct of_device_id wsa_macro_dt_match[] = { 2445809bcbceSSrinivas Kandagatla {.compatible = "qcom,sm8250-lpass-wsa-macro"}, 2446809bcbceSSrinivas Kandagatla {} 2447809bcbceSSrinivas Kandagatla }; 2448809bcbceSSrinivas Kandagatla MODULE_DEVICE_TABLE(of, wsa_macro_dt_match); 2449809bcbceSSrinivas Kandagatla 2450809bcbceSSrinivas Kandagatla static struct platform_driver wsa_macro_driver = { 2451809bcbceSSrinivas Kandagatla .driver = { 2452809bcbceSSrinivas Kandagatla .name = "wsa_macro", 2453809bcbceSSrinivas Kandagatla .of_match_table = wsa_macro_dt_match, 2454809bcbceSSrinivas Kandagatla }, 2455809bcbceSSrinivas Kandagatla .probe = wsa_macro_probe, 2456809bcbceSSrinivas Kandagatla .remove = wsa_macro_remove, 2457809bcbceSSrinivas Kandagatla }; 2458809bcbceSSrinivas Kandagatla 2459809bcbceSSrinivas Kandagatla module_platform_driver(wsa_macro_driver); 2460809bcbceSSrinivas Kandagatla MODULE_DESCRIPTION("WSA macro driver"); 2461809bcbceSSrinivas Kandagatla MODULE_LICENSE("GPL"); 2462