1809bcbceSSrinivas Kandagatla // SPDX-License-Identifier: GPL-2.0-only 2809bcbceSSrinivas Kandagatla // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3809bcbceSSrinivas Kandagatla 4809bcbceSSrinivas Kandagatla #include <linux/module.h> 5809bcbceSSrinivas Kandagatla #include <linux/init.h> 6809bcbceSSrinivas Kandagatla #include <linux/io.h> 79f63869aSKrzysztof Kozlowski #include <linux/of.h> 8809bcbceSSrinivas Kandagatla #include <linux/platform_device.h> 9809bcbceSSrinivas Kandagatla #include <linux/clk.h> 10809bcbceSSrinivas Kandagatla #include <linux/of_clk.h> 11809bcbceSSrinivas Kandagatla #include <linux/clk-provider.h> 12809bcbceSSrinivas Kandagatla #include <sound/soc.h> 13809bcbceSSrinivas Kandagatla #include <sound/soc-dapm.h> 14c96baa29SSrinivas Kandagatla #include <linux/pm_runtime.h> 15809bcbceSSrinivas Kandagatla #include <linux/of_platform.h> 16809bcbceSSrinivas Kandagatla #include <sound/tlv.h> 17809bcbceSSrinivas Kandagatla #include "lpass-wsa-macro.h" 18809bcbceSSrinivas Kandagatla 19809bcbceSSrinivas Kandagatla #define CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 20809bcbceSSrinivas Kandagatla #define CDC_WSA_MCLK_EN_MASK BIT(0) 21809bcbceSSrinivas Kandagatla #define CDC_WSA_MCLK_ENABLE BIT(0) 22809bcbceSSrinivas Kandagatla #define CDC_WSA_MCLK_DISABLE 0 23809bcbceSSrinivas Kandagatla #define CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 24809bcbceSSrinivas Kandagatla #define CDC_WSA_FS_CNT_EN_MASK BIT(0) 25809bcbceSSrinivas Kandagatla #define CDC_WSA_FS_CNT_ENABLE BIT(0) 26809bcbceSSrinivas Kandagatla #define CDC_WSA_FS_CNT_DISABLE 0 27809bcbceSSrinivas Kandagatla #define CDC_WSA_CLK_RST_CTRL_SWR_CONTROL (0x0008) 28809bcbceSSrinivas Kandagatla #define CDC_WSA_SWR_CLK_EN_MASK BIT(0) 29809bcbceSSrinivas Kandagatla #define CDC_WSA_SWR_CLK_ENABLE BIT(0) 30809bcbceSSrinivas Kandagatla #define CDC_WSA_SWR_RST_EN_MASK BIT(1) 31809bcbceSSrinivas Kandagatla #define CDC_WSA_SWR_RST_ENABLE BIT(1) 32809bcbceSSrinivas Kandagatla #define CDC_WSA_SWR_RST_DISABLE 0 33809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_TOP_CFG0 (0x0080) 34809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_TOP_CFG1 (0x0084) 35809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_FREQ_MCLK (0x0088) 36809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_DEBUG_BUS_SEL (0x008C) 37809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_DEBUG_EN0 (0x0090) 38809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_DEBUG_EN1 (0x0094) 39809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_DEBUG_DSM_LB (0x0098) 40809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_RX_I2S_CTL (0x009C) 41809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_TX_I2S_CTL (0x00A0) 42809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_I2S_CLK (0x00A4) 43809bcbceSSrinivas Kandagatla #define CDC_WSA_TOP_I2S_RESET (0x00A8) 44809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 (0x0100) 457db4c4cdSSrinivas Kandagatla #define CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(2, 0) 467db4c4cdSSrinivas Kandagatla #define CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK GENMASK(5, 3) 47809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_RX_INT0_CFG1 (0x0104) 487db4c4cdSSrinivas Kandagatla #define CDC_WSA_RX_INTX_2_SEL_MASK GENMASK(2, 0) 497db4c4cdSSrinivas Kandagatla #define CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK GENMASK(5, 3) 50809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG0 (0x0108) 51809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_RX_INT1_CFG1 (0x010C) 52809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_RX_MIX_CFG0 (0x0110) 53809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_MIX_TX1_SEL_MASK GENMASK(5, 3) 54809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_MIX_TX1_SEL_SHFT 3 55809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_MIX_TX0_SEL_MASK GENMASK(2, 0) 56809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_RX_EC_CFG0 (0x0114) 57809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0 (0x0118) 58809bcbceSSrinivas Kandagatla #define CDC_WSA_TX0_SPKR_PROT_PATH_CTL (0x0244) 59809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_RESET_MASK BIT(5) 60809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_RESET BIT(5) 61809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_NO_RESET 0 62809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK BIT(4) 63809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_CLK_ENABLE BIT(4) 64809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_CLK_DISABLE 0 65809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK GENMASK(3, 0) 66809bcbceSSrinivas Kandagatla #define CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K 0 67809bcbceSSrinivas Kandagatla #define CDC_WSA_TX0_SPKR_PROT_PATH_CFG0 (0x0248) 68809bcbceSSrinivas Kandagatla #define CDC_WSA_TX1_SPKR_PROT_PATH_CTL (0x0264) 69809bcbceSSrinivas Kandagatla #define CDC_WSA_TX1_SPKR_PROT_PATH_CFG0 (0x0268) 70809bcbceSSrinivas Kandagatla #define CDC_WSA_TX2_SPKR_PROT_PATH_CTL (0x0284) 71809bcbceSSrinivas Kandagatla #define CDC_WSA_TX2_SPKR_PROT_PATH_CFG0 (0x0288) 72809bcbceSSrinivas Kandagatla #define CDC_WSA_TX3_SPKR_PROT_PATH_CTL (0x02A4) 73809bcbceSSrinivas Kandagatla #define CDC_WSA_TX3_SPKR_PROT_PATH_CFG0 (0x02A8) 74809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_CFG (0x0340) 75809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_CLR_COMMIT (0x0344) 76809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_PIN1_MASK0 (0x0360) 77809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_PIN1_STATUS0 (0x0368) 78809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_PIN1_CLEAR0 (0x0370) 79809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_PIN2_MASK0 (0x0380) 80809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_PIN2_STATUS0 (0x0388) 81809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_PIN2_CLEAR0 (0x0390) 82809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_LEVEL0 (0x03C0) 83809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_BYPASS0 (0x03C8) 84809bcbceSSrinivas Kandagatla #define CDC_WSA_INTR_CTRL_SET0 (0x03D0) 85809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_CTL (0x0400) 86809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_CLK_EN_MASK BIT(5) 87809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_CLK_ENABLE BIT(5) 88809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_CLK_DISABLE 0 89809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK BIT(4) 90809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_PGA_MUTE_ENABLE BIT(4) 91809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_PGA_MUTE_DISABLE 0 92809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_CFG0 (0x0404) 93809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_COMP_EN_MASK BIT(1) 94809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_COMP_ENABLE BIT(1) 95809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_HD2_EN_MASK BIT(2) 96809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_HD2_ENABLE BIT(2) 97809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_SPKR_RATE_MASK BIT(3) 98809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072 BIT(3) 99809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_CFG1 (0x0408) 100809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_SMART_BST_EN_MASK BIT(0) 101809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_SMART_BST_ENABLE BIT(0) 102809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_SMART_BST_DISABLE 0 103809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_CFG2 (0x040C) 104809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_CFG3 (0x0410) 105809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_DC_DCOEFF_MASK GENMASK(1, 0) 106809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_VOL_CTL (0x0414) 107809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_MIX_CTL (0x0418) 108809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_MIX_CLK_EN_MASK BIT(5) 109809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_MIX_CLK_ENABLE BIT(5) 110809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_MIX_CLK_DISABLE 0 111809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_MIX_CFG (0x041C) 112809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_VOL_MIX_CTL (0x0420) 113809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC0 (0x0424) 114809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC1 (0x0428) 115809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PGA_HALF_DB_MASK BIT(0) 116809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PGA_HALF_DB_ENABLE BIT(0) 117809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PGA_HALF_DB_DISABLE 0 118809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC2 (0x042C) 119809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC3 (0x0430) 120809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_HD2_SCALE_MASK GENMASK(1, 0) 121809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_PATH_HD2_ALPHA_MASK GENMASK(5, 2) 122809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC5 (0x0438) 123809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC6 (0x043C) 124809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_SEC7 (0x0440) 125809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_MIX_SEC0 (0x0444) 126809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_MIX_SEC1 (0x0448) 127809bcbceSSrinivas Kandagatla #define CDC_WSA_RX0_RX_PATH_DSMDEM_CTL (0x044C) 128809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_DSMDEM_CLK_EN_MASK BIT(0) 129809bcbceSSrinivas Kandagatla #define CDC_WSA_RX_DSMDEM_CLK_ENABLE BIT(0) 130809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_CTL (0x0480) 131809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_CFG0 (0x0484) 132809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_CFG1 (0x0488) 133809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_CFG2 (0x048C) 134809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_CFG3 (0x0490) 135809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_VOL_CTL (0x0494) 136809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_MIX_CTL (0x0498) 137809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_MIX_CFG (0x049C) 138809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_VOL_MIX_CTL (0x04A0) 139809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC0 (0x04A4) 140809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC1 (0x04A8) 141809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC2 (0x04AC) 142809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC3 (0x04B0) 143809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC5 (0x04B8) 144809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC6 (0x04BC) 145809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_SEC7 (0x04C0) 146809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_MIX_SEC0 (0x04C4) 147809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_MIX_SEC1 (0x04C8) 148809bcbceSSrinivas Kandagatla #define CDC_WSA_RX1_RX_PATH_DSMDEM_CTL (0x04CC) 149809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST0_BOOST_PATH_CTL (0x0500) 150809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST_PATH_CLK_EN_MASK BIT(4) 151809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST_PATH_CLK_ENABLE BIT(4) 152809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST_PATH_CLK_DISABLE 0 153809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST0_BOOST_CTL (0x0504) 154809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST0_BOOST_CFG1 (0x0508) 155809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST0_BOOST_CFG2 (0x050C) 156809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST1_BOOST_PATH_CTL (0x0540) 157809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST1_BOOST_CTL (0x0544) 158809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST1_BOOST_CFG1 (0x0548) 159809bcbceSSrinivas Kandagatla #define CDC_WSA_BOOST1_BOOST_CFG2 (0x054C) 160809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL0 (0x0580) 161809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER_CLK_EN_MASK BIT(0) 162809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER_CLK_ENABLE BIT(0) 163809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER_SOFT_RST_MASK BIT(1) 164809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER_SOFT_RST_ENABLE BIT(1) 165809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER_HALT_MASK BIT(2) 166809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER_HALT BIT(2) 167809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL1 (0x0584) 168809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL2 (0x0588) 169809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL3 (0x058C) 170809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL4 (0x0590) 171809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL5 (0x0594) 172809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL6 (0x0598) 173809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER0_CTL7 (0x059C) 174809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL0 (0x05C0) 175809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL1 (0x05C4) 176809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL2 (0x05C8) 177809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL3 (0x05CC) 178809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL4 (0x05D0) 179809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL5 (0x05D4) 180809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL6 (0x05D8) 181809bcbceSSrinivas Kandagatla #define CDC_WSA_COMPANDER1_CTL7 (0x05DC) 182809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP0_CRC (0x0600) 183809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP_CLK_EN_MASK BIT(0) 184809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP_CLK_ENABLE BIT(0) 185809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL (0x0604) 186809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP_EN_MASK BIT(0) 187809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP_ENABLE BIT(0) 188809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP1_CRC (0x0640) 189809bcbceSSrinivas Kandagatla #define CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL (0x0644) 190809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL (0x0680) 191809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ_EC_CLK_EN_MASK BIT(0) 192809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ_EC_CLK_ENABLE BIT(0) 193809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 (0x0684) 194809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK GENMASK(4, 1) 195809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K BIT(3) 196809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL (0x06C0) 197809bcbceSSrinivas Kandagatla #define CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0 (0x06C4) 198809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL (0x0700) 199809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_CTL0 (0x0704) 200809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_CTL1 (0x0708) 201809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_FIFO_CTL (0x070C) 202809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB (0x0710) 203809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB (0x0714) 204809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB (0x0718) 205809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB (0x071C) 206809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC0_STATUS_FIFO (0x0720) 207809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL (0x0740) 208809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_CTL0 (0x0744) 209809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_CTL1 (0x0748) 210809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_FIFO_CTL (0x074C) 211809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB (0x0750) 212809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB (0x0754) 213809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB (0x0758) 214809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB (0x075C) 215809bcbceSSrinivas Kandagatla #define CDC_WSA_SPLINE_ASRC1_STATUS_FIFO (0x0760) 216809bcbceSSrinivas Kandagatla #define WSA_MAX_OFFSET (0x0760) 217809bcbceSSrinivas Kandagatla 218809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 219809bcbceSSrinivas Kandagatla SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 220809bcbceSSrinivas Kandagatla SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 221809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_MIX_RATES (SNDRV_PCM_RATE_48000 |\ 222809bcbceSSrinivas Kandagatla SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 223809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 224809bcbceSSrinivas Kandagatla SNDRV_PCM_FMTBIT_S24_LE |\ 225809bcbceSSrinivas Kandagatla SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE) 226809bcbceSSrinivas Kandagatla 227809bcbceSSrinivas Kandagatla #define WSA_MACRO_ECHO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 228809bcbceSSrinivas Kandagatla SNDRV_PCM_RATE_48000) 229809bcbceSSrinivas Kandagatla #define WSA_MACRO_ECHO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 230809bcbceSSrinivas Kandagatla SNDRV_PCM_FMTBIT_S24_LE |\ 231809bcbceSSrinivas Kandagatla SNDRV_PCM_FMTBIT_S24_3LE) 232809bcbceSSrinivas Kandagatla 233809bcbceSSrinivas Kandagatla #define NUM_INTERPOLATORS 2 234809bcbceSSrinivas Kandagatla #define WSA_NUM_CLKS_MAX 5 235809bcbceSSrinivas Kandagatla #define WSA_MACRO_MCLK_FREQ 19200000 236809bcbceSSrinivas Kandagatla #define WSA_MACRO_MUX_INP_MASK2 0x38 237809bcbceSSrinivas Kandagatla #define WSA_MACRO_MUX_CFG_OFFSET 0x8 238809bcbceSSrinivas Kandagatla #define WSA_MACRO_MUX_CFG1_OFFSET 0x4 239809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_COMP_OFFSET 0x40 240809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_SOFTCLIP_OFFSET 0x40 241809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_PATH_OFFSET 0x80 242809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_PATH_CFG3_OFFSET 0x10 243809bcbceSSrinivas Kandagatla #define WSA_MACRO_RX_PATH_DSMDEM_OFFSET 0x4C 244809bcbceSSrinivas Kandagatla #define WSA_MACRO_FS_RATE_MASK 0x0F 245809bcbceSSrinivas Kandagatla #define WSA_MACRO_EC_MIX_TX0_MASK 0x03 246809bcbceSSrinivas Kandagatla #define WSA_MACRO_EC_MIX_TX1_MASK 0x18 247809bcbceSSrinivas Kandagatla #define WSA_MACRO_MAX_DMA_CH_PER_PORT 0x2 248809bcbceSSrinivas Kandagatla 249809bcbceSSrinivas Kandagatla enum { 250809bcbceSSrinivas Kandagatla WSA_MACRO_GAIN_OFFSET_M1P5_DB, 251809bcbceSSrinivas Kandagatla WSA_MACRO_GAIN_OFFSET_0_DB, 252809bcbceSSrinivas Kandagatla }; 253809bcbceSSrinivas Kandagatla enum { 254809bcbceSSrinivas Kandagatla WSA_MACRO_RX0 = 0, 255809bcbceSSrinivas Kandagatla WSA_MACRO_RX1, 256809bcbceSSrinivas Kandagatla WSA_MACRO_RX_MIX, 257809bcbceSSrinivas Kandagatla WSA_MACRO_RX_MIX0 = WSA_MACRO_RX_MIX, 258809bcbceSSrinivas Kandagatla WSA_MACRO_RX_MIX1, 259809bcbceSSrinivas Kandagatla WSA_MACRO_RX_MAX, 260809bcbceSSrinivas Kandagatla }; 261809bcbceSSrinivas Kandagatla 262809bcbceSSrinivas Kandagatla enum { 263809bcbceSSrinivas Kandagatla WSA_MACRO_TX0 = 0, 264809bcbceSSrinivas Kandagatla WSA_MACRO_TX1, 265809bcbceSSrinivas Kandagatla WSA_MACRO_TX_MAX, 266809bcbceSSrinivas Kandagatla }; 267809bcbceSSrinivas Kandagatla 268809bcbceSSrinivas Kandagatla enum { 269809bcbceSSrinivas Kandagatla WSA_MACRO_EC0_MUX = 0, 270809bcbceSSrinivas Kandagatla WSA_MACRO_EC1_MUX, 271809bcbceSSrinivas Kandagatla WSA_MACRO_EC_MUX_MAX, 272809bcbceSSrinivas Kandagatla }; 273809bcbceSSrinivas Kandagatla 274809bcbceSSrinivas Kandagatla enum { 275809bcbceSSrinivas Kandagatla WSA_MACRO_COMP1, /* SPK_L */ 276809bcbceSSrinivas Kandagatla WSA_MACRO_COMP2, /* SPK_R */ 277809bcbceSSrinivas Kandagatla WSA_MACRO_COMP_MAX 278809bcbceSSrinivas Kandagatla }; 279809bcbceSSrinivas Kandagatla 280809bcbceSSrinivas Kandagatla enum { 281809bcbceSSrinivas Kandagatla WSA_MACRO_SOFTCLIP0, /* RX0 */ 282809bcbceSSrinivas Kandagatla WSA_MACRO_SOFTCLIP1, /* RX1 */ 283809bcbceSSrinivas Kandagatla WSA_MACRO_SOFTCLIP_MAX 284809bcbceSSrinivas Kandagatla }; 285809bcbceSSrinivas Kandagatla 286809bcbceSSrinivas Kandagatla enum { 287809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_ZERO = 0, 288809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_RX0, 289809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_RX1, 290809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_RX2, 291809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_RX3, 292809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_DEC0, 293809bcbceSSrinivas Kandagatla INTn_1_INP_SEL_DEC1, 294809bcbceSSrinivas Kandagatla }; 295809bcbceSSrinivas Kandagatla 296809bcbceSSrinivas Kandagatla enum { 297809bcbceSSrinivas Kandagatla INTn_2_INP_SEL_ZERO = 0, 298809bcbceSSrinivas Kandagatla INTn_2_INP_SEL_RX0, 299809bcbceSSrinivas Kandagatla INTn_2_INP_SEL_RX1, 300809bcbceSSrinivas Kandagatla INTn_2_INP_SEL_RX2, 301809bcbceSSrinivas Kandagatla INTn_2_INP_SEL_RX3, 302809bcbceSSrinivas Kandagatla }; 303809bcbceSSrinivas Kandagatla 304809bcbceSSrinivas Kandagatla struct interp_sample_rate { 305809bcbceSSrinivas Kandagatla int sample_rate; 306809bcbceSSrinivas Kandagatla int rate_val; 307809bcbceSSrinivas Kandagatla }; 308809bcbceSSrinivas Kandagatla 309809bcbceSSrinivas Kandagatla static struct interp_sample_rate int_prim_sample_rate_val[] = { 310809bcbceSSrinivas Kandagatla {8000, 0x0}, /* 8K */ 311809bcbceSSrinivas Kandagatla {16000, 0x1}, /* 16K */ 312809bcbceSSrinivas Kandagatla {24000, -EINVAL},/* 24K */ 313809bcbceSSrinivas Kandagatla {32000, 0x3}, /* 32K */ 314809bcbceSSrinivas Kandagatla {48000, 0x4}, /* 48K */ 315809bcbceSSrinivas Kandagatla {96000, 0x5}, /* 96K */ 316809bcbceSSrinivas Kandagatla {192000, 0x6}, /* 192K */ 317809bcbceSSrinivas Kandagatla {384000, 0x7}, /* 384K */ 318809bcbceSSrinivas Kandagatla {44100, 0x8}, /* 44.1K */ 319809bcbceSSrinivas Kandagatla }; 320809bcbceSSrinivas Kandagatla 321809bcbceSSrinivas Kandagatla static struct interp_sample_rate int_mix_sample_rate_val[] = { 322809bcbceSSrinivas Kandagatla {48000, 0x4}, /* 48K */ 323809bcbceSSrinivas Kandagatla {96000, 0x5}, /* 96K */ 324809bcbceSSrinivas Kandagatla {192000, 0x6}, /* 192K */ 325809bcbceSSrinivas Kandagatla }; 326809bcbceSSrinivas Kandagatla 327809bcbceSSrinivas Kandagatla enum { 328809bcbceSSrinivas Kandagatla WSA_MACRO_AIF_INVALID = 0, 329809bcbceSSrinivas Kandagatla WSA_MACRO_AIF1_PB, 330809bcbceSSrinivas Kandagatla WSA_MACRO_AIF_MIX1_PB, 331809bcbceSSrinivas Kandagatla WSA_MACRO_AIF_VI, 332809bcbceSSrinivas Kandagatla WSA_MACRO_AIF_ECHO, 333809bcbceSSrinivas Kandagatla WSA_MACRO_MAX_DAIS, 334809bcbceSSrinivas Kandagatla }; 335809bcbceSSrinivas Kandagatla 336809bcbceSSrinivas Kandagatla struct wsa_macro { 337809bcbceSSrinivas Kandagatla struct device *dev; 338809bcbceSSrinivas Kandagatla int comp_enabled[WSA_MACRO_COMP_MAX]; 339809bcbceSSrinivas Kandagatla int ec_hq[WSA_MACRO_RX1 + 1]; 340809bcbceSSrinivas Kandagatla u16 prim_int_users[WSA_MACRO_RX1 + 1]; 341809bcbceSSrinivas Kandagatla u16 wsa_mclk_users; 342809bcbceSSrinivas Kandagatla unsigned long active_ch_mask[WSA_MACRO_MAX_DAIS]; 343809bcbceSSrinivas Kandagatla unsigned long active_ch_cnt[WSA_MACRO_MAX_DAIS]; 344809bcbceSSrinivas Kandagatla int rx_port_value[WSA_MACRO_RX_MAX]; 345809bcbceSSrinivas Kandagatla int ear_spkr_gain; 346809bcbceSSrinivas Kandagatla int spkr_gain_offset; 347809bcbceSSrinivas Kandagatla int spkr_mode; 348809bcbceSSrinivas Kandagatla int is_softclip_on[WSA_MACRO_SOFTCLIP_MAX]; 349809bcbceSSrinivas Kandagatla int softclip_clk_users[WSA_MACRO_SOFTCLIP_MAX]; 350809bcbceSSrinivas Kandagatla struct regmap *regmap; 351e252801dSSrinivas Kandagatla struct clk *mclk; 352e252801dSSrinivas Kandagatla struct clk *npl; 353e252801dSSrinivas Kandagatla struct clk *macro; 354e252801dSSrinivas Kandagatla struct clk *dcodec; 355e252801dSSrinivas Kandagatla struct clk *fsgen; 356809bcbceSSrinivas Kandagatla struct clk_hw hw; 357809bcbceSSrinivas Kandagatla }; 358809bcbceSSrinivas Kandagatla #define to_wsa_macro(_hw) container_of(_hw, struct wsa_macro, hw) 359809bcbceSSrinivas Kandagatla 360809bcbceSSrinivas Kandagatla static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 361809bcbceSSrinivas Kandagatla 3622c4066e5SSrinivas Kandagatla static const char *const rx_text[] = { 3632c4066e5SSrinivas Kandagatla "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1", "DEC0", "DEC1" 3642c4066e5SSrinivas Kandagatla }; 3652c4066e5SSrinivas Kandagatla 3662c4066e5SSrinivas Kandagatla static const char *const rx_mix_text[] = { 3672c4066e5SSrinivas Kandagatla "ZERO", "RX0", "RX1", "RX_MIX0", "RX_MIX1" 3682c4066e5SSrinivas Kandagatla }; 3692c4066e5SSrinivas Kandagatla 3702c4066e5SSrinivas Kandagatla static const char *const rx_mix_ec_text[] = { 3712c4066e5SSrinivas Kandagatla "ZERO", "RX_MIX_TX0", "RX_MIX_TX1" 3722c4066e5SSrinivas Kandagatla }; 3732c4066e5SSrinivas Kandagatla 3742c4066e5SSrinivas Kandagatla static const char *const rx_mux_text[] = { 3752c4066e5SSrinivas Kandagatla "ZERO", "AIF1_PB", "AIF_MIX1_PB" 3762c4066e5SSrinivas Kandagatla }; 3772c4066e5SSrinivas Kandagatla 3782c4066e5SSrinivas Kandagatla static const char *const rx_sidetone_mix_text[] = { 3792c4066e5SSrinivas Kandagatla "ZERO", "SRC0" 3802c4066e5SSrinivas Kandagatla }; 3812c4066e5SSrinivas Kandagatla 382809bcbceSSrinivas Kandagatla static const char * const wsa_macro_ear_spkr_pa_gain_text[] = { 383809bcbceSSrinivas Kandagatla "G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB", 384809bcbceSSrinivas Kandagatla "G_4_DB", "G_5_DB", "G_6_DB" 385809bcbceSSrinivas Kandagatla }; 386809bcbceSSrinivas Kandagatla 387809bcbceSSrinivas Kandagatla static SOC_ENUM_SINGLE_EXT_DECL(wsa_macro_ear_spkr_pa_gain_enum, 388809bcbceSSrinivas Kandagatla wsa_macro_ear_spkr_pa_gain_text); 389809bcbceSSrinivas Kandagatla 3902c4066e5SSrinivas Kandagatla /* RX INT0 */ 3912c4066e5SSrinivas Kandagatla static const struct soc_enum rx0_prim_inp0_chain_enum = 3922c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 3932c4066e5SSrinivas Kandagatla 0, 7, rx_text); 3942c4066e5SSrinivas Kandagatla 3952c4066e5SSrinivas Kandagatla static const struct soc_enum rx0_prim_inp1_chain_enum = 3962c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 3972c4066e5SSrinivas Kandagatla 3, 7, rx_text); 3982c4066e5SSrinivas Kandagatla 3992c4066e5SSrinivas Kandagatla static const struct soc_enum rx0_prim_inp2_chain_enum = 4002c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 4012c4066e5SSrinivas Kandagatla 3, 7, rx_text); 4022c4066e5SSrinivas Kandagatla 4032c4066e5SSrinivas Kandagatla static const struct soc_enum rx0_mix_chain_enum = 4042c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 4052c4066e5SSrinivas Kandagatla 0, 5, rx_mix_text); 4062c4066e5SSrinivas Kandagatla 4072c4066e5SSrinivas Kandagatla static const struct soc_enum rx0_sidetone_mix_enum = 4082c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_sidetone_mix_text); 4092c4066e5SSrinivas Kandagatla 4102c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx0_prim_inp0_mux = 4112c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX0 INP0 Mux", rx0_prim_inp0_chain_enum); 4122c4066e5SSrinivas Kandagatla 4132c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx0_prim_inp1_mux = 4142c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX0 INP1 Mux", rx0_prim_inp1_chain_enum); 4152c4066e5SSrinivas Kandagatla 4162c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx0_prim_inp2_mux = 4172c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX0 INP2 Mux", rx0_prim_inp2_chain_enum); 4182c4066e5SSrinivas Kandagatla 4192c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx0_mix_mux = 4202c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX0 MIX Mux", rx0_mix_chain_enum); 4212c4066e5SSrinivas Kandagatla 4222c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx0_sidetone_mix_mux = 4232c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX0 SIDETONE MIX Mux", rx0_sidetone_mix_enum); 4242c4066e5SSrinivas Kandagatla 4252c4066e5SSrinivas Kandagatla /* RX INT1 */ 4262c4066e5SSrinivas Kandagatla static const struct soc_enum rx1_prim_inp0_chain_enum = 4272c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 4282c4066e5SSrinivas Kandagatla 0, 7, rx_text); 4292c4066e5SSrinivas Kandagatla 4302c4066e5SSrinivas Kandagatla static const struct soc_enum rx1_prim_inp1_chain_enum = 4312c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 4322c4066e5SSrinivas Kandagatla 3, 7, rx_text); 4332c4066e5SSrinivas Kandagatla 4342c4066e5SSrinivas Kandagatla static const struct soc_enum rx1_prim_inp2_chain_enum = 4352c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 4362c4066e5SSrinivas Kandagatla 3, 7, rx_text); 4372c4066e5SSrinivas Kandagatla 4382c4066e5SSrinivas Kandagatla static const struct soc_enum rx1_mix_chain_enum = 4392c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 4402c4066e5SSrinivas Kandagatla 0, 5, rx_mix_text); 4412c4066e5SSrinivas Kandagatla 4422c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx1_prim_inp0_mux = 4432c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX1 INP0 Mux", rx1_prim_inp0_chain_enum); 4442c4066e5SSrinivas Kandagatla 4452c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx1_prim_inp1_mux = 4462c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX1 INP1 Mux", rx1_prim_inp1_chain_enum); 4472c4066e5SSrinivas Kandagatla 4482c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx1_prim_inp2_mux = 4492c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX1 INP2 Mux", rx1_prim_inp2_chain_enum); 4502c4066e5SSrinivas Kandagatla 4512c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx1_mix_mux = 4522c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA_RX1 MIX Mux", rx1_mix_chain_enum); 4532c4066e5SSrinivas Kandagatla 4542c4066e5SSrinivas Kandagatla static const struct soc_enum rx_mix_ec0_enum = 4552c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 4562c4066e5SSrinivas Kandagatla 0, 3, rx_mix_ec_text); 4572c4066e5SSrinivas Kandagatla 4582c4066e5SSrinivas Kandagatla static const struct soc_enum rx_mix_ec1_enum = 4592c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE(CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 4602c4066e5SSrinivas Kandagatla 3, 3, rx_mix_ec_text); 4612c4066e5SSrinivas Kandagatla 4622c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx_mix_ec0_mux = 4632c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA RX_MIX EC0_Mux", rx_mix_ec0_enum); 4642c4066e5SSrinivas Kandagatla 4652c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx_mix_ec1_mux = 4662c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM("WSA RX_MIX EC1_Mux", rx_mix_ec1_enum); 4672c4066e5SSrinivas Kandagatla 468809bcbceSSrinivas Kandagatla static const struct reg_default wsa_defaults[] = { 469809bcbceSSrinivas Kandagatla /* WSA Macro */ 470809bcbceSSrinivas Kandagatla { CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, 471809bcbceSSrinivas Kandagatla { CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, 472809bcbceSSrinivas Kandagatla { CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 473809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_TOP_CFG0, 0x00}, 474809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_TOP_CFG1, 0x00}, 475809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_FREQ_MCLK, 0x00}, 476809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_DEBUG_BUS_SEL, 0x00}, 477809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_DEBUG_EN0, 0x00}, 478809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_DEBUG_EN1, 0x00}, 479809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_DEBUG_DSM_LB, 0x88}, 480809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_RX_I2S_CTL, 0x0C}, 481809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_TX_I2S_CTL, 0x0C}, 482809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_I2S_CLK, 0x02}, 483809bcbceSSrinivas Kandagatla { CDC_WSA_TOP_I2S_RESET, 0x00}, 484809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_RX_INT0_CFG0, 0x00}, 485809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_RX_INT0_CFG1, 0x00}, 486809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_RX_INT1_CFG0, 0x00}, 487809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_RX_INT1_CFG1, 0x00}, 488809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_RX_MIX_CFG0, 0x00}, 489809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_RX_EC_CFG0, 0x00}, 490809bcbceSSrinivas Kandagatla { CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 0x00}, 491809bcbceSSrinivas Kandagatla { CDC_WSA_TX0_SPKR_PROT_PATH_CTL, 0x02}, 492809bcbceSSrinivas Kandagatla { CDC_WSA_TX0_SPKR_PROT_PATH_CFG0, 0x00}, 493809bcbceSSrinivas Kandagatla { CDC_WSA_TX1_SPKR_PROT_PATH_CTL, 0x02}, 494809bcbceSSrinivas Kandagatla { CDC_WSA_TX1_SPKR_PROT_PATH_CFG0, 0x00}, 495809bcbceSSrinivas Kandagatla { CDC_WSA_TX2_SPKR_PROT_PATH_CTL, 0x02}, 496809bcbceSSrinivas Kandagatla { CDC_WSA_TX2_SPKR_PROT_PATH_CFG0, 0x00}, 497809bcbceSSrinivas Kandagatla { CDC_WSA_TX3_SPKR_PROT_PATH_CTL, 0x02}, 498809bcbceSSrinivas Kandagatla { CDC_WSA_TX3_SPKR_PROT_PATH_CFG0, 0x00}, 499809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_CFG, 0x00}, 500809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_CLR_COMMIT, 0x00}, 501809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_PIN1_MASK0, 0xFF}, 502809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_PIN1_STATUS0, 0x00}, 503809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_PIN1_CLEAR0, 0x00}, 504809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_PIN2_MASK0, 0xFF}, 505809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_PIN2_STATUS0, 0x00}, 506809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_PIN2_CLEAR0, 0x00}, 507809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_LEVEL0, 0x00}, 508809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_BYPASS0, 0x00}, 509809bcbceSSrinivas Kandagatla { CDC_WSA_INTR_CTRL_SET0, 0x00}, 510809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_CTL, 0x04}, 511809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_CFG0, 0x00}, 512809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_CFG1, 0x64}, 513809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_CFG2, 0x8F}, 514809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_CFG3, 0x00}, 515809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_VOL_CTL, 0x00}, 516809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_MIX_CTL, 0x04}, 517809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_MIX_CFG, 0x7E}, 518809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_VOL_MIX_CTL, 0x00}, 519809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC0, 0x04}, 520809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC1, 0x08}, 521809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC2, 0x00}, 522809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC3, 0x00}, 523809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC5, 0x00}, 524809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC6, 0x00}, 525809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_SEC7, 0x00}, 526809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_MIX_SEC0, 0x08}, 527809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_MIX_SEC1, 0x00}, 528809bcbceSSrinivas Kandagatla { CDC_WSA_RX0_RX_PATH_DSMDEM_CTL, 0x00}, 529809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_CFG0, 0x00}, 530809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_CFG1, 0x64}, 531809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_CFG2, 0x8F}, 532809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_CFG3, 0x00}, 533809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_VOL_CTL, 0x00}, 534809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_MIX_CTL, 0x04}, 535809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_MIX_CFG, 0x7E}, 536809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_VOL_MIX_CTL, 0x00}, 537809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC0, 0x04}, 538809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC1, 0x08}, 539809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC2, 0x00}, 540809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC3, 0x00}, 541809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC5, 0x00}, 542809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC6, 0x00}, 543809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_SEC7, 0x00}, 544809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_MIX_SEC0, 0x08}, 545809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_MIX_SEC1, 0x00}, 546809bcbceSSrinivas Kandagatla { CDC_WSA_RX1_RX_PATH_DSMDEM_CTL, 0x00}, 547809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST0_BOOST_PATH_CTL, 0x00}, 548809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST0_BOOST_CTL, 0xD0}, 549809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST0_BOOST_CFG1, 0x89}, 550809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST0_BOOST_CFG2, 0x04}, 551809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST1_BOOST_PATH_CTL, 0x00}, 552809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST1_BOOST_CTL, 0xD0}, 553809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST1_BOOST_CFG1, 0x89}, 554809bcbceSSrinivas Kandagatla { CDC_WSA_BOOST1_BOOST_CFG2, 0x04}, 555809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL0, 0x60}, 556809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL1, 0xDB}, 557809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL2, 0xFF}, 558809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL3, 0x35}, 559809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL4, 0xFF}, 560809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL5, 0x00}, 561809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL6, 0x01}, 562809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER0_CTL7, 0x28}, 563809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL0, 0x60}, 564809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL1, 0xDB}, 565809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL2, 0xFF}, 566809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL3, 0x35}, 567809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL4, 0xFF}, 568809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL5, 0x00}, 569809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL6, 0x01}, 570809bcbceSSrinivas Kandagatla { CDC_WSA_COMPANDER1_CTL7, 0x28}, 571809bcbceSSrinivas Kandagatla { CDC_WSA_SOFTCLIP0_CRC, 0x00}, 572809bcbceSSrinivas Kandagatla { CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL, 0x38}, 573809bcbceSSrinivas Kandagatla { CDC_WSA_SOFTCLIP1_CRC, 0x00}, 574809bcbceSSrinivas Kandagatla { CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL, 0x38}, 575809bcbceSSrinivas Kandagatla { CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL, 0x00}, 576809bcbceSSrinivas Kandagatla { CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0, 0x01}, 577809bcbceSSrinivas Kandagatla { CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL, 0x00}, 578809bcbceSSrinivas Kandagatla { CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0, 0x01}, 579809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL, 0x00}, 580809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_CTL0, 0x00}, 581809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_CTL1, 0x00}, 582809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_FIFO_CTL, 0xA8}, 583809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00}, 584809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00}, 585809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00}, 586809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00}, 587809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC0_STATUS_FIFO, 0x00}, 588809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL, 0x00}, 589809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_CTL0, 0x00}, 590809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_CTL1, 0x00}, 591809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_FIFO_CTL, 0xA8}, 592809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00}, 593809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00}, 594809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00}, 595809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00}, 596809bcbceSSrinivas Kandagatla { CDC_WSA_SPLINE_ASRC1_STATUS_FIFO, 0x00}, 597809bcbceSSrinivas Kandagatla }; 598809bcbceSSrinivas Kandagatla 599809bcbceSSrinivas Kandagatla static bool wsa_is_wronly_register(struct device *dev, 600809bcbceSSrinivas Kandagatla unsigned int reg) 601809bcbceSSrinivas Kandagatla { 602809bcbceSSrinivas Kandagatla switch (reg) { 603809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_CLR_COMMIT: 604809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN1_CLEAR0: 605809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN2_CLEAR0: 606809bcbceSSrinivas Kandagatla return true; 607809bcbceSSrinivas Kandagatla } 608809bcbceSSrinivas Kandagatla 609809bcbceSSrinivas Kandagatla return false; 610809bcbceSSrinivas Kandagatla } 611809bcbceSSrinivas Kandagatla 612809bcbceSSrinivas Kandagatla static bool wsa_is_rw_register(struct device *dev, unsigned int reg) 613809bcbceSSrinivas Kandagatla { 614809bcbceSSrinivas Kandagatla switch (reg) { 615809bcbceSSrinivas Kandagatla case CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL: 616809bcbceSSrinivas Kandagatla case CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL: 617809bcbceSSrinivas Kandagatla case CDC_WSA_CLK_RST_CTRL_SWR_CONTROL: 618809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_TOP_CFG0: 619809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_TOP_CFG1: 620809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_FREQ_MCLK: 621809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_DEBUG_BUS_SEL: 622809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_DEBUG_EN0: 623809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_DEBUG_EN1: 624809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_DEBUG_DSM_LB: 625809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_RX_I2S_CTL: 626809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_TX_I2S_CTL: 627809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_I2S_CLK: 628809bcbceSSrinivas Kandagatla case CDC_WSA_TOP_I2S_RESET: 629809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_RX_INT0_CFG0: 630809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_RX_INT0_CFG1: 631809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_RX_INT1_CFG0: 632809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_RX_INT1_CFG1: 633809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_RX_MIX_CFG0: 634809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_RX_EC_CFG0: 635809bcbceSSrinivas Kandagatla case CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0: 636809bcbceSSrinivas Kandagatla case CDC_WSA_TX0_SPKR_PROT_PATH_CTL: 637809bcbceSSrinivas Kandagatla case CDC_WSA_TX0_SPKR_PROT_PATH_CFG0: 638809bcbceSSrinivas Kandagatla case CDC_WSA_TX1_SPKR_PROT_PATH_CTL: 639809bcbceSSrinivas Kandagatla case CDC_WSA_TX1_SPKR_PROT_PATH_CFG0: 640809bcbceSSrinivas Kandagatla case CDC_WSA_TX2_SPKR_PROT_PATH_CTL: 641809bcbceSSrinivas Kandagatla case CDC_WSA_TX2_SPKR_PROT_PATH_CFG0: 642809bcbceSSrinivas Kandagatla case CDC_WSA_TX3_SPKR_PROT_PATH_CTL: 643809bcbceSSrinivas Kandagatla case CDC_WSA_TX3_SPKR_PROT_PATH_CFG0: 644809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_CFG: 645809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN1_MASK0: 646809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN2_MASK0: 647809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_LEVEL0: 648809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_BYPASS0: 649809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_SET0: 650809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_CTL: 651809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_CFG0: 652809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_CFG1: 653809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_CFG2: 654809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_CFG3: 655809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_VOL_CTL: 656809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_MIX_CTL: 657809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_MIX_CFG: 658809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_VOL_MIX_CTL: 659809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC0: 660809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC1: 661809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC2: 662809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC3: 663809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC5: 664809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC6: 665809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_SEC7: 666809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_MIX_SEC0: 667809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_MIX_SEC1: 668809bcbceSSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_DSMDEM_CTL: 669809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_CTL: 670809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_CFG0: 671809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_CFG1: 672809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_CFG2: 673809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_CFG3: 674809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_VOL_CTL: 675809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_MIX_CTL: 676809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_MIX_CFG: 677809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_VOL_MIX_CTL: 678809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC0: 679809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC1: 680809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC2: 681809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC3: 682809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC5: 683809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC6: 684809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_SEC7: 685809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_MIX_SEC0: 686809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_MIX_SEC1: 687809bcbceSSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_DSMDEM_CTL: 688809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST0_BOOST_PATH_CTL: 689809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST0_BOOST_CTL: 690809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST0_BOOST_CFG1: 691809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST0_BOOST_CFG2: 692809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST1_BOOST_PATH_CTL: 693809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST1_BOOST_CTL: 694809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST1_BOOST_CFG1: 695809bcbceSSrinivas Kandagatla case CDC_WSA_BOOST1_BOOST_CFG2: 696809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL0: 697809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL1: 698809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL2: 699809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL3: 700809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL4: 701809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL5: 702809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL7: 703809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL0: 704809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL1: 705809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL2: 706809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL3: 707809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL4: 708809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL5: 709809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL7: 710809bcbceSSrinivas Kandagatla case CDC_WSA_SOFTCLIP0_CRC: 711809bcbceSSrinivas Kandagatla case CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL: 712809bcbceSSrinivas Kandagatla case CDC_WSA_SOFTCLIP1_CRC: 713809bcbceSSrinivas Kandagatla case CDC_WSA_SOFTCLIP1_SOFTCLIP_CTRL: 714809bcbceSSrinivas Kandagatla case CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL: 715809bcbceSSrinivas Kandagatla case CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0: 716809bcbceSSrinivas Kandagatla case CDC_WSA_EC_HQ1_EC_REF_HQ_PATH_CTL: 717809bcbceSSrinivas Kandagatla case CDC_WSA_EC_HQ1_EC_REF_HQ_CFG0: 718809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_CLK_RST_CTL: 719809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_CTL0: 720809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_CTL1: 721809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_FIFO_CTL: 722809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_CLK_RST_CTL: 723809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_CTL0: 724809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_CTL1: 725809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_FIFO_CTL: 726809bcbceSSrinivas Kandagatla return true; 727809bcbceSSrinivas Kandagatla } 728809bcbceSSrinivas Kandagatla 729809bcbceSSrinivas Kandagatla return false; 730809bcbceSSrinivas Kandagatla } 731809bcbceSSrinivas Kandagatla 732809bcbceSSrinivas Kandagatla static bool wsa_is_writeable_register(struct device *dev, unsigned int reg) 733809bcbceSSrinivas Kandagatla { 734809bcbceSSrinivas Kandagatla bool ret; 735809bcbceSSrinivas Kandagatla 736809bcbceSSrinivas Kandagatla ret = wsa_is_rw_register(dev, reg); 737809bcbceSSrinivas Kandagatla if (!ret) 738809bcbceSSrinivas Kandagatla return wsa_is_wronly_register(dev, reg); 739809bcbceSSrinivas Kandagatla 740809bcbceSSrinivas Kandagatla return ret; 741809bcbceSSrinivas Kandagatla } 742809bcbceSSrinivas Kandagatla 743809bcbceSSrinivas Kandagatla static bool wsa_is_readable_register(struct device *dev, unsigned int reg) 744809bcbceSSrinivas Kandagatla { 745809bcbceSSrinivas Kandagatla switch (reg) { 746809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_CLR_COMMIT: 747809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN1_CLEAR0: 748809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN2_CLEAR0: 749809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN1_STATUS0: 750809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN2_STATUS0: 751809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL6: 752809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL6: 753809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: 754809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: 755809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: 756809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB: 757809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO: 758809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB: 759809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB: 760809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB: 761809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB: 762809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO: 763809bcbceSSrinivas Kandagatla return true; 764809bcbceSSrinivas Kandagatla } 765809bcbceSSrinivas Kandagatla 766809bcbceSSrinivas Kandagatla return wsa_is_rw_register(dev, reg); 767809bcbceSSrinivas Kandagatla } 768809bcbceSSrinivas Kandagatla 769809bcbceSSrinivas Kandagatla static bool wsa_is_volatile_register(struct device *dev, unsigned int reg) 770809bcbceSSrinivas Kandagatla { 771809bcbceSSrinivas Kandagatla /* Update volatile list for rx/tx macros */ 772809bcbceSSrinivas Kandagatla switch (reg) { 773809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN1_STATUS0: 774809bcbceSSrinivas Kandagatla case CDC_WSA_INTR_CTRL_PIN2_STATUS0: 775809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER0_CTL6: 776809bcbceSSrinivas Kandagatla case CDC_WSA_COMPANDER1_CTL6: 777809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_LSB: 778809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMIN_CNTR_MSB: 779809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_LSB: 780809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FMAX_CNTR_MSB: 781809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC0_STATUS_FIFO: 782809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_LSB: 783809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMIN_CNTR_MSB: 784809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_LSB: 785809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FMAX_CNTR_MSB: 786809bcbceSSrinivas Kandagatla case CDC_WSA_SPLINE_ASRC1_STATUS_FIFO: 787809bcbceSSrinivas Kandagatla return true; 788809bcbceSSrinivas Kandagatla } 789809bcbceSSrinivas Kandagatla return false; 790809bcbceSSrinivas Kandagatla } 791809bcbceSSrinivas Kandagatla 792809bcbceSSrinivas Kandagatla static const struct regmap_config wsa_regmap_config = { 793809bcbceSSrinivas Kandagatla .name = "wsa_macro", 794809bcbceSSrinivas Kandagatla .reg_bits = 16, 795809bcbceSSrinivas Kandagatla .val_bits = 32, /* 8 but with 32 bit read/write */ 796809bcbceSSrinivas Kandagatla .reg_stride = 4, 797809bcbceSSrinivas Kandagatla .cache_type = REGCACHE_FLAT, 798809bcbceSSrinivas Kandagatla .reg_defaults = wsa_defaults, 799809bcbceSSrinivas Kandagatla .num_reg_defaults = ARRAY_SIZE(wsa_defaults), 800809bcbceSSrinivas Kandagatla .max_register = WSA_MAX_OFFSET, 801809bcbceSSrinivas Kandagatla .writeable_reg = wsa_is_writeable_register, 802809bcbceSSrinivas Kandagatla .volatile_reg = wsa_is_volatile_register, 803809bcbceSSrinivas Kandagatla .readable_reg = wsa_is_readable_register, 804809bcbceSSrinivas Kandagatla }; 805809bcbceSSrinivas Kandagatla 806809bcbceSSrinivas Kandagatla /** 807809bcbceSSrinivas Kandagatla * wsa_macro_set_spkr_mode - Configures speaker compander and smartboost 808809bcbceSSrinivas Kandagatla * settings based on speaker mode. 809809bcbceSSrinivas Kandagatla * 810809bcbceSSrinivas Kandagatla * @component: codec instance 811809bcbceSSrinivas Kandagatla * @mode: Indicates speaker configuration mode. 812809bcbceSSrinivas Kandagatla * 813809bcbceSSrinivas Kandagatla * Returns 0 on success or -EINVAL on error. 814809bcbceSSrinivas Kandagatla */ 815809bcbceSSrinivas Kandagatla int wsa_macro_set_spkr_mode(struct snd_soc_component *component, int mode) 816809bcbceSSrinivas Kandagatla { 817809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 818809bcbceSSrinivas Kandagatla 819809bcbceSSrinivas Kandagatla wsa->spkr_mode = mode; 820809bcbceSSrinivas Kandagatla 821809bcbceSSrinivas Kandagatla switch (mode) { 822809bcbceSSrinivas Kandagatla case WSA_MACRO_SPKR_MODE_1: 823809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x00); 824809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x00); 825809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00); 826809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x00); 827809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x44); 828809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x44); 829809bcbceSSrinivas Kandagatla break; 830809bcbceSSrinivas Kandagatla default: 831809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80); 832809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL3, 0x80, 0x80); 833809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01); 834809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_COMPANDER1_CTL7, 0x01, 0x01); 835809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_BOOST0_BOOST_CTL, 0x7C, 0x58); 836809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, CDC_WSA_BOOST1_BOOST_CTL, 0x7C, 0x58); 837809bcbceSSrinivas Kandagatla break; 838809bcbceSSrinivas Kandagatla } 839809bcbceSSrinivas Kandagatla return 0; 840809bcbceSSrinivas Kandagatla } 841809bcbceSSrinivas Kandagatla EXPORT_SYMBOL(wsa_macro_set_spkr_mode); 842809bcbceSSrinivas Kandagatla 843809bcbceSSrinivas Kandagatla static int wsa_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai, 844809bcbceSSrinivas Kandagatla u8 int_prim_fs_rate_reg_val, 845809bcbceSSrinivas Kandagatla u32 sample_rate) 846809bcbceSSrinivas Kandagatla { 847809bcbceSSrinivas Kandagatla u8 int_1_mix1_inp; 848809bcbceSSrinivas Kandagatla u32 j, port; 849809bcbceSSrinivas Kandagatla u16 int_mux_cfg0, int_mux_cfg1; 850809bcbceSSrinivas Kandagatla u16 int_fs_reg; 851809bcbceSSrinivas Kandagatla u8 inp0_sel, inp1_sel, inp2_sel; 852809bcbceSSrinivas Kandagatla struct snd_soc_component *component = dai->component; 853809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 854809bcbceSSrinivas Kandagatla 855809bcbceSSrinivas Kandagatla for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) { 856809bcbceSSrinivas Kandagatla int_1_mix1_inp = port; 857809bcbceSSrinivas Kandagatla if ((int_1_mix1_inp < WSA_MACRO_RX0) || (int_1_mix1_inp > WSA_MACRO_RX_MIX1)) { 858809bcbceSSrinivas Kandagatla dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n", 859809bcbceSSrinivas Kandagatla __func__, dai->id); 860809bcbceSSrinivas Kandagatla return -EINVAL; 861809bcbceSSrinivas Kandagatla } 862809bcbceSSrinivas Kandagatla 863809bcbceSSrinivas Kandagatla int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0; 864809bcbceSSrinivas Kandagatla 865809bcbceSSrinivas Kandagatla /* 866809bcbceSSrinivas Kandagatla * Loop through all interpolator MUX inputs and find out 867809bcbceSSrinivas Kandagatla * to which interpolator input, the cdc_dma rx port 868809bcbceSSrinivas Kandagatla * is connected 869809bcbceSSrinivas Kandagatla */ 870809bcbceSSrinivas Kandagatla for (j = 0; j < NUM_INTERPOLATORS; j++) { 871809bcbceSSrinivas Kandagatla int_mux_cfg1 = int_mux_cfg0 + WSA_MACRO_MUX_CFG1_OFFSET; 8727db4c4cdSSrinivas Kandagatla inp0_sel = snd_soc_component_read_field(component, int_mux_cfg0, 8737db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK); 8747db4c4cdSSrinivas Kandagatla inp1_sel = snd_soc_component_read_field(component, int_mux_cfg0, 8757db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK); 8767db4c4cdSSrinivas Kandagatla inp2_sel = snd_soc_component_read_field(component, int_mux_cfg1, 8777db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK); 8787db4c4cdSSrinivas Kandagatla 879809bcbceSSrinivas Kandagatla if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 880809bcbceSSrinivas Kandagatla (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) || 881809bcbceSSrinivas Kandagatla (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) { 882809bcbceSSrinivas Kandagatla int_fs_reg = CDC_WSA_RX0_RX_PATH_CTL + 883809bcbceSSrinivas Kandagatla WSA_MACRO_RX_PATH_OFFSET * j; 884809bcbceSSrinivas Kandagatla /* sample_rate is in Hz */ 885809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, int_fs_reg, 886809bcbceSSrinivas Kandagatla WSA_MACRO_FS_RATE_MASK, 887809bcbceSSrinivas Kandagatla int_prim_fs_rate_reg_val); 888809bcbceSSrinivas Kandagatla } 889809bcbceSSrinivas Kandagatla int_mux_cfg0 += WSA_MACRO_MUX_CFG_OFFSET; 890809bcbceSSrinivas Kandagatla } 891809bcbceSSrinivas Kandagatla } 892809bcbceSSrinivas Kandagatla 893809bcbceSSrinivas Kandagatla return 0; 894809bcbceSSrinivas Kandagatla } 895809bcbceSSrinivas Kandagatla 896809bcbceSSrinivas Kandagatla static int wsa_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai, 897809bcbceSSrinivas Kandagatla u8 int_mix_fs_rate_reg_val, 898809bcbceSSrinivas Kandagatla u32 sample_rate) 899809bcbceSSrinivas Kandagatla { 900809bcbceSSrinivas Kandagatla u8 int_2_inp; 901809bcbceSSrinivas Kandagatla u32 j, port; 902809bcbceSSrinivas Kandagatla u16 int_mux_cfg1, int_fs_reg; 903809bcbceSSrinivas Kandagatla u8 int_mux_cfg1_val; 904809bcbceSSrinivas Kandagatla struct snd_soc_component *component = dai->component; 905809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 906809bcbceSSrinivas Kandagatla 907809bcbceSSrinivas Kandagatla for_each_set_bit(port, &wsa->active_ch_mask[dai->id], WSA_MACRO_RX_MAX) { 908809bcbceSSrinivas Kandagatla int_2_inp = port; 909809bcbceSSrinivas Kandagatla if ((int_2_inp < WSA_MACRO_RX0) || (int_2_inp > WSA_MACRO_RX_MIX1)) { 910809bcbceSSrinivas Kandagatla dev_err(component->dev, "%s: Invalid RX port, Dai ID is %d\n", 911809bcbceSSrinivas Kandagatla __func__, dai->id); 912809bcbceSSrinivas Kandagatla return -EINVAL; 913809bcbceSSrinivas Kandagatla } 914809bcbceSSrinivas Kandagatla 915809bcbceSSrinivas Kandagatla int_mux_cfg1 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG1; 916809bcbceSSrinivas Kandagatla for (j = 0; j < NUM_INTERPOLATORS; j++) { 9177db4c4cdSSrinivas Kandagatla int_mux_cfg1_val = snd_soc_component_read_field(component, int_mux_cfg1, 9187db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_2_SEL_MASK); 9197db4c4cdSSrinivas Kandagatla 920809bcbceSSrinivas Kandagatla if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) { 921809bcbceSSrinivas Kandagatla int_fs_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL + 922809bcbceSSrinivas Kandagatla WSA_MACRO_RX_PATH_OFFSET * j; 923809bcbceSSrinivas Kandagatla 924809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(component, 925809bcbceSSrinivas Kandagatla int_fs_reg, 926809bcbceSSrinivas Kandagatla WSA_MACRO_FS_RATE_MASK, 927809bcbceSSrinivas Kandagatla int_mix_fs_rate_reg_val); 928809bcbceSSrinivas Kandagatla } 929809bcbceSSrinivas Kandagatla int_mux_cfg1 += WSA_MACRO_MUX_CFG_OFFSET; 930809bcbceSSrinivas Kandagatla } 931809bcbceSSrinivas Kandagatla } 932809bcbceSSrinivas Kandagatla return 0; 933809bcbceSSrinivas Kandagatla } 934809bcbceSSrinivas Kandagatla 935809bcbceSSrinivas Kandagatla static int wsa_macro_set_interpolator_rate(struct snd_soc_dai *dai, 936809bcbceSSrinivas Kandagatla u32 sample_rate) 937809bcbceSSrinivas Kandagatla { 938809bcbceSSrinivas Kandagatla int rate_val = 0; 939809bcbceSSrinivas Kandagatla int i, ret; 940809bcbceSSrinivas Kandagatla 941809bcbceSSrinivas Kandagatla /* set mixing path rate */ 942809bcbceSSrinivas Kandagatla for (i = 0; i < ARRAY_SIZE(int_mix_sample_rate_val); i++) { 943809bcbceSSrinivas Kandagatla if (sample_rate == int_mix_sample_rate_val[i].sample_rate) { 944809bcbceSSrinivas Kandagatla rate_val = int_mix_sample_rate_val[i].rate_val; 945809bcbceSSrinivas Kandagatla break; 946809bcbceSSrinivas Kandagatla } 947809bcbceSSrinivas Kandagatla } 948809bcbceSSrinivas Kandagatla if ((i == ARRAY_SIZE(int_mix_sample_rate_val)) || (rate_val < 0)) 949809bcbceSSrinivas Kandagatla goto prim_rate; 950809bcbceSSrinivas Kandagatla 951809bcbceSSrinivas Kandagatla ret = wsa_macro_set_mix_interpolator_rate(dai, (u8) rate_val, sample_rate); 9524b4f2119SPierre-Louis Bossart if (ret < 0) 9534b4f2119SPierre-Louis Bossart return ret; 954809bcbceSSrinivas Kandagatla prim_rate: 955809bcbceSSrinivas Kandagatla /* set primary path sample rate */ 956809bcbceSSrinivas Kandagatla for (i = 0; i < ARRAY_SIZE(int_prim_sample_rate_val); i++) { 957809bcbceSSrinivas Kandagatla if (sample_rate == int_prim_sample_rate_val[i].sample_rate) { 958809bcbceSSrinivas Kandagatla rate_val = int_prim_sample_rate_val[i].rate_val; 959809bcbceSSrinivas Kandagatla break; 960809bcbceSSrinivas Kandagatla } 961809bcbceSSrinivas Kandagatla } 962809bcbceSSrinivas Kandagatla if ((i == ARRAY_SIZE(int_prim_sample_rate_val)) || (rate_val < 0)) 963809bcbceSSrinivas Kandagatla return -EINVAL; 964809bcbceSSrinivas Kandagatla 965809bcbceSSrinivas Kandagatla ret = wsa_macro_set_prim_interpolator_rate(dai, (u8) rate_val, sample_rate); 966809bcbceSSrinivas Kandagatla 967809bcbceSSrinivas Kandagatla return ret; 968809bcbceSSrinivas Kandagatla } 969809bcbceSSrinivas Kandagatla 970809bcbceSSrinivas Kandagatla static int wsa_macro_hw_params(struct snd_pcm_substream *substream, 971809bcbceSSrinivas Kandagatla struct snd_pcm_hw_params *params, 972809bcbceSSrinivas Kandagatla struct snd_soc_dai *dai) 973809bcbceSSrinivas Kandagatla { 974809bcbceSSrinivas Kandagatla struct snd_soc_component *component = dai->component; 975809bcbceSSrinivas Kandagatla int ret; 976809bcbceSSrinivas Kandagatla 977809bcbceSSrinivas Kandagatla switch (substream->stream) { 978809bcbceSSrinivas Kandagatla case SNDRV_PCM_STREAM_PLAYBACK: 979809bcbceSSrinivas Kandagatla ret = wsa_macro_set_interpolator_rate(dai, params_rate(params)); 980809bcbceSSrinivas Kandagatla if (ret) { 981809bcbceSSrinivas Kandagatla dev_err(component->dev, 982809bcbceSSrinivas Kandagatla "%s: cannot set sample rate: %u\n", 983809bcbceSSrinivas Kandagatla __func__, params_rate(params)); 984809bcbceSSrinivas Kandagatla return ret; 985809bcbceSSrinivas Kandagatla } 986809bcbceSSrinivas Kandagatla break; 987809bcbceSSrinivas Kandagatla default: 988809bcbceSSrinivas Kandagatla break; 989809bcbceSSrinivas Kandagatla } 990809bcbceSSrinivas Kandagatla return 0; 991809bcbceSSrinivas Kandagatla } 992809bcbceSSrinivas Kandagatla 993809bcbceSSrinivas Kandagatla static int wsa_macro_get_channel_map(struct snd_soc_dai *dai, 994809bcbceSSrinivas Kandagatla unsigned int *tx_num, unsigned int *tx_slot, 995809bcbceSSrinivas Kandagatla unsigned int *rx_num, unsigned int *rx_slot) 996809bcbceSSrinivas Kandagatla { 997809bcbceSSrinivas Kandagatla struct snd_soc_component *component = dai->component; 998809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 999809bcbceSSrinivas Kandagatla u16 val, mask = 0, cnt = 0, temp; 1000809bcbceSSrinivas Kandagatla 1001809bcbceSSrinivas Kandagatla switch (dai->id) { 1002809bcbceSSrinivas Kandagatla case WSA_MACRO_AIF_VI: 1003809bcbceSSrinivas Kandagatla *tx_slot = wsa->active_ch_mask[dai->id]; 1004809bcbceSSrinivas Kandagatla *tx_num = wsa->active_ch_cnt[dai->id]; 1005809bcbceSSrinivas Kandagatla break; 1006809bcbceSSrinivas Kandagatla case WSA_MACRO_AIF1_PB: 1007809bcbceSSrinivas Kandagatla case WSA_MACRO_AIF_MIX1_PB: 1008809bcbceSSrinivas Kandagatla for_each_set_bit(temp, &wsa->active_ch_mask[dai->id], 1009809bcbceSSrinivas Kandagatla WSA_MACRO_RX_MAX) { 1010809bcbceSSrinivas Kandagatla mask |= (1 << temp); 1011809bcbceSSrinivas Kandagatla if (++cnt == WSA_MACRO_MAX_DMA_CH_PER_PORT) 1012809bcbceSSrinivas Kandagatla break; 1013809bcbceSSrinivas Kandagatla } 1014809bcbceSSrinivas Kandagatla if (mask & 0x0C) 1015809bcbceSSrinivas Kandagatla mask = mask >> 0x2; 1016809bcbceSSrinivas Kandagatla *rx_slot = mask; 1017809bcbceSSrinivas Kandagatla *rx_num = cnt; 1018809bcbceSSrinivas Kandagatla break; 1019809bcbceSSrinivas Kandagatla case WSA_MACRO_AIF_ECHO: 1020809bcbceSSrinivas Kandagatla val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0); 1021809bcbceSSrinivas Kandagatla if (val & WSA_MACRO_EC_MIX_TX1_MASK) { 1022809bcbceSSrinivas Kandagatla mask |= 0x2; 1023809bcbceSSrinivas Kandagatla cnt++; 1024809bcbceSSrinivas Kandagatla } 1025809bcbceSSrinivas Kandagatla if (val & WSA_MACRO_EC_MIX_TX0_MASK) { 1026809bcbceSSrinivas Kandagatla mask |= 0x1; 1027809bcbceSSrinivas Kandagatla cnt++; 1028809bcbceSSrinivas Kandagatla } 1029809bcbceSSrinivas Kandagatla *tx_slot = mask; 1030809bcbceSSrinivas Kandagatla *tx_num = cnt; 1031809bcbceSSrinivas Kandagatla break; 1032809bcbceSSrinivas Kandagatla default: 1033809bcbceSSrinivas Kandagatla dev_err(component->dev, "%s: Invalid AIF\n", __func__); 1034809bcbceSSrinivas Kandagatla break; 1035809bcbceSSrinivas Kandagatla } 1036809bcbceSSrinivas Kandagatla return 0; 1037809bcbceSSrinivas Kandagatla } 1038809bcbceSSrinivas Kandagatla 1039a893a666SYe Bin static const struct snd_soc_dai_ops wsa_macro_dai_ops = { 1040809bcbceSSrinivas Kandagatla .hw_params = wsa_macro_hw_params, 1041809bcbceSSrinivas Kandagatla .get_channel_map = wsa_macro_get_channel_map, 1042809bcbceSSrinivas Kandagatla }; 1043809bcbceSSrinivas Kandagatla 1044809bcbceSSrinivas Kandagatla static struct snd_soc_dai_driver wsa_macro_dai[] = { 1045809bcbceSSrinivas Kandagatla { 1046809bcbceSSrinivas Kandagatla .name = "wsa_macro_rx1", 1047809bcbceSSrinivas Kandagatla .id = WSA_MACRO_AIF1_PB, 1048809bcbceSSrinivas Kandagatla .playback = { 1049809bcbceSSrinivas Kandagatla .stream_name = "WSA_AIF1 Playback", 1050809bcbceSSrinivas Kandagatla .rates = WSA_MACRO_RX_RATES, 1051809bcbceSSrinivas Kandagatla .formats = WSA_MACRO_RX_FORMATS, 1052809bcbceSSrinivas Kandagatla .rate_max = 384000, 1053809bcbceSSrinivas Kandagatla .rate_min = 8000, 1054809bcbceSSrinivas Kandagatla .channels_min = 1, 1055809bcbceSSrinivas Kandagatla .channels_max = 2, 1056809bcbceSSrinivas Kandagatla }, 1057809bcbceSSrinivas Kandagatla .ops = &wsa_macro_dai_ops, 1058809bcbceSSrinivas Kandagatla }, 1059809bcbceSSrinivas Kandagatla { 1060809bcbceSSrinivas Kandagatla .name = "wsa_macro_rx_mix", 1061809bcbceSSrinivas Kandagatla .id = WSA_MACRO_AIF_MIX1_PB, 1062809bcbceSSrinivas Kandagatla .playback = { 1063809bcbceSSrinivas Kandagatla .stream_name = "WSA_AIF_MIX1 Playback", 1064809bcbceSSrinivas Kandagatla .rates = WSA_MACRO_RX_MIX_RATES, 1065809bcbceSSrinivas Kandagatla .formats = WSA_MACRO_RX_FORMATS, 1066809bcbceSSrinivas Kandagatla .rate_max = 192000, 1067809bcbceSSrinivas Kandagatla .rate_min = 48000, 1068809bcbceSSrinivas Kandagatla .channels_min = 1, 1069809bcbceSSrinivas Kandagatla .channels_max = 2, 1070809bcbceSSrinivas Kandagatla }, 1071809bcbceSSrinivas Kandagatla .ops = &wsa_macro_dai_ops, 1072809bcbceSSrinivas Kandagatla }, 1073809bcbceSSrinivas Kandagatla { 1074809bcbceSSrinivas Kandagatla .name = "wsa_macro_vifeedback", 1075809bcbceSSrinivas Kandagatla .id = WSA_MACRO_AIF_VI, 1076809bcbceSSrinivas Kandagatla .capture = { 1077809bcbceSSrinivas Kandagatla .stream_name = "WSA_AIF_VI Capture", 1078809bcbceSSrinivas Kandagatla .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_48000, 1079809bcbceSSrinivas Kandagatla .formats = WSA_MACRO_RX_FORMATS, 1080809bcbceSSrinivas Kandagatla .rate_max = 48000, 1081809bcbceSSrinivas Kandagatla .rate_min = 8000, 1082809bcbceSSrinivas Kandagatla .channels_min = 1, 1083809bcbceSSrinivas Kandagatla .channels_max = 4, 1084809bcbceSSrinivas Kandagatla }, 1085809bcbceSSrinivas Kandagatla .ops = &wsa_macro_dai_ops, 1086809bcbceSSrinivas Kandagatla }, 1087809bcbceSSrinivas Kandagatla { 1088809bcbceSSrinivas Kandagatla .name = "wsa_macro_echo", 1089809bcbceSSrinivas Kandagatla .id = WSA_MACRO_AIF_ECHO, 1090809bcbceSSrinivas Kandagatla .capture = { 1091809bcbceSSrinivas Kandagatla .stream_name = "WSA_AIF_ECHO Capture", 1092809bcbceSSrinivas Kandagatla .rates = WSA_MACRO_ECHO_RATES, 1093809bcbceSSrinivas Kandagatla .formats = WSA_MACRO_ECHO_FORMATS, 1094809bcbceSSrinivas Kandagatla .rate_max = 48000, 1095809bcbceSSrinivas Kandagatla .rate_min = 8000, 1096809bcbceSSrinivas Kandagatla .channels_min = 1, 1097809bcbceSSrinivas Kandagatla .channels_max = 2, 1098809bcbceSSrinivas Kandagatla }, 1099809bcbceSSrinivas Kandagatla .ops = &wsa_macro_dai_ops, 1100809bcbceSSrinivas Kandagatla }, 1101809bcbceSSrinivas Kandagatla }; 1102809bcbceSSrinivas Kandagatla 1103809bcbceSSrinivas Kandagatla static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable) 1104809bcbceSSrinivas Kandagatla { 1105809bcbceSSrinivas Kandagatla struct regmap *regmap = wsa->regmap; 1106809bcbceSSrinivas Kandagatla 1107809bcbceSSrinivas Kandagatla if (mclk_enable) { 1108809bcbceSSrinivas Kandagatla if (wsa->wsa_mclk_users == 0) { 1109809bcbceSSrinivas Kandagatla regcache_mark_dirty(regmap); 1110809bcbceSSrinivas Kandagatla regcache_sync(regmap); 1111809bcbceSSrinivas Kandagatla /* 9.6MHz MCLK, set value 0x00 if other frequency */ 1112809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, CDC_WSA_TOP_FREQ_MCLK, 0x01, 0x01); 1113809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, 1114809bcbceSSrinivas Kandagatla CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 1115809bcbceSSrinivas Kandagatla CDC_WSA_MCLK_EN_MASK, 1116809bcbceSSrinivas Kandagatla CDC_WSA_MCLK_ENABLE); 1117809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, 1118809bcbceSSrinivas Kandagatla CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 1119809bcbceSSrinivas Kandagatla CDC_WSA_FS_CNT_EN_MASK, 1120809bcbceSSrinivas Kandagatla CDC_WSA_FS_CNT_ENABLE); 1121809bcbceSSrinivas Kandagatla } 1122809bcbceSSrinivas Kandagatla wsa->wsa_mclk_users++; 1123809bcbceSSrinivas Kandagatla } else { 1124809bcbceSSrinivas Kandagatla if (wsa->wsa_mclk_users <= 0) { 1125809bcbceSSrinivas Kandagatla dev_err(wsa->dev, "clock already disabled\n"); 1126809bcbceSSrinivas Kandagatla wsa->wsa_mclk_users = 0; 1127809bcbceSSrinivas Kandagatla return; 1128809bcbceSSrinivas Kandagatla } 1129809bcbceSSrinivas Kandagatla wsa->wsa_mclk_users--; 1130809bcbceSSrinivas Kandagatla if (wsa->wsa_mclk_users == 0) { 1131809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, 1132809bcbceSSrinivas Kandagatla CDC_WSA_CLK_RST_CTRL_FS_CNT_CONTROL, 1133809bcbceSSrinivas Kandagatla CDC_WSA_FS_CNT_EN_MASK, 1134809bcbceSSrinivas Kandagatla CDC_WSA_FS_CNT_DISABLE); 1135809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, 1136809bcbceSSrinivas Kandagatla CDC_WSA_CLK_RST_CTRL_MCLK_CONTROL, 1137809bcbceSSrinivas Kandagatla CDC_WSA_MCLK_EN_MASK, 1138809bcbceSSrinivas Kandagatla CDC_WSA_MCLK_DISABLE); 1139809bcbceSSrinivas Kandagatla } 1140809bcbceSSrinivas Kandagatla } 1141809bcbceSSrinivas Kandagatla } 1142809bcbceSSrinivas Kandagatla 11432c4066e5SSrinivas Kandagatla static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w, 11442c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, int event) 11452c4066e5SSrinivas Kandagatla { 11462c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 11472c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 11482c4066e5SSrinivas Kandagatla 11492c4066e5SSrinivas Kandagatla wsa_macro_mclk_enable(wsa, event == SND_SOC_DAPM_PRE_PMU); 11502c4066e5SSrinivas Kandagatla return 0; 11512c4066e5SSrinivas Kandagatla } 11522c4066e5SSrinivas Kandagatla 11532c4066e5SSrinivas Kandagatla static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w, 11542c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, 11552c4066e5SSrinivas Kandagatla int event) 11562c4066e5SSrinivas Kandagatla { 11572c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 11582c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 11592c4066e5SSrinivas Kandagatla u32 tx_reg0, tx_reg1; 11602c4066e5SSrinivas Kandagatla 11612c4066e5SSrinivas Kandagatla if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 11622c4066e5SSrinivas Kandagatla tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL; 11632c4066e5SSrinivas Kandagatla tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL; 11642c4066e5SSrinivas Kandagatla } else if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 11652c4066e5SSrinivas Kandagatla tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL; 11662c4066e5SSrinivas Kandagatla tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL; 11672c4066e5SSrinivas Kandagatla } 11682c4066e5SSrinivas Kandagatla 11692c4066e5SSrinivas Kandagatla switch (event) { 11702c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMU: 11712c4066e5SSrinivas Kandagatla /* Enable V&I sensing */ 11722c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg0, 11732c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET_MASK, 11742c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET); 11752c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg1, 11762c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET_MASK, 11772c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET); 11782c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg0, 11792c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK, 11802c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K); 11812c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg1, 11822c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK, 11832c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_PCM_RATE_8K); 11842c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg0, 11852c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 11862c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_ENABLE); 11872c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg1, 11882c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 11892c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_ENABLE); 11902c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg0, 11912c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET_MASK, 11922c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_NO_RESET); 11932c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg1, 11942c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET_MASK, 11952c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_NO_RESET); 11962c4066e5SSrinivas Kandagatla break; 11972c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMD: 11982c4066e5SSrinivas Kandagatla /* Disable V&I sensing */ 11992c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg0, 12002c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET_MASK, 12012c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET); 12022c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg1, 12032c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET_MASK, 12042c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_RESET); 12052c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg0, 12062c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 12072c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_DISABLE); 12082c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, tx_reg1, 12092c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK, 12102c4066e5SSrinivas Kandagatla CDC_WSA_TX_SPKR_PROT_CLK_DISABLE); 12112c4066e5SSrinivas Kandagatla break; 12122c4066e5SSrinivas Kandagatla } 12132c4066e5SSrinivas Kandagatla 12142c4066e5SSrinivas Kandagatla return 0; 12152c4066e5SSrinivas Kandagatla } 12162c4066e5SSrinivas Kandagatla 12172c4066e5SSrinivas Kandagatla static int wsa_macro_enable_mix_path(struct snd_soc_dapm_widget *w, 12182c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, int event) 12192c4066e5SSrinivas Kandagatla { 12202c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 1221e4b8b7c9SJonathan Marek u16 path_reg, gain_reg; 12222c4066e5SSrinivas Kandagatla int val; 12232c4066e5SSrinivas Kandagatla 1224e4b8b7c9SJonathan Marek switch (w->shift) { 1225e4b8b7c9SJonathan Marek case WSA_MACRO_RX_MIX0: 1226e4b8b7c9SJonathan Marek path_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL; 12272c4066e5SSrinivas Kandagatla gain_reg = CDC_WSA_RX0_RX_VOL_MIX_CTL; 12282c4066e5SSrinivas Kandagatla break; 1229e4b8b7c9SJonathan Marek case WSA_MACRO_RX_MIX1: 1230e4b8b7c9SJonathan Marek path_reg = CDC_WSA_RX1_RX_PATH_MIX_CTL; 12312c4066e5SSrinivas Kandagatla gain_reg = CDC_WSA_RX1_RX_VOL_MIX_CTL; 12322c4066e5SSrinivas Kandagatla break; 12332c4066e5SSrinivas Kandagatla default: 12342c4066e5SSrinivas Kandagatla return 0; 12352c4066e5SSrinivas Kandagatla } 12362c4066e5SSrinivas Kandagatla 12372c4066e5SSrinivas Kandagatla switch (event) { 12382c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMU: 12392c4066e5SSrinivas Kandagatla val = snd_soc_component_read(component, gain_reg); 12402c4066e5SSrinivas Kandagatla snd_soc_component_write(component, gain_reg, val); 12412c4066e5SSrinivas Kandagatla break; 12422c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMD: 1243e4b8b7c9SJonathan Marek snd_soc_component_update_bits(component, path_reg, 12442c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_MIX_CLK_EN_MASK, 12452c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_MIX_CLK_DISABLE); 12462c4066e5SSrinivas Kandagatla break; 12472c4066e5SSrinivas Kandagatla } 12482c4066e5SSrinivas Kandagatla 12492c4066e5SSrinivas Kandagatla return 0; 12502c4066e5SSrinivas Kandagatla } 12512c4066e5SSrinivas Kandagatla 12522c4066e5SSrinivas Kandagatla static void wsa_macro_hd2_control(struct snd_soc_component *component, 12532c4066e5SSrinivas Kandagatla u16 reg, int event) 12542c4066e5SSrinivas Kandagatla { 12552c4066e5SSrinivas Kandagatla u16 hd2_scale_reg; 12562c4066e5SSrinivas Kandagatla u16 hd2_enable_reg; 12572c4066e5SSrinivas Kandagatla 12582c4066e5SSrinivas Kandagatla if (reg == CDC_WSA_RX0_RX_PATH_CTL) { 12592c4066e5SSrinivas Kandagatla hd2_scale_reg = CDC_WSA_RX0_RX_PATH_SEC3; 12602c4066e5SSrinivas Kandagatla hd2_enable_reg = CDC_WSA_RX0_RX_PATH_CFG0; 12612c4066e5SSrinivas Kandagatla } 12622c4066e5SSrinivas Kandagatla if (reg == CDC_WSA_RX1_RX_PATH_CTL) { 12632c4066e5SSrinivas Kandagatla hd2_scale_reg = CDC_WSA_RX1_RX_PATH_SEC3; 12642c4066e5SSrinivas Kandagatla hd2_enable_reg = CDC_WSA_RX1_RX_PATH_CFG0; 12652c4066e5SSrinivas Kandagatla } 12662c4066e5SSrinivas Kandagatla 12672c4066e5SSrinivas Kandagatla if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) { 12682c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, hd2_scale_reg, 12692c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_ALPHA_MASK, 12702c4066e5SSrinivas Kandagatla 0x10); 12712c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, hd2_scale_reg, 12722c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_SCALE_MASK, 12732c4066e5SSrinivas Kandagatla 0x1); 12742c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, hd2_enable_reg, 12752c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_EN_MASK, 12762c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_ENABLE); 12772c4066e5SSrinivas Kandagatla } 12782c4066e5SSrinivas Kandagatla 12792c4066e5SSrinivas Kandagatla if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) { 12802c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, hd2_enable_reg, 12812c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_EN_MASK, 0); 12822c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, hd2_scale_reg, 12832c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_SCALE_MASK, 12842c4066e5SSrinivas Kandagatla 0); 12852c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, hd2_scale_reg, 12862c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_HD2_ALPHA_MASK, 12872c4066e5SSrinivas Kandagatla 0); 12882c4066e5SSrinivas Kandagatla } 12892c4066e5SSrinivas Kandagatla } 12902c4066e5SSrinivas Kandagatla 12912c4066e5SSrinivas Kandagatla static int wsa_macro_config_compander(struct snd_soc_component *component, 12922c4066e5SSrinivas Kandagatla int comp, int event) 12932c4066e5SSrinivas Kandagatla { 12942c4066e5SSrinivas Kandagatla u16 comp_ctl0_reg, rx_path_cfg0_reg; 12952c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 12962c4066e5SSrinivas Kandagatla 12972c4066e5SSrinivas Kandagatla if (!wsa->comp_enabled[comp]) 12982c4066e5SSrinivas Kandagatla return 0; 12992c4066e5SSrinivas Kandagatla 13002c4066e5SSrinivas Kandagatla comp_ctl0_reg = CDC_WSA_COMPANDER0_CTL0 + 13012c4066e5SSrinivas Kandagatla (comp * WSA_MACRO_RX_COMP_OFFSET); 13022c4066e5SSrinivas Kandagatla rx_path_cfg0_reg = CDC_WSA_RX0_RX_PATH_CFG0 + 13032c4066e5SSrinivas Kandagatla (comp * WSA_MACRO_RX_PATH_OFFSET); 13042c4066e5SSrinivas Kandagatla 13052c4066e5SSrinivas Kandagatla if (SND_SOC_DAPM_EVENT_ON(event)) { 13062c4066e5SSrinivas Kandagatla /* Enable Compander Clock */ 13072c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13082c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_CLK_EN_MASK, 13092c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_CLK_ENABLE); 13102c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13112c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_SOFT_RST_MASK, 13122c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_SOFT_RST_ENABLE); 13132c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13142c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_SOFT_RST_MASK, 13152c4066e5SSrinivas Kandagatla 0); 13162c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, rx_path_cfg0_reg, 13172c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_COMP_EN_MASK, 13182c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_COMP_ENABLE); 13192c4066e5SSrinivas Kandagatla } 13202c4066e5SSrinivas Kandagatla 13212c4066e5SSrinivas Kandagatla if (SND_SOC_DAPM_EVENT_OFF(event)) { 13222c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13232c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_HALT_MASK, 13242c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_HALT); 13252c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, rx_path_cfg0_reg, 13262c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_COMP_EN_MASK, 0); 13272c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13282c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_SOFT_RST_MASK, 13292c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_SOFT_RST_ENABLE); 13302c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13312c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_SOFT_RST_MASK, 13322c4066e5SSrinivas Kandagatla 0); 13332c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13342c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_CLK_EN_MASK, 0); 13352c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, comp_ctl0_reg, 13362c4066e5SSrinivas Kandagatla CDC_WSA_COMPANDER_HALT_MASK, 0); 13372c4066e5SSrinivas Kandagatla } 13382c4066e5SSrinivas Kandagatla 13392c4066e5SSrinivas Kandagatla return 0; 13402c4066e5SSrinivas Kandagatla } 13412c4066e5SSrinivas Kandagatla 13422c4066e5SSrinivas Kandagatla static void wsa_macro_enable_softclip_clk(struct snd_soc_component *component, 13432c4066e5SSrinivas Kandagatla struct wsa_macro *wsa, 13442c4066e5SSrinivas Kandagatla int path, 13452c4066e5SSrinivas Kandagatla bool enable) 13462c4066e5SSrinivas Kandagatla { 13472c4066e5SSrinivas Kandagatla u16 softclip_clk_reg = CDC_WSA_SOFTCLIP0_CRC + 13482c4066e5SSrinivas Kandagatla (path * WSA_MACRO_RX_SOFTCLIP_OFFSET); 13492c4066e5SSrinivas Kandagatla u8 softclip_mux_mask = (1 << path); 13502c4066e5SSrinivas Kandagatla u8 softclip_mux_value = (1 << path); 13512c4066e5SSrinivas Kandagatla 13522c4066e5SSrinivas Kandagatla if (enable) { 13532c4066e5SSrinivas Kandagatla if (wsa->softclip_clk_users[path] == 0) { 13542c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 13552c4066e5SSrinivas Kandagatla softclip_clk_reg, 13562c4066e5SSrinivas Kandagatla CDC_WSA_SOFTCLIP_CLK_EN_MASK, 13572c4066e5SSrinivas Kandagatla CDC_WSA_SOFTCLIP_CLK_ENABLE); 13582c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 13592c4066e5SSrinivas Kandagatla CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 13602c4066e5SSrinivas Kandagatla softclip_mux_mask, softclip_mux_value); 13612c4066e5SSrinivas Kandagatla } 13622c4066e5SSrinivas Kandagatla wsa->softclip_clk_users[path]++; 13632c4066e5SSrinivas Kandagatla } else { 13642c4066e5SSrinivas Kandagatla wsa->softclip_clk_users[path]--; 13652c4066e5SSrinivas Kandagatla if (wsa->softclip_clk_users[path] == 0) { 13662c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 13672c4066e5SSrinivas Kandagatla softclip_clk_reg, 13682c4066e5SSrinivas Kandagatla CDC_WSA_SOFTCLIP_CLK_EN_MASK, 13692c4066e5SSrinivas Kandagatla 0); 13702c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 13712c4066e5SSrinivas Kandagatla CDC_WSA_RX_INP_MUX_SOFTCLIP_CFG0, 13722c4066e5SSrinivas Kandagatla softclip_mux_mask, 0x00); 13732c4066e5SSrinivas Kandagatla } 13742c4066e5SSrinivas Kandagatla } 13752c4066e5SSrinivas Kandagatla } 13762c4066e5SSrinivas Kandagatla 13772c4066e5SSrinivas Kandagatla static int wsa_macro_config_softclip(struct snd_soc_component *component, 13782c4066e5SSrinivas Kandagatla int path, int event) 13792c4066e5SSrinivas Kandagatla { 13802c4066e5SSrinivas Kandagatla u16 softclip_ctrl_reg; 13812c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 13822c4066e5SSrinivas Kandagatla int softclip_path = 0; 13832c4066e5SSrinivas Kandagatla 13842c4066e5SSrinivas Kandagatla if (path == WSA_MACRO_COMP1) 13852c4066e5SSrinivas Kandagatla softclip_path = WSA_MACRO_SOFTCLIP0; 13862c4066e5SSrinivas Kandagatla else if (path == WSA_MACRO_COMP2) 13872c4066e5SSrinivas Kandagatla softclip_path = WSA_MACRO_SOFTCLIP1; 13882c4066e5SSrinivas Kandagatla 13892c4066e5SSrinivas Kandagatla if (!wsa->is_softclip_on[softclip_path]) 13902c4066e5SSrinivas Kandagatla return 0; 13912c4066e5SSrinivas Kandagatla 13922c4066e5SSrinivas Kandagatla softclip_ctrl_reg = CDC_WSA_SOFTCLIP0_SOFTCLIP_CTRL + 13932c4066e5SSrinivas Kandagatla (softclip_path * WSA_MACRO_RX_SOFTCLIP_OFFSET); 13942c4066e5SSrinivas Kandagatla 13952c4066e5SSrinivas Kandagatla if (SND_SOC_DAPM_EVENT_ON(event)) { 13962c4066e5SSrinivas Kandagatla /* Enable Softclip clock and mux */ 13972c4066e5SSrinivas Kandagatla wsa_macro_enable_softclip_clk(component, wsa, softclip_path, 13982c4066e5SSrinivas Kandagatla true); 13992c4066e5SSrinivas Kandagatla /* Enable Softclip control */ 14002c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, softclip_ctrl_reg, 14012c4066e5SSrinivas Kandagatla CDC_WSA_SOFTCLIP_EN_MASK, 14022c4066e5SSrinivas Kandagatla CDC_WSA_SOFTCLIP_ENABLE); 14032c4066e5SSrinivas Kandagatla } 14042c4066e5SSrinivas Kandagatla 14052c4066e5SSrinivas Kandagatla if (SND_SOC_DAPM_EVENT_OFF(event)) { 14062c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, softclip_ctrl_reg, 14072c4066e5SSrinivas Kandagatla CDC_WSA_SOFTCLIP_EN_MASK, 0); 14082c4066e5SSrinivas Kandagatla wsa_macro_enable_softclip_clk(component, wsa, softclip_path, 14092c4066e5SSrinivas Kandagatla false); 14102c4066e5SSrinivas Kandagatla } 14112c4066e5SSrinivas Kandagatla 14122c4066e5SSrinivas Kandagatla return 0; 14132c4066e5SSrinivas Kandagatla } 14142c4066e5SSrinivas Kandagatla 14152c4066e5SSrinivas Kandagatla static bool wsa_macro_adie_lb(struct snd_soc_component *component, 14162c4066e5SSrinivas Kandagatla int interp_idx) 14172c4066e5SSrinivas Kandagatla { 14182c4066e5SSrinivas Kandagatla u16 int_mux_cfg0, int_mux_cfg1; 14192c4066e5SSrinivas Kandagatla u8 int_n_inp0, int_n_inp1, int_n_inp2; 14202c4066e5SSrinivas Kandagatla 14212c4066e5SSrinivas Kandagatla int_mux_cfg0 = CDC_WSA_RX_INP_MUX_RX_INT0_CFG0 + interp_idx * 8; 14222c4066e5SSrinivas Kandagatla int_mux_cfg1 = int_mux_cfg0 + 4; 14232c4066e5SSrinivas Kandagatla 14247db4c4cdSSrinivas Kandagatla int_n_inp0 = snd_soc_component_read_field(component, int_mux_cfg0, 14257db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_1_MIX_INP0_SEL_MASK); 14262c4066e5SSrinivas Kandagatla if (int_n_inp0 == INTn_1_INP_SEL_DEC0 || 14272c4066e5SSrinivas Kandagatla int_n_inp0 == INTn_1_INP_SEL_DEC1) 14282c4066e5SSrinivas Kandagatla return true; 14292c4066e5SSrinivas Kandagatla 14307db4c4cdSSrinivas Kandagatla int_n_inp1 = snd_soc_component_read_field(component, int_mux_cfg0, 14317db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_1_MIX_INP1_SEL_MASK); 14322c4066e5SSrinivas Kandagatla if (int_n_inp1 == INTn_1_INP_SEL_DEC0 || 14332c4066e5SSrinivas Kandagatla int_n_inp1 == INTn_1_INP_SEL_DEC1) 14342c4066e5SSrinivas Kandagatla return true; 14352c4066e5SSrinivas Kandagatla 14367db4c4cdSSrinivas Kandagatla int_n_inp2 = snd_soc_component_read_field(component, int_mux_cfg1, 14377db4c4cdSSrinivas Kandagatla CDC_WSA_RX_INTX_1_MIX_INP2_SEL_MASK); 14382c4066e5SSrinivas Kandagatla if (int_n_inp2 == INTn_1_INP_SEL_DEC0 || 14392c4066e5SSrinivas Kandagatla int_n_inp2 == INTn_1_INP_SEL_DEC1) 14402c4066e5SSrinivas Kandagatla return true; 14412c4066e5SSrinivas Kandagatla 14422c4066e5SSrinivas Kandagatla return false; 14432c4066e5SSrinivas Kandagatla } 14442c4066e5SSrinivas Kandagatla 14452c4066e5SSrinivas Kandagatla static int wsa_macro_enable_main_path(struct snd_soc_dapm_widget *w, 14462c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, 14472c4066e5SSrinivas Kandagatla int event) 14482c4066e5SSrinivas Kandagatla { 14492c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 14502c4066e5SSrinivas Kandagatla u16 reg; 14512c4066e5SSrinivas Kandagatla 14522c4066e5SSrinivas Kandagatla reg = CDC_WSA_RX0_RX_PATH_CTL + WSA_MACRO_RX_PATH_OFFSET * w->shift; 14532c4066e5SSrinivas Kandagatla switch (event) { 14542c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_PRE_PMU: 14552c4066e5SSrinivas Kandagatla if (wsa_macro_adie_lb(component, w->shift)) { 14562c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, reg, 14572c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_CLK_EN_MASK, 14582c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_CLK_ENABLE); 14592c4066e5SSrinivas Kandagatla } 14602c4066e5SSrinivas Kandagatla break; 14612c4066e5SSrinivas Kandagatla default: 14622c4066e5SSrinivas Kandagatla break; 14632c4066e5SSrinivas Kandagatla } 14642c4066e5SSrinivas Kandagatla return 0; 14652c4066e5SSrinivas Kandagatla } 14662c4066e5SSrinivas Kandagatla 14672c4066e5SSrinivas Kandagatla static int wsa_macro_interp_get_primary_reg(u16 reg, u16 *ind) 14682c4066e5SSrinivas Kandagatla { 14692c4066e5SSrinivas Kandagatla u16 prim_int_reg = 0; 14702c4066e5SSrinivas Kandagatla 14712c4066e5SSrinivas Kandagatla switch (reg) { 14722c4066e5SSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_CTL: 14732c4066e5SSrinivas Kandagatla case CDC_WSA_RX0_RX_PATH_MIX_CTL: 14742c4066e5SSrinivas Kandagatla prim_int_reg = CDC_WSA_RX0_RX_PATH_CTL; 14752c4066e5SSrinivas Kandagatla *ind = 0; 14762c4066e5SSrinivas Kandagatla break; 14772c4066e5SSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_CTL: 14782c4066e5SSrinivas Kandagatla case CDC_WSA_RX1_RX_PATH_MIX_CTL: 14792c4066e5SSrinivas Kandagatla prim_int_reg = CDC_WSA_RX1_RX_PATH_CTL; 14802c4066e5SSrinivas Kandagatla *ind = 1; 14812c4066e5SSrinivas Kandagatla break; 14822c4066e5SSrinivas Kandagatla } 14832c4066e5SSrinivas Kandagatla 14842c4066e5SSrinivas Kandagatla return prim_int_reg; 14852c4066e5SSrinivas Kandagatla } 14862c4066e5SSrinivas Kandagatla 14872c4066e5SSrinivas Kandagatla static int wsa_macro_enable_prim_interpolator(struct snd_soc_component *component, 14882c4066e5SSrinivas Kandagatla u16 reg, int event) 14892c4066e5SSrinivas Kandagatla { 14902c4066e5SSrinivas Kandagatla u16 prim_int_reg; 14912c4066e5SSrinivas Kandagatla u16 ind = 0; 14922c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 14932c4066e5SSrinivas Kandagatla 14942c4066e5SSrinivas Kandagatla prim_int_reg = wsa_macro_interp_get_primary_reg(reg, &ind); 14952c4066e5SSrinivas Kandagatla 14962c4066e5SSrinivas Kandagatla switch (event) { 14972c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_PRE_PMU: 14982c4066e5SSrinivas Kandagatla wsa->prim_int_users[ind]++; 14992c4066e5SSrinivas Kandagatla if (wsa->prim_int_users[ind] == 1) { 15002c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 15012c4066e5SSrinivas Kandagatla prim_int_reg + WSA_MACRO_RX_PATH_CFG3_OFFSET, 15022c4066e5SSrinivas Kandagatla CDC_WSA_RX_DC_DCOEFF_MASK, 15032c4066e5SSrinivas Kandagatla 0x3); 15042c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, prim_int_reg, 15052c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_PGA_MUTE_EN_MASK, 15062c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_PGA_MUTE_ENABLE); 15072c4066e5SSrinivas Kandagatla wsa_macro_hd2_control(component, prim_int_reg, event); 15082c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 15092c4066e5SSrinivas Kandagatla prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET, 15102c4066e5SSrinivas Kandagatla CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 15112c4066e5SSrinivas Kandagatla CDC_WSA_RX_DSMDEM_CLK_ENABLE); 15122c4066e5SSrinivas Kandagatla } 15132c4066e5SSrinivas Kandagatla if ((reg != prim_int_reg) && 15142c4066e5SSrinivas Kandagatla ((snd_soc_component_read( 15152c4066e5SSrinivas Kandagatla component, prim_int_reg)) & 0x10)) 15162c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, reg, 15172c4066e5SSrinivas Kandagatla 0x10, 0x10); 15182c4066e5SSrinivas Kandagatla break; 15192c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMD: 15202c4066e5SSrinivas Kandagatla wsa->prim_int_users[ind]--; 15212c4066e5SSrinivas Kandagatla if (wsa->prim_int_users[ind] == 0) { 15222c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 15232c4066e5SSrinivas Kandagatla prim_int_reg + WSA_MACRO_RX_PATH_DSMDEM_OFFSET, 15242c4066e5SSrinivas Kandagatla CDC_WSA_RX_DSMDEM_CLK_EN_MASK, 0); 15252c4066e5SSrinivas Kandagatla wsa_macro_hd2_control(component, prim_int_reg, event); 15262c4066e5SSrinivas Kandagatla } 15272c4066e5SSrinivas Kandagatla break; 15282c4066e5SSrinivas Kandagatla } 15292c4066e5SSrinivas Kandagatla 15302c4066e5SSrinivas Kandagatla return 0; 15312c4066e5SSrinivas Kandagatla } 15322c4066e5SSrinivas Kandagatla 15332c4066e5SSrinivas Kandagatla static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component, 15342c4066e5SSrinivas Kandagatla struct wsa_macro *wsa, 15352c4066e5SSrinivas Kandagatla int event, int gain_reg) 15362c4066e5SSrinivas Kandagatla { 15372c4066e5SSrinivas Kandagatla int comp_gain_offset, val; 15382c4066e5SSrinivas Kandagatla 15392c4066e5SSrinivas Kandagatla switch (wsa->spkr_mode) { 15402c4066e5SSrinivas Kandagatla /* Compander gain in WSA_MACRO_SPKR_MODE1 case is 12 dB */ 15412c4066e5SSrinivas Kandagatla case WSA_MACRO_SPKR_MODE_1: 15422c4066e5SSrinivas Kandagatla comp_gain_offset = -12; 15432c4066e5SSrinivas Kandagatla break; 15442c4066e5SSrinivas Kandagatla /* Default case compander gain is 15 dB */ 15452c4066e5SSrinivas Kandagatla default: 15462c4066e5SSrinivas Kandagatla comp_gain_offset = -15; 15472c4066e5SSrinivas Kandagatla break; 15482c4066e5SSrinivas Kandagatla } 15492c4066e5SSrinivas Kandagatla 15502c4066e5SSrinivas Kandagatla switch (event) { 15512c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMU: 15522c4066e5SSrinivas Kandagatla /* Apply ear spkr gain only if compander is enabled */ 15532c4066e5SSrinivas Kandagatla if (wsa->comp_enabled[WSA_MACRO_COMP1] && 15542c4066e5SSrinivas Kandagatla (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) && 15552c4066e5SSrinivas Kandagatla (wsa->ear_spkr_gain != 0)) { 15562c4066e5SSrinivas Kandagatla /* For example, val is -8(-12+5-1) for 4dB of gain */ 15572c4066e5SSrinivas Kandagatla val = comp_gain_offset + wsa->ear_spkr_gain - 1; 15582c4066e5SSrinivas Kandagatla snd_soc_component_write(component, gain_reg, val); 15592c4066e5SSrinivas Kandagatla } 15602c4066e5SSrinivas Kandagatla break; 15612c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMD: 15622c4066e5SSrinivas Kandagatla /* 15632c4066e5SSrinivas Kandagatla * Reset RX0 volume to 0 dB if compander is enabled and 15642c4066e5SSrinivas Kandagatla * ear_spkr_gain is non-zero. 15652c4066e5SSrinivas Kandagatla */ 15662c4066e5SSrinivas Kandagatla if (wsa->comp_enabled[WSA_MACRO_COMP1] && 15672c4066e5SSrinivas Kandagatla (gain_reg == CDC_WSA_RX0_RX_VOL_CTL) && 15682c4066e5SSrinivas Kandagatla (wsa->ear_spkr_gain != 0)) { 15692c4066e5SSrinivas Kandagatla snd_soc_component_write(component, gain_reg, 0x0); 15702c4066e5SSrinivas Kandagatla } 15712c4066e5SSrinivas Kandagatla break; 15722c4066e5SSrinivas Kandagatla } 15732c4066e5SSrinivas Kandagatla 15742c4066e5SSrinivas Kandagatla return 0; 15752c4066e5SSrinivas Kandagatla } 15762c4066e5SSrinivas Kandagatla 15772c4066e5SSrinivas Kandagatla static int wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w, 15782c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, 15792c4066e5SSrinivas Kandagatla int event) 15802c4066e5SSrinivas Kandagatla { 15812c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 15822c4066e5SSrinivas Kandagatla u16 gain_reg; 15832c4066e5SSrinivas Kandagatla u16 reg; 15842c4066e5SSrinivas Kandagatla int val; 15852c4066e5SSrinivas Kandagatla int offset_val = 0; 15862c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 15872c4066e5SSrinivas Kandagatla 15882c4066e5SSrinivas Kandagatla if (w->shift == WSA_MACRO_COMP1) { 15892c4066e5SSrinivas Kandagatla reg = CDC_WSA_RX0_RX_PATH_CTL; 15902c4066e5SSrinivas Kandagatla gain_reg = CDC_WSA_RX0_RX_VOL_CTL; 15912c4066e5SSrinivas Kandagatla } else if (w->shift == WSA_MACRO_COMP2) { 15922c4066e5SSrinivas Kandagatla reg = CDC_WSA_RX1_RX_PATH_CTL; 15932c4066e5SSrinivas Kandagatla gain_reg = CDC_WSA_RX1_RX_VOL_CTL; 15942c4066e5SSrinivas Kandagatla } 15952c4066e5SSrinivas Kandagatla 15962c4066e5SSrinivas Kandagatla switch (event) { 15972c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_PRE_PMU: 15982c4066e5SSrinivas Kandagatla /* Reset if needed */ 15992c4066e5SSrinivas Kandagatla wsa_macro_enable_prim_interpolator(component, reg, event); 16002c4066e5SSrinivas Kandagatla break; 16012c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMU: 16022c4066e5SSrinivas Kandagatla wsa_macro_config_compander(component, w->shift, event); 16032c4066e5SSrinivas Kandagatla wsa_macro_config_softclip(component, w->shift, event); 16042c4066e5SSrinivas Kandagatla /* apply gain after int clk is enabled */ 16052c4066e5SSrinivas Kandagatla if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) && 16062c4066e5SSrinivas Kandagatla (wsa->comp_enabled[WSA_MACRO_COMP1] || 16072c4066e5SSrinivas Kandagatla wsa->comp_enabled[WSA_MACRO_COMP2])) { 16082c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16092c4066e5SSrinivas Kandagatla CDC_WSA_RX0_RX_PATH_SEC1, 16102c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16112c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_ENABLE); 16122c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16132c4066e5SSrinivas Kandagatla CDC_WSA_RX0_RX_PATH_MIX_SEC0, 16142c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16152c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_ENABLE); 16162c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16172c4066e5SSrinivas Kandagatla CDC_WSA_RX1_RX_PATH_SEC1, 16182c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16192c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_ENABLE); 16202c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16212c4066e5SSrinivas Kandagatla CDC_WSA_RX1_RX_PATH_MIX_SEC0, 16222c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16232c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_ENABLE); 16242c4066e5SSrinivas Kandagatla offset_val = -2; 16252c4066e5SSrinivas Kandagatla } 16262c4066e5SSrinivas Kandagatla val = snd_soc_component_read(component, gain_reg); 16272c4066e5SSrinivas Kandagatla val += offset_val; 16282c4066e5SSrinivas Kandagatla snd_soc_component_write(component, gain_reg, val); 16292c4066e5SSrinivas Kandagatla wsa_macro_config_ear_spkr_gain(component, wsa, 16302c4066e5SSrinivas Kandagatla event, gain_reg); 16312c4066e5SSrinivas Kandagatla break; 16322c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMD: 16332c4066e5SSrinivas Kandagatla wsa_macro_config_compander(component, w->shift, event); 16342c4066e5SSrinivas Kandagatla wsa_macro_config_softclip(component, w->shift, event); 16352c4066e5SSrinivas Kandagatla wsa_macro_enable_prim_interpolator(component, reg, event); 16362c4066e5SSrinivas Kandagatla if ((wsa->spkr_gain_offset == WSA_MACRO_GAIN_OFFSET_M1P5_DB) && 16372c4066e5SSrinivas Kandagatla (wsa->comp_enabled[WSA_MACRO_COMP1] || 16382c4066e5SSrinivas Kandagatla wsa->comp_enabled[WSA_MACRO_COMP2])) { 16392c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16402c4066e5SSrinivas Kandagatla CDC_WSA_RX0_RX_PATH_SEC1, 16412c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16422c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_DISABLE); 16432c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16442c4066e5SSrinivas Kandagatla CDC_WSA_RX0_RX_PATH_MIX_SEC0, 16452c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16462c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_DISABLE); 16472c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16482c4066e5SSrinivas Kandagatla CDC_WSA_RX1_RX_PATH_SEC1, 16492c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16502c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_DISABLE); 16512c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, 16522c4066e5SSrinivas Kandagatla CDC_WSA_RX1_RX_PATH_MIX_SEC0, 16532c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_MASK, 16542c4066e5SSrinivas Kandagatla CDC_WSA_RX_PGA_HALF_DB_DISABLE); 16552c4066e5SSrinivas Kandagatla offset_val = 2; 16562c4066e5SSrinivas Kandagatla val = snd_soc_component_read(component, gain_reg); 16572c4066e5SSrinivas Kandagatla val += offset_val; 16582c4066e5SSrinivas Kandagatla snd_soc_component_write(component, gain_reg, val); 16592c4066e5SSrinivas Kandagatla } 16602c4066e5SSrinivas Kandagatla wsa_macro_config_ear_spkr_gain(component, wsa, 16612c4066e5SSrinivas Kandagatla event, gain_reg); 16622c4066e5SSrinivas Kandagatla break; 16632c4066e5SSrinivas Kandagatla } 16642c4066e5SSrinivas Kandagatla 16652c4066e5SSrinivas Kandagatla return 0; 16662c4066e5SSrinivas Kandagatla } 16672c4066e5SSrinivas Kandagatla 16682c4066e5SSrinivas Kandagatla static int wsa_macro_spk_boost_event(struct snd_soc_dapm_widget *w, 16692c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, 16702c4066e5SSrinivas Kandagatla int event) 16712c4066e5SSrinivas Kandagatla { 16722c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 16732c4066e5SSrinivas Kandagatla u16 boost_path_ctl, boost_path_cfg1; 16742c4066e5SSrinivas Kandagatla u16 reg, reg_mix; 16752c4066e5SSrinivas Kandagatla 16762c4066e5SSrinivas Kandagatla if (!strcmp(w->name, "WSA_RX INT0 CHAIN")) { 16772c4066e5SSrinivas Kandagatla boost_path_ctl = CDC_WSA_BOOST0_BOOST_PATH_CTL; 16782c4066e5SSrinivas Kandagatla boost_path_cfg1 = CDC_WSA_RX0_RX_PATH_CFG1; 16792c4066e5SSrinivas Kandagatla reg = CDC_WSA_RX0_RX_PATH_CTL; 16802c4066e5SSrinivas Kandagatla reg_mix = CDC_WSA_RX0_RX_PATH_MIX_CTL; 16812c4066e5SSrinivas Kandagatla } else if (!strcmp(w->name, "WSA_RX INT1 CHAIN")) { 16822c4066e5SSrinivas Kandagatla boost_path_ctl = CDC_WSA_BOOST1_BOOST_PATH_CTL; 16832c4066e5SSrinivas Kandagatla boost_path_cfg1 = CDC_WSA_RX1_RX_PATH_CFG1; 16842c4066e5SSrinivas Kandagatla reg = CDC_WSA_RX1_RX_PATH_CTL; 16852c4066e5SSrinivas Kandagatla reg_mix = CDC_WSA_RX1_RX_PATH_MIX_CTL; 16862c4066e5SSrinivas Kandagatla } 16872c4066e5SSrinivas Kandagatla 16882c4066e5SSrinivas Kandagatla switch (event) { 16892c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_PRE_PMU: 16902c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, boost_path_cfg1, 16912c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_SMART_BST_EN_MASK, 16922c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_SMART_BST_ENABLE); 16932c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, boost_path_ctl, 16942c4066e5SSrinivas Kandagatla CDC_WSA_BOOST_PATH_CLK_EN_MASK, 16952c4066e5SSrinivas Kandagatla CDC_WSA_BOOST_PATH_CLK_ENABLE); 16962c4066e5SSrinivas Kandagatla if ((snd_soc_component_read(component, reg_mix)) & 0x10) 16972c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, reg_mix, 16982c4066e5SSrinivas Kandagatla 0x10, 0x00); 16992c4066e5SSrinivas Kandagatla break; 17002c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMU: 17012c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, reg, 0x10, 0x00); 17022c4066e5SSrinivas Kandagatla break; 17032c4066e5SSrinivas Kandagatla case SND_SOC_DAPM_POST_PMD: 17042c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, boost_path_ctl, 17052c4066e5SSrinivas Kandagatla CDC_WSA_BOOST_PATH_CLK_EN_MASK, 17062c4066e5SSrinivas Kandagatla CDC_WSA_BOOST_PATH_CLK_DISABLE); 17072c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, boost_path_cfg1, 17082c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_SMART_BST_EN_MASK, 17092c4066e5SSrinivas Kandagatla CDC_WSA_RX_PATH_SMART_BST_DISABLE); 17102c4066e5SSrinivas Kandagatla break; 17112c4066e5SSrinivas Kandagatla } 17122c4066e5SSrinivas Kandagatla 17132c4066e5SSrinivas Kandagatla return 0; 17142c4066e5SSrinivas Kandagatla } 17152c4066e5SSrinivas Kandagatla 17162c4066e5SSrinivas Kandagatla static int wsa_macro_enable_echo(struct snd_soc_dapm_widget *w, 17172c4066e5SSrinivas Kandagatla struct snd_kcontrol *kcontrol, 17182c4066e5SSrinivas Kandagatla int event) 17192c4066e5SSrinivas Kandagatla { 17202c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); 17212c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 17222c4066e5SSrinivas Kandagatla u16 val, ec_tx, ec_hq_reg; 17232c4066e5SSrinivas Kandagatla 17242c4066e5SSrinivas Kandagatla val = snd_soc_component_read(component, CDC_WSA_RX_INP_MUX_RX_MIX_CFG0); 17252c4066e5SSrinivas Kandagatla 17262c4066e5SSrinivas Kandagatla switch (w->shift) { 17272c4066e5SSrinivas Kandagatla case WSA_MACRO_EC0_MUX: 17282c4066e5SSrinivas Kandagatla val = val & CDC_WSA_RX_MIX_TX0_SEL_MASK; 17292c4066e5SSrinivas Kandagatla ec_tx = val - 1; 17302c4066e5SSrinivas Kandagatla break; 17312c4066e5SSrinivas Kandagatla case WSA_MACRO_EC1_MUX: 17322c4066e5SSrinivas Kandagatla val = val & CDC_WSA_RX_MIX_TX1_SEL_MASK; 17332c4066e5SSrinivas Kandagatla ec_tx = (val >> CDC_WSA_RX_MIX_TX1_SEL_SHFT) - 1; 17342c4066e5SSrinivas Kandagatla break; 173558f01c7fSTom Rix default: 173658f01c7fSTom Rix dev_err(component->dev, "%s: Invalid shift %u\n", 173758f01c7fSTom Rix __func__, w->shift); 173858f01c7fSTom Rix return -EINVAL; 17392c4066e5SSrinivas Kandagatla } 17402c4066e5SSrinivas Kandagatla 17412c4066e5SSrinivas Kandagatla if (wsa->ec_hq[ec_tx]) { 17422c4066e5SSrinivas Kandagatla ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_PATH_CTL + 0x40 * ec_tx; 17432c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, ec_hq_reg, 17442c4066e5SSrinivas Kandagatla CDC_WSA_EC_HQ_EC_CLK_EN_MASK, 17452c4066e5SSrinivas Kandagatla CDC_WSA_EC_HQ_EC_CLK_ENABLE); 17462c4066e5SSrinivas Kandagatla ec_hq_reg = CDC_WSA_EC_HQ0_EC_REF_HQ_CFG0 + 0x40 * ec_tx; 17472c4066e5SSrinivas Kandagatla /* default set to 48k */ 17482c4066e5SSrinivas Kandagatla snd_soc_component_update_bits(component, ec_hq_reg, 17492c4066e5SSrinivas Kandagatla CDC_WSA_EC_HQ_EC_REF_PCM_RATE_MASK, 17502c4066e5SSrinivas Kandagatla CDC_WSA_EC_HQ_EC_REF_PCM_RATE_48K); 17512c4066e5SSrinivas Kandagatla } 17522c4066e5SSrinivas Kandagatla 17532c4066e5SSrinivas Kandagatla return 0; 17542c4066e5SSrinivas Kandagatla } 17552c4066e5SSrinivas Kandagatla 1756809bcbceSSrinivas Kandagatla static int wsa_macro_get_ec_hq(struct snd_kcontrol *kcontrol, 1757809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1758809bcbceSSrinivas Kandagatla { 1759809bcbceSSrinivas Kandagatla 1760809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1761809bcbceSSrinivas Kandagatla int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1762809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1763809bcbceSSrinivas Kandagatla 1764809bcbceSSrinivas Kandagatla ucontrol->value.integer.value[0] = wsa->ec_hq[ec_tx]; 1765809bcbceSSrinivas Kandagatla 1766809bcbceSSrinivas Kandagatla return 0; 1767809bcbceSSrinivas Kandagatla } 1768809bcbceSSrinivas Kandagatla 1769809bcbceSSrinivas Kandagatla static int wsa_macro_set_ec_hq(struct snd_kcontrol *kcontrol, 1770809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1771809bcbceSSrinivas Kandagatla { 1772809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1773809bcbceSSrinivas Kandagatla int ec_tx = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1774809bcbceSSrinivas Kandagatla int value = ucontrol->value.integer.value[0]; 1775809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1776809bcbceSSrinivas Kandagatla 1777809bcbceSSrinivas Kandagatla wsa->ec_hq[ec_tx] = value; 1778809bcbceSSrinivas Kandagatla 1779809bcbceSSrinivas Kandagatla return 0; 1780809bcbceSSrinivas Kandagatla } 1781809bcbceSSrinivas Kandagatla 1782809bcbceSSrinivas Kandagatla static int wsa_macro_get_compander(struct snd_kcontrol *kcontrol, 1783809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1784809bcbceSSrinivas Kandagatla { 1785809bcbceSSrinivas Kandagatla 1786809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1787809bcbceSSrinivas Kandagatla int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1788809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1789809bcbceSSrinivas Kandagatla 1790809bcbceSSrinivas Kandagatla ucontrol->value.integer.value[0] = wsa->comp_enabled[comp]; 1791809bcbceSSrinivas Kandagatla return 0; 1792809bcbceSSrinivas Kandagatla } 1793809bcbceSSrinivas Kandagatla 1794809bcbceSSrinivas Kandagatla static int wsa_macro_set_compander(struct snd_kcontrol *kcontrol, 1795809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1796809bcbceSSrinivas Kandagatla { 1797809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1798809bcbceSSrinivas Kandagatla int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1799809bcbceSSrinivas Kandagatla int value = ucontrol->value.integer.value[0]; 1800809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1801809bcbceSSrinivas Kandagatla 1802809bcbceSSrinivas Kandagatla wsa->comp_enabled[comp] = value; 1803809bcbceSSrinivas Kandagatla 1804809bcbceSSrinivas Kandagatla return 0; 1805809bcbceSSrinivas Kandagatla } 1806809bcbceSSrinivas Kandagatla 1807809bcbceSSrinivas Kandagatla static int wsa_macro_ear_spkr_pa_gain_get(struct snd_kcontrol *kcontrol, 1808809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1809809bcbceSSrinivas Kandagatla { 1810809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1811809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1812809bcbceSSrinivas Kandagatla 1813809bcbceSSrinivas Kandagatla ucontrol->value.integer.value[0] = wsa->ear_spkr_gain; 1814809bcbceSSrinivas Kandagatla 1815809bcbceSSrinivas Kandagatla return 0; 1816809bcbceSSrinivas Kandagatla } 1817809bcbceSSrinivas Kandagatla 1818809bcbceSSrinivas Kandagatla static int wsa_macro_ear_spkr_pa_gain_put(struct snd_kcontrol *kcontrol, 1819809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1820809bcbceSSrinivas Kandagatla { 1821809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1822809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1823809bcbceSSrinivas Kandagatla 1824809bcbceSSrinivas Kandagatla wsa->ear_spkr_gain = ucontrol->value.integer.value[0]; 1825809bcbceSSrinivas Kandagatla 1826809bcbceSSrinivas Kandagatla return 0; 1827809bcbceSSrinivas Kandagatla } 1828809bcbceSSrinivas Kandagatla 18292c4066e5SSrinivas Kandagatla static int wsa_macro_rx_mux_get(struct snd_kcontrol *kcontrol, 18302c4066e5SSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 18312c4066e5SSrinivas Kandagatla { 18322c4066e5SSrinivas Kandagatla struct snd_soc_dapm_widget *widget = 18332c4066e5SSrinivas Kandagatla snd_soc_dapm_kcontrol_widget(kcontrol); 18342c4066e5SSrinivas Kandagatla struct snd_soc_component *component = 18352c4066e5SSrinivas Kandagatla snd_soc_dapm_to_component(widget->dapm); 18362c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 18372c4066e5SSrinivas Kandagatla 18382c4066e5SSrinivas Kandagatla ucontrol->value.integer.value[0] = 18392c4066e5SSrinivas Kandagatla wsa->rx_port_value[widget->shift]; 18402c4066e5SSrinivas Kandagatla return 0; 18412c4066e5SSrinivas Kandagatla } 18422c4066e5SSrinivas Kandagatla 18432c4066e5SSrinivas Kandagatla static int wsa_macro_rx_mux_put(struct snd_kcontrol *kcontrol, 18442c4066e5SSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 18452c4066e5SSrinivas Kandagatla { 18462c4066e5SSrinivas Kandagatla struct snd_soc_dapm_widget *widget = 18472c4066e5SSrinivas Kandagatla snd_soc_dapm_kcontrol_widget(kcontrol); 18482c4066e5SSrinivas Kandagatla struct snd_soc_component *component = 18492c4066e5SSrinivas Kandagatla snd_soc_dapm_to_component(widget->dapm); 18502c4066e5SSrinivas Kandagatla struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 18512c4066e5SSrinivas Kandagatla struct snd_soc_dapm_update *update = NULL; 18522c4066e5SSrinivas Kandagatla u32 rx_port_value = ucontrol->value.integer.value[0]; 18532c4066e5SSrinivas Kandagatla u32 bit_input; 18542c4066e5SSrinivas Kandagatla u32 aif_rst; 18552c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 18562c4066e5SSrinivas Kandagatla 18572c4066e5SSrinivas Kandagatla aif_rst = wsa->rx_port_value[widget->shift]; 18582c4066e5SSrinivas Kandagatla if (!rx_port_value) { 1859777af241SSrinivas Kandagatla if (aif_rst == 0) 18602c4066e5SSrinivas Kandagatla return 0; 18612c4066e5SSrinivas Kandagatla if (aif_rst >= WSA_MACRO_RX_MAX) { 18622c4066e5SSrinivas Kandagatla dev_err(component->dev, "%s: Invalid AIF reset\n", __func__); 18632c4066e5SSrinivas Kandagatla return 0; 18642c4066e5SSrinivas Kandagatla } 18652c4066e5SSrinivas Kandagatla } 18662c4066e5SSrinivas Kandagatla wsa->rx_port_value[widget->shift] = rx_port_value; 18672c4066e5SSrinivas Kandagatla 18682c4066e5SSrinivas Kandagatla bit_input = widget->shift; 18692c4066e5SSrinivas Kandagatla 18702c4066e5SSrinivas Kandagatla switch (rx_port_value) { 18712c4066e5SSrinivas Kandagatla case 0: 18722c4066e5SSrinivas Kandagatla if (wsa->active_ch_cnt[aif_rst]) { 18732c4066e5SSrinivas Kandagatla clear_bit(bit_input, 18742c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[aif_rst]); 18752c4066e5SSrinivas Kandagatla wsa->active_ch_cnt[aif_rst]--; 18762c4066e5SSrinivas Kandagatla } 18772c4066e5SSrinivas Kandagatla break; 18782c4066e5SSrinivas Kandagatla case 1: 18792c4066e5SSrinivas Kandagatla case 2: 18802c4066e5SSrinivas Kandagatla set_bit(bit_input, 18812c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[rx_port_value]); 18822c4066e5SSrinivas Kandagatla wsa->active_ch_cnt[rx_port_value]++; 18832c4066e5SSrinivas Kandagatla break; 18842c4066e5SSrinivas Kandagatla default: 18852c4066e5SSrinivas Kandagatla dev_err(component->dev, 18862c4066e5SSrinivas Kandagatla "%s: Invalid AIF_ID for WSA RX MUX %d\n", 18872c4066e5SSrinivas Kandagatla __func__, rx_port_value); 18882c4066e5SSrinivas Kandagatla return -EINVAL; 18892c4066e5SSrinivas Kandagatla } 18902c4066e5SSrinivas Kandagatla 18912c4066e5SSrinivas Kandagatla snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, 18922c4066e5SSrinivas Kandagatla rx_port_value, e, update); 18932c4066e5SSrinivas Kandagatla return 0; 18942c4066e5SSrinivas Kandagatla } 18952c4066e5SSrinivas Kandagatla 1896809bcbceSSrinivas Kandagatla static int wsa_macro_soft_clip_enable_get(struct snd_kcontrol *kcontrol, 1897809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1898809bcbceSSrinivas Kandagatla { 1899809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1900809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1901809bcbceSSrinivas Kandagatla int path = ((struct soc_mixer_control *)kcontrol->private_value)->shift; 1902809bcbceSSrinivas Kandagatla 1903809bcbceSSrinivas Kandagatla ucontrol->value.integer.value[0] = wsa->is_softclip_on[path]; 1904809bcbceSSrinivas Kandagatla 1905809bcbceSSrinivas Kandagatla return 0; 1906809bcbceSSrinivas Kandagatla } 1907809bcbceSSrinivas Kandagatla 1908809bcbceSSrinivas Kandagatla static int wsa_macro_soft_clip_enable_put(struct snd_kcontrol *kcontrol, 1909809bcbceSSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 1910809bcbceSSrinivas Kandagatla { 1911809bcbceSSrinivas Kandagatla struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); 1912809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 1913809bcbceSSrinivas Kandagatla int path = ((struct soc_mixer_control *) kcontrol->private_value)->shift; 1914809bcbceSSrinivas Kandagatla 1915809bcbceSSrinivas Kandagatla wsa->is_softclip_on[path] = ucontrol->value.integer.value[0]; 1916809bcbceSSrinivas Kandagatla 1917809bcbceSSrinivas Kandagatla return 0; 1918809bcbceSSrinivas Kandagatla } 1919809bcbceSSrinivas Kandagatla 1920809bcbceSSrinivas Kandagatla static const struct snd_kcontrol_new wsa_macro_snd_controls[] = { 1921809bcbceSSrinivas Kandagatla SOC_ENUM_EXT("EAR SPKR PA Gain", wsa_macro_ear_spkr_pa_gain_enum, 1922809bcbceSSrinivas Kandagatla wsa_macro_ear_spkr_pa_gain_get, 1923809bcbceSSrinivas Kandagatla wsa_macro_ear_spkr_pa_gain_put), 1924809bcbceSSrinivas Kandagatla SOC_SINGLE_EXT("WSA_Softclip0 Enable", SND_SOC_NOPM, 1925809bcbceSSrinivas Kandagatla WSA_MACRO_SOFTCLIP0, 1, 0, 1926809bcbceSSrinivas Kandagatla wsa_macro_soft_clip_enable_get, 1927809bcbceSSrinivas Kandagatla wsa_macro_soft_clip_enable_put), 1928809bcbceSSrinivas Kandagatla SOC_SINGLE_EXT("WSA_Softclip1 Enable", SND_SOC_NOPM, 1929809bcbceSSrinivas Kandagatla WSA_MACRO_SOFTCLIP1, 1, 0, 1930809bcbceSSrinivas Kandagatla wsa_macro_soft_clip_enable_get, 1931809bcbceSSrinivas Kandagatla wsa_macro_soft_clip_enable_put), 1932809bcbceSSrinivas Kandagatla 1933809bcbceSSrinivas Kandagatla SOC_SINGLE_S8_TLV("WSA_RX0 Digital Volume", CDC_WSA_RX0_RX_VOL_CTL, 1934809bcbceSSrinivas Kandagatla -84, 40, digital_gain), 1935809bcbceSSrinivas Kandagatla SOC_SINGLE_S8_TLV("WSA_RX1 Digital Volume", CDC_WSA_RX1_RX_VOL_CTL, 1936809bcbceSSrinivas Kandagatla -84, 40, digital_gain), 1937809bcbceSSrinivas Kandagatla 1938809bcbceSSrinivas Kandagatla SOC_SINGLE("WSA_RX0 Digital Mute", CDC_WSA_RX0_RX_PATH_CTL, 4, 1, 0), 1939809bcbceSSrinivas Kandagatla SOC_SINGLE("WSA_RX1 Digital Mute", CDC_WSA_RX1_RX_PATH_CTL, 4, 1, 0), 1940809bcbceSSrinivas Kandagatla SOC_SINGLE("WSA_RX0_MIX Digital Mute", CDC_WSA_RX0_RX_PATH_MIX_CTL, 4, 1941809bcbceSSrinivas Kandagatla 1, 0), 1942809bcbceSSrinivas Kandagatla SOC_SINGLE("WSA_RX1_MIX Digital Mute", CDC_WSA_RX1_RX_PATH_MIX_CTL, 4, 1943809bcbceSSrinivas Kandagatla 1, 0), 1944809bcbceSSrinivas Kandagatla SOC_SINGLE_EXT("WSA_COMP1 Switch", SND_SOC_NOPM, WSA_MACRO_COMP1, 1, 0, 1945809bcbceSSrinivas Kandagatla wsa_macro_get_compander, wsa_macro_set_compander), 1946809bcbceSSrinivas Kandagatla SOC_SINGLE_EXT("WSA_COMP2 Switch", SND_SOC_NOPM, WSA_MACRO_COMP2, 1, 0, 1947809bcbceSSrinivas Kandagatla wsa_macro_get_compander, wsa_macro_set_compander), 1948809bcbceSSrinivas Kandagatla SOC_SINGLE_EXT("WSA_RX0 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX0, 1, 0, 1949809bcbceSSrinivas Kandagatla wsa_macro_get_ec_hq, wsa_macro_set_ec_hq), 1950809bcbceSSrinivas Kandagatla SOC_SINGLE_EXT("WSA_RX1 EC_HQ Switch", SND_SOC_NOPM, WSA_MACRO_RX1, 1, 0, 1951809bcbceSSrinivas Kandagatla wsa_macro_get_ec_hq, wsa_macro_set_ec_hq), 1952809bcbceSSrinivas Kandagatla }; 1953809bcbceSSrinivas Kandagatla 19542c4066e5SSrinivas Kandagatla static const struct soc_enum rx_mux_enum = 19552c4066e5SSrinivas Kandagatla SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_mux_text), rx_mux_text); 19562c4066e5SSrinivas Kandagatla 19572c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new rx_mux[WSA_MACRO_RX_MAX] = { 19582c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM_EXT("WSA RX0 Mux", rx_mux_enum, 19592c4066e5SSrinivas Kandagatla wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 19602c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM_EXT("WSA RX1 Mux", rx_mux_enum, 19612c4066e5SSrinivas Kandagatla wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 19622c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM_EXT("WSA RX_MIX0 Mux", rx_mux_enum, 19632c4066e5SSrinivas Kandagatla wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 19642c4066e5SSrinivas Kandagatla SOC_DAPM_ENUM_EXT("WSA RX_MIX1 Mux", rx_mux_enum, 19652c4066e5SSrinivas Kandagatla wsa_macro_rx_mux_get, wsa_macro_rx_mux_put), 19662c4066e5SSrinivas Kandagatla }; 19672c4066e5SSrinivas Kandagatla 19682c4066e5SSrinivas Kandagatla static int wsa_macro_vi_feed_mixer_get(struct snd_kcontrol *kcontrol, 19692c4066e5SSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 19702c4066e5SSrinivas Kandagatla { 19712c4066e5SSrinivas Kandagatla struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 19722c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 19732c4066e5SSrinivas Kandagatla struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 19742c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 19752c4066e5SSrinivas Kandagatla u32 spk_tx_id = mixer->shift; 19762c4066e5SSrinivas Kandagatla u32 dai_id = widget->shift; 19772c4066e5SSrinivas Kandagatla 19782c4066e5SSrinivas Kandagatla if (test_bit(spk_tx_id, &wsa->active_ch_mask[dai_id])) 19792c4066e5SSrinivas Kandagatla ucontrol->value.integer.value[0] = 1; 19802c4066e5SSrinivas Kandagatla else 19812c4066e5SSrinivas Kandagatla ucontrol->value.integer.value[0] = 0; 19822c4066e5SSrinivas Kandagatla 19832c4066e5SSrinivas Kandagatla return 0; 19842c4066e5SSrinivas Kandagatla } 19852c4066e5SSrinivas Kandagatla 19862c4066e5SSrinivas Kandagatla static int wsa_macro_vi_feed_mixer_put(struct snd_kcontrol *kcontrol, 19872c4066e5SSrinivas Kandagatla struct snd_ctl_elem_value *ucontrol) 19882c4066e5SSrinivas Kandagatla { 19892c4066e5SSrinivas Kandagatla struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol); 19902c4066e5SSrinivas Kandagatla struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); 19912c4066e5SSrinivas Kandagatla struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value; 19922c4066e5SSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(component); 19932c4066e5SSrinivas Kandagatla u32 enable = ucontrol->value.integer.value[0]; 19942c4066e5SSrinivas Kandagatla u32 spk_tx_id = mixer->shift; 19952c4066e5SSrinivas Kandagatla 19962c4066e5SSrinivas Kandagatla if (enable) { 19972c4066e5SSrinivas Kandagatla if (spk_tx_id == WSA_MACRO_TX0 && 19982c4066e5SSrinivas Kandagatla !test_bit(WSA_MACRO_TX0, 19992c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 20002c4066e5SSrinivas Kandagatla set_bit(WSA_MACRO_TX0, 20012c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 20022c4066e5SSrinivas Kandagatla wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++; 20032c4066e5SSrinivas Kandagatla } 20042c4066e5SSrinivas Kandagatla if (spk_tx_id == WSA_MACRO_TX1 && 20052c4066e5SSrinivas Kandagatla !test_bit(WSA_MACRO_TX1, 20062c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 20072c4066e5SSrinivas Kandagatla set_bit(WSA_MACRO_TX1, 20082c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 20092c4066e5SSrinivas Kandagatla wsa->active_ch_cnt[WSA_MACRO_AIF_VI]++; 20102c4066e5SSrinivas Kandagatla } 20112c4066e5SSrinivas Kandagatla } else { 20122c4066e5SSrinivas Kandagatla if (spk_tx_id == WSA_MACRO_TX0 && 20132c4066e5SSrinivas Kandagatla test_bit(WSA_MACRO_TX0, 20142c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 20152c4066e5SSrinivas Kandagatla clear_bit(WSA_MACRO_TX0, 20162c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 20172c4066e5SSrinivas Kandagatla wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--; 20182c4066e5SSrinivas Kandagatla } 20192c4066e5SSrinivas Kandagatla if (spk_tx_id == WSA_MACRO_TX1 && 20202c4066e5SSrinivas Kandagatla test_bit(WSA_MACRO_TX1, 20212c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) { 20222c4066e5SSrinivas Kandagatla clear_bit(WSA_MACRO_TX1, 20232c4066e5SSrinivas Kandagatla &wsa->active_ch_mask[WSA_MACRO_AIF_VI]); 20242c4066e5SSrinivas Kandagatla wsa->active_ch_cnt[WSA_MACRO_AIF_VI]--; 20252c4066e5SSrinivas Kandagatla } 20262c4066e5SSrinivas Kandagatla } 20272c4066e5SSrinivas Kandagatla snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, NULL); 20282c4066e5SSrinivas Kandagatla 20292c4066e5SSrinivas Kandagatla return 0; 20302c4066e5SSrinivas Kandagatla } 20312c4066e5SSrinivas Kandagatla 20322c4066e5SSrinivas Kandagatla static const struct snd_kcontrol_new aif_vi_mixer[] = { 20332c4066e5SSrinivas Kandagatla SOC_SINGLE_EXT("WSA_SPKR_VI_1", SND_SOC_NOPM, WSA_MACRO_TX0, 1, 0, 20342c4066e5SSrinivas Kandagatla wsa_macro_vi_feed_mixer_get, 20352c4066e5SSrinivas Kandagatla wsa_macro_vi_feed_mixer_put), 20362c4066e5SSrinivas Kandagatla SOC_SINGLE_EXT("WSA_SPKR_VI_2", SND_SOC_NOPM, WSA_MACRO_TX1, 1, 0, 20372c4066e5SSrinivas Kandagatla wsa_macro_vi_feed_mixer_get, 20382c4066e5SSrinivas Kandagatla wsa_macro_vi_feed_mixer_put), 20392c4066e5SSrinivas Kandagatla }; 20402c4066e5SSrinivas Kandagatla 20412c4066e5SSrinivas Kandagatla static const struct snd_soc_dapm_widget wsa_macro_dapm_widgets[] = { 20422c4066e5SSrinivas Kandagatla SND_SOC_DAPM_AIF_IN("WSA AIF1 PB", "WSA_AIF1 Playback", 0, 20432c4066e5SSrinivas Kandagatla SND_SOC_NOPM, 0, 0), 20442c4066e5SSrinivas Kandagatla SND_SOC_DAPM_AIF_IN("WSA AIF_MIX1 PB", "WSA_AIF_MIX1 Playback", 0, 20452c4066e5SSrinivas Kandagatla SND_SOC_NOPM, 0, 0), 20462c4066e5SSrinivas Kandagatla 20472c4066e5SSrinivas Kandagatla SND_SOC_DAPM_AIF_OUT_E("WSA AIF_VI", "WSA_AIF_VI Capture", 0, 20482c4066e5SSrinivas Kandagatla SND_SOC_NOPM, WSA_MACRO_AIF_VI, 0, 20492c4066e5SSrinivas Kandagatla wsa_macro_enable_vi_feedback, 20502c4066e5SSrinivas Kandagatla SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), 20512c4066e5SSrinivas Kandagatla SND_SOC_DAPM_AIF_OUT("WSA AIF_ECHO", "WSA_AIF_ECHO Capture", 0, 20522c4066e5SSrinivas Kandagatla SND_SOC_NOPM, 0, 0), 20532c4066e5SSrinivas Kandagatla 20542c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA_AIF_VI Mixer", SND_SOC_NOPM, WSA_MACRO_AIF_VI, 20552c4066e5SSrinivas Kandagatla 0, aif_vi_mixer, ARRAY_SIZE(aif_vi_mixer)), 20562c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX_E("WSA RX_MIX EC0_MUX", SND_SOC_NOPM, 20572c4066e5SSrinivas Kandagatla WSA_MACRO_EC0_MUX, 0, 20582c4066e5SSrinivas Kandagatla &rx_mix_ec0_mux, wsa_macro_enable_echo, 20592c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 20602c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX_E("WSA RX_MIX EC1_MUX", SND_SOC_NOPM, 20612c4066e5SSrinivas Kandagatla WSA_MACRO_EC1_MUX, 0, 20622c4066e5SSrinivas Kandagatla &rx_mix_ec1_mux, wsa_macro_enable_echo, 20632c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 20642c4066e5SSrinivas Kandagatla 20652c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA RX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX0, 0, 20662c4066e5SSrinivas Kandagatla &rx_mux[WSA_MACRO_RX0]), 20672c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA RX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX1, 0, 20682c4066e5SSrinivas Kandagatla &rx_mux[WSA_MACRO_RX1]), 20692c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA RX_MIX0 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 0, 20702c4066e5SSrinivas Kandagatla &rx_mux[WSA_MACRO_RX_MIX0]), 20712c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA RX_MIX1 MUX", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 0, 20722c4066e5SSrinivas Kandagatla &rx_mux[WSA_MACRO_RX_MIX1]), 20732c4066e5SSrinivas Kandagatla 20742c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA RX0", SND_SOC_NOPM, 0, 0, NULL, 0), 20752c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA RX1", SND_SOC_NOPM, 0, 0, NULL, 0), 20762c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA RX_MIX0", SND_SOC_NOPM, 0, 0, NULL, 0), 20772c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA RX_MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), 20782c4066e5SSrinivas Kandagatla 20792c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0, &rx0_prim_inp0_mux), 20802c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0, &rx0_prim_inp1_mux), 20812c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0, &rx0_prim_inp2_mux), 2082e4b8b7c9SJonathan Marek SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX0, 2083e4b8b7c9SJonathan Marek 0, &rx0_mix_mux, wsa_macro_enable_mix_path, 20842c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 20852c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0, &rx1_prim_inp0_mux), 20862c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0, &rx1_prim_inp1_mux), 20872c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0, &rx1_prim_inp2_mux), 2088e4b8b7c9SJonathan Marek SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX1, 2089e4b8b7c9SJonathan Marek 0, &rx1_mix_mux, wsa_macro_enable_mix_path, 20902c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 20912c4066e5SSrinivas Kandagatla 20922c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER_E("WSA_RX INT0 MIX", SND_SOC_NOPM, 0, 0, NULL, 0, 20932c4066e5SSrinivas Kandagatla wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU), 20942c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER_E("WSA_RX INT1 MIX", SND_SOC_NOPM, 1, 0, NULL, 0, 20952c4066e5SSrinivas Kandagatla wsa_macro_enable_main_path, SND_SOC_DAPM_PRE_PMU), 20962c4066e5SSrinivas Kandagatla 20972c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA_RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 20982c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER("WSA_RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0), 20992c4066e5SSrinivas Kandagatla 21002c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MUX("WSA_RX0 INT0 SIDETONE MIX", CDC_WSA_RX0_RX_PATH_CFG1, 21012c4066e5SSrinivas Kandagatla 4, 0, &rx0_sidetone_mix_mux), 21022c4066e5SSrinivas Kandagatla 21032c4066e5SSrinivas Kandagatla SND_SOC_DAPM_INPUT("WSA SRC0_INP"), 21042c4066e5SSrinivas Kandagatla SND_SOC_DAPM_INPUT("WSA_TX DEC0_INP"), 21052c4066e5SSrinivas Kandagatla SND_SOC_DAPM_INPUT("WSA_TX DEC1_INP"), 21062c4066e5SSrinivas Kandagatla 21072c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER_E("WSA_RX INT0 INTERP", SND_SOC_NOPM, 21082c4066e5SSrinivas Kandagatla WSA_MACRO_COMP1, 0, NULL, 0, 21092c4066e5SSrinivas Kandagatla wsa_macro_enable_interpolator, 21102c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 21112c4066e5SSrinivas Kandagatla SND_SOC_DAPM_POST_PMD), 21122c4066e5SSrinivas Kandagatla 21132c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER_E("WSA_RX INT1 INTERP", SND_SOC_NOPM, 21142c4066e5SSrinivas Kandagatla WSA_MACRO_COMP2, 0, NULL, 0, 21152c4066e5SSrinivas Kandagatla wsa_macro_enable_interpolator, 21162c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 21172c4066e5SSrinivas Kandagatla SND_SOC_DAPM_POST_PMD), 21182c4066e5SSrinivas Kandagatla 21192c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER_E("WSA_RX INT0 CHAIN", SND_SOC_NOPM, 0, 0, 21202c4066e5SSrinivas Kandagatla NULL, 0, wsa_macro_spk_boost_event, 21212c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 21222c4066e5SSrinivas Kandagatla SND_SOC_DAPM_POST_PMD), 21232c4066e5SSrinivas Kandagatla 21242c4066e5SSrinivas Kandagatla SND_SOC_DAPM_MIXER_E("WSA_RX INT1 CHAIN", SND_SOC_NOPM, 0, 0, 21252c4066e5SSrinivas Kandagatla NULL, 0, wsa_macro_spk_boost_event, 21262c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 21272c4066e5SSrinivas Kandagatla SND_SOC_DAPM_POST_PMD), 21282c4066e5SSrinivas Kandagatla 21292c4066e5SSrinivas Kandagatla SND_SOC_DAPM_INPUT("VIINPUT_WSA"), 21302c4066e5SSrinivas Kandagatla SND_SOC_DAPM_OUTPUT("WSA_SPK1 OUT"), 21312c4066e5SSrinivas Kandagatla SND_SOC_DAPM_OUTPUT("WSA_SPK2 OUT"), 21322c4066e5SSrinivas Kandagatla 21332c4066e5SSrinivas Kandagatla SND_SOC_DAPM_SUPPLY("WSA_RX0_CLK", CDC_WSA_RX0_RX_PATH_CTL, 5, 0, NULL, 0), 21342c4066e5SSrinivas Kandagatla SND_SOC_DAPM_SUPPLY("WSA_RX1_CLK", CDC_WSA_RX1_RX_PATH_CTL, 5, 0, NULL, 0), 21352c4066e5SSrinivas Kandagatla SND_SOC_DAPM_SUPPLY("WSA_RX_MIX0_CLK", CDC_WSA_RX0_RX_PATH_MIX_CTL, 5, 0, NULL, 0), 21362c4066e5SSrinivas Kandagatla SND_SOC_DAPM_SUPPLY("WSA_RX_MIX1_CLK", CDC_WSA_RX1_RX_PATH_MIX_CTL, 5, 0, NULL, 0), 21372c4066e5SSrinivas Kandagatla SND_SOC_DAPM_SUPPLY_S("WSA_MCLK", 0, SND_SOC_NOPM, 0, 0, 21382c4066e5SSrinivas Kandagatla wsa_macro_mclk_event, 21392c4066e5SSrinivas Kandagatla SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 21402c4066e5SSrinivas Kandagatla }; 21412c4066e5SSrinivas Kandagatla 21422c4066e5SSrinivas Kandagatla static const struct snd_soc_dapm_route wsa_audio_map[] = { 21432c4066e5SSrinivas Kandagatla /* VI Feedback */ 21442c4066e5SSrinivas Kandagatla {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_1", "VIINPUT_WSA"}, 21452c4066e5SSrinivas Kandagatla {"WSA_AIF_VI Mixer", "WSA_SPKR_VI_2", "VIINPUT_WSA"}, 21462c4066e5SSrinivas Kandagatla {"WSA AIF_VI", NULL, "WSA_AIF_VI Mixer"}, 21472c4066e5SSrinivas Kandagatla {"WSA AIF_VI", NULL, "WSA_MCLK"}, 21482c4066e5SSrinivas Kandagatla 21492c4066e5SSrinivas Kandagatla {"WSA RX_MIX EC0_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"}, 21502c4066e5SSrinivas Kandagatla {"WSA RX_MIX EC1_MUX", "RX_MIX_TX0", "WSA_RX INT0 SEC MIX"}, 21512c4066e5SSrinivas Kandagatla {"WSA RX_MIX EC0_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"}, 21522c4066e5SSrinivas Kandagatla {"WSA RX_MIX EC1_MUX", "RX_MIX_TX1", "WSA_RX INT1 SEC MIX"}, 21532c4066e5SSrinivas Kandagatla {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC0_MUX"}, 21542c4066e5SSrinivas Kandagatla {"WSA AIF_ECHO", NULL, "WSA RX_MIX EC1_MUX"}, 21552c4066e5SSrinivas Kandagatla {"WSA AIF_ECHO", NULL, "WSA_MCLK"}, 21562c4066e5SSrinivas Kandagatla 21572c4066e5SSrinivas Kandagatla {"WSA AIF1 PB", NULL, "WSA_MCLK"}, 21582c4066e5SSrinivas Kandagatla {"WSA AIF_MIX1 PB", NULL, "WSA_MCLK"}, 21592c4066e5SSrinivas Kandagatla 21602c4066e5SSrinivas Kandagatla {"WSA RX0 MUX", "AIF1_PB", "WSA AIF1 PB"}, 21612c4066e5SSrinivas Kandagatla {"WSA RX1 MUX", "AIF1_PB", "WSA AIF1 PB"}, 21622c4066e5SSrinivas Kandagatla {"WSA RX_MIX0 MUX", "AIF1_PB", "WSA AIF1 PB"}, 21632c4066e5SSrinivas Kandagatla {"WSA RX_MIX1 MUX", "AIF1_PB", "WSA AIF1 PB"}, 21642c4066e5SSrinivas Kandagatla 21652c4066e5SSrinivas Kandagatla {"WSA RX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 21662c4066e5SSrinivas Kandagatla {"WSA RX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 21672c4066e5SSrinivas Kandagatla {"WSA RX_MIX0 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 21682c4066e5SSrinivas Kandagatla {"WSA RX_MIX1 MUX", "AIF_MIX1_PB", "WSA AIF_MIX1 PB"}, 21692c4066e5SSrinivas Kandagatla 21702c4066e5SSrinivas Kandagatla {"WSA RX0", NULL, "WSA RX0 MUX"}, 21712c4066e5SSrinivas Kandagatla {"WSA RX1", NULL, "WSA RX1 MUX"}, 21722c4066e5SSrinivas Kandagatla {"WSA RX_MIX0", NULL, "WSA RX_MIX0 MUX"}, 21732c4066e5SSrinivas Kandagatla {"WSA RX_MIX1", NULL, "WSA RX_MIX1 MUX"}, 21742c4066e5SSrinivas Kandagatla 21752c4066e5SSrinivas Kandagatla {"WSA RX0", NULL, "WSA_RX0_CLK"}, 21762c4066e5SSrinivas Kandagatla {"WSA RX1", NULL, "WSA_RX1_CLK"}, 21772c4066e5SSrinivas Kandagatla {"WSA RX_MIX0", NULL, "WSA_RX_MIX0_CLK"}, 21782c4066e5SSrinivas Kandagatla {"WSA RX_MIX1", NULL, "WSA_RX_MIX1_CLK"}, 21792c4066e5SSrinivas Kandagatla 21802c4066e5SSrinivas Kandagatla {"WSA_RX0 INP0", "RX0", "WSA RX0"}, 21812c4066e5SSrinivas Kandagatla {"WSA_RX0 INP0", "RX1", "WSA RX1"}, 21822c4066e5SSrinivas Kandagatla {"WSA_RX0 INP0", "RX_MIX0", "WSA RX_MIX0"}, 21832c4066e5SSrinivas Kandagatla {"WSA_RX0 INP0", "RX_MIX1", "WSA RX_MIX1"}, 21842c4066e5SSrinivas Kandagatla {"WSA_RX0 INP0", "DEC0", "WSA_TX DEC0_INP"}, 21852c4066e5SSrinivas Kandagatla {"WSA_RX0 INP0", "DEC1", "WSA_TX DEC1_INP"}, 21862c4066e5SSrinivas Kandagatla {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP0"}, 21872c4066e5SSrinivas Kandagatla 21882c4066e5SSrinivas Kandagatla {"WSA_RX0 INP1", "RX0", "WSA RX0"}, 21892c4066e5SSrinivas Kandagatla {"WSA_RX0 INP1", "RX1", "WSA RX1"}, 21902c4066e5SSrinivas Kandagatla {"WSA_RX0 INP1", "RX_MIX0", "WSA RX_MIX0"}, 21912c4066e5SSrinivas Kandagatla {"WSA_RX0 INP1", "RX_MIX1", "WSA RX_MIX1"}, 21922c4066e5SSrinivas Kandagatla {"WSA_RX0 INP1", "DEC0", "WSA_TX DEC0_INP"}, 21932c4066e5SSrinivas Kandagatla {"WSA_RX0 INP1", "DEC1", "WSA_TX DEC1_INP"}, 21942c4066e5SSrinivas Kandagatla {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP1"}, 21952c4066e5SSrinivas Kandagatla 21962c4066e5SSrinivas Kandagatla {"WSA_RX0 INP2", "RX0", "WSA RX0"}, 21972c4066e5SSrinivas Kandagatla {"WSA_RX0 INP2", "RX1", "WSA RX1"}, 21982c4066e5SSrinivas Kandagatla {"WSA_RX0 INP2", "RX_MIX0", "WSA RX_MIX0"}, 21992c4066e5SSrinivas Kandagatla {"WSA_RX0 INP2", "RX_MIX1", "WSA RX_MIX1"}, 22002c4066e5SSrinivas Kandagatla {"WSA_RX0 INP2", "DEC0", "WSA_TX DEC0_INP"}, 22012c4066e5SSrinivas Kandagatla {"WSA_RX0 INP2", "DEC1", "WSA_TX DEC1_INP"}, 22022c4066e5SSrinivas Kandagatla {"WSA_RX INT0 MIX", NULL, "WSA_RX0 INP2"}, 22032c4066e5SSrinivas Kandagatla 22042c4066e5SSrinivas Kandagatla {"WSA_RX0 MIX INP", "RX0", "WSA RX0"}, 22052c4066e5SSrinivas Kandagatla {"WSA_RX0 MIX INP", "RX1", "WSA RX1"}, 22062c4066e5SSrinivas Kandagatla {"WSA_RX0 MIX INP", "RX_MIX0", "WSA RX_MIX0"}, 22072c4066e5SSrinivas Kandagatla {"WSA_RX0 MIX INP", "RX_MIX1", "WSA RX_MIX1"}, 22082c4066e5SSrinivas Kandagatla {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX0 MIX INP"}, 22092c4066e5SSrinivas Kandagatla 22102c4066e5SSrinivas Kandagatla {"WSA_RX INT0 SEC MIX", NULL, "WSA_RX INT0 MIX"}, 22112c4066e5SSrinivas Kandagatla {"WSA_RX INT0 INTERP", NULL, "WSA_RX INT0 SEC MIX"}, 22122c4066e5SSrinivas Kandagatla {"WSA_RX0 INT0 SIDETONE MIX", "SRC0", "WSA SRC0_INP"}, 22132c4066e5SSrinivas Kandagatla {"WSA_RX INT0 INTERP", NULL, "WSA_RX0 INT0 SIDETONE MIX"}, 22142c4066e5SSrinivas Kandagatla {"WSA_RX INT0 CHAIN", NULL, "WSA_RX INT0 INTERP"}, 22152c4066e5SSrinivas Kandagatla 22162c4066e5SSrinivas Kandagatla {"WSA_SPK1 OUT", NULL, "WSA_RX INT0 CHAIN"}, 22172c4066e5SSrinivas Kandagatla {"WSA_SPK1 OUT", NULL, "WSA_MCLK"}, 22182c4066e5SSrinivas Kandagatla 22192c4066e5SSrinivas Kandagatla {"WSA_RX1 INP0", "RX0", "WSA RX0"}, 22202c4066e5SSrinivas Kandagatla {"WSA_RX1 INP0", "RX1", "WSA RX1"}, 22212c4066e5SSrinivas Kandagatla {"WSA_RX1 INP0", "RX_MIX0", "WSA RX_MIX0"}, 22222c4066e5SSrinivas Kandagatla {"WSA_RX1 INP0", "RX_MIX1", "WSA RX_MIX1"}, 22232c4066e5SSrinivas Kandagatla {"WSA_RX1 INP0", "DEC0", "WSA_TX DEC0_INP"}, 22242c4066e5SSrinivas Kandagatla {"WSA_RX1 INP0", "DEC1", "WSA_TX DEC1_INP"}, 22252c4066e5SSrinivas Kandagatla {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP0"}, 22262c4066e5SSrinivas Kandagatla 22272c4066e5SSrinivas Kandagatla {"WSA_RX1 INP1", "RX0", "WSA RX0"}, 22282c4066e5SSrinivas Kandagatla {"WSA_RX1 INP1", "RX1", "WSA RX1"}, 22292c4066e5SSrinivas Kandagatla {"WSA_RX1 INP1", "RX_MIX0", "WSA RX_MIX0"}, 22302c4066e5SSrinivas Kandagatla {"WSA_RX1 INP1", "RX_MIX1", "WSA RX_MIX1"}, 22312c4066e5SSrinivas Kandagatla {"WSA_RX1 INP1", "DEC0", "WSA_TX DEC0_INP"}, 22322c4066e5SSrinivas Kandagatla {"WSA_RX1 INP1", "DEC1", "WSA_TX DEC1_INP"}, 22332c4066e5SSrinivas Kandagatla {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP1"}, 22342c4066e5SSrinivas Kandagatla 22352c4066e5SSrinivas Kandagatla {"WSA_RX1 INP2", "RX0", "WSA RX0"}, 22362c4066e5SSrinivas Kandagatla {"WSA_RX1 INP2", "RX1", "WSA RX1"}, 22372c4066e5SSrinivas Kandagatla {"WSA_RX1 INP2", "RX_MIX0", "WSA RX_MIX0"}, 22382c4066e5SSrinivas Kandagatla {"WSA_RX1 INP2", "RX_MIX1", "WSA RX_MIX1"}, 22392c4066e5SSrinivas Kandagatla {"WSA_RX1 INP2", "DEC0", "WSA_TX DEC0_INP"}, 22402c4066e5SSrinivas Kandagatla {"WSA_RX1 INP2", "DEC1", "WSA_TX DEC1_INP"}, 22412c4066e5SSrinivas Kandagatla {"WSA_RX INT1 MIX", NULL, "WSA_RX1 INP2"}, 22422c4066e5SSrinivas Kandagatla 22432c4066e5SSrinivas Kandagatla {"WSA_RX1 MIX INP", "RX0", "WSA RX0"}, 22442c4066e5SSrinivas Kandagatla {"WSA_RX1 MIX INP", "RX1", "WSA RX1"}, 22452c4066e5SSrinivas Kandagatla {"WSA_RX1 MIX INP", "RX_MIX0", "WSA RX_MIX0"}, 22462c4066e5SSrinivas Kandagatla {"WSA_RX1 MIX INP", "RX_MIX1", "WSA RX_MIX1"}, 22472c4066e5SSrinivas Kandagatla {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX1 MIX INP"}, 22482c4066e5SSrinivas Kandagatla 22492c4066e5SSrinivas Kandagatla {"WSA_RX INT1 SEC MIX", NULL, "WSA_RX INT1 MIX"}, 22502c4066e5SSrinivas Kandagatla {"WSA_RX INT1 INTERP", NULL, "WSA_RX INT1 SEC MIX"}, 22512c4066e5SSrinivas Kandagatla 22522c4066e5SSrinivas Kandagatla {"WSA_RX INT1 CHAIN", NULL, "WSA_RX INT1 INTERP"}, 22532c4066e5SSrinivas Kandagatla {"WSA_SPK2 OUT", NULL, "WSA_RX INT1 CHAIN"}, 22542c4066e5SSrinivas Kandagatla {"WSA_SPK2 OUT", NULL, "WSA_MCLK"}, 22552c4066e5SSrinivas Kandagatla }; 22562c4066e5SSrinivas Kandagatla 2257809bcbceSSrinivas Kandagatla static int wsa_swrm_clock(struct wsa_macro *wsa, bool enable) 2258809bcbceSSrinivas Kandagatla { 2259809bcbceSSrinivas Kandagatla struct regmap *regmap = wsa->regmap; 2260809bcbceSSrinivas Kandagatla 2261809bcbceSSrinivas Kandagatla if (enable) { 226205a41340SSrinivas Kandagatla int ret; 226305a41340SSrinivas Kandagatla 226405a41340SSrinivas Kandagatla ret = clk_prepare_enable(wsa->mclk); 226505a41340SSrinivas Kandagatla if (ret) { 226605a41340SSrinivas Kandagatla dev_err(wsa->dev, "failed to enable mclk\n"); 226705a41340SSrinivas Kandagatla return ret; 226805a41340SSrinivas Kandagatla } 2269809bcbceSSrinivas Kandagatla wsa_macro_mclk_enable(wsa, true); 2270809bcbceSSrinivas Kandagatla 2271809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2272809bcbceSSrinivas Kandagatla CDC_WSA_SWR_CLK_EN_MASK, 2273809bcbceSSrinivas Kandagatla CDC_WSA_SWR_CLK_ENABLE); 2274809bcbceSSrinivas Kandagatla 2275809bcbceSSrinivas Kandagatla } else { 2276809bcbceSSrinivas Kandagatla regmap_update_bits(regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2277809bcbceSSrinivas Kandagatla CDC_WSA_SWR_CLK_EN_MASK, 0); 2278809bcbceSSrinivas Kandagatla wsa_macro_mclk_enable(wsa, false); 227905a41340SSrinivas Kandagatla clk_disable_unprepare(wsa->mclk); 2280809bcbceSSrinivas Kandagatla } 2281809bcbceSSrinivas Kandagatla 2282809bcbceSSrinivas Kandagatla return 0; 2283809bcbceSSrinivas Kandagatla } 2284809bcbceSSrinivas Kandagatla 2285809bcbceSSrinivas Kandagatla static int wsa_macro_component_probe(struct snd_soc_component *comp) 2286809bcbceSSrinivas Kandagatla { 2287809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = snd_soc_component_get_drvdata(comp); 2288809bcbceSSrinivas Kandagatla 2289809bcbceSSrinivas Kandagatla snd_soc_component_init_regmap(comp, wsa->regmap); 2290809bcbceSSrinivas Kandagatla 2291809bcbceSSrinivas Kandagatla wsa->spkr_gain_offset = WSA_MACRO_GAIN_OFFSET_M1P5_DB; 2292809bcbceSSrinivas Kandagatla 2293809bcbceSSrinivas Kandagatla /* set SPKR rate to FS_2P4_3P072 */ 2294809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(comp, CDC_WSA_RX0_RX_PATH_CFG1, 2295809bcbceSSrinivas Kandagatla CDC_WSA_RX_PATH_SPKR_RATE_MASK, 2296809bcbceSSrinivas Kandagatla CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072); 2297809bcbceSSrinivas Kandagatla 2298809bcbceSSrinivas Kandagatla snd_soc_component_update_bits(comp, CDC_WSA_RX1_RX_PATH_CFG1, 2299809bcbceSSrinivas Kandagatla CDC_WSA_RX_PATH_SPKR_RATE_MASK, 2300809bcbceSSrinivas Kandagatla CDC_WSA_RX_PATH_SPKR_RATE_FS_2P4_3P072); 2301809bcbceSSrinivas Kandagatla 2302809bcbceSSrinivas Kandagatla wsa_macro_set_spkr_mode(comp, WSA_MACRO_SPKR_MODE_1); 2303809bcbceSSrinivas Kandagatla 2304809bcbceSSrinivas Kandagatla return 0; 2305809bcbceSSrinivas Kandagatla } 2306809bcbceSSrinivas Kandagatla 2307809bcbceSSrinivas Kandagatla static int swclk_gate_enable(struct clk_hw *hw) 2308809bcbceSSrinivas Kandagatla { 2309809bcbceSSrinivas Kandagatla return wsa_swrm_clock(to_wsa_macro(hw), true); 2310809bcbceSSrinivas Kandagatla } 2311809bcbceSSrinivas Kandagatla 2312809bcbceSSrinivas Kandagatla static void swclk_gate_disable(struct clk_hw *hw) 2313809bcbceSSrinivas Kandagatla { 2314809bcbceSSrinivas Kandagatla wsa_swrm_clock(to_wsa_macro(hw), false); 2315809bcbceSSrinivas Kandagatla } 2316809bcbceSSrinivas Kandagatla 2317809bcbceSSrinivas Kandagatla static int swclk_gate_is_enabled(struct clk_hw *hw) 2318809bcbceSSrinivas Kandagatla { 2319809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = to_wsa_macro(hw); 2320809bcbceSSrinivas Kandagatla int ret, val; 2321809bcbceSSrinivas Kandagatla 2322809bcbceSSrinivas Kandagatla regmap_read(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, &val); 2323809bcbceSSrinivas Kandagatla ret = val & BIT(0); 2324809bcbceSSrinivas Kandagatla 2325809bcbceSSrinivas Kandagatla return ret; 2326809bcbceSSrinivas Kandagatla } 2327809bcbceSSrinivas Kandagatla 2328809bcbceSSrinivas Kandagatla static unsigned long swclk_recalc_rate(struct clk_hw *hw, 2329809bcbceSSrinivas Kandagatla unsigned long parent_rate) 2330809bcbceSSrinivas Kandagatla { 2331809bcbceSSrinivas Kandagatla return parent_rate / 2; 2332809bcbceSSrinivas Kandagatla } 2333809bcbceSSrinivas Kandagatla 2334809bcbceSSrinivas Kandagatla static const struct clk_ops swclk_gate_ops = { 2335809bcbceSSrinivas Kandagatla .prepare = swclk_gate_enable, 2336809bcbceSSrinivas Kandagatla .unprepare = swclk_gate_disable, 2337809bcbceSSrinivas Kandagatla .is_enabled = swclk_gate_is_enabled, 2338809bcbceSSrinivas Kandagatla .recalc_rate = swclk_recalc_rate, 2339809bcbceSSrinivas Kandagatla }; 2340809bcbceSSrinivas Kandagatla 234127dc72b4SJerome Brunet static int wsa_macro_register_mclk_output(struct wsa_macro *wsa) 2342809bcbceSSrinivas Kandagatla { 2343809bcbceSSrinivas Kandagatla struct device *dev = wsa->dev; 2344809bcbceSSrinivas Kandagatla const char *parent_clk_name; 2345809bcbceSSrinivas Kandagatla struct clk_hw *hw; 2346809bcbceSSrinivas Kandagatla struct clk_init_data init; 2347809bcbceSSrinivas Kandagatla int ret; 2348809bcbceSSrinivas Kandagatla 234905a41340SSrinivas Kandagatla parent_clk_name = __clk_get_name(wsa->npl); 2350809bcbceSSrinivas Kandagatla 23519f63869aSKrzysztof Kozlowski init.name = "mclk"; 23529f63869aSKrzysztof Kozlowski of_property_read_string(dev_of_node(dev), "clock-output-names", 23539f63869aSKrzysztof Kozlowski &init.name); 2354809bcbceSSrinivas Kandagatla init.ops = &swclk_gate_ops; 2355809bcbceSSrinivas Kandagatla init.flags = 0; 2356809bcbceSSrinivas Kandagatla init.parent_names = &parent_clk_name; 2357809bcbceSSrinivas Kandagatla init.num_parents = 1; 2358809bcbceSSrinivas Kandagatla wsa->hw.init = &init; 2359809bcbceSSrinivas Kandagatla hw = &wsa->hw; 2360809bcbceSSrinivas Kandagatla ret = clk_hw_register(wsa->dev, hw); 2361809bcbceSSrinivas Kandagatla if (ret) 236227dc72b4SJerome Brunet return ret; 2363809bcbceSSrinivas Kandagatla 236427dc72b4SJerome Brunet return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw); 2365809bcbceSSrinivas Kandagatla } 2366809bcbceSSrinivas Kandagatla 2367809bcbceSSrinivas Kandagatla static const struct snd_soc_component_driver wsa_macro_component_drv = { 2368809bcbceSSrinivas Kandagatla .name = "WSA MACRO", 2369809bcbceSSrinivas Kandagatla .probe = wsa_macro_component_probe, 2370809bcbceSSrinivas Kandagatla .controls = wsa_macro_snd_controls, 2371809bcbceSSrinivas Kandagatla .num_controls = ARRAY_SIZE(wsa_macro_snd_controls), 23722c4066e5SSrinivas Kandagatla .dapm_widgets = wsa_macro_dapm_widgets, 23732c4066e5SSrinivas Kandagatla .num_dapm_widgets = ARRAY_SIZE(wsa_macro_dapm_widgets), 23742c4066e5SSrinivas Kandagatla .dapm_routes = wsa_audio_map, 23752c4066e5SSrinivas Kandagatla .num_dapm_routes = ARRAY_SIZE(wsa_audio_map), 2376809bcbceSSrinivas Kandagatla }; 2377809bcbceSSrinivas Kandagatla 2378809bcbceSSrinivas Kandagatla static int wsa_macro_probe(struct platform_device *pdev) 2379809bcbceSSrinivas Kandagatla { 2380809bcbceSSrinivas Kandagatla struct device *dev = &pdev->dev; 2381809bcbceSSrinivas Kandagatla struct wsa_macro *wsa; 2382809bcbceSSrinivas Kandagatla void __iomem *base; 2383809bcbceSSrinivas Kandagatla int ret; 2384809bcbceSSrinivas Kandagatla 2385809bcbceSSrinivas Kandagatla wsa = devm_kzalloc(dev, sizeof(*wsa), GFP_KERNEL); 2386809bcbceSSrinivas Kandagatla if (!wsa) 2387809bcbceSSrinivas Kandagatla return -ENOMEM; 2388809bcbceSSrinivas Kandagatla 2389e252801dSSrinivas Kandagatla wsa->macro = devm_clk_get_optional(dev, "macro"); 2390e252801dSSrinivas Kandagatla if (IS_ERR(wsa->macro)) 2391e252801dSSrinivas Kandagatla return PTR_ERR(wsa->macro); 2392809bcbceSSrinivas Kandagatla 2393e252801dSSrinivas Kandagatla wsa->dcodec = devm_clk_get_optional(dev, "dcodec"); 2394e252801dSSrinivas Kandagatla if (IS_ERR(wsa->dcodec)) 2395e252801dSSrinivas Kandagatla return PTR_ERR(wsa->dcodec); 2396e252801dSSrinivas Kandagatla 2397e252801dSSrinivas Kandagatla wsa->mclk = devm_clk_get(dev, "mclk"); 2398e252801dSSrinivas Kandagatla if (IS_ERR(wsa->mclk)) 2399e252801dSSrinivas Kandagatla return PTR_ERR(wsa->mclk); 2400e252801dSSrinivas Kandagatla 2401e252801dSSrinivas Kandagatla wsa->npl = devm_clk_get(dev, "npl"); 2402e252801dSSrinivas Kandagatla if (IS_ERR(wsa->npl)) 2403e252801dSSrinivas Kandagatla return PTR_ERR(wsa->npl); 2404e252801dSSrinivas Kandagatla 2405e252801dSSrinivas Kandagatla wsa->fsgen = devm_clk_get(dev, "fsgen"); 2406e252801dSSrinivas Kandagatla if (IS_ERR(wsa->fsgen)) 2407e252801dSSrinivas Kandagatla return PTR_ERR(wsa->fsgen); 2408809bcbceSSrinivas Kandagatla 2409809bcbceSSrinivas Kandagatla base = devm_platform_ioremap_resource(pdev, 0); 2410809bcbceSSrinivas Kandagatla if (IS_ERR(base)) 2411809bcbceSSrinivas Kandagatla return PTR_ERR(base); 2412809bcbceSSrinivas Kandagatla 2413809bcbceSSrinivas Kandagatla wsa->regmap = devm_regmap_init_mmio(dev, base, &wsa_regmap_config); 2414aa505eccSJiasheng Jiang if (IS_ERR(wsa->regmap)) 2415aa505eccSJiasheng Jiang return PTR_ERR(wsa->regmap); 2416809bcbceSSrinivas Kandagatla 2417809bcbceSSrinivas Kandagatla dev_set_drvdata(dev, wsa); 2418809bcbceSSrinivas Kandagatla 2419809bcbceSSrinivas Kandagatla wsa->dev = dev; 2420809bcbceSSrinivas Kandagatla 2421809bcbceSSrinivas Kandagatla /* set MCLK and NPL rates */ 2422e252801dSSrinivas Kandagatla clk_set_rate(wsa->mclk, WSA_MACRO_MCLK_FREQ); 2423e252801dSSrinivas Kandagatla clk_set_rate(wsa->npl, WSA_MACRO_MCLK_FREQ); 2424809bcbceSSrinivas Kandagatla 2425e252801dSSrinivas Kandagatla ret = clk_prepare_enable(wsa->macro); 2426809bcbceSSrinivas Kandagatla if (ret) 2427e252801dSSrinivas Kandagatla goto err; 2428809bcbceSSrinivas Kandagatla 2429e252801dSSrinivas Kandagatla ret = clk_prepare_enable(wsa->dcodec); 2430e252801dSSrinivas Kandagatla if (ret) 2431e252801dSSrinivas Kandagatla goto err_dcodec; 2432e252801dSSrinivas Kandagatla 2433e252801dSSrinivas Kandagatla ret = clk_prepare_enable(wsa->mclk); 2434e252801dSSrinivas Kandagatla if (ret) 2435e252801dSSrinivas Kandagatla goto err_mclk; 2436e252801dSSrinivas Kandagatla 2437e252801dSSrinivas Kandagatla ret = clk_prepare_enable(wsa->npl); 2438e252801dSSrinivas Kandagatla if (ret) 2439e252801dSSrinivas Kandagatla goto err_npl; 2440e252801dSSrinivas Kandagatla 2441e252801dSSrinivas Kandagatla ret = clk_prepare_enable(wsa->fsgen); 2442e252801dSSrinivas Kandagatla if (ret) 2443e252801dSSrinivas Kandagatla goto err_fsgen; 2444e252801dSSrinivas Kandagatla 2445ddffe3b8SSrinivas Kandagatla /* reset swr ip */ 2446ddffe3b8SSrinivas Kandagatla regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2447ddffe3b8SSrinivas Kandagatla CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_ENABLE); 2448ddffe3b8SSrinivas Kandagatla 2449ddffe3b8SSrinivas Kandagatla regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2450ddffe3b8SSrinivas Kandagatla CDC_WSA_SWR_CLK_EN_MASK, CDC_WSA_SWR_CLK_ENABLE); 2451ddffe3b8SSrinivas Kandagatla 2452ddffe3b8SSrinivas Kandagatla /* Bring out of reset */ 2453ddffe3b8SSrinivas Kandagatla regmap_update_bits(wsa->regmap, CDC_WSA_CLK_RST_CTRL_SWR_CONTROL, 2454ddffe3b8SSrinivas Kandagatla CDC_WSA_SWR_RST_EN_MASK, CDC_WSA_SWR_RST_DISABLE); 2455ddffe3b8SSrinivas Kandagatla 2456809bcbceSSrinivas Kandagatla ret = devm_snd_soc_register_component(dev, &wsa_macro_component_drv, 2457809bcbceSSrinivas Kandagatla wsa_macro_dai, 2458809bcbceSSrinivas Kandagatla ARRAY_SIZE(wsa_macro_dai)); 2459809bcbceSSrinivas Kandagatla if (ret) 2460e252801dSSrinivas Kandagatla goto err_clkout; 2461809bcbceSSrinivas Kandagatla 2462c96baa29SSrinivas Kandagatla pm_runtime_set_autosuspend_delay(dev, 3000); 2463c96baa29SSrinivas Kandagatla pm_runtime_use_autosuspend(dev); 2464c96baa29SSrinivas Kandagatla pm_runtime_mark_last_busy(dev); 2465c96baa29SSrinivas Kandagatla pm_runtime_set_active(dev); 2466c96baa29SSrinivas Kandagatla pm_runtime_enable(dev); 2467c96baa29SSrinivas Kandagatla 24681dc34590SSrinivas Kandagatla ret = wsa_macro_register_mclk_output(wsa); 24691dc34590SSrinivas Kandagatla if (ret) 24701dc34590SSrinivas Kandagatla goto err_clkout; 24711dc34590SSrinivas Kandagatla 2472e252801dSSrinivas Kandagatla return 0; 2473e252801dSSrinivas Kandagatla 2474e252801dSSrinivas Kandagatla err_clkout: 2475e252801dSSrinivas Kandagatla clk_disable_unprepare(wsa->fsgen); 2476e252801dSSrinivas Kandagatla err_fsgen: 2477e252801dSSrinivas Kandagatla clk_disable_unprepare(wsa->npl); 2478e252801dSSrinivas Kandagatla err_npl: 2479e252801dSSrinivas Kandagatla clk_disable_unprepare(wsa->mclk); 2480e252801dSSrinivas Kandagatla err_mclk: 2481e252801dSSrinivas Kandagatla clk_disable_unprepare(wsa->dcodec); 2482e252801dSSrinivas Kandagatla err_dcodec: 2483e252801dSSrinivas Kandagatla clk_disable_unprepare(wsa->macro); 2484809bcbceSSrinivas Kandagatla err: 2485809bcbceSSrinivas Kandagatla return ret; 2486809bcbceSSrinivas Kandagatla 2487809bcbceSSrinivas Kandagatla } 2488809bcbceSSrinivas Kandagatla 2489*23a3ef65SUwe Kleine-König static void wsa_macro_remove(struct platform_device *pdev) 2490809bcbceSSrinivas Kandagatla { 2491809bcbceSSrinivas Kandagatla struct wsa_macro *wsa = dev_get_drvdata(&pdev->dev); 2492809bcbceSSrinivas Kandagatla 2493e252801dSSrinivas Kandagatla clk_disable_unprepare(wsa->macro); 2494e252801dSSrinivas Kandagatla clk_disable_unprepare(wsa->dcodec); 2495e252801dSSrinivas Kandagatla clk_disable_unprepare(wsa->mclk); 2496e252801dSSrinivas Kandagatla clk_disable_unprepare(wsa->npl); 2497e252801dSSrinivas Kandagatla clk_disable_unprepare(wsa->fsgen); 2498809bcbceSSrinivas Kandagatla } 2499809bcbceSSrinivas Kandagatla 2500c96baa29SSrinivas Kandagatla static int __maybe_unused wsa_macro_runtime_suspend(struct device *dev) 2501c96baa29SSrinivas Kandagatla { 2502c96baa29SSrinivas Kandagatla struct wsa_macro *wsa = dev_get_drvdata(dev); 2503c96baa29SSrinivas Kandagatla 2504c96baa29SSrinivas Kandagatla regcache_cache_only(wsa->regmap, true); 2505c96baa29SSrinivas Kandagatla regcache_mark_dirty(wsa->regmap); 2506c96baa29SSrinivas Kandagatla 2507c96baa29SSrinivas Kandagatla clk_disable_unprepare(wsa->mclk); 2508c96baa29SSrinivas Kandagatla clk_disable_unprepare(wsa->npl); 2509c96baa29SSrinivas Kandagatla clk_disable_unprepare(wsa->fsgen); 2510c96baa29SSrinivas Kandagatla 2511c96baa29SSrinivas Kandagatla return 0; 2512c96baa29SSrinivas Kandagatla } 2513c96baa29SSrinivas Kandagatla 2514c96baa29SSrinivas Kandagatla static int __maybe_unused wsa_macro_runtime_resume(struct device *dev) 2515c96baa29SSrinivas Kandagatla { 2516c96baa29SSrinivas Kandagatla struct wsa_macro *wsa = dev_get_drvdata(dev); 2517c96baa29SSrinivas Kandagatla int ret; 2518c96baa29SSrinivas Kandagatla 2519c96baa29SSrinivas Kandagatla ret = clk_prepare_enable(wsa->mclk); 2520c96baa29SSrinivas Kandagatla if (ret) { 2521c96baa29SSrinivas Kandagatla dev_err(dev, "unable to prepare mclk\n"); 2522c96baa29SSrinivas Kandagatla return ret; 2523c96baa29SSrinivas Kandagatla } 2524c96baa29SSrinivas Kandagatla 2525c96baa29SSrinivas Kandagatla ret = clk_prepare_enable(wsa->npl); 2526c96baa29SSrinivas Kandagatla if (ret) { 2527c96baa29SSrinivas Kandagatla dev_err(dev, "unable to prepare mclkx2\n"); 2528c96baa29SSrinivas Kandagatla goto err_npl; 2529c96baa29SSrinivas Kandagatla } 2530c96baa29SSrinivas Kandagatla 2531c96baa29SSrinivas Kandagatla ret = clk_prepare_enable(wsa->fsgen); 2532c96baa29SSrinivas Kandagatla if (ret) { 2533c96baa29SSrinivas Kandagatla dev_err(dev, "unable to prepare fsgen\n"); 2534c96baa29SSrinivas Kandagatla goto err_fsgen; 2535c96baa29SSrinivas Kandagatla } 2536c96baa29SSrinivas Kandagatla 2537c96baa29SSrinivas Kandagatla regcache_cache_only(wsa->regmap, false); 2538c96baa29SSrinivas Kandagatla regcache_sync(wsa->regmap); 2539c96baa29SSrinivas Kandagatla 2540c96baa29SSrinivas Kandagatla return 0; 2541c96baa29SSrinivas Kandagatla err_fsgen: 2542c96baa29SSrinivas Kandagatla clk_disable_unprepare(wsa->npl); 2543c96baa29SSrinivas Kandagatla err_npl: 2544c96baa29SSrinivas Kandagatla clk_disable_unprepare(wsa->mclk); 2545c96baa29SSrinivas Kandagatla 2546c96baa29SSrinivas Kandagatla return ret; 2547c96baa29SSrinivas Kandagatla } 2548c96baa29SSrinivas Kandagatla 2549c96baa29SSrinivas Kandagatla static const struct dev_pm_ops wsa_macro_pm_ops = { 2550c96baa29SSrinivas Kandagatla SET_RUNTIME_PM_OPS(wsa_macro_runtime_suspend, wsa_macro_runtime_resume, NULL) 2551c96baa29SSrinivas Kandagatla }; 2552c96baa29SSrinivas Kandagatla 2553809bcbceSSrinivas Kandagatla static const struct of_device_id wsa_macro_dt_match[] = { 25549d8c6981SSrinivasa Rao Mandadapu {.compatible = "qcom,sc7280-lpass-wsa-macro"}, 2555809bcbceSSrinivas Kandagatla {.compatible = "qcom,sm8250-lpass-wsa-macro"}, 25568d2be441SSrinivas Kandagatla {.compatible = "qcom,sm8450-lpass-wsa-macro"}, 25578d2be441SSrinivas Kandagatla {.compatible = "qcom,sc8280xp-lpass-wsa-macro" }, 2558809bcbceSSrinivas Kandagatla {} 2559809bcbceSSrinivas Kandagatla }; 2560809bcbceSSrinivas Kandagatla MODULE_DEVICE_TABLE(of, wsa_macro_dt_match); 2561809bcbceSSrinivas Kandagatla 2562809bcbceSSrinivas Kandagatla static struct platform_driver wsa_macro_driver = { 2563809bcbceSSrinivas Kandagatla .driver = { 2564809bcbceSSrinivas Kandagatla .name = "wsa_macro", 2565809bcbceSSrinivas Kandagatla .of_match_table = wsa_macro_dt_match, 2566c96baa29SSrinivas Kandagatla .pm = &wsa_macro_pm_ops, 2567809bcbceSSrinivas Kandagatla }, 2568809bcbceSSrinivas Kandagatla .probe = wsa_macro_probe, 2569*23a3ef65SUwe Kleine-König .remove_new = wsa_macro_remove, 2570809bcbceSSrinivas Kandagatla }; 2571809bcbceSSrinivas Kandagatla 2572809bcbceSSrinivas Kandagatla module_platform_driver(wsa_macro_driver); 2573809bcbceSSrinivas Kandagatla MODULE_DESCRIPTION("WSA macro driver"); 2574809bcbceSSrinivas Kandagatla MODULE_LICENSE("GPL"); 2575