1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/clk-provider.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/module.h> 9 #include <linux/of_clk.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <sound/soc.h> 16 #include <sound/soc-dapm.h> 17 #include <sound/tlv.h> 18 19 #include "lpass-macro-common.h" 20 21 /* VA macro registers */ 22 #define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 23 #define CDC_VA_MCLK_CONTROL_EN BIT(0) 24 #define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 25 #define CDC_VA_FS_CONTROL_EN BIT(0) 26 #define CDC_VA_FS_COUNTER_CLR BIT(1) 27 #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL (0x0008) 28 #define CDC_VA_SWR_RESET_MASK BIT(1) 29 #define CDC_VA_SWR_RESET_ENABLE BIT(1) 30 #define CDC_VA_SWR_CLK_EN_MASK BIT(0) 31 #define CDC_VA_SWR_CLK_ENABLE BIT(0) 32 #define CDC_VA_TOP_CSR_TOP_CFG0 (0x0080) 33 #define CDC_VA_FS_BROADCAST_EN BIT(1) 34 #define CDC_VA_TOP_CSR_DMIC0_CTL (0x0084) 35 #define CDC_VA_TOP_CSR_DMIC1_CTL (0x0088) 36 #define CDC_VA_TOP_CSR_DMIC2_CTL (0x008C) 37 #define CDC_VA_TOP_CSR_DMIC3_CTL (0x0090) 38 #define CDC_VA_DMIC_EN_MASK BIT(0) 39 #define CDC_VA_DMIC_ENABLE BIT(0) 40 #define CDC_VA_DMIC_CLK_SEL_MASK GENMASK(3, 1) 41 #define CDC_VA_DMIC_CLK_SEL_SHFT 1 42 #define CDC_VA_DMIC_CLK_SEL_DIV0 0x0 43 #define CDC_VA_DMIC_CLK_SEL_DIV1 0x2 44 #define CDC_VA_DMIC_CLK_SEL_DIV2 0x4 45 #define CDC_VA_DMIC_CLK_SEL_DIV3 0x6 46 #define CDC_VA_DMIC_CLK_SEL_DIV4 0x8 47 #define CDC_VA_DMIC_CLK_SEL_DIV5 0xa 48 #define CDC_VA_TOP_CSR_DMIC_CFG (0x0094) 49 #define CDC_VA_RESET_ALL_DMICS_MASK BIT(7) 50 #define CDC_VA_RESET_ALL_DMICS_RESET BIT(7) 51 #define CDC_VA_RESET_ALL_DMICS_DISABLE 0 52 #define CDC_VA_DMIC3_FREQ_CHANGE_MASK BIT(3) 53 #define CDC_VA_DMIC3_FREQ_CHANGE_EN BIT(3) 54 #define CDC_VA_DMIC2_FREQ_CHANGE_MASK BIT(2) 55 #define CDC_VA_DMIC2_FREQ_CHANGE_EN BIT(2) 56 #define CDC_VA_DMIC1_FREQ_CHANGE_MASK BIT(1) 57 #define CDC_VA_DMIC1_FREQ_CHANGE_EN BIT(1) 58 #define CDC_VA_DMIC0_FREQ_CHANGE_MASK BIT(0) 59 #define CDC_VA_DMIC0_FREQ_CHANGE_EN BIT(0) 60 #define CDC_VA_DMIC_FREQ_CHANGE_DISABLE 0 61 #define CDC_VA_TOP_CSR_DEBUG_BUS (0x009C) 62 #define CDC_VA_TOP_CSR_DEBUG_EN (0x00A0) 63 #define CDC_VA_TOP_CSR_TX_I2S_CTL (0x00A4) 64 #define CDC_VA_TOP_CSR_I2S_CLK (0x00A8) 65 #define CDC_VA_TOP_CSR_I2S_RESET (0x00AC) 66 #define CDC_VA_TOP_CSR_CORE_ID_0 (0x00C0) 67 #define CDC_VA_TOP_CSR_CORE_ID_1 (0x00C4) 68 #define CDC_VA_TOP_CSR_CORE_ID_2 (0x00C8) 69 #define CDC_VA_TOP_CSR_CORE_ID_3 (0x00CC) 70 #define CDC_VA_TOP_CSR_SWR_MIC_CTL0 (0x00D0) 71 #define CDC_VA_TOP_CSR_SWR_MIC_CTL1 (0x00D4) 72 #define CDC_VA_TOP_CSR_SWR_MIC_CTL2 (0x00D8) 73 #define CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK (0xEE) 74 #define CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1 (0xCC) 75 #define CDC_VA_TOP_CSR_SWR_CTRL (0x00DC) 76 #define CDC_VA_INP_MUX_ADC_MUX0_CFG0 (0x0100) 77 #define CDC_VA_INP_MUX_ADC_MUX0_CFG1 (0x0104) 78 #define CDC_VA_INP_MUX_ADC_MUX1_CFG0 (0x0108) 79 #define CDC_VA_INP_MUX_ADC_MUX1_CFG1 (0x010C) 80 #define CDC_VA_INP_MUX_ADC_MUX2_CFG0 (0x0110) 81 #define CDC_VA_INP_MUX_ADC_MUX2_CFG1 (0x0114) 82 #define CDC_VA_INP_MUX_ADC_MUX3_CFG0 (0x0118) 83 #define CDC_VA_INP_MUX_ADC_MUX3_CFG1 (0x011C) 84 #define CDC_VA_TX0_TX_PATH_CTL (0x0400) 85 #define CDC_VA_TX_PATH_CLK_EN_MASK BIT(5) 86 #define CDC_VA_TX_PATH_CLK_EN BIT(5) 87 #define CDC_VA_TX_PATH_CLK_DISABLE 0 88 #define CDC_VA_TX_PATH_PGA_MUTE_EN_MASK BIT(4) 89 #define CDC_VA_TX_PATH_PGA_MUTE_EN BIT(4) 90 #define CDC_VA_TX_PATH_PGA_MUTE_DISABLE 0 91 #define CDC_VA_TX0_TX_PATH_CFG0 (0x0404) 92 #define CDC_VA_ADC_MODE_MASK GENMASK(2, 1) 93 #define CDC_VA_ADC_MODE_SHIFT 1 94 #define TX_HPF_CUT_OFF_FREQ_MASK GENMASK(6, 5) 95 #define CF_MIN_3DB_4HZ 0x0 96 #define CF_MIN_3DB_75HZ 0x1 97 #define CF_MIN_3DB_150HZ 0x2 98 #define CDC_VA_TX0_TX_PATH_CFG1 (0x0408) 99 #define CDC_VA_TX0_TX_VOL_CTL (0x040C) 100 #define CDC_VA_TX0_TX_PATH_SEC0 (0x0410) 101 #define CDC_VA_TX0_TX_PATH_SEC1 (0x0414) 102 #define CDC_VA_TX0_TX_PATH_SEC2 (0x0418) 103 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK BIT(1) 104 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ BIT(1) 105 #define CDC_VA_TX_HPF_ZERO_GATE_MASK BIT(0) 106 #define CDC_VA_TX_HPF_ZERO_NO_GATE BIT(0) 107 #define CDC_VA_TX_HPF_ZERO_GATE 0 108 #define CDC_VA_TX0_TX_PATH_SEC3 (0x041C) 109 #define CDC_VA_TX0_TX_PATH_SEC4 (0x0420) 110 #define CDC_VA_TX0_TX_PATH_SEC5 (0x0424) 111 #define CDC_VA_TX0_TX_PATH_SEC6 (0x0428) 112 #define CDC_VA_TX0_TX_PATH_SEC7 (0x042C) 113 #define CDC_VA_TX1_TX_PATH_CTL (0x0480) 114 #define CDC_VA_TX1_TX_PATH_CFG0 (0x0484) 115 #define CDC_VA_TX1_TX_PATH_CFG1 (0x0488) 116 #define CDC_VA_TX1_TX_VOL_CTL (0x048C) 117 #define CDC_VA_TX1_TX_PATH_SEC0 (0x0490) 118 #define CDC_VA_TX1_TX_PATH_SEC1 (0x0494) 119 #define CDC_VA_TX1_TX_PATH_SEC2 (0x0498) 120 #define CDC_VA_TX1_TX_PATH_SEC3 (0x049C) 121 #define CDC_VA_TX1_TX_PATH_SEC4 (0x04A0) 122 #define CDC_VA_TX1_TX_PATH_SEC5 (0x04A4) 123 #define CDC_VA_TX1_TX_PATH_SEC6 (0x04A8) 124 #define CDC_VA_TX2_TX_PATH_CTL (0x0500) 125 #define CDC_VA_TX2_TX_PATH_CFG0 (0x0504) 126 #define CDC_VA_TX2_TX_PATH_CFG1 (0x0508) 127 #define CDC_VA_TX2_TX_VOL_CTL (0x050C) 128 #define CDC_VA_TX2_TX_PATH_SEC0 (0x0510) 129 #define CDC_VA_TX2_TX_PATH_SEC1 (0x0514) 130 #define CDC_VA_TX2_TX_PATH_SEC2 (0x0518) 131 #define CDC_VA_TX2_TX_PATH_SEC3 (0x051C) 132 #define CDC_VA_TX2_TX_PATH_SEC4 (0x0520) 133 #define CDC_VA_TX2_TX_PATH_SEC5 (0x0524) 134 #define CDC_VA_TX2_TX_PATH_SEC6 (0x0528) 135 #define CDC_VA_TX3_TX_PATH_CTL (0x0580) 136 #define CDC_VA_TX3_TX_PATH_CFG0 (0x0584) 137 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK BIT(7) 138 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC BIT(7) 139 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC 0 140 #define CDC_VA_TX3_TX_PATH_CFG1 (0x0588) 141 #define CDC_VA_TX3_TX_VOL_CTL (0x058C) 142 #define CDC_VA_TX3_TX_PATH_SEC0 (0x0590) 143 #define CDC_VA_TX3_TX_PATH_SEC1 (0x0594) 144 #define CDC_VA_TX3_TX_PATH_SEC2 (0x0598) 145 #define CDC_VA_TX3_TX_PATH_SEC3 (0x059C) 146 #define CDC_VA_TX3_TX_PATH_SEC4 (0x05A0) 147 #define CDC_VA_TX3_TX_PATH_SEC5 (0x05A4) 148 #define CDC_VA_TX3_TX_PATH_SEC6 (0x05A8) 149 150 #define VA_MAX_OFFSET (0x07A8) 151 152 #define VA_MACRO_NUM_DECIMATORS 4 153 #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 154 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 155 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 156 #define VA_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 157 SNDRV_PCM_FMTBIT_S24_LE |\ 158 SNDRV_PCM_FMTBIT_S24_3LE) 159 160 #define VA_MACRO_MCLK_FREQ 9600000 161 #define VA_MACRO_TX_PATH_OFFSET 0x80 162 #define VA_MACRO_SWR_MIC_MUX_SEL_MASK 0xF 163 #define VA_MACRO_ADC_MUX_CFG_OFFSET 0x8 164 165 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 166 167 enum { 168 VA_MACRO_AIF_INVALID = 0, 169 VA_MACRO_AIF1_CAP, 170 VA_MACRO_AIF2_CAP, 171 VA_MACRO_AIF3_CAP, 172 VA_MACRO_MAX_DAIS, 173 }; 174 175 enum { 176 VA_MACRO_DEC0, 177 VA_MACRO_DEC1, 178 VA_MACRO_DEC2, 179 VA_MACRO_DEC3, 180 VA_MACRO_DEC4, 181 VA_MACRO_DEC5, 182 VA_MACRO_DEC6, 183 VA_MACRO_DEC7, 184 VA_MACRO_DEC_MAX, 185 }; 186 187 enum { 188 VA_MACRO_CLK_DIV_2, 189 VA_MACRO_CLK_DIV_3, 190 VA_MACRO_CLK_DIV_4, 191 VA_MACRO_CLK_DIV_6, 192 VA_MACRO_CLK_DIV_8, 193 VA_MACRO_CLK_DIV_16, 194 }; 195 196 #define VA_NUM_CLKS_MAX 3 197 198 struct va_macro { 199 struct device *dev; 200 unsigned long active_ch_mask[VA_MACRO_MAX_DAIS]; 201 unsigned long active_ch_cnt[VA_MACRO_MAX_DAIS]; 202 u16 dmic_clk_div; 203 bool has_swr_master; 204 205 int dec_mode[VA_MACRO_NUM_DECIMATORS]; 206 struct regmap *regmap; 207 struct clk *mclk; 208 struct clk *macro; 209 struct clk *dcodec; 210 struct clk *fsgen; 211 struct clk_hw hw; 212 struct lpass_macro *pds; 213 214 s32 dmic_0_1_clk_cnt; 215 s32 dmic_2_3_clk_cnt; 216 s32 dmic_4_5_clk_cnt; 217 s32 dmic_6_7_clk_cnt; 218 u8 dmic_0_1_clk_div; 219 u8 dmic_2_3_clk_div; 220 u8 dmic_4_5_clk_div; 221 u8 dmic_6_7_clk_div; 222 }; 223 224 #define to_va_macro(_hw) container_of(_hw, struct va_macro, hw) 225 226 struct va_macro_data { 227 bool has_swr_master; 228 }; 229 230 static const struct va_macro_data sm8250_va_data = { 231 .has_swr_master = false, 232 }; 233 234 static const struct va_macro_data sm8450_va_data = { 235 .has_swr_master = true, 236 }; 237 238 static bool va_is_volatile_register(struct device *dev, unsigned int reg) 239 { 240 switch (reg) { 241 case CDC_VA_TOP_CSR_CORE_ID_0: 242 case CDC_VA_TOP_CSR_CORE_ID_1: 243 case CDC_VA_TOP_CSR_CORE_ID_2: 244 case CDC_VA_TOP_CSR_CORE_ID_3: 245 case CDC_VA_TOP_CSR_DMIC0_CTL: 246 case CDC_VA_TOP_CSR_DMIC1_CTL: 247 case CDC_VA_TOP_CSR_DMIC2_CTL: 248 case CDC_VA_TOP_CSR_DMIC3_CTL: 249 return true; 250 } 251 return false; 252 } 253 254 static const struct reg_default va_defaults[] = { 255 /* VA macro */ 256 { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, 257 { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, 258 { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 259 { CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, 260 { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, 261 { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, 262 { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00}, 263 { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00}, 264 { CDC_VA_TOP_CSR_DMIC_CFG, 0x80}, 265 { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00}, 266 { CDC_VA_TOP_CSR_DEBUG_EN, 0x00}, 267 { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C}, 268 { CDC_VA_TOP_CSR_I2S_CLK, 0x00}, 269 { CDC_VA_TOP_CSR_I2S_RESET, 0x00}, 270 { CDC_VA_TOP_CSR_CORE_ID_0, 0x00}, 271 { CDC_VA_TOP_CSR_CORE_ID_1, 0x00}, 272 { CDC_VA_TOP_CSR_CORE_ID_2, 0x00}, 273 { CDC_VA_TOP_CSR_CORE_ID_3, 0x00}, 274 { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE}, 275 { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE}, 276 { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE}, 277 { CDC_VA_TOP_CSR_SWR_CTRL, 0x06}, 278 279 /* VA core */ 280 { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00}, 281 { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00}, 282 { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00}, 283 { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00}, 284 { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00}, 285 { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00}, 286 { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00}, 287 { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00}, 288 { CDC_VA_TX0_TX_PATH_CTL, 0x04}, 289 { CDC_VA_TX0_TX_PATH_CFG0, 0x10}, 290 { CDC_VA_TX0_TX_PATH_CFG1, 0x0B}, 291 { CDC_VA_TX0_TX_VOL_CTL, 0x00}, 292 { CDC_VA_TX0_TX_PATH_SEC0, 0x00}, 293 { CDC_VA_TX0_TX_PATH_SEC1, 0x00}, 294 { CDC_VA_TX0_TX_PATH_SEC2, 0x01}, 295 { CDC_VA_TX0_TX_PATH_SEC3, 0x3C}, 296 { CDC_VA_TX0_TX_PATH_SEC4, 0x20}, 297 { CDC_VA_TX0_TX_PATH_SEC5, 0x00}, 298 { CDC_VA_TX0_TX_PATH_SEC6, 0x00}, 299 { CDC_VA_TX0_TX_PATH_SEC7, 0x25}, 300 { CDC_VA_TX1_TX_PATH_CTL, 0x04}, 301 { CDC_VA_TX1_TX_PATH_CFG0, 0x10}, 302 { CDC_VA_TX1_TX_PATH_CFG1, 0x0B}, 303 { CDC_VA_TX1_TX_VOL_CTL, 0x00}, 304 { CDC_VA_TX1_TX_PATH_SEC0, 0x00}, 305 { CDC_VA_TX1_TX_PATH_SEC1, 0x00}, 306 { CDC_VA_TX1_TX_PATH_SEC2, 0x01}, 307 { CDC_VA_TX1_TX_PATH_SEC3, 0x3C}, 308 { CDC_VA_TX1_TX_PATH_SEC4, 0x20}, 309 { CDC_VA_TX1_TX_PATH_SEC5, 0x00}, 310 { CDC_VA_TX1_TX_PATH_SEC6, 0x00}, 311 { CDC_VA_TX2_TX_PATH_CTL, 0x04}, 312 { CDC_VA_TX2_TX_PATH_CFG0, 0x10}, 313 { CDC_VA_TX2_TX_PATH_CFG1, 0x0B}, 314 { CDC_VA_TX2_TX_VOL_CTL, 0x00}, 315 { CDC_VA_TX2_TX_PATH_SEC0, 0x00}, 316 { CDC_VA_TX2_TX_PATH_SEC1, 0x00}, 317 { CDC_VA_TX2_TX_PATH_SEC2, 0x01}, 318 { CDC_VA_TX2_TX_PATH_SEC3, 0x3C}, 319 { CDC_VA_TX2_TX_PATH_SEC4, 0x20}, 320 { CDC_VA_TX2_TX_PATH_SEC5, 0x00}, 321 { CDC_VA_TX2_TX_PATH_SEC6, 0x00}, 322 { CDC_VA_TX3_TX_PATH_CTL, 0x04}, 323 { CDC_VA_TX3_TX_PATH_CFG0, 0x10}, 324 { CDC_VA_TX3_TX_PATH_CFG1, 0x0B}, 325 { CDC_VA_TX3_TX_VOL_CTL, 0x00}, 326 { CDC_VA_TX3_TX_PATH_SEC0, 0x00}, 327 { CDC_VA_TX3_TX_PATH_SEC1, 0x00}, 328 { CDC_VA_TX3_TX_PATH_SEC2, 0x01}, 329 { CDC_VA_TX3_TX_PATH_SEC3, 0x3C}, 330 { CDC_VA_TX3_TX_PATH_SEC4, 0x20}, 331 { CDC_VA_TX3_TX_PATH_SEC5, 0x00}, 332 { CDC_VA_TX3_TX_PATH_SEC6, 0x00}, 333 }; 334 335 static bool va_is_rw_register(struct device *dev, unsigned int reg) 336 { 337 switch (reg) { 338 case CDC_VA_CLK_RST_CTRL_MCLK_CONTROL: 339 case CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL: 340 case CDC_VA_CLK_RST_CTRL_SWR_CONTROL: 341 case CDC_VA_TOP_CSR_TOP_CFG0: 342 case CDC_VA_TOP_CSR_DMIC0_CTL: 343 case CDC_VA_TOP_CSR_DMIC1_CTL: 344 case CDC_VA_TOP_CSR_DMIC2_CTL: 345 case CDC_VA_TOP_CSR_DMIC3_CTL: 346 case CDC_VA_TOP_CSR_DMIC_CFG: 347 case CDC_VA_TOP_CSR_SWR_MIC_CTL0: 348 case CDC_VA_TOP_CSR_SWR_MIC_CTL1: 349 case CDC_VA_TOP_CSR_SWR_MIC_CTL2: 350 case CDC_VA_TOP_CSR_DEBUG_BUS: 351 case CDC_VA_TOP_CSR_DEBUG_EN: 352 case CDC_VA_TOP_CSR_TX_I2S_CTL: 353 case CDC_VA_TOP_CSR_I2S_CLK: 354 case CDC_VA_TOP_CSR_I2S_RESET: 355 case CDC_VA_INP_MUX_ADC_MUX0_CFG0: 356 case CDC_VA_INP_MUX_ADC_MUX0_CFG1: 357 case CDC_VA_INP_MUX_ADC_MUX1_CFG0: 358 case CDC_VA_INP_MUX_ADC_MUX1_CFG1: 359 case CDC_VA_INP_MUX_ADC_MUX2_CFG0: 360 case CDC_VA_INP_MUX_ADC_MUX2_CFG1: 361 case CDC_VA_INP_MUX_ADC_MUX3_CFG0: 362 case CDC_VA_INP_MUX_ADC_MUX3_CFG1: 363 case CDC_VA_TX0_TX_PATH_CTL: 364 case CDC_VA_TX0_TX_PATH_CFG0: 365 case CDC_VA_TX0_TX_PATH_CFG1: 366 case CDC_VA_TX0_TX_VOL_CTL: 367 case CDC_VA_TX0_TX_PATH_SEC0: 368 case CDC_VA_TX0_TX_PATH_SEC1: 369 case CDC_VA_TX0_TX_PATH_SEC2: 370 case CDC_VA_TX0_TX_PATH_SEC3: 371 case CDC_VA_TX0_TX_PATH_SEC4: 372 case CDC_VA_TX0_TX_PATH_SEC5: 373 case CDC_VA_TX0_TX_PATH_SEC6: 374 case CDC_VA_TX0_TX_PATH_SEC7: 375 case CDC_VA_TX1_TX_PATH_CTL: 376 case CDC_VA_TX1_TX_PATH_CFG0: 377 case CDC_VA_TX1_TX_PATH_CFG1: 378 case CDC_VA_TX1_TX_VOL_CTL: 379 case CDC_VA_TX1_TX_PATH_SEC0: 380 case CDC_VA_TX1_TX_PATH_SEC1: 381 case CDC_VA_TX1_TX_PATH_SEC2: 382 case CDC_VA_TX1_TX_PATH_SEC3: 383 case CDC_VA_TX1_TX_PATH_SEC4: 384 case CDC_VA_TX1_TX_PATH_SEC5: 385 case CDC_VA_TX1_TX_PATH_SEC6: 386 case CDC_VA_TX2_TX_PATH_CTL: 387 case CDC_VA_TX2_TX_PATH_CFG0: 388 case CDC_VA_TX2_TX_PATH_CFG1: 389 case CDC_VA_TX2_TX_VOL_CTL: 390 case CDC_VA_TX2_TX_PATH_SEC0: 391 case CDC_VA_TX2_TX_PATH_SEC1: 392 case CDC_VA_TX2_TX_PATH_SEC2: 393 case CDC_VA_TX2_TX_PATH_SEC3: 394 case CDC_VA_TX2_TX_PATH_SEC4: 395 case CDC_VA_TX2_TX_PATH_SEC5: 396 case CDC_VA_TX2_TX_PATH_SEC6: 397 case CDC_VA_TX3_TX_PATH_CTL: 398 case CDC_VA_TX3_TX_PATH_CFG0: 399 case CDC_VA_TX3_TX_PATH_CFG1: 400 case CDC_VA_TX3_TX_VOL_CTL: 401 case CDC_VA_TX3_TX_PATH_SEC0: 402 case CDC_VA_TX3_TX_PATH_SEC1: 403 case CDC_VA_TX3_TX_PATH_SEC2: 404 case CDC_VA_TX3_TX_PATH_SEC3: 405 case CDC_VA_TX3_TX_PATH_SEC4: 406 case CDC_VA_TX3_TX_PATH_SEC5: 407 case CDC_VA_TX3_TX_PATH_SEC6: 408 return true; 409 } 410 411 return false; 412 } 413 414 static bool va_is_readable_register(struct device *dev, unsigned int reg) 415 { 416 switch (reg) { 417 case CDC_VA_TOP_CSR_CORE_ID_0: 418 case CDC_VA_TOP_CSR_CORE_ID_1: 419 case CDC_VA_TOP_CSR_CORE_ID_2: 420 case CDC_VA_TOP_CSR_CORE_ID_3: 421 return true; 422 } 423 424 return va_is_rw_register(dev, reg); 425 } 426 427 static const struct regmap_config va_regmap_config = { 428 .name = "va_macro", 429 .reg_bits = 32, 430 .val_bits = 32, 431 .reg_stride = 4, 432 .cache_type = REGCACHE_FLAT, 433 .reg_defaults = va_defaults, 434 .num_reg_defaults = ARRAY_SIZE(va_defaults), 435 .max_register = VA_MAX_OFFSET, 436 .volatile_reg = va_is_volatile_register, 437 .readable_reg = va_is_readable_register, 438 .writeable_reg = va_is_rw_register, 439 }; 440 441 static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable) 442 { 443 struct regmap *regmap = va->regmap; 444 445 if (enable) { 446 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 447 CDC_VA_MCLK_CONTROL_EN, 448 CDC_VA_MCLK_CONTROL_EN); 449 /* clear the fs counter */ 450 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 451 CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR, 452 CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR); 453 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 454 CDC_VA_FS_CONTROL_EN | CDC_VA_FS_COUNTER_CLR, 455 CDC_VA_FS_CONTROL_EN); 456 457 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0, 458 CDC_VA_FS_BROADCAST_EN, 459 CDC_VA_FS_BROADCAST_EN); 460 } else { 461 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 462 CDC_VA_MCLK_CONTROL_EN, 0x0); 463 464 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 465 CDC_VA_FS_CONTROL_EN, 0x0); 466 467 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0, 468 CDC_VA_FS_BROADCAST_EN, 0x0); 469 } 470 471 return 0; 472 } 473 474 static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable) 475 { 476 struct regmap *regmap = va->regmap; 477 478 if (mclk_enable) { 479 va_clk_rsc_fs_gen_request(va, true); 480 regcache_mark_dirty(regmap); 481 regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET); 482 } else { 483 va_clk_rsc_fs_gen_request(va, false); 484 } 485 486 return 0; 487 } 488 489 static int va_macro_mclk_event(struct snd_soc_dapm_widget *w, 490 struct snd_kcontrol *kcontrol, int event) 491 { 492 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 493 struct va_macro *va = snd_soc_component_get_drvdata(comp); 494 495 switch (event) { 496 case SND_SOC_DAPM_PRE_PMU: 497 return clk_prepare_enable(va->fsgen); 498 case SND_SOC_DAPM_POST_PMD: 499 clk_disable_unprepare(va->fsgen); 500 } 501 502 return 0; 503 } 504 505 static int va_macro_put_dec_enum(struct snd_kcontrol *kcontrol, 506 struct snd_ctl_elem_value *ucontrol) 507 { 508 struct snd_soc_dapm_widget *widget = 509 snd_soc_dapm_kcontrol_widget(kcontrol); 510 struct snd_soc_component *component = 511 snd_soc_dapm_to_component(widget->dapm); 512 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 513 unsigned int val; 514 u16 mic_sel_reg; 515 516 val = ucontrol->value.enumerated.item[0]; 517 518 switch (e->reg) { 519 case CDC_VA_INP_MUX_ADC_MUX0_CFG0: 520 mic_sel_reg = CDC_VA_TX0_TX_PATH_CFG0; 521 break; 522 case CDC_VA_INP_MUX_ADC_MUX1_CFG0: 523 mic_sel_reg = CDC_VA_TX1_TX_PATH_CFG0; 524 break; 525 case CDC_VA_INP_MUX_ADC_MUX2_CFG0: 526 mic_sel_reg = CDC_VA_TX2_TX_PATH_CFG0; 527 break; 528 case CDC_VA_INP_MUX_ADC_MUX3_CFG0: 529 mic_sel_reg = CDC_VA_TX3_TX_PATH_CFG0; 530 break; 531 default: 532 dev_err(component->dev, "%s: e->reg: 0x%x not expected\n", 533 __func__, e->reg); 534 return -EINVAL; 535 } 536 537 if (val != 0) 538 snd_soc_component_update_bits(component, mic_sel_reg, 539 CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK, 540 CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC); 541 542 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 543 } 544 545 static int va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol, 546 struct snd_ctl_elem_value *ucontrol) 547 { 548 struct snd_soc_dapm_widget *widget = 549 snd_soc_dapm_kcontrol_widget(kcontrol); 550 struct snd_soc_component *component = 551 snd_soc_dapm_to_component(widget->dapm); 552 struct soc_mixer_control *mc = 553 (struct soc_mixer_control *)kcontrol->private_value; 554 u32 dai_id = widget->shift; 555 u32 dec_id = mc->shift; 556 struct va_macro *va = snd_soc_component_get_drvdata(component); 557 558 if (test_bit(dec_id, &va->active_ch_mask[dai_id])) 559 ucontrol->value.integer.value[0] = 1; 560 else 561 ucontrol->value.integer.value[0] = 0; 562 563 return 0; 564 } 565 566 static int va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol, 567 struct snd_ctl_elem_value *ucontrol) 568 { 569 struct snd_soc_dapm_widget *widget = 570 snd_soc_dapm_kcontrol_widget(kcontrol); 571 struct snd_soc_component *component = 572 snd_soc_dapm_to_component(widget->dapm); 573 struct snd_soc_dapm_update *update = NULL; 574 struct soc_mixer_control *mc = 575 (struct soc_mixer_control *)kcontrol->private_value; 576 u32 dai_id = widget->shift; 577 u32 dec_id = mc->shift; 578 u32 enable = ucontrol->value.integer.value[0]; 579 struct va_macro *va = snd_soc_component_get_drvdata(component); 580 581 if (enable) { 582 set_bit(dec_id, &va->active_ch_mask[dai_id]); 583 va->active_ch_cnt[dai_id]++; 584 } else { 585 clear_bit(dec_id, &va->active_ch_mask[dai_id]); 586 va->active_ch_cnt[dai_id]--; 587 } 588 589 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); 590 591 return 0; 592 } 593 594 static int va_dmic_clk_enable(struct snd_soc_component *component, 595 u32 dmic, bool enable) 596 { 597 struct va_macro *va = snd_soc_component_get_drvdata(component); 598 u16 dmic_clk_reg; 599 s32 *dmic_clk_cnt; 600 u8 *dmic_clk_div; 601 u8 freq_change_mask; 602 u8 clk_div; 603 604 switch (dmic) { 605 case 0: 606 case 1: 607 dmic_clk_cnt = &(va->dmic_0_1_clk_cnt); 608 dmic_clk_div = &(va->dmic_0_1_clk_div); 609 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC0_CTL; 610 freq_change_mask = CDC_VA_DMIC0_FREQ_CHANGE_MASK; 611 break; 612 case 2: 613 case 3: 614 dmic_clk_cnt = &(va->dmic_2_3_clk_cnt); 615 dmic_clk_div = &(va->dmic_2_3_clk_div); 616 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC1_CTL; 617 freq_change_mask = CDC_VA_DMIC1_FREQ_CHANGE_MASK; 618 break; 619 case 4: 620 case 5: 621 dmic_clk_cnt = &(va->dmic_4_5_clk_cnt); 622 dmic_clk_div = &(va->dmic_4_5_clk_div); 623 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC2_CTL; 624 freq_change_mask = CDC_VA_DMIC2_FREQ_CHANGE_MASK; 625 break; 626 case 6: 627 case 7: 628 dmic_clk_cnt = &(va->dmic_6_7_clk_cnt); 629 dmic_clk_div = &(va->dmic_6_7_clk_div); 630 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC3_CTL; 631 freq_change_mask = CDC_VA_DMIC3_FREQ_CHANGE_MASK; 632 break; 633 default: 634 dev_err(component->dev, "%s: Invalid DMIC Selection\n", 635 __func__); 636 return -EINVAL; 637 } 638 639 if (enable) { 640 clk_div = va->dmic_clk_div; 641 (*dmic_clk_cnt)++; 642 if (*dmic_clk_cnt == 1) { 643 snd_soc_component_update_bits(component, 644 CDC_VA_TOP_CSR_DMIC_CFG, 645 CDC_VA_RESET_ALL_DMICS_MASK, 646 CDC_VA_RESET_ALL_DMICS_DISABLE); 647 snd_soc_component_update_bits(component, dmic_clk_reg, 648 CDC_VA_DMIC_CLK_SEL_MASK, 649 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 650 snd_soc_component_update_bits(component, dmic_clk_reg, 651 CDC_VA_DMIC_EN_MASK, 652 CDC_VA_DMIC_ENABLE); 653 } else { 654 if (*dmic_clk_div > clk_div) { 655 snd_soc_component_update_bits(component, 656 CDC_VA_TOP_CSR_DMIC_CFG, 657 freq_change_mask, 658 freq_change_mask); 659 snd_soc_component_update_bits(component, dmic_clk_reg, 660 CDC_VA_DMIC_CLK_SEL_MASK, 661 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 662 snd_soc_component_update_bits(component, 663 CDC_VA_TOP_CSR_DMIC_CFG, 664 freq_change_mask, 665 CDC_VA_DMIC_FREQ_CHANGE_DISABLE); 666 } else { 667 clk_div = *dmic_clk_div; 668 } 669 } 670 *dmic_clk_div = clk_div; 671 } else { 672 (*dmic_clk_cnt)--; 673 if (*dmic_clk_cnt == 0) { 674 snd_soc_component_update_bits(component, dmic_clk_reg, 675 CDC_VA_DMIC_EN_MASK, 0); 676 clk_div = 0; 677 snd_soc_component_update_bits(component, dmic_clk_reg, 678 CDC_VA_DMIC_CLK_SEL_MASK, 679 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 680 } else { 681 clk_div = va->dmic_clk_div; 682 if (*dmic_clk_div > clk_div) { 683 clk_div = va->dmic_clk_div; 684 snd_soc_component_update_bits(component, 685 CDC_VA_TOP_CSR_DMIC_CFG, 686 freq_change_mask, 687 freq_change_mask); 688 snd_soc_component_update_bits(component, dmic_clk_reg, 689 CDC_VA_DMIC_CLK_SEL_MASK, 690 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 691 snd_soc_component_update_bits(component, 692 CDC_VA_TOP_CSR_DMIC_CFG, 693 freq_change_mask, 694 CDC_VA_DMIC_FREQ_CHANGE_DISABLE); 695 } else { 696 clk_div = *dmic_clk_div; 697 } 698 } 699 *dmic_clk_div = clk_div; 700 } 701 702 return 0; 703 } 704 705 static int va_macro_enable_dmic(struct snd_soc_dapm_widget *w, 706 struct snd_kcontrol *kcontrol, int event) 707 { 708 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 709 unsigned int dmic = w->shift; 710 711 switch (event) { 712 case SND_SOC_DAPM_PRE_PMU: 713 va_dmic_clk_enable(comp, dmic, true); 714 break; 715 case SND_SOC_DAPM_POST_PMD: 716 va_dmic_clk_enable(comp, dmic, false); 717 break; 718 } 719 720 return 0; 721 } 722 723 static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 724 struct snd_kcontrol *kcontrol, int event) 725 { 726 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 727 unsigned int decimator; 728 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg; 729 u16 tx_gain_ctl_reg; 730 u8 hpf_cut_off_freq; 731 732 struct va_macro *va = snd_soc_component_get_drvdata(comp); 733 734 decimator = w->shift; 735 736 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL + 737 VA_MACRO_TX_PATH_OFFSET * decimator; 738 hpf_gate_reg = CDC_VA_TX0_TX_PATH_SEC2 + 739 VA_MACRO_TX_PATH_OFFSET * decimator; 740 dec_cfg_reg = CDC_VA_TX0_TX_PATH_CFG0 + 741 VA_MACRO_TX_PATH_OFFSET * decimator; 742 tx_gain_ctl_reg = CDC_VA_TX0_TX_VOL_CTL + 743 VA_MACRO_TX_PATH_OFFSET * decimator; 744 745 switch (event) { 746 case SND_SOC_DAPM_PRE_PMU: 747 snd_soc_component_update_bits(comp, 748 dec_cfg_reg, CDC_VA_ADC_MODE_MASK, 749 va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT); 750 /* Enable TX PGA Mute */ 751 break; 752 case SND_SOC_DAPM_POST_PMU: 753 /* Enable TX CLK */ 754 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 755 CDC_VA_TX_PATH_CLK_EN_MASK, 756 CDC_VA_TX_PATH_CLK_EN); 757 snd_soc_component_update_bits(comp, hpf_gate_reg, 758 CDC_VA_TX_HPF_ZERO_GATE_MASK, 759 CDC_VA_TX_HPF_ZERO_GATE); 760 761 usleep_range(1000, 1010); 762 hpf_cut_off_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 763 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 764 765 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) { 766 snd_soc_component_update_bits(comp, dec_cfg_reg, 767 TX_HPF_CUT_OFF_FREQ_MASK, 768 CF_MIN_3DB_150HZ << 5); 769 770 snd_soc_component_update_bits(comp, hpf_gate_reg, 771 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK, 772 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ); 773 774 /* 775 * Minimum 1 clk cycle delay is required as per HW spec 776 */ 777 usleep_range(1000, 1010); 778 779 snd_soc_component_update_bits(comp, 780 hpf_gate_reg, 781 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK, 782 0x0); 783 } 784 785 786 usleep_range(1000, 1010); 787 snd_soc_component_update_bits(comp, hpf_gate_reg, 788 CDC_VA_TX_HPF_ZERO_GATE_MASK, 789 CDC_VA_TX_HPF_ZERO_NO_GATE); 790 /* 791 * 6ms delay is required as per HW spec 792 */ 793 usleep_range(6000, 6010); 794 /* apply gain after decimator is enabled */ 795 snd_soc_component_write(comp, tx_gain_ctl_reg, 796 snd_soc_component_read(comp, tx_gain_ctl_reg)); 797 break; 798 case SND_SOC_DAPM_POST_PMD: 799 /* Disable TX CLK */ 800 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 801 CDC_VA_TX_PATH_CLK_EN_MASK, 802 CDC_VA_TX_PATH_CLK_DISABLE); 803 break; 804 } 805 return 0; 806 } 807 808 static int va_macro_dec_mode_get(struct snd_kcontrol *kcontrol, 809 struct snd_ctl_elem_value *ucontrol) 810 { 811 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 812 struct va_macro *va = snd_soc_component_get_drvdata(comp); 813 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 814 int path = e->shift_l; 815 816 ucontrol->value.enumerated.item[0] = va->dec_mode[path]; 817 818 return 0; 819 } 820 821 static int va_macro_dec_mode_put(struct snd_kcontrol *kcontrol, 822 struct snd_ctl_elem_value *ucontrol) 823 { 824 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 825 int value = ucontrol->value.enumerated.item[0]; 826 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 827 int path = e->shift_l; 828 struct va_macro *va = snd_soc_component_get_drvdata(comp); 829 830 va->dec_mode[path] = value; 831 832 return 0; 833 } 834 835 static int va_macro_hw_params(struct snd_pcm_substream *substream, 836 struct snd_pcm_hw_params *params, 837 struct snd_soc_dai *dai) 838 { 839 int tx_fs_rate; 840 struct snd_soc_component *component = dai->component; 841 u32 decimator, sample_rate; 842 u16 tx_fs_reg; 843 struct device *va_dev = component->dev; 844 struct va_macro *va = snd_soc_component_get_drvdata(component); 845 846 sample_rate = params_rate(params); 847 switch (sample_rate) { 848 case 8000: 849 tx_fs_rate = 0; 850 break; 851 case 16000: 852 tx_fs_rate = 1; 853 break; 854 case 32000: 855 tx_fs_rate = 3; 856 break; 857 case 48000: 858 tx_fs_rate = 4; 859 break; 860 case 96000: 861 tx_fs_rate = 5; 862 break; 863 case 192000: 864 tx_fs_rate = 6; 865 break; 866 case 384000: 867 tx_fs_rate = 7; 868 break; 869 default: 870 dev_err(va_dev, "%s: Invalid TX sample rate: %d\n", 871 __func__, params_rate(params)); 872 return -EINVAL; 873 } 874 875 for_each_set_bit(decimator, &va->active_ch_mask[dai->id], 876 VA_MACRO_DEC_MAX) { 877 tx_fs_reg = CDC_VA_TX0_TX_PATH_CTL + 878 VA_MACRO_TX_PATH_OFFSET * decimator; 879 snd_soc_component_update_bits(component, tx_fs_reg, 0x0F, 880 tx_fs_rate); 881 } 882 return 0; 883 } 884 885 static int va_macro_get_channel_map(struct snd_soc_dai *dai, 886 unsigned int *tx_num, unsigned int *tx_slot, 887 unsigned int *rx_num, unsigned int *rx_slot) 888 { 889 struct snd_soc_component *component = dai->component; 890 struct device *va_dev = component->dev; 891 struct va_macro *va = snd_soc_component_get_drvdata(component); 892 893 switch (dai->id) { 894 case VA_MACRO_AIF1_CAP: 895 case VA_MACRO_AIF2_CAP: 896 case VA_MACRO_AIF3_CAP: 897 *tx_slot = va->active_ch_mask[dai->id]; 898 *tx_num = va->active_ch_cnt[dai->id]; 899 break; 900 default: 901 dev_err(va_dev, "%s: Invalid AIF\n", __func__); 902 break; 903 } 904 return 0; 905 } 906 907 static int va_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 908 { 909 struct snd_soc_component *component = dai->component; 910 struct va_macro *va = snd_soc_component_get_drvdata(component); 911 u16 tx_vol_ctl_reg, decimator; 912 913 for_each_set_bit(decimator, &va->active_ch_mask[dai->id], 914 VA_MACRO_DEC_MAX) { 915 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL + 916 VA_MACRO_TX_PATH_OFFSET * decimator; 917 if (mute) 918 snd_soc_component_update_bits(component, tx_vol_ctl_reg, 919 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK, 920 CDC_VA_TX_PATH_PGA_MUTE_EN); 921 else 922 snd_soc_component_update_bits(component, tx_vol_ctl_reg, 923 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK, 924 CDC_VA_TX_PATH_PGA_MUTE_DISABLE); 925 } 926 927 return 0; 928 } 929 930 static const struct snd_soc_dai_ops va_macro_dai_ops = { 931 .hw_params = va_macro_hw_params, 932 .get_channel_map = va_macro_get_channel_map, 933 .mute_stream = va_macro_digital_mute, 934 }; 935 936 static struct snd_soc_dai_driver va_macro_dais[] = { 937 { 938 .name = "va_macro_tx1", 939 .id = VA_MACRO_AIF1_CAP, 940 .capture = { 941 .stream_name = "VA_AIF1 Capture", 942 .rates = VA_MACRO_RATES, 943 .formats = VA_MACRO_FORMATS, 944 .rate_max = 192000, 945 .rate_min = 8000, 946 .channels_min = 1, 947 .channels_max = 8, 948 }, 949 .ops = &va_macro_dai_ops, 950 }, 951 { 952 .name = "va_macro_tx2", 953 .id = VA_MACRO_AIF2_CAP, 954 .capture = { 955 .stream_name = "VA_AIF2 Capture", 956 .rates = VA_MACRO_RATES, 957 .formats = VA_MACRO_FORMATS, 958 .rate_max = 192000, 959 .rate_min = 8000, 960 .channels_min = 1, 961 .channels_max = 8, 962 }, 963 .ops = &va_macro_dai_ops, 964 }, 965 { 966 .name = "va_macro_tx3", 967 .id = VA_MACRO_AIF3_CAP, 968 .capture = { 969 .stream_name = "VA_AIF3 Capture", 970 .rates = VA_MACRO_RATES, 971 .formats = VA_MACRO_FORMATS, 972 .rate_max = 192000, 973 .rate_min = 8000, 974 .channels_min = 1, 975 .channels_max = 8, 976 }, 977 .ops = &va_macro_dai_ops, 978 }, 979 }; 980 981 static const char * const adc_mux_text[] = { 982 "VA_DMIC", "SWR_MIC" 983 }; 984 985 static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG1, 986 0, adc_mux_text); 987 static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG1, 988 0, adc_mux_text); 989 static SOC_ENUM_SINGLE_DECL(va_dec2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG1, 990 0, adc_mux_text); 991 static SOC_ENUM_SINGLE_DECL(va_dec3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG1, 992 0, adc_mux_text); 993 994 static const struct snd_kcontrol_new va_dec0_mux = SOC_DAPM_ENUM("va_dec0", 995 va_dec0_enum); 996 static const struct snd_kcontrol_new va_dec1_mux = SOC_DAPM_ENUM("va_dec1", 997 va_dec1_enum); 998 static const struct snd_kcontrol_new va_dec2_mux = SOC_DAPM_ENUM("va_dec2", 999 va_dec2_enum); 1000 static const struct snd_kcontrol_new va_dec3_mux = SOC_DAPM_ENUM("va_dec3", 1001 va_dec3_enum); 1002 1003 static const char * const dmic_mux_text[] = { 1004 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", 1005 "DMIC4", "DMIC5", "DMIC6", "DMIC7" 1006 }; 1007 1008 static SOC_ENUM_SINGLE_DECL(va_dmic0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG0, 1009 4, dmic_mux_text); 1010 1011 static SOC_ENUM_SINGLE_DECL(va_dmic1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG0, 1012 4, dmic_mux_text); 1013 1014 static SOC_ENUM_SINGLE_DECL(va_dmic2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG0, 1015 4, dmic_mux_text); 1016 1017 static SOC_ENUM_SINGLE_DECL(va_dmic3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG0, 1018 4, dmic_mux_text); 1019 1020 static const struct snd_kcontrol_new va_dmic0_mux = SOC_DAPM_ENUM_EXT("va_dmic0", 1021 va_dmic0_enum, snd_soc_dapm_get_enum_double, 1022 va_macro_put_dec_enum); 1023 1024 static const struct snd_kcontrol_new va_dmic1_mux = SOC_DAPM_ENUM_EXT("va_dmic1", 1025 va_dmic1_enum, snd_soc_dapm_get_enum_double, 1026 va_macro_put_dec_enum); 1027 1028 static const struct snd_kcontrol_new va_dmic2_mux = SOC_DAPM_ENUM_EXT("va_dmic2", 1029 va_dmic2_enum, snd_soc_dapm_get_enum_double, 1030 va_macro_put_dec_enum); 1031 1032 static const struct snd_kcontrol_new va_dmic3_mux = SOC_DAPM_ENUM_EXT("va_dmic3", 1033 va_dmic3_enum, snd_soc_dapm_get_enum_double, 1034 va_macro_put_dec_enum); 1035 1036 static const struct snd_kcontrol_new va_aif1_cap_mixer[] = { 1037 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0, 1038 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1039 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0, 1040 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1041 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0, 1042 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1043 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0, 1044 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1045 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0, 1046 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1047 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0, 1048 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1049 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0, 1050 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1051 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0, 1052 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1053 }; 1054 1055 static const struct snd_kcontrol_new va_aif2_cap_mixer[] = { 1056 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0, 1057 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1058 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0, 1059 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1060 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0, 1061 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1062 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0, 1063 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1064 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0, 1065 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1066 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0, 1067 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1068 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0, 1069 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1070 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0, 1071 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1072 }; 1073 1074 static const struct snd_kcontrol_new va_aif3_cap_mixer[] = { 1075 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0, 1076 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1077 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0, 1078 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1079 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0, 1080 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1081 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0, 1082 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1083 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0, 1084 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1085 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0, 1086 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1087 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0, 1088 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1089 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0, 1090 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1091 }; 1092 1093 static const struct snd_soc_dapm_widget va_macro_dapm_widgets[] = { 1094 SND_SOC_DAPM_AIF_OUT("VA_AIF1 CAP", "VA_AIF1 Capture", 0, 1095 SND_SOC_NOPM, VA_MACRO_AIF1_CAP, 0), 1096 1097 SND_SOC_DAPM_AIF_OUT("VA_AIF2 CAP", "VA_AIF2 Capture", 0, 1098 SND_SOC_NOPM, VA_MACRO_AIF2_CAP, 0), 1099 1100 SND_SOC_DAPM_AIF_OUT("VA_AIF3 CAP", "VA_AIF3 Capture", 0, 1101 SND_SOC_NOPM, VA_MACRO_AIF3_CAP, 0), 1102 1103 SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM, 1104 VA_MACRO_AIF1_CAP, 0, 1105 va_aif1_cap_mixer, ARRAY_SIZE(va_aif1_cap_mixer)), 1106 1107 SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM, 1108 VA_MACRO_AIF2_CAP, 0, 1109 va_aif2_cap_mixer, ARRAY_SIZE(va_aif2_cap_mixer)), 1110 1111 SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM, 1112 VA_MACRO_AIF3_CAP, 0, 1113 va_aif3_cap_mixer, ARRAY_SIZE(va_aif3_cap_mixer)), 1114 1115 SND_SOC_DAPM_MUX("VA DMIC MUX0", SND_SOC_NOPM, 0, 0, &va_dmic0_mux), 1116 SND_SOC_DAPM_MUX("VA DMIC MUX1", SND_SOC_NOPM, 0, 0, &va_dmic1_mux), 1117 SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux), 1118 SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux), 1119 1120 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0), 1121 SND_SOC_DAPM_INPUT("DMIC0 Pin"), 1122 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 1123 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 1124 SND_SOC_DAPM_INPUT("DMIC3 Pin"), 1125 SND_SOC_DAPM_INPUT("DMIC4 Pin"), 1126 SND_SOC_DAPM_INPUT("DMIC5 Pin"), 1127 SND_SOC_DAPM_INPUT("DMIC6 Pin"), 1128 SND_SOC_DAPM_INPUT("DMIC7 Pin"), 1129 1130 SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0, 1131 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1132 SND_SOC_DAPM_POST_PMD), 1133 1134 SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, SND_SOC_NOPM, 1, 0, 1135 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1136 SND_SOC_DAPM_POST_PMD), 1137 1138 SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, SND_SOC_NOPM, 2, 0, 1139 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1140 SND_SOC_DAPM_POST_PMD), 1141 1142 SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, SND_SOC_NOPM, 3, 0, 1143 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1144 SND_SOC_DAPM_POST_PMD), 1145 1146 SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, SND_SOC_NOPM, 4, 0, 1147 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1148 SND_SOC_DAPM_POST_PMD), 1149 1150 SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, SND_SOC_NOPM, 5, 0, 1151 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1152 SND_SOC_DAPM_POST_PMD), 1153 1154 SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, SND_SOC_NOPM, 6, 0, 1155 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1156 SND_SOC_DAPM_POST_PMD), 1157 1158 SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, SND_SOC_NOPM, 7, 0, 1159 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1160 SND_SOC_DAPM_POST_PMD), 1161 1162 SND_SOC_DAPM_INPUT("VA SWR_ADC0"), 1163 SND_SOC_DAPM_INPUT("VA SWR_ADC1"), 1164 SND_SOC_DAPM_INPUT("VA SWR_ADC2"), 1165 SND_SOC_DAPM_INPUT("VA SWR_ADC3"), 1166 SND_SOC_DAPM_INPUT("VA SWR_MIC0"), 1167 SND_SOC_DAPM_INPUT("VA SWR_MIC1"), 1168 SND_SOC_DAPM_INPUT("VA SWR_MIC2"), 1169 SND_SOC_DAPM_INPUT("VA SWR_MIC3"), 1170 SND_SOC_DAPM_INPUT("VA SWR_MIC4"), 1171 SND_SOC_DAPM_INPUT("VA SWR_MIC5"), 1172 SND_SOC_DAPM_INPUT("VA SWR_MIC6"), 1173 SND_SOC_DAPM_INPUT("VA SWR_MIC7"), 1174 1175 SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, VA_MACRO_DEC0, 0, 1176 &va_dec0_mux, va_macro_enable_dec, 1177 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1178 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1179 1180 SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, VA_MACRO_DEC1, 0, 1181 &va_dec1_mux, va_macro_enable_dec, 1182 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1183 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1184 1185 SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, VA_MACRO_DEC2, 0, 1186 &va_dec2_mux, va_macro_enable_dec, 1187 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1188 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1189 1190 SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, VA_MACRO_DEC3, 0, 1191 &va_dec3_mux, va_macro_enable_dec, 1192 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1193 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1194 1195 SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0, 1196 va_macro_mclk_event, 1197 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1198 }; 1199 1200 static const struct snd_soc_dapm_route va_audio_map[] = { 1201 {"VA_AIF1 CAP", NULL, "VA_MCLK"}, 1202 {"VA_AIF2 CAP", NULL, "VA_MCLK"}, 1203 {"VA_AIF3 CAP", NULL, "VA_MCLK"}, 1204 1205 {"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mixer"}, 1206 {"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mixer"}, 1207 {"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mixer"}, 1208 1209 {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"}, 1210 {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"}, 1211 {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"}, 1212 {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"}, 1213 1214 {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"}, 1215 {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"}, 1216 {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"}, 1217 {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"}, 1218 1219 {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"}, 1220 {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"}, 1221 {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"}, 1222 {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"}, 1223 1224 {"VA DEC0 MUX", "VA_DMIC", "VA DMIC MUX0"}, 1225 {"VA DMIC MUX0", "DMIC0", "VA DMIC0"}, 1226 {"VA DMIC MUX0", "DMIC1", "VA DMIC1"}, 1227 {"VA DMIC MUX0", "DMIC2", "VA DMIC2"}, 1228 {"VA DMIC MUX0", "DMIC3", "VA DMIC3"}, 1229 {"VA DMIC MUX0", "DMIC4", "VA DMIC4"}, 1230 {"VA DMIC MUX0", "DMIC5", "VA DMIC5"}, 1231 {"VA DMIC MUX0", "DMIC6", "VA DMIC6"}, 1232 {"VA DMIC MUX0", "DMIC7", "VA DMIC7"}, 1233 1234 {"VA DEC1 MUX", "VA_DMIC", "VA DMIC MUX1"}, 1235 {"VA DMIC MUX1", "DMIC0", "VA DMIC0"}, 1236 {"VA DMIC MUX1", "DMIC1", "VA DMIC1"}, 1237 {"VA DMIC MUX1", "DMIC2", "VA DMIC2"}, 1238 {"VA DMIC MUX1", "DMIC3", "VA DMIC3"}, 1239 {"VA DMIC MUX1", "DMIC4", "VA DMIC4"}, 1240 {"VA DMIC MUX1", "DMIC5", "VA DMIC5"}, 1241 {"VA DMIC MUX1", "DMIC6", "VA DMIC6"}, 1242 {"VA DMIC MUX1", "DMIC7", "VA DMIC7"}, 1243 1244 {"VA DEC2 MUX", "VA_DMIC", "VA DMIC MUX2"}, 1245 {"VA DMIC MUX2", "DMIC0", "VA DMIC0"}, 1246 {"VA DMIC MUX2", "DMIC1", "VA DMIC1"}, 1247 {"VA DMIC MUX2", "DMIC2", "VA DMIC2"}, 1248 {"VA DMIC MUX2", "DMIC3", "VA DMIC3"}, 1249 {"VA DMIC MUX2", "DMIC4", "VA DMIC4"}, 1250 {"VA DMIC MUX2", "DMIC5", "VA DMIC5"}, 1251 {"VA DMIC MUX2", "DMIC6", "VA DMIC6"}, 1252 {"VA DMIC MUX2", "DMIC7", "VA DMIC7"}, 1253 1254 {"VA DEC3 MUX", "VA_DMIC", "VA DMIC MUX3"}, 1255 {"VA DMIC MUX3", "DMIC0", "VA DMIC0"}, 1256 {"VA DMIC MUX3", "DMIC1", "VA DMIC1"}, 1257 {"VA DMIC MUX3", "DMIC2", "VA DMIC2"}, 1258 {"VA DMIC MUX3", "DMIC3", "VA DMIC3"}, 1259 {"VA DMIC MUX3", "DMIC4", "VA DMIC4"}, 1260 {"VA DMIC MUX3", "DMIC5", "VA DMIC5"}, 1261 {"VA DMIC MUX3", "DMIC6", "VA DMIC6"}, 1262 {"VA DMIC MUX3", "DMIC7", "VA DMIC7"}, 1263 1264 { "VA DMIC0", NULL, "DMIC0 Pin" }, 1265 { "VA DMIC1", NULL, "DMIC1 Pin" }, 1266 { "VA DMIC2", NULL, "DMIC2 Pin" }, 1267 { "VA DMIC3", NULL, "DMIC3 Pin" }, 1268 { "VA DMIC4", NULL, "DMIC4 Pin" }, 1269 { "VA DMIC5", NULL, "DMIC5 Pin" }, 1270 { "VA DMIC6", NULL, "DMIC6 Pin" }, 1271 { "VA DMIC7", NULL, "DMIC7 Pin" }, 1272 }; 1273 1274 static const char * const dec_mode_mux_text[] = { 1275 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF", 1276 }; 1277 1278 static const struct soc_enum dec_mode_mux_enum[] = { 1279 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text), 1280 dec_mode_mux_text), 1281 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text), 1282 dec_mode_mux_text), 1283 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text), 1284 dec_mode_mux_text), 1285 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text), 1286 dec_mode_mux_text), 1287 }; 1288 1289 static const struct snd_kcontrol_new va_macro_snd_controls[] = { 1290 SOC_SINGLE_S8_TLV("VA_DEC0 Volume", CDC_VA_TX0_TX_VOL_CTL, 1291 -84, 40, digital_gain), 1292 SOC_SINGLE_S8_TLV("VA_DEC1 Volume", CDC_VA_TX1_TX_VOL_CTL, 1293 -84, 40, digital_gain), 1294 SOC_SINGLE_S8_TLV("VA_DEC2 Volume", CDC_VA_TX2_TX_VOL_CTL, 1295 -84, 40, digital_gain), 1296 SOC_SINGLE_S8_TLV("VA_DEC3 Volume", CDC_VA_TX3_TX_VOL_CTL, 1297 -84, 40, digital_gain), 1298 1299 SOC_ENUM_EXT("VA_DEC0 MODE", dec_mode_mux_enum[0], 1300 va_macro_dec_mode_get, va_macro_dec_mode_put), 1301 SOC_ENUM_EXT("VA_DEC1 MODE", dec_mode_mux_enum[1], 1302 va_macro_dec_mode_get, va_macro_dec_mode_put), 1303 SOC_ENUM_EXT("VA_DEC2 MODE", dec_mode_mux_enum[2], 1304 va_macro_dec_mode_get, va_macro_dec_mode_put), 1305 SOC_ENUM_EXT("VA_DEC3 MODE", dec_mode_mux_enum[3], 1306 va_macro_dec_mode_get, va_macro_dec_mode_put), 1307 }; 1308 1309 static int va_macro_component_probe(struct snd_soc_component *component) 1310 { 1311 struct va_macro *va = snd_soc_component_get_drvdata(component); 1312 1313 snd_soc_component_init_regmap(component, va->regmap); 1314 1315 return 0; 1316 } 1317 1318 static const struct snd_soc_component_driver va_macro_component_drv = { 1319 .name = "VA MACRO", 1320 .probe = va_macro_component_probe, 1321 .controls = va_macro_snd_controls, 1322 .num_controls = ARRAY_SIZE(va_macro_snd_controls), 1323 .dapm_widgets = va_macro_dapm_widgets, 1324 .num_dapm_widgets = ARRAY_SIZE(va_macro_dapm_widgets), 1325 .dapm_routes = va_audio_map, 1326 .num_dapm_routes = ARRAY_SIZE(va_audio_map), 1327 }; 1328 1329 static int fsgen_gate_enable(struct clk_hw *hw) 1330 { 1331 struct va_macro *va = to_va_macro(hw); 1332 struct regmap *regmap = va->regmap; 1333 int ret; 1334 1335 ret = va_macro_mclk_enable(va, true); 1336 if (va->has_swr_master) 1337 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 1338 CDC_VA_SWR_CLK_EN_MASK, CDC_VA_SWR_CLK_ENABLE); 1339 1340 return ret; 1341 } 1342 1343 static void fsgen_gate_disable(struct clk_hw *hw) 1344 { 1345 struct va_macro *va = to_va_macro(hw); 1346 struct regmap *regmap = va->regmap; 1347 1348 if (va->has_swr_master) 1349 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 1350 CDC_VA_SWR_CLK_EN_MASK, 0x0); 1351 1352 va_macro_mclk_enable(va, false); 1353 } 1354 1355 static int fsgen_gate_is_enabled(struct clk_hw *hw) 1356 { 1357 struct va_macro *va = to_va_macro(hw); 1358 int val; 1359 1360 regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val); 1361 1362 return !!(val & CDC_VA_FS_BROADCAST_EN); 1363 } 1364 1365 static const struct clk_ops fsgen_gate_ops = { 1366 .prepare = fsgen_gate_enable, 1367 .unprepare = fsgen_gate_disable, 1368 .is_enabled = fsgen_gate_is_enabled, 1369 }; 1370 1371 static int va_macro_register_fsgen_output(struct va_macro *va) 1372 { 1373 struct clk *parent = va->mclk; 1374 struct device *dev = va->dev; 1375 struct device_node *np = dev->of_node; 1376 const char *parent_clk_name; 1377 const char *clk_name = "fsgen"; 1378 struct clk_init_data init; 1379 int ret; 1380 1381 parent_clk_name = __clk_get_name(parent); 1382 1383 of_property_read_string(np, "clock-output-names", &clk_name); 1384 1385 init.name = clk_name; 1386 init.ops = &fsgen_gate_ops; 1387 init.flags = 0; 1388 init.parent_names = &parent_clk_name; 1389 init.num_parents = 1; 1390 va->hw.init = &init; 1391 ret = devm_clk_hw_register(va->dev, &va->hw); 1392 if (ret) 1393 return ret; 1394 1395 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &va->hw); 1396 } 1397 1398 static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate, 1399 struct va_macro *va) 1400 { 1401 u32 div_factor; 1402 u32 mclk_rate = VA_MACRO_MCLK_FREQ; 1403 1404 if (!dmic_sample_rate || mclk_rate % dmic_sample_rate != 0) 1405 goto undefined_rate; 1406 1407 div_factor = mclk_rate / dmic_sample_rate; 1408 1409 switch (div_factor) { 1410 case 2: 1411 va->dmic_clk_div = VA_MACRO_CLK_DIV_2; 1412 break; 1413 case 3: 1414 va->dmic_clk_div = VA_MACRO_CLK_DIV_3; 1415 break; 1416 case 4: 1417 va->dmic_clk_div = VA_MACRO_CLK_DIV_4; 1418 break; 1419 case 6: 1420 va->dmic_clk_div = VA_MACRO_CLK_DIV_6; 1421 break; 1422 case 8: 1423 va->dmic_clk_div = VA_MACRO_CLK_DIV_8; 1424 break; 1425 case 16: 1426 va->dmic_clk_div = VA_MACRO_CLK_DIV_16; 1427 break; 1428 default: 1429 /* Any other DIV factor is invalid */ 1430 goto undefined_rate; 1431 } 1432 1433 return dmic_sample_rate; 1434 1435 undefined_rate: 1436 dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n", 1437 __func__, dmic_sample_rate, mclk_rate); 1438 dmic_sample_rate = 0; 1439 1440 return dmic_sample_rate; 1441 } 1442 1443 static int va_macro_probe(struct platform_device *pdev) 1444 { 1445 struct device *dev = &pdev->dev; 1446 const struct va_macro_data *data; 1447 struct va_macro *va; 1448 void __iomem *base; 1449 u32 sample_rate = 0; 1450 int ret; 1451 1452 va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL); 1453 if (!va) 1454 return -ENOMEM; 1455 1456 va->dev = dev; 1457 1458 va->macro = devm_clk_get_optional(dev, "macro"); 1459 if (IS_ERR(va->macro)) 1460 return PTR_ERR(va->macro); 1461 1462 va->dcodec = devm_clk_get_optional(dev, "dcodec"); 1463 if (IS_ERR(va->dcodec)) 1464 return PTR_ERR(va->dcodec); 1465 1466 va->mclk = devm_clk_get(dev, "mclk"); 1467 if (IS_ERR(va->mclk)) 1468 return PTR_ERR(va->mclk); 1469 1470 va->pds = lpass_macro_pds_init(dev); 1471 if (IS_ERR(va->pds)) 1472 return PTR_ERR(va->pds); 1473 1474 ret = of_property_read_u32(dev->of_node, "qcom,dmic-sample-rate", 1475 &sample_rate); 1476 if (ret) { 1477 dev_err(dev, "qcom,dmic-sample-rate dt entry missing\n"); 1478 va->dmic_clk_div = VA_MACRO_CLK_DIV_2; 1479 } else { 1480 ret = va_macro_validate_dmic_sample_rate(sample_rate, va); 1481 if (!ret) { 1482 ret = -EINVAL; 1483 goto err; 1484 } 1485 } 1486 1487 base = devm_platform_ioremap_resource(pdev, 0); 1488 if (IS_ERR(base)) { 1489 ret = PTR_ERR(base); 1490 goto err; 1491 } 1492 1493 va->regmap = devm_regmap_init_mmio(dev, base, &va_regmap_config); 1494 if (IS_ERR(va->regmap)) { 1495 ret = -EINVAL; 1496 goto err; 1497 } 1498 1499 dev_set_drvdata(dev, va); 1500 1501 data = of_device_get_match_data(dev); 1502 va->has_swr_master = data->has_swr_master; 1503 1504 /* mclk rate */ 1505 clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ); 1506 1507 ret = clk_prepare_enable(va->macro); 1508 if (ret) 1509 goto err; 1510 1511 ret = clk_prepare_enable(va->dcodec); 1512 if (ret) 1513 goto err_dcodec; 1514 1515 ret = clk_prepare_enable(va->mclk); 1516 if (ret) 1517 goto err_mclk; 1518 1519 if (va->has_swr_master) { 1520 /* Set default CLK div to 1 */ 1521 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL0, 1522 CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK, 1523 CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1); 1524 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL1, 1525 CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK, 1526 CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1); 1527 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL2, 1528 CDC_VA_SWR_MIC_CLK_SEL_0_1_MASK, 1529 CDC_VA_SWR_MIC_CLK_SEL_0_1_DIV1); 1530 1531 } 1532 1533 if (va->has_swr_master) { 1534 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 1535 CDC_VA_SWR_RESET_MASK, CDC_VA_SWR_RESET_ENABLE); 1536 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 1537 CDC_VA_SWR_CLK_EN_MASK, CDC_VA_SWR_CLK_ENABLE); 1538 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 1539 CDC_VA_SWR_RESET_MASK, 0x0); 1540 } 1541 1542 ret = devm_snd_soc_register_component(dev, &va_macro_component_drv, 1543 va_macro_dais, 1544 ARRAY_SIZE(va_macro_dais)); 1545 if (ret) 1546 goto err_clkout; 1547 1548 pm_runtime_set_autosuspend_delay(dev, 3000); 1549 pm_runtime_use_autosuspend(dev); 1550 pm_runtime_mark_last_busy(dev); 1551 pm_runtime_set_active(dev); 1552 pm_runtime_enable(dev); 1553 1554 ret = va_macro_register_fsgen_output(va); 1555 if (ret) 1556 goto err_clkout; 1557 1558 va->fsgen = clk_hw_get_clk(&va->hw, "fsgen"); 1559 if (IS_ERR(va->fsgen)) { 1560 ret = PTR_ERR(va->fsgen); 1561 goto err_clkout; 1562 } 1563 1564 return 0; 1565 1566 err_clkout: 1567 clk_disable_unprepare(va->mclk); 1568 err_mclk: 1569 clk_disable_unprepare(va->dcodec); 1570 err_dcodec: 1571 clk_disable_unprepare(va->macro); 1572 err: 1573 lpass_macro_pds_exit(va->pds); 1574 1575 return ret; 1576 } 1577 1578 static void va_macro_remove(struct platform_device *pdev) 1579 { 1580 struct va_macro *va = dev_get_drvdata(&pdev->dev); 1581 1582 clk_disable_unprepare(va->mclk); 1583 clk_disable_unprepare(va->dcodec); 1584 clk_disable_unprepare(va->macro); 1585 1586 lpass_macro_pds_exit(va->pds); 1587 } 1588 1589 static int __maybe_unused va_macro_runtime_suspend(struct device *dev) 1590 { 1591 struct va_macro *va = dev_get_drvdata(dev); 1592 1593 regcache_cache_only(va->regmap, true); 1594 regcache_mark_dirty(va->regmap); 1595 1596 clk_disable_unprepare(va->mclk); 1597 1598 return 0; 1599 } 1600 1601 static int __maybe_unused va_macro_runtime_resume(struct device *dev) 1602 { 1603 struct va_macro *va = dev_get_drvdata(dev); 1604 int ret; 1605 1606 ret = clk_prepare_enable(va->mclk); 1607 if (ret) { 1608 dev_err(va->dev, "unable to prepare mclk\n"); 1609 return ret; 1610 } 1611 1612 regcache_cache_only(va->regmap, false); 1613 regcache_sync(va->regmap); 1614 1615 return 0; 1616 } 1617 1618 1619 static const struct dev_pm_ops va_macro_pm_ops = { 1620 SET_RUNTIME_PM_OPS(va_macro_runtime_suspend, va_macro_runtime_resume, NULL) 1621 }; 1622 1623 static const struct of_device_id va_macro_dt_match[] = { 1624 { .compatible = "qcom,sc7280-lpass-va-macro", .data = &sm8250_va_data }, 1625 { .compatible = "qcom,sm8250-lpass-va-macro", .data = &sm8250_va_data }, 1626 { .compatible = "qcom,sm8450-lpass-va-macro", .data = &sm8450_va_data }, 1627 { .compatible = "qcom,sc8280xp-lpass-va-macro", .data = &sm8450_va_data }, 1628 {} 1629 }; 1630 MODULE_DEVICE_TABLE(of, va_macro_dt_match); 1631 1632 static struct platform_driver va_macro_driver = { 1633 .driver = { 1634 .name = "va_macro", 1635 .of_match_table = va_macro_dt_match, 1636 .suppress_bind_attrs = true, 1637 .pm = &va_macro_pm_ops, 1638 }, 1639 .probe = va_macro_probe, 1640 .remove_new = va_macro_remove, 1641 }; 1642 1643 module_platform_driver(va_macro_driver); 1644 MODULE_DESCRIPTION("VA macro driver"); 1645 MODULE_LICENSE("GPL"); 1646