1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/clk-provider.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/module.h> 9 #include <linux/of_clk.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <linux/regulator/consumer.h> 15 #include <sound/soc.h> 16 #include <sound/soc-dapm.h> 17 #include <sound/tlv.h> 18 19 #include "lpass-macro-common.h" 20 21 /* VA macro registers */ 22 #define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 23 #define CDC_VA_MCLK_CONTROL_EN BIT(0) 24 #define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 25 #define CDC_VA_FS_CONTROL_EN BIT(0) 26 #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL (0x0008) 27 #define CDC_VA_TOP_CSR_TOP_CFG0 (0x0080) 28 #define CDC_VA_FS_BROADCAST_EN BIT(1) 29 #define CDC_VA_TOP_CSR_DMIC0_CTL (0x0084) 30 #define CDC_VA_TOP_CSR_DMIC1_CTL (0x0088) 31 #define CDC_VA_TOP_CSR_DMIC2_CTL (0x008C) 32 #define CDC_VA_TOP_CSR_DMIC3_CTL (0x0090) 33 #define CDC_VA_DMIC_EN_MASK BIT(0) 34 #define CDC_VA_DMIC_ENABLE BIT(0) 35 #define CDC_VA_DMIC_CLK_SEL_MASK GENMASK(3, 1) 36 #define CDC_VA_DMIC_CLK_SEL_SHFT 1 37 #define CDC_VA_DMIC_CLK_SEL_DIV0 0x0 38 #define CDC_VA_DMIC_CLK_SEL_DIV1 0x2 39 #define CDC_VA_DMIC_CLK_SEL_DIV2 0x4 40 #define CDC_VA_DMIC_CLK_SEL_DIV3 0x6 41 #define CDC_VA_DMIC_CLK_SEL_DIV4 0x8 42 #define CDC_VA_DMIC_CLK_SEL_DIV5 0xa 43 #define CDC_VA_TOP_CSR_DMIC_CFG (0x0094) 44 #define CDC_VA_RESET_ALL_DMICS_MASK BIT(7) 45 #define CDC_VA_RESET_ALL_DMICS_RESET BIT(7) 46 #define CDC_VA_RESET_ALL_DMICS_DISABLE 0 47 #define CDC_VA_DMIC3_FREQ_CHANGE_MASK BIT(3) 48 #define CDC_VA_DMIC3_FREQ_CHANGE_EN BIT(3) 49 #define CDC_VA_DMIC2_FREQ_CHANGE_MASK BIT(2) 50 #define CDC_VA_DMIC2_FREQ_CHANGE_EN BIT(2) 51 #define CDC_VA_DMIC1_FREQ_CHANGE_MASK BIT(1) 52 #define CDC_VA_DMIC1_FREQ_CHANGE_EN BIT(1) 53 #define CDC_VA_DMIC0_FREQ_CHANGE_MASK BIT(0) 54 #define CDC_VA_DMIC0_FREQ_CHANGE_EN BIT(0) 55 #define CDC_VA_DMIC_FREQ_CHANGE_DISABLE 0 56 #define CDC_VA_TOP_CSR_DEBUG_BUS (0x009C) 57 #define CDC_VA_TOP_CSR_DEBUG_EN (0x00A0) 58 #define CDC_VA_TOP_CSR_TX_I2S_CTL (0x00A4) 59 #define CDC_VA_TOP_CSR_I2S_CLK (0x00A8) 60 #define CDC_VA_TOP_CSR_I2S_RESET (0x00AC) 61 #define CDC_VA_TOP_CSR_CORE_ID_0 (0x00C0) 62 #define CDC_VA_TOP_CSR_CORE_ID_1 (0x00C4) 63 #define CDC_VA_TOP_CSR_CORE_ID_2 (0x00C8) 64 #define CDC_VA_TOP_CSR_CORE_ID_3 (0x00CC) 65 #define CDC_VA_TOP_CSR_SWR_MIC_CTL0 (0x00D0) 66 #define CDC_VA_TOP_CSR_SWR_MIC_CTL1 (0x00D4) 67 #define CDC_VA_TOP_CSR_SWR_MIC_CTL2 (0x00D8) 68 #define CDC_VA_TOP_CSR_SWR_CTRL (0x00DC) 69 #define CDC_VA_INP_MUX_ADC_MUX0_CFG0 (0x0100) 70 #define CDC_VA_INP_MUX_ADC_MUX0_CFG1 (0x0104) 71 #define CDC_VA_INP_MUX_ADC_MUX1_CFG0 (0x0108) 72 #define CDC_VA_INP_MUX_ADC_MUX1_CFG1 (0x010C) 73 #define CDC_VA_INP_MUX_ADC_MUX2_CFG0 (0x0110) 74 #define CDC_VA_INP_MUX_ADC_MUX2_CFG1 (0x0114) 75 #define CDC_VA_INP_MUX_ADC_MUX3_CFG0 (0x0118) 76 #define CDC_VA_INP_MUX_ADC_MUX3_CFG1 (0x011C) 77 #define CDC_VA_TX0_TX_PATH_CTL (0x0400) 78 #define CDC_VA_TX_PATH_CLK_EN_MASK BIT(5) 79 #define CDC_VA_TX_PATH_CLK_EN BIT(5) 80 #define CDC_VA_TX_PATH_CLK_DISABLE 0 81 #define CDC_VA_TX_PATH_PGA_MUTE_EN_MASK BIT(4) 82 #define CDC_VA_TX_PATH_PGA_MUTE_EN BIT(4) 83 #define CDC_VA_TX_PATH_PGA_MUTE_DISABLE 0 84 #define CDC_VA_TX0_TX_PATH_CFG0 (0x0404) 85 #define CDC_VA_ADC_MODE_MASK GENMASK(2, 1) 86 #define CDC_VA_ADC_MODE_SHIFT 1 87 #define TX_HPF_CUT_OFF_FREQ_MASK GENMASK(6, 5) 88 #define CF_MIN_3DB_4HZ 0x0 89 #define CF_MIN_3DB_75HZ 0x1 90 #define CF_MIN_3DB_150HZ 0x2 91 #define CDC_VA_TX0_TX_PATH_CFG1 (0x0408) 92 #define CDC_VA_TX0_TX_VOL_CTL (0x040C) 93 #define CDC_VA_TX0_TX_PATH_SEC0 (0x0410) 94 #define CDC_VA_TX0_TX_PATH_SEC1 (0x0414) 95 #define CDC_VA_TX0_TX_PATH_SEC2 (0x0418) 96 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK BIT(1) 97 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ BIT(1) 98 #define CDC_VA_TX_HPF_ZERO_GATE_MASK BIT(0) 99 #define CDC_VA_TX_HPF_ZERO_NO_GATE BIT(0) 100 #define CDC_VA_TX_HPF_ZERO_GATE 0 101 #define CDC_VA_TX0_TX_PATH_SEC3 (0x041C) 102 #define CDC_VA_TX0_TX_PATH_SEC4 (0x0420) 103 #define CDC_VA_TX0_TX_PATH_SEC5 (0x0424) 104 #define CDC_VA_TX0_TX_PATH_SEC6 (0x0428) 105 #define CDC_VA_TX0_TX_PATH_SEC7 (0x042C) 106 #define CDC_VA_TX1_TX_PATH_CTL (0x0480) 107 #define CDC_VA_TX1_TX_PATH_CFG0 (0x0484) 108 #define CDC_VA_TX1_TX_PATH_CFG1 (0x0488) 109 #define CDC_VA_TX1_TX_VOL_CTL (0x048C) 110 #define CDC_VA_TX1_TX_PATH_SEC0 (0x0490) 111 #define CDC_VA_TX1_TX_PATH_SEC1 (0x0494) 112 #define CDC_VA_TX1_TX_PATH_SEC2 (0x0498) 113 #define CDC_VA_TX1_TX_PATH_SEC3 (0x049C) 114 #define CDC_VA_TX1_TX_PATH_SEC4 (0x04A0) 115 #define CDC_VA_TX1_TX_PATH_SEC5 (0x04A4) 116 #define CDC_VA_TX1_TX_PATH_SEC6 (0x04A8) 117 #define CDC_VA_TX2_TX_PATH_CTL (0x0500) 118 #define CDC_VA_TX2_TX_PATH_CFG0 (0x0504) 119 #define CDC_VA_TX2_TX_PATH_CFG1 (0x0508) 120 #define CDC_VA_TX2_TX_VOL_CTL (0x050C) 121 #define CDC_VA_TX2_TX_PATH_SEC0 (0x0510) 122 #define CDC_VA_TX2_TX_PATH_SEC1 (0x0514) 123 #define CDC_VA_TX2_TX_PATH_SEC2 (0x0518) 124 #define CDC_VA_TX2_TX_PATH_SEC3 (0x051C) 125 #define CDC_VA_TX2_TX_PATH_SEC4 (0x0520) 126 #define CDC_VA_TX2_TX_PATH_SEC5 (0x0524) 127 #define CDC_VA_TX2_TX_PATH_SEC6 (0x0528) 128 #define CDC_VA_TX3_TX_PATH_CTL (0x0580) 129 #define CDC_VA_TX3_TX_PATH_CFG0 (0x0584) 130 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK BIT(7) 131 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC BIT(7) 132 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC 0 133 #define CDC_VA_TX3_TX_PATH_CFG1 (0x0588) 134 #define CDC_VA_TX3_TX_VOL_CTL (0x058C) 135 #define CDC_VA_TX3_TX_PATH_SEC0 (0x0590) 136 #define CDC_VA_TX3_TX_PATH_SEC1 (0x0594) 137 #define CDC_VA_TX3_TX_PATH_SEC2 (0x0598) 138 #define CDC_VA_TX3_TX_PATH_SEC3 (0x059C) 139 #define CDC_VA_TX3_TX_PATH_SEC4 (0x05A0) 140 #define CDC_VA_TX3_TX_PATH_SEC5 (0x05A4) 141 #define CDC_VA_TX3_TX_PATH_SEC6 (0x05A8) 142 143 #define VA_MAX_OFFSET (0x07A8) 144 145 #define VA_MACRO_NUM_DECIMATORS 4 146 #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 147 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 148 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 149 #define VA_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 150 SNDRV_PCM_FMTBIT_S24_LE |\ 151 SNDRV_PCM_FMTBIT_S24_3LE) 152 153 #define VA_MACRO_MCLK_FREQ 9600000 154 #define VA_MACRO_TX_PATH_OFFSET 0x80 155 #define VA_MACRO_SWR_MIC_MUX_SEL_MASK 0xF 156 #define VA_MACRO_ADC_MUX_CFG_OFFSET 0x8 157 158 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 159 160 enum { 161 VA_MACRO_AIF_INVALID = 0, 162 VA_MACRO_AIF1_CAP, 163 VA_MACRO_AIF2_CAP, 164 VA_MACRO_AIF3_CAP, 165 VA_MACRO_MAX_DAIS, 166 }; 167 168 enum { 169 VA_MACRO_DEC0, 170 VA_MACRO_DEC1, 171 VA_MACRO_DEC2, 172 VA_MACRO_DEC3, 173 VA_MACRO_DEC4, 174 VA_MACRO_DEC5, 175 VA_MACRO_DEC6, 176 VA_MACRO_DEC7, 177 VA_MACRO_DEC_MAX, 178 }; 179 180 enum { 181 VA_MACRO_CLK_DIV_2, 182 VA_MACRO_CLK_DIV_3, 183 VA_MACRO_CLK_DIV_4, 184 VA_MACRO_CLK_DIV_6, 185 VA_MACRO_CLK_DIV_8, 186 VA_MACRO_CLK_DIV_16, 187 }; 188 189 #define VA_NUM_CLKS_MAX 3 190 191 struct va_macro { 192 struct device *dev; 193 unsigned long active_ch_mask[VA_MACRO_MAX_DAIS]; 194 unsigned long active_ch_cnt[VA_MACRO_MAX_DAIS]; 195 u16 dmic_clk_div; 196 197 int dec_mode[VA_MACRO_NUM_DECIMATORS]; 198 struct regmap *regmap; 199 struct clk *mclk; 200 struct clk *macro; 201 struct clk *dcodec; 202 struct clk *fsgen; 203 struct clk_hw hw; 204 struct lpass_macro *pds; 205 206 s32 dmic_0_1_clk_cnt; 207 s32 dmic_2_3_clk_cnt; 208 s32 dmic_4_5_clk_cnt; 209 s32 dmic_6_7_clk_cnt; 210 u8 dmic_0_1_clk_div; 211 u8 dmic_2_3_clk_div; 212 u8 dmic_4_5_clk_div; 213 u8 dmic_6_7_clk_div; 214 }; 215 216 #define to_va_macro(_hw) container_of(_hw, struct va_macro, hw) 217 218 static bool va_is_volatile_register(struct device *dev, unsigned int reg) 219 { 220 switch (reg) { 221 case CDC_VA_TOP_CSR_CORE_ID_0: 222 case CDC_VA_TOP_CSR_CORE_ID_1: 223 case CDC_VA_TOP_CSR_CORE_ID_2: 224 case CDC_VA_TOP_CSR_CORE_ID_3: 225 case CDC_VA_TOP_CSR_DMIC0_CTL: 226 case CDC_VA_TOP_CSR_DMIC1_CTL: 227 case CDC_VA_TOP_CSR_DMIC2_CTL: 228 case CDC_VA_TOP_CSR_DMIC3_CTL: 229 return true; 230 } 231 return false; 232 } 233 234 static const struct reg_default va_defaults[] = { 235 /* VA macro */ 236 { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, 237 { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, 238 { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 239 { CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, 240 { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, 241 { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, 242 { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00}, 243 { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00}, 244 { CDC_VA_TOP_CSR_DMIC_CFG, 0x80}, 245 { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00}, 246 { CDC_VA_TOP_CSR_DEBUG_EN, 0x00}, 247 { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C}, 248 { CDC_VA_TOP_CSR_I2S_CLK, 0x00}, 249 { CDC_VA_TOP_CSR_I2S_RESET, 0x00}, 250 { CDC_VA_TOP_CSR_CORE_ID_0, 0x00}, 251 { CDC_VA_TOP_CSR_CORE_ID_1, 0x00}, 252 { CDC_VA_TOP_CSR_CORE_ID_2, 0x00}, 253 { CDC_VA_TOP_CSR_CORE_ID_3, 0x00}, 254 { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE}, 255 { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE}, 256 { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE}, 257 { CDC_VA_TOP_CSR_SWR_CTRL, 0x06}, 258 259 /* VA core */ 260 { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00}, 261 { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00}, 262 { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00}, 263 { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00}, 264 { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00}, 265 { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00}, 266 { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00}, 267 { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00}, 268 { CDC_VA_TX0_TX_PATH_CTL, 0x04}, 269 { CDC_VA_TX0_TX_PATH_CFG0, 0x10}, 270 { CDC_VA_TX0_TX_PATH_CFG1, 0x0B}, 271 { CDC_VA_TX0_TX_VOL_CTL, 0x00}, 272 { CDC_VA_TX0_TX_PATH_SEC0, 0x00}, 273 { CDC_VA_TX0_TX_PATH_SEC1, 0x00}, 274 { CDC_VA_TX0_TX_PATH_SEC2, 0x01}, 275 { CDC_VA_TX0_TX_PATH_SEC3, 0x3C}, 276 { CDC_VA_TX0_TX_PATH_SEC4, 0x20}, 277 { CDC_VA_TX0_TX_PATH_SEC5, 0x00}, 278 { CDC_VA_TX0_TX_PATH_SEC6, 0x00}, 279 { CDC_VA_TX0_TX_PATH_SEC7, 0x25}, 280 { CDC_VA_TX1_TX_PATH_CTL, 0x04}, 281 { CDC_VA_TX1_TX_PATH_CFG0, 0x10}, 282 { CDC_VA_TX1_TX_PATH_CFG1, 0x0B}, 283 { CDC_VA_TX1_TX_VOL_CTL, 0x00}, 284 { CDC_VA_TX1_TX_PATH_SEC0, 0x00}, 285 { CDC_VA_TX1_TX_PATH_SEC1, 0x00}, 286 { CDC_VA_TX1_TX_PATH_SEC2, 0x01}, 287 { CDC_VA_TX1_TX_PATH_SEC3, 0x3C}, 288 { CDC_VA_TX1_TX_PATH_SEC4, 0x20}, 289 { CDC_VA_TX1_TX_PATH_SEC5, 0x00}, 290 { CDC_VA_TX1_TX_PATH_SEC6, 0x00}, 291 { CDC_VA_TX2_TX_PATH_CTL, 0x04}, 292 { CDC_VA_TX2_TX_PATH_CFG0, 0x10}, 293 { CDC_VA_TX2_TX_PATH_CFG1, 0x0B}, 294 { CDC_VA_TX2_TX_VOL_CTL, 0x00}, 295 { CDC_VA_TX2_TX_PATH_SEC0, 0x00}, 296 { CDC_VA_TX2_TX_PATH_SEC1, 0x00}, 297 { CDC_VA_TX2_TX_PATH_SEC2, 0x01}, 298 { CDC_VA_TX2_TX_PATH_SEC3, 0x3C}, 299 { CDC_VA_TX2_TX_PATH_SEC4, 0x20}, 300 { CDC_VA_TX2_TX_PATH_SEC5, 0x00}, 301 { CDC_VA_TX2_TX_PATH_SEC6, 0x00}, 302 { CDC_VA_TX3_TX_PATH_CTL, 0x04}, 303 { CDC_VA_TX3_TX_PATH_CFG0, 0x10}, 304 { CDC_VA_TX3_TX_PATH_CFG1, 0x0B}, 305 { CDC_VA_TX3_TX_VOL_CTL, 0x00}, 306 { CDC_VA_TX3_TX_PATH_SEC0, 0x00}, 307 { CDC_VA_TX3_TX_PATH_SEC1, 0x00}, 308 { CDC_VA_TX3_TX_PATH_SEC2, 0x01}, 309 { CDC_VA_TX3_TX_PATH_SEC3, 0x3C}, 310 { CDC_VA_TX3_TX_PATH_SEC4, 0x20}, 311 { CDC_VA_TX3_TX_PATH_SEC5, 0x00}, 312 { CDC_VA_TX3_TX_PATH_SEC6, 0x00}, 313 }; 314 315 static bool va_is_rw_register(struct device *dev, unsigned int reg) 316 { 317 switch (reg) { 318 case CDC_VA_CLK_RST_CTRL_MCLK_CONTROL: 319 case CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL: 320 case CDC_VA_CLK_RST_CTRL_SWR_CONTROL: 321 case CDC_VA_TOP_CSR_TOP_CFG0: 322 case CDC_VA_TOP_CSR_DMIC0_CTL: 323 case CDC_VA_TOP_CSR_DMIC1_CTL: 324 case CDC_VA_TOP_CSR_DMIC2_CTL: 325 case CDC_VA_TOP_CSR_DMIC3_CTL: 326 case CDC_VA_TOP_CSR_DMIC_CFG: 327 case CDC_VA_TOP_CSR_DEBUG_BUS: 328 case CDC_VA_TOP_CSR_DEBUG_EN: 329 case CDC_VA_TOP_CSR_TX_I2S_CTL: 330 case CDC_VA_TOP_CSR_I2S_CLK: 331 case CDC_VA_TOP_CSR_I2S_RESET: 332 case CDC_VA_INP_MUX_ADC_MUX0_CFG0: 333 case CDC_VA_INP_MUX_ADC_MUX0_CFG1: 334 case CDC_VA_INP_MUX_ADC_MUX1_CFG0: 335 case CDC_VA_INP_MUX_ADC_MUX1_CFG1: 336 case CDC_VA_INP_MUX_ADC_MUX2_CFG0: 337 case CDC_VA_INP_MUX_ADC_MUX2_CFG1: 338 case CDC_VA_INP_MUX_ADC_MUX3_CFG0: 339 case CDC_VA_INP_MUX_ADC_MUX3_CFG1: 340 case CDC_VA_TX0_TX_PATH_CTL: 341 case CDC_VA_TX0_TX_PATH_CFG0: 342 case CDC_VA_TX0_TX_PATH_CFG1: 343 case CDC_VA_TX0_TX_VOL_CTL: 344 case CDC_VA_TX0_TX_PATH_SEC0: 345 case CDC_VA_TX0_TX_PATH_SEC1: 346 case CDC_VA_TX0_TX_PATH_SEC2: 347 case CDC_VA_TX0_TX_PATH_SEC3: 348 case CDC_VA_TX0_TX_PATH_SEC4: 349 case CDC_VA_TX0_TX_PATH_SEC5: 350 case CDC_VA_TX0_TX_PATH_SEC6: 351 case CDC_VA_TX0_TX_PATH_SEC7: 352 case CDC_VA_TX1_TX_PATH_CTL: 353 case CDC_VA_TX1_TX_PATH_CFG0: 354 case CDC_VA_TX1_TX_PATH_CFG1: 355 case CDC_VA_TX1_TX_VOL_CTL: 356 case CDC_VA_TX1_TX_PATH_SEC0: 357 case CDC_VA_TX1_TX_PATH_SEC1: 358 case CDC_VA_TX1_TX_PATH_SEC2: 359 case CDC_VA_TX1_TX_PATH_SEC3: 360 case CDC_VA_TX1_TX_PATH_SEC4: 361 case CDC_VA_TX1_TX_PATH_SEC5: 362 case CDC_VA_TX1_TX_PATH_SEC6: 363 case CDC_VA_TX2_TX_PATH_CTL: 364 case CDC_VA_TX2_TX_PATH_CFG0: 365 case CDC_VA_TX2_TX_PATH_CFG1: 366 case CDC_VA_TX2_TX_VOL_CTL: 367 case CDC_VA_TX2_TX_PATH_SEC0: 368 case CDC_VA_TX2_TX_PATH_SEC1: 369 case CDC_VA_TX2_TX_PATH_SEC2: 370 case CDC_VA_TX2_TX_PATH_SEC3: 371 case CDC_VA_TX2_TX_PATH_SEC4: 372 case CDC_VA_TX2_TX_PATH_SEC5: 373 case CDC_VA_TX2_TX_PATH_SEC6: 374 case CDC_VA_TX3_TX_PATH_CTL: 375 case CDC_VA_TX3_TX_PATH_CFG0: 376 case CDC_VA_TX3_TX_PATH_CFG1: 377 case CDC_VA_TX3_TX_VOL_CTL: 378 case CDC_VA_TX3_TX_PATH_SEC0: 379 case CDC_VA_TX3_TX_PATH_SEC1: 380 case CDC_VA_TX3_TX_PATH_SEC2: 381 case CDC_VA_TX3_TX_PATH_SEC3: 382 case CDC_VA_TX3_TX_PATH_SEC4: 383 case CDC_VA_TX3_TX_PATH_SEC5: 384 case CDC_VA_TX3_TX_PATH_SEC6: 385 return true; 386 } 387 388 return false; 389 } 390 391 static bool va_is_readable_register(struct device *dev, unsigned int reg) 392 { 393 switch (reg) { 394 case CDC_VA_TOP_CSR_CORE_ID_0: 395 case CDC_VA_TOP_CSR_CORE_ID_1: 396 case CDC_VA_TOP_CSR_CORE_ID_2: 397 case CDC_VA_TOP_CSR_CORE_ID_3: 398 return true; 399 } 400 401 return va_is_rw_register(dev, reg); 402 } 403 404 static const struct regmap_config va_regmap_config = { 405 .name = "va_macro", 406 .reg_bits = 32, 407 .val_bits = 32, 408 .reg_stride = 4, 409 .cache_type = REGCACHE_FLAT, 410 .reg_defaults = va_defaults, 411 .num_reg_defaults = ARRAY_SIZE(va_defaults), 412 .max_register = VA_MAX_OFFSET, 413 .volatile_reg = va_is_volatile_register, 414 .readable_reg = va_is_readable_register, 415 .writeable_reg = va_is_rw_register, 416 }; 417 418 static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable) 419 { 420 struct regmap *regmap = va->regmap; 421 422 if (enable) { 423 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 424 CDC_VA_MCLK_CONTROL_EN, 425 CDC_VA_MCLK_CONTROL_EN); 426 427 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 428 CDC_VA_FS_CONTROL_EN, 429 CDC_VA_FS_CONTROL_EN); 430 431 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0, 432 CDC_VA_FS_BROADCAST_EN, 433 CDC_VA_FS_BROADCAST_EN); 434 } else { 435 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 436 CDC_VA_MCLK_CONTROL_EN, 0x0); 437 438 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 439 CDC_VA_FS_CONTROL_EN, 0x0); 440 441 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0, 442 CDC_VA_FS_BROADCAST_EN, 0x0); 443 } 444 445 return 0; 446 } 447 448 static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable) 449 { 450 struct regmap *regmap = va->regmap; 451 452 if (mclk_enable) { 453 va_clk_rsc_fs_gen_request(va, true); 454 regcache_mark_dirty(regmap); 455 regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET); 456 } else { 457 va_clk_rsc_fs_gen_request(va, false); 458 } 459 460 return 0; 461 } 462 463 static int va_macro_mclk_event(struct snd_soc_dapm_widget *w, 464 struct snd_kcontrol *kcontrol, int event) 465 { 466 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 467 struct va_macro *va = snd_soc_component_get_drvdata(comp); 468 469 switch (event) { 470 case SND_SOC_DAPM_PRE_PMU: 471 return clk_prepare_enable(va->fsgen); 472 case SND_SOC_DAPM_POST_PMD: 473 clk_disable_unprepare(va->fsgen); 474 } 475 476 return 0; 477 } 478 479 static int va_macro_put_dec_enum(struct snd_kcontrol *kcontrol, 480 struct snd_ctl_elem_value *ucontrol) 481 { 482 struct snd_soc_dapm_widget *widget = 483 snd_soc_dapm_kcontrol_widget(kcontrol); 484 struct snd_soc_component *component = 485 snd_soc_dapm_to_component(widget->dapm); 486 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 487 unsigned int val; 488 u16 mic_sel_reg; 489 490 val = ucontrol->value.enumerated.item[0]; 491 492 switch (e->reg) { 493 case CDC_VA_INP_MUX_ADC_MUX0_CFG0: 494 mic_sel_reg = CDC_VA_TX0_TX_PATH_CFG0; 495 break; 496 case CDC_VA_INP_MUX_ADC_MUX1_CFG0: 497 mic_sel_reg = CDC_VA_TX1_TX_PATH_CFG0; 498 break; 499 case CDC_VA_INP_MUX_ADC_MUX2_CFG0: 500 mic_sel_reg = CDC_VA_TX2_TX_PATH_CFG0; 501 break; 502 case CDC_VA_INP_MUX_ADC_MUX3_CFG0: 503 mic_sel_reg = CDC_VA_TX3_TX_PATH_CFG0; 504 break; 505 default: 506 dev_err(component->dev, "%s: e->reg: 0x%x not expected\n", 507 __func__, e->reg); 508 return -EINVAL; 509 } 510 511 if (val != 0) 512 snd_soc_component_update_bits(component, mic_sel_reg, 513 CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK, 514 CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC); 515 516 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 517 } 518 519 static int va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol, 520 struct snd_ctl_elem_value *ucontrol) 521 { 522 struct snd_soc_dapm_widget *widget = 523 snd_soc_dapm_kcontrol_widget(kcontrol); 524 struct snd_soc_component *component = 525 snd_soc_dapm_to_component(widget->dapm); 526 struct soc_mixer_control *mc = 527 (struct soc_mixer_control *)kcontrol->private_value; 528 u32 dai_id = widget->shift; 529 u32 dec_id = mc->shift; 530 struct va_macro *va = snd_soc_component_get_drvdata(component); 531 532 if (test_bit(dec_id, &va->active_ch_mask[dai_id])) 533 ucontrol->value.integer.value[0] = 1; 534 else 535 ucontrol->value.integer.value[0] = 0; 536 537 return 0; 538 } 539 540 static int va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol, 541 struct snd_ctl_elem_value *ucontrol) 542 { 543 struct snd_soc_dapm_widget *widget = 544 snd_soc_dapm_kcontrol_widget(kcontrol); 545 struct snd_soc_component *component = 546 snd_soc_dapm_to_component(widget->dapm); 547 struct snd_soc_dapm_update *update = NULL; 548 struct soc_mixer_control *mc = 549 (struct soc_mixer_control *)kcontrol->private_value; 550 u32 dai_id = widget->shift; 551 u32 dec_id = mc->shift; 552 u32 enable = ucontrol->value.integer.value[0]; 553 struct va_macro *va = snd_soc_component_get_drvdata(component); 554 555 if (enable) { 556 set_bit(dec_id, &va->active_ch_mask[dai_id]); 557 va->active_ch_cnt[dai_id]++; 558 } else { 559 clear_bit(dec_id, &va->active_ch_mask[dai_id]); 560 va->active_ch_cnt[dai_id]--; 561 } 562 563 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); 564 565 return 0; 566 } 567 568 static int va_dmic_clk_enable(struct snd_soc_component *component, 569 u32 dmic, bool enable) 570 { 571 struct va_macro *va = snd_soc_component_get_drvdata(component); 572 u16 dmic_clk_reg; 573 s32 *dmic_clk_cnt; 574 u8 *dmic_clk_div; 575 u8 freq_change_mask; 576 u8 clk_div; 577 578 switch (dmic) { 579 case 0: 580 case 1: 581 dmic_clk_cnt = &(va->dmic_0_1_clk_cnt); 582 dmic_clk_div = &(va->dmic_0_1_clk_div); 583 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC0_CTL; 584 freq_change_mask = CDC_VA_DMIC0_FREQ_CHANGE_MASK; 585 break; 586 case 2: 587 case 3: 588 dmic_clk_cnt = &(va->dmic_2_3_clk_cnt); 589 dmic_clk_div = &(va->dmic_2_3_clk_div); 590 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC1_CTL; 591 freq_change_mask = CDC_VA_DMIC1_FREQ_CHANGE_MASK; 592 break; 593 case 4: 594 case 5: 595 dmic_clk_cnt = &(va->dmic_4_5_clk_cnt); 596 dmic_clk_div = &(va->dmic_4_5_clk_div); 597 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC2_CTL; 598 freq_change_mask = CDC_VA_DMIC2_FREQ_CHANGE_MASK; 599 break; 600 case 6: 601 case 7: 602 dmic_clk_cnt = &(va->dmic_6_7_clk_cnt); 603 dmic_clk_div = &(va->dmic_6_7_clk_div); 604 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC3_CTL; 605 freq_change_mask = CDC_VA_DMIC3_FREQ_CHANGE_MASK; 606 break; 607 default: 608 dev_err(component->dev, "%s: Invalid DMIC Selection\n", 609 __func__); 610 return -EINVAL; 611 } 612 613 if (enable) { 614 clk_div = va->dmic_clk_div; 615 (*dmic_clk_cnt)++; 616 if (*dmic_clk_cnt == 1) { 617 snd_soc_component_update_bits(component, 618 CDC_VA_TOP_CSR_DMIC_CFG, 619 CDC_VA_RESET_ALL_DMICS_MASK, 620 CDC_VA_RESET_ALL_DMICS_DISABLE); 621 snd_soc_component_update_bits(component, dmic_clk_reg, 622 CDC_VA_DMIC_CLK_SEL_MASK, 623 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 624 snd_soc_component_update_bits(component, dmic_clk_reg, 625 CDC_VA_DMIC_EN_MASK, 626 CDC_VA_DMIC_ENABLE); 627 } else { 628 if (*dmic_clk_div > clk_div) { 629 snd_soc_component_update_bits(component, 630 CDC_VA_TOP_CSR_DMIC_CFG, 631 freq_change_mask, 632 freq_change_mask); 633 snd_soc_component_update_bits(component, dmic_clk_reg, 634 CDC_VA_DMIC_CLK_SEL_MASK, 635 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 636 snd_soc_component_update_bits(component, 637 CDC_VA_TOP_CSR_DMIC_CFG, 638 freq_change_mask, 639 CDC_VA_DMIC_FREQ_CHANGE_DISABLE); 640 } else { 641 clk_div = *dmic_clk_div; 642 } 643 } 644 *dmic_clk_div = clk_div; 645 } else { 646 (*dmic_clk_cnt)--; 647 if (*dmic_clk_cnt == 0) { 648 snd_soc_component_update_bits(component, dmic_clk_reg, 649 CDC_VA_DMIC_EN_MASK, 0); 650 clk_div = 0; 651 snd_soc_component_update_bits(component, dmic_clk_reg, 652 CDC_VA_DMIC_CLK_SEL_MASK, 653 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 654 } else { 655 clk_div = va->dmic_clk_div; 656 if (*dmic_clk_div > clk_div) { 657 clk_div = va->dmic_clk_div; 658 snd_soc_component_update_bits(component, 659 CDC_VA_TOP_CSR_DMIC_CFG, 660 freq_change_mask, 661 freq_change_mask); 662 snd_soc_component_update_bits(component, dmic_clk_reg, 663 CDC_VA_DMIC_CLK_SEL_MASK, 664 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 665 snd_soc_component_update_bits(component, 666 CDC_VA_TOP_CSR_DMIC_CFG, 667 freq_change_mask, 668 CDC_VA_DMIC_FREQ_CHANGE_DISABLE); 669 } else { 670 clk_div = *dmic_clk_div; 671 } 672 } 673 *dmic_clk_div = clk_div; 674 } 675 676 return 0; 677 } 678 679 static int va_macro_enable_dmic(struct snd_soc_dapm_widget *w, 680 struct snd_kcontrol *kcontrol, int event) 681 { 682 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 683 unsigned int dmic = w->shift; 684 685 switch (event) { 686 case SND_SOC_DAPM_PRE_PMU: 687 va_dmic_clk_enable(comp, dmic, true); 688 break; 689 case SND_SOC_DAPM_POST_PMD: 690 va_dmic_clk_enable(comp, dmic, false); 691 break; 692 } 693 694 return 0; 695 } 696 697 static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 698 struct snd_kcontrol *kcontrol, int event) 699 { 700 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 701 unsigned int decimator; 702 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg; 703 u16 tx_gain_ctl_reg; 704 u8 hpf_cut_off_freq; 705 706 struct va_macro *va = snd_soc_component_get_drvdata(comp); 707 708 decimator = w->shift; 709 710 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL + 711 VA_MACRO_TX_PATH_OFFSET * decimator; 712 hpf_gate_reg = CDC_VA_TX0_TX_PATH_SEC2 + 713 VA_MACRO_TX_PATH_OFFSET * decimator; 714 dec_cfg_reg = CDC_VA_TX0_TX_PATH_CFG0 + 715 VA_MACRO_TX_PATH_OFFSET * decimator; 716 tx_gain_ctl_reg = CDC_VA_TX0_TX_VOL_CTL + 717 VA_MACRO_TX_PATH_OFFSET * decimator; 718 719 switch (event) { 720 case SND_SOC_DAPM_PRE_PMU: 721 snd_soc_component_update_bits(comp, 722 dec_cfg_reg, CDC_VA_ADC_MODE_MASK, 723 va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT); 724 /* Enable TX PGA Mute */ 725 break; 726 case SND_SOC_DAPM_POST_PMU: 727 /* Enable TX CLK */ 728 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 729 CDC_VA_TX_PATH_CLK_EN_MASK, 730 CDC_VA_TX_PATH_CLK_EN); 731 snd_soc_component_update_bits(comp, hpf_gate_reg, 732 CDC_VA_TX_HPF_ZERO_GATE_MASK, 733 CDC_VA_TX_HPF_ZERO_GATE); 734 735 usleep_range(1000, 1010); 736 hpf_cut_off_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 737 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 738 739 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) { 740 snd_soc_component_update_bits(comp, dec_cfg_reg, 741 TX_HPF_CUT_OFF_FREQ_MASK, 742 CF_MIN_3DB_150HZ << 5); 743 744 snd_soc_component_update_bits(comp, hpf_gate_reg, 745 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK, 746 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ); 747 748 /* 749 * Minimum 1 clk cycle delay is required as per HW spec 750 */ 751 usleep_range(1000, 1010); 752 753 snd_soc_component_update_bits(comp, 754 hpf_gate_reg, 755 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK, 756 0x0); 757 } 758 759 760 usleep_range(1000, 1010); 761 snd_soc_component_update_bits(comp, hpf_gate_reg, 762 CDC_VA_TX_HPF_ZERO_GATE_MASK, 763 CDC_VA_TX_HPF_ZERO_NO_GATE); 764 /* 765 * 6ms delay is required as per HW spec 766 */ 767 usleep_range(6000, 6010); 768 /* apply gain after decimator is enabled */ 769 snd_soc_component_write(comp, tx_gain_ctl_reg, 770 snd_soc_component_read(comp, tx_gain_ctl_reg)); 771 break; 772 case SND_SOC_DAPM_POST_PMD: 773 /* Disable TX CLK */ 774 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 775 CDC_VA_TX_PATH_CLK_EN_MASK, 776 CDC_VA_TX_PATH_CLK_DISABLE); 777 break; 778 } 779 return 0; 780 } 781 782 static int va_macro_dec_mode_get(struct snd_kcontrol *kcontrol, 783 struct snd_ctl_elem_value *ucontrol) 784 { 785 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 786 struct va_macro *va = snd_soc_component_get_drvdata(comp); 787 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 788 int path = e->shift_l; 789 790 ucontrol->value.enumerated.item[0] = va->dec_mode[path]; 791 792 return 0; 793 } 794 795 static int va_macro_dec_mode_put(struct snd_kcontrol *kcontrol, 796 struct snd_ctl_elem_value *ucontrol) 797 { 798 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 799 int value = ucontrol->value.enumerated.item[0]; 800 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 801 int path = e->shift_l; 802 struct va_macro *va = snd_soc_component_get_drvdata(comp); 803 804 va->dec_mode[path] = value; 805 806 return 0; 807 } 808 809 static int va_macro_hw_params(struct snd_pcm_substream *substream, 810 struct snd_pcm_hw_params *params, 811 struct snd_soc_dai *dai) 812 { 813 int tx_fs_rate; 814 struct snd_soc_component *component = dai->component; 815 u32 decimator, sample_rate; 816 u16 tx_fs_reg; 817 struct device *va_dev = component->dev; 818 struct va_macro *va = snd_soc_component_get_drvdata(component); 819 820 sample_rate = params_rate(params); 821 switch (sample_rate) { 822 case 8000: 823 tx_fs_rate = 0; 824 break; 825 case 16000: 826 tx_fs_rate = 1; 827 break; 828 case 32000: 829 tx_fs_rate = 3; 830 break; 831 case 48000: 832 tx_fs_rate = 4; 833 break; 834 case 96000: 835 tx_fs_rate = 5; 836 break; 837 case 192000: 838 tx_fs_rate = 6; 839 break; 840 case 384000: 841 tx_fs_rate = 7; 842 break; 843 default: 844 dev_err(va_dev, "%s: Invalid TX sample rate: %d\n", 845 __func__, params_rate(params)); 846 return -EINVAL; 847 } 848 849 for_each_set_bit(decimator, &va->active_ch_mask[dai->id], 850 VA_MACRO_DEC_MAX) { 851 tx_fs_reg = CDC_VA_TX0_TX_PATH_CTL + 852 VA_MACRO_TX_PATH_OFFSET * decimator; 853 snd_soc_component_update_bits(component, tx_fs_reg, 0x0F, 854 tx_fs_rate); 855 } 856 return 0; 857 } 858 859 static int va_macro_get_channel_map(struct snd_soc_dai *dai, 860 unsigned int *tx_num, unsigned int *tx_slot, 861 unsigned int *rx_num, unsigned int *rx_slot) 862 { 863 struct snd_soc_component *component = dai->component; 864 struct device *va_dev = component->dev; 865 struct va_macro *va = snd_soc_component_get_drvdata(component); 866 867 switch (dai->id) { 868 case VA_MACRO_AIF1_CAP: 869 case VA_MACRO_AIF2_CAP: 870 case VA_MACRO_AIF3_CAP: 871 *tx_slot = va->active_ch_mask[dai->id]; 872 *tx_num = va->active_ch_cnt[dai->id]; 873 break; 874 default: 875 dev_err(va_dev, "%s: Invalid AIF\n", __func__); 876 break; 877 } 878 return 0; 879 } 880 881 static int va_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 882 { 883 struct snd_soc_component *component = dai->component; 884 struct va_macro *va = snd_soc_component_get_drvdata(component); 885 u16 tx_vol_ctl_reg, decimator; 886 887 for_each_set_bit(decimator, &va->active_ch_mask[dai->id], 888 VA_MACRO_DEC_MAX) { 889 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL + 890 VA_MACRO_TX_PATH_OFFSET * decimator; 891 if (mute) 892 snd_soc_component_update_bits(component, tx_vol_ctl_reg, 893 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK, 894 CDC_VA_TX_PATH_PGA_MUTE_EN); 895 else 896 snd_soc_component_update_bits(component, tx_vol_ctl_reg, 897 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK, 898 CDC_VA_TX_PATH_PGA_MUTE_DISABLE); 899 } 900 901 return 0; 902 } 903 904 static const struct snd_soc_dai_ops va_macro_dai_ops = { 905 .hw_params = va_macro_hw_params, 906 .get_channel_map = va_macro_get_channel_map, 907 .mute_stream = va_macro_digital_mute, 908 }; 909 910 static struct snd_soc_dai_driver va_macro_dais[] = { 911 { 912 .name = "va_macro_tx1", 913 .id = VA_MACRO_AIF1_CAP, 914 .capture = { 915 .stream_name = "VA_AIF1 Capture", 916 .rates = VA_MACRO_RATES, 917 .formats = VA_MACRO_FORMATS, 918 .rate_max = 192000, 919 .rate_min = 8000, 920 .channels_min = 1, 921 .channels_max = 8, 922 }, 923 .ops = &va_macro_dai_ops, 924 }, 925 { 926 .name = "va_macro_tx2", 927 .id = VA_MACRO_AIF2_CAP, 928 .capture = { 929 .stream_name = "VA_AIF2 Capture", 930 .rates = VA_MACRO_RATES, 931 .formats = VA_MACRO_FORMATS, 932 .rate_max = 192000, 933 .rate_min = 8000, 934 .channels_min = 1, 935 .channels_max = 8, 936 }, 937 .ops = &va_macro_dai_ops, 938 }, 939 { 940 .name = "va_macro_tx3", 941 .id = VA_MACRO_AIF3_CAP, 942 .capture = { 943 .stream_name = "VA_AIF3 Capture", 944 .rates = VA_MACRO_RATES, 945 .formats = VA_MACRO_FORMATS, 946 .rate_max = 192000, 947 .rate_min = 8000, 948 .channels_min = 1, 949 .channels_max = 8, 950 }, 951 .ops = &va_macro_dai_ops, 952 }, 953 }; 954 955 static const char * const adc_mux_text[] = { 956 "VA_DMIC", "SWR_MIC" 957 }; 958 959 static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG1, 960 0, adc_mux_text); 961 static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG1, 962 0, adc_mux_text); 963 static SOC_ENUM_SINGLE_DECL(va_dec2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG1, 964 0, adc_mux_text); 965 static SOC_ENUM_SINGLE_DECL(va_dec3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG1, 966 0, adc_mux_text); 967 968 static const struct snd_kcontrol_new va_dec0_mux = SOC_DAPM_ENUM("va_dec0", 969 va_dec0_enum); 970 static const struct snd_kcontrol_new va_dec1_mux = SOC_DAPM_ENUM("va_dec1", 971 va_dec1_enum); 972 static const struct snd_kcontrol_new va_dec2_mux = SOC_DAPM_ENUM("va_dec2", 973 va_dec2_enum); 974 static const struct snd_kcontrol_new va_dec3_mux = SOC_DAPM_ENUM("va_dec3", 975 va_dec3_enum); 976 977 static const char * const dmic_mux_text[] = { 978 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", 979 "DMIC4", "DMIC5", "DMIC6", "DMIC7" 980 }; 981 982 static SOC_ENUM_SINGLE_DECL(va_dmic0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG0, 983 4, dmic_mux_text); 984 985 static SOC_ENUM_SINGLE_DECL(va_dmic1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG0, 986 4, dmic_mux_text); 987 988 static SOC_ENUM_SINGLE_DECL(va_dmic2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG0, 989 4, dmic_mux_text); 990 991 static SOC_ENUM_SINGLE_DECL(va_dmic3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG0, 992 4, dmic_mux_text); 993 994 static const struct snd_kcontrol_new va_dmic0_mux = SOC_DAPM_ENUM_EXT("va_dmic0", 995 va_dmic0_enum, snd_soc_dapm_get_enum_double, 996 va_macro_put_dec_enum); 997 998 static const struct snd_kcontrol_new va_dmic1_mux = SOC_DAPM_ENUM_EXT("va_dmic1", 999 va_dmic1_enum, snd_soc_dapm_get_enum_double, 1000 va_macro_put_dec_enum); 1001 1002 static const struct snd_kcontrol_new va_dmic2_mux = SOC_DAPM_ENUM_EXT("va_dmic2", 1003 va_dmic2_enum, snd_soc_dapm_get_enum_double, 1004 va_macro_put_dec_enum); 1005 1006 static const struct snd_kcontrol_new va_dmic3_mux = SOC_DAPM_ENUM_EXT("va_dmic3", 1007 va_dmic3_enum, snd_soc_dapm_get_enum_double, 1008 va_macro_put_dec_enum); 1009 1010 static const struct snd_kcontrol_new va_aif1_cap_mixer[] = { 1011 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0, 1012 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1013 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0, 1014 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1015 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0, 1016 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1017 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0, 1018 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1019 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0, 1020 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1021 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0, 1022 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1023 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0, 1024 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1025 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0, 1026 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1027 }; 1028 1029 static const struct snd_kcontrol_new va_aif2_cap_mixer[] = { 1030 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0, 1031 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1032 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0, 1033 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1034 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0, 1035 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1036 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0, 1037 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1038 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0, 1039 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1040 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0, 1041 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1042 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0, 1043 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1044 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0, 1045 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1046 }; 1047 1048 static const struct snd_kcontrol_new va_aif3_cap_mixer[] = { 1049 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0, 1050 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1051 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0, 1052 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1053 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0, 1054 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1055 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0, 1056 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1057 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0, 1058 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1059 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0, 1060 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1061 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0, 1062 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1063 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0, 1064 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1065 }; 1066 1067 static const struct snd_soc_dapm_widget va_macro_dapm_widgets[] = { 1068 SND_SOC_DAPM_AIF_OUT("VA_AIF1 CAP", "VA_AIF1 Capture", 0, 1069 SND_SOC_NOPM, VA_MACRO_AIF1_CAP, 0), 1070 1071 SND_SOC_DAPM_AIF_OUT("VA_AIF2 CAP", "VA_AIF2 Capture", 0, 1072 SND_SOC_NOPM, VA_MACRO_AIF2_CAP, 0), 1073 1074 SND_SOC_DAPM_AIF_OUT("VA_AIF3 CAP", "VA_AIF3 Capture", 0, 1075 SND_SOC_NOPM, VA_MACRO_AIF3_CAP, 0), 1076 1077 SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM, 1078 VA_MACRO_AIF1_CAP, 0, 1079 va_aif1_cap_mixer, ARRAY_SIZE(va_aif1_cap_mixer)), 1080 1081 SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM, 1082 VA_MACRO_AIF2_CAP, 0, 1083 va_aif2_cap_mixer, ARRAY_SIZE(va_aif2_cap_mixer)), 1084 1085 SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM, 1086 VA_MACRO_AIF3_CAP, 0, 1087 va_aif3_cap_mixer, ARRAY_SIZE(va_aif3_cap_mixer)), 1088 1089 SND_SOC_DAPM_MUX("VA DMIC MUX0", SND_SOC_NOPM, 0, 0, &va_dmic0_mux), 1090 SND_SOC_DAPM_MUX("VA DMIC MUX1", SND_SOC_NOPM, 0, 0, &va_dmic1_mux), 1091 SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux), 1092 SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux), 1093 1094 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0), 1095 SND_SOC_DAPM_INPUT("DMIC0 Pin"), 1096 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 1097 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 1098 SND_SOC_DAPM_INPUT("DMIC3 Pin"), 1099 SND_SOC_DAPM_INPUT("DMIC4 Pin"), 1100 SND_SOC_DAPM_INPUT("DMIC5 Pin"), 1101 SND_SOC_DAPM_INPUT("DMIC6 Pin"), 1102 SND_SOC_DAPM_INPUT("DMIC7 Pin"), 1103 1104 SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0, 1105 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1106 SND_SOC_DAPM_POST_PMD), 1107 1108 SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, SND_SOC_NOPM, 1, 0, 1109 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1110 SND_SOC_DAPM_POST_PMD), 1111 1112 SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, SND_SOC_NOPM, 2, 0, 1113 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1114 SND_SOC_DAPM_POST_PMD), 1115 1116 SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, SND_SOC_NOPM, 3, 0, 1117 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1118 SND_SOC_DAPM_POST_PMD), 1119 1120 SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, SND_SOC_NOPM, 4, 0, 1121 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1122 SND_SOC_DAPM_POST_PMD), 1123 1124 SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, SND_SOC_NOPM, 5, 0, 1125 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1126 SND_SOC_DAPM_POST_PMD), 1127 1128 SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, SND_SOC_NOPM, 6, 0, 1129 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1130 SND_SOC_DAPM_POST_PMD), 1131 1132 SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, SND_SOC_NOPM, 7, 0, 1133 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1134 SND_SOC_DAPM_POST_PMD), 1135 1136 SND_SOC_DAPM_INPUT("VA SWR_ADC0"), 1137 SND_SOC_DAPM_INPUT("VA SWR_ADC1"), 1138 SND_SOC_DAPM_INPUT("VA SWR_ADC2"), 1139 SND_SOC_DAPM_INPUT("VA SWR_ADC3"), 1140 SND_SOC_DAPM_INPUT("VA SWR_MIC0"), 1141 SND_SOC_DAPM_INPUT("VA SWR_MIC1"), 1142 SND_SOC_DAPM_INPUT("VA SWR_MIC2"), 1143 SND_SOC_DAPM_INPUT("VA SWR_MIC3"), 1144 SND_SOC_DAPM_INPUT("VA SWR_MIC4"), 1145 SND_SOC_DAPM_INPUT("VA SWR_MIC5"), 1146 SND_SOC_DAPM_INPUT("VA SWR_MIC6"), 1147 SND_SOC_DAPM_INPUT("VA SWR_MIC7"), 1148 1149 SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, VA_MACRO_DEC0, 0, 1150 &va_dec0_mux, va_macro_enable_dec, 1151 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1152 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1153 1154 SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, VA_MACRO_DEC1, 0, 1155 &va_dec1_mux, va_macro_enable_dec, 1156 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1157 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1158 1159 SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, VA_MACRO_DEC2, 0, 1160 &va_dec2_mux, va_macro_enable_dec, 1161 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1162 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1163 1164 SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, VA_MACRO_DEC3, 0, 1165 &va_dec3_mux, va_macro_enable_dec, 1166 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1167 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1168 1169 SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0, 1170 va_macro_mclk_event, 1171 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1172 }; 1173 1174 static const struct snd_soc_dapm_route va_audio_map[] = { 1175 {"VA_AIF1 CAP", NULL, "VA_MCLK"}, 1176 {"VA_AIF2 CAP", NULL, "VA_MCLK"}, 1177 {"VA_AIF3 CAP", NULL, "VA_MCLK"}, 1178 1179 {"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mixer"}, 1180 {"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mixer"}, 1181 {"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mixer"}, 1182 1183 {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"}, 1184 {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"}, 1185 {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"}, 1186 {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"}, 1187 1188 {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"}, 1189 {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"}, 1190 {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"}, 1191 {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"}, 1192 1193 {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"}, 1194 {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"}, 1195 {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"}, 1196 {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"}, 1197 1198 {"VA DEC0 MUX", "VA_DMIC", "VA DMIC MUX0"}, 1199 {"VA DMIC MUX0", "DMIC0", "VA DMIC0"}, 1200 {"VA DMIC MUX0", "DMIC1", "VA DMIC1"}, 1201 {"VA DMIC MUX0", "DMIC2", "VA DMIC2"}, 1202 {"VA DMIC MUX0", "DMIC3", "VA DMIC3"}, 1203 {"VA DMIC MUX0", "DMIC4", "VA DMIC4"}, 1204 {"VA DMIC MUX0", "DMIC5", "VA DMIC5"}, 1205 {"VA DMIC MUX0", "DMIC6", "VA DMIC6"}, 1206 {"VA DMIC MUX0", "DMIC7", "VA DMIC7"}, 1207 1208 {"VA DEC1 MUX", "VA_DMIC", "VA DMIC MUX1"}, 1209 {"VA DMIC MUX1", "DMIC0", "VA DMIC0"}, 1210 {"VA DMIC MUX1", "DMIC1", "VA DMIC1"}, 1211 {"VA DMIC MUX1", "DMIC2", "VA DMIC2"}, 1212 {"VA DMIC MUX1", "DMIC3", "VA DMIC3"}, 1213 {"VA DMIC MUX1", "DMIC4", "VA DMIC4"}, 1214 {"VA DMIC MUX1", "DMIC5", "VA DMIC5"}, 1215 {"VA DMIC MUX1", "DMIC6", "VA DMIC6"}, 1216 {"VA DMIC MUX1", "DMIC7", "VA DMIC7"}, 1217 1218 {"VA DEC2 MUX", "VA_DMIC", "VA DMIC MUX2"}, 1219 {"VA DMIC MUX2", "DMIC0", "VA DMIC0"}, 1220 {"VA DMIC MUX2", "DMIC1", "VA DMIC1"}, 1221 {"VA DMIC MUX2", "DMIC2", "VA DMIC2"}, 1222 {"VA DMIC MUX2", "DMIC3", "VA DMIC3"}, 1223 {"VA DMIC MUX2", "DMIC4", "VA DMIC4"}, 1224 {"VA DMIC MUX2", "DMIC5", "VA DMIC5"}, 1225 {"VA DMIC MUX2", "DMIC6", "VA DMIC6"}, 1226 {"VA DMIC MUX2", "DMIC7", "VA DMIC7"}, 1227 1228 {"VA DEC3 MUX", "VA_DMIC", "VA DMIC MUX3"}, 1229 {"VA DMIC MUX3", "DMIC0", "VA DMIC0"}, 1230 {"VA DMIC MUX3", "DMIC1", "VA DMIC1"}, 1231 {"VA DMIC MUX3", "DMIC2", "VA DMIC2"}, 1232 {"VA DMIC MUX3", "DMIC3", "VA DMIC3"}, 1233 {"VA DMIC MUX3", "DMIC4", "VA DMIC4"}, 1234 {"VA DMIC MUX3", "DMIC5", "VA DMIC5"}, 1235 {"VA DMIC MUX3", "DMIC6", "VA DMIC6"}, 1236 {"VA DMIC MUX3", "DMIC7", "VA DMIC7"}, 1237 1238 { "VA DMIC0", NULL, "DMIC0 Pin" }, 1239 { "VA DMIC1", NULL, "DMIC1 Pin" }, 1240 { "VA DMIC2", NULL, "DMIC2 Pin" }, 1241 { "VA DMIC3", NULL, "DMIC3 Pin" }, 1242 { "VA DMIC4", NULL, "DMIC4 Pin" }, 1243 { "VA DMIC5", NULL, "DMIC5 Pin" }, 1244 { "VA DMIC6", NULL, "DMIC6 Pin" }, 1245 { "VA DMIC7", NULL, "DMIC7 Pin" }, 1246 }; 1247 1248 static const char * const dec_mode_mux_text[] = { 1249 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF", 1250 }; 1251 1252 static const struct soc_enum dec_mode_mux_enum[] = { 1253 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text), 1254 dec_mode_mux_text), 1255 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text), 1256 dec_mode_mux_text), 1257 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text), 1258 dec_mode_mux_text), 1259 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text), 1260 dec_mode_mux_text), 1261 }; 1262 1263 static const struct snd_kcontrol_new va_macro_snd_controls[] = { 1264 SOC_SINGLE_S8_TLV("VA_DEC0 Volume", CDC_VA_TX0_TX_VOL_CTL, 1265 -84, 40, digital_gain), 1266 SOC_SINGLE_S8_TLV("VA_DEC1 Volume", CDC_VA_TX1_TX_VOL_CTL, 1267 -84, 40, digital_gain), 1268 SOC_SINGLE_S8_TLV("VA_DEC2 Volume", CDC_VA_TX2_TX_VOL_CTL, 1269 -84, 40, digital_gain), 1270 SOC_SINGLE_S8_TLV("VA_DEC3 Volume", CDC_VA_TX3_TX_VOL_CTL, 1271 -84, 40, digital_gain), 1272 1273 SOC_ENUM_EXT("VA_DEC0 MODE", dec_mode_mux_enum[0], 1274 va_macro_dec_mode_get, va_macro_dec_mode_put), 1275 SOC_ENUM_EXT("VA_DEC1 MODE", dec_mode_mux_enum[1], 1276 va_macro_dec_mode_get, va_macro_dec_mode_put), 1277 SOC_ENUM_EXT("VA_DEC2 MODE", dec_mode_mux_enum[2], 1278 va_macro_dec_mode_get, va_macro_dec_mode_put), 1279 SOC_ENUM_EXT("VA_DEC3 MODE", dec_mode_mux_enum[3], 1280 va_macro_dec_mode_get, va_macro_dec_mode_put), 1281 }; 1282 1283 static int va_macro_component_probe(struct snd_soc_component *component) 1284 { 1285 struct va_macro *va = snd_soc_component_get_drvdata(component); 1286 1287 snd_soc_component_init_regmap(component, va->regmap); 1288 1289 return 0; 1290 } 1291 1292 static const struct snd_soc_component_driver va_macro_component_drv = { 1293 .name = "VA MACRO", 1294 .probe = va_macro_component_probe, 1295 .controls = va_macro_snd_controls, 1296 .num_controls = ARRAY_SIZE(va_macro_snd_controls), 1297 .dapm_widgets = va_macro_dapm_widgets, 1298 .num_dapm_widgets = ARRAY_SIZE(va_macro_dapm_widgets), 1299 .dapm_routes = va_audio_map, 1300 .num_dapm_routes = ARRAY_SIZE(va_audio_map), 1301 }; 1302 1303 static int fsgen_gate_enable(struct clk_hw *hw) 1304 { 1305 return va_macro_mclk_enable(to_va_macro(hw), true); 1306 } 1307 1308 static void fsgen_gate_disable(struct clk_hw *hw) 1309 { 1310 va_macro_mclk_enable(to_va_macro(hw), false); 1311 } 1312 1313 static int fsgen_gate_is_enabled(struct clk_hw *hw) 1314 { 1315 struct va_macro *va = to_va_macro(hw); 1316 int val; 1317 1318 regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val); 1319 1320 return !!(val & CDC_VA_FS_BROADCAST_EN); 1321 } 1322 1323 static const struct clk_ops fsgen_gate_ops = { 1324 .prepare = fsgen_gate_enable, 1325 .unprepare = fsgen_gate_disable, 1326 .is_enabled = fsgen_gate_is_enabled, 1327 }; 1328 1329 static int va_macro_register_fsgen_output(struct va_macro *va) 1330 { 1331 struct clk *parent = va->mclk; 1332 struct device *dev = va->dev; 1333 struct device_node *np = dev->of_node; 1334 const char *parent_clk_name; 1335 const char *clk_name = "fsgen"; 1336 struct clk_init_data init; 1337 int ret; 1338 1339 parent_clk_name = __clk_get_name(parent); 1340 1341 of_property_read_string(np, "clock-output-names", &clk_name); 1342 1343 init.name = clk_name; 1344 init.ops = &fsgen_gate_ops; 1345 init.flags = 0; 1346 init.parent_names = &parent_clk_name; 1347 init.num_parents = 1; 1348 va->hw.init = &init; 1349 ret = devm_clk_hw_register(va->dev, &va->hw); 1350 if (ret) 1351 return ret; 1352 1353 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &va->hw); 1354 } 1355 1356 static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate, 1357 struct va_macro *va) 1358 { 1359 u32 div_factor; 1360 u32 mclk_rate = VA_MACRO_MCLK_FREQ; 1361 1362 if (!dmic_sample_rate || mclk_rate % dmic_sample_rate != 0) 1363 goto undefined_rate; 1364 1365 div_factor = mclk_rate / dmic_sample_rate; 1366 1367 switch (div_factor) { 1368 case 2: 1369 va->dmic_clk_div = VA_MACRO_CLK_DIV_2; 1370 break; 1371 case 3: 1372 va->dmic_clk_div = VA_MACRO_CLK_DIV_3; 1373 break; 1374 case 4: 1375 va->dmic_clk_div = VA_MACRO_CLK_DIV_4; 1376 break; 1377 case 6: 1378 va->dmic_clk_div = VA_MACRO_CLK_DIV_6; 1379 break; 1380 case 8: 1381 va->dmic_clk_div = VA_MACRO_CLK_DIV_8; 1382 break; 1383 case 16: 1384 va->dmic_clk_div = VA_MACRO_CLK_DIV_16; 1385 break; 1386 default: 1387 /* Any other DIV factor is invalid */ 1388 goto undefined_rate; 1389 } 1390 1391 return dmic_sample_rate; 1392 1393 undefined_rate: 1394 dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n", 1395 __func__, dmic_sample_rate, mclk_rate); 1396 dmic_sample_rate = 0; 1397 1398 return dmic_sample_rate; 1399 } 1400 1401 static int va_macro_probe(struct platform_device *pdev) 1402 { 1403 struct device *dev = &pdev->dev; 1404 struct va_macro *va; 1405 void __iomem *base; 1406 u32 sample_rate = 0; 1407 int ret; 1408 1409 va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL); 1410 if (!va) 1411 return -ENOMEM; 1412 1413 va->dev = dev; 1414 1415 va->macro = devm_clk_get_optional(dev, "macro"); 1416 if (IS_ERR(va->macro)) 1417 return PTR_ERR(va->macro); 1418 1419 va->dcodec = devm_clk_get_optional(dev, "dcodec"); 1420 if (IS_ERR(va->dcodec)) 1421 return PTR_ERR(va->dcodec); 1422 1423 va->mclk = devm_clk_get(dev, "mclk"); 1424 if (IS_ERR(va->mclk)) 1425 return PTR_ERR(va->mclk); 1426 1427 va->pds = lpass_macro_pds_init(dev); 1428 if (IS_ERR(va->pds)) 1429 return PTR_ERR(va->pds); 1430 1431 ret = of_property_read_u32(dev->of_node, "qcom,dmic-sample-rate", 1432 &sample_rate); 1433 if (ret) { 1434 dev_err(dev, "qcom,dmic-sample-rate dt entry missing\n"); 1435 va->dmic_clk_div = VA_MACRO_CLK_DIV_2; 1436 } else { 1437 ret = va_macro_validate_dmic_sample_rate(sample_rate, va); 1438 if (!ret) { 1439 ret = -EINVAL; 1440 goto err; 1441 } 1442 } 1443 1444 base = devm_platform_ioremap_resource(pdev, 0); 1445 if (IS_ERR(base)) { 1446 ret = PTR_ERR(base); 1447 goto err; 1448 } 1449 1450 va->regmap = devm_regmap_init_mmio(dev, base, &va_regmap_config); 1451 if (IS_ERR(va->regmap)) { 1452 ret = -EINVAL; 1453 goto err; 1454 } 1455 1456 dev_set_drvdata(dev, va); 1457 1458 /* mclk rate */ 1459 clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ); 1460 1461 ret = clk_prepare_enable(va->macro); 1462 if (ret) 1463 goto err; 1464 1465 ret = clk_prepare_enable(va->dcodec); 1466 if (ret) 1467 goto err_dcodec; 1468 1469 ret = clk_prepare_enable(va->mclk); 1470 if (ret) 1471 goto err_mclk; 1472 1473 ret = va_macro_register_fsgen_output(va); 1474 if (ret) 1475 goto err_clkout; 1476 1477 va->fsgen = clk_hw_get_clk(&va->hw, "fsgen"); 1478 if (IS_ERR(va->fsgen)) { 1479 ret = PTR_ERR(va->fsgen); 1480 goto err_clkout; 1481 } 1482 1483 ret = devm_snd_soc_register_component(dev, &va_macro_component_drv, 1484 va_macro_dais, 1485 ARRAY_SIZE(va_macro_dais)); 1486 if (ret) 1487 goto err_clkout; 1488 1489 pm_runtime_set_autosuspend_delay(dev, 3000); 1490 pm_runtime_use_autosuspend(dev); 1491 pm_runtime_mark_last_busy(dev); 1492 pm_runtime_set_active(dev); 1493 pm_runtime_enable(dev); 1494 1495 return 0; 1496 1497 err_clkout: 1498 clk_disable_unprepare(va->mclk); 1499 err_mclk: 1500 clk_disable_unprepare(va->dcodec); 1501 err_dcodec: 1502 clk_disable_unprepare(va->macro); 1503 err: 1504 lpass_macro_pds_exit(va->pds); 1505 1506 return ret; 1507 } 1508 1509 static int va_macro_remove(struct platform_device *pdev) 1510 { 1511 struct va_macro *va = dev_get_drvdata(&pdev->dev); 1512 1513 clk_disable_unprepare(va->mclk); 1514 clk_disable_unprepare(va->dcodec); 1515 clk_disable_unprepare(va->macro); 1516 1517 lpass_macro_pds_exit(va->pds); 1518 1519 return 0; 1520 } 1521 1522 static int __maybe_unused va_macro_runtime_suspend(struct device *dev) 1523 { 1524 struct va_macro *va = dev_get_drvdata(dev); 1525 1526 regcache_cache_only(va->regmap, true); 1527 regcache_mark_dirty(va->regmap); 1528 1529 clk_disable_unprepare(va->mclk); 1530 1531 return 0; 1532 } 1533 1534 static int __maybe_unused va_macro_runtime_resume(struct device *dev) 1535 { 1536 struct va_macro *va = dev_get_drvdata(dev); 1537 int ret; 1538 1539 ret = clk_prepare_enable(va->mclk); 1540 if (ret) { 1541 dev_err(va->dev, "unable to prepare mclk\n"); 1542 return ret; 1543 } 1544 1545 regcache_cache_only(va->regmap, false); 1546 regcache_sync(va->regmap); 1547 1548 return 0; 1549 } 1550 1551 1552 static const struct dev_pm_ops va_macro_pm_ops = { 1553 SET_RUNTIME_PM_OPS(va_macro_runtime_suspend, va_macro_runtime_resume, NULL) 1554 }; 1555 1556 static const struct of_device_id va_macro_dt_match[] = { 1557 { .compatible = "qcom,sc7280-lpass-va-macro" }, 1558 { .compatible = "qcom,sm8250-lpass-va-macro" }, 1559 {} 1560 }; 1561 MODULE_DEVICE_TABLE(of, va_macro_dt_match); 1562 1563 static struct platform_driver va_macro_driver = { 1564 .driver = { 1565 .name = "va_macro", 1566 .of_match_table = va_macro_dt_match, 1567 .suppress_bind_attrs = true, 1568 .pm = &va_macro_pm_ops, 1569 }, 1570 .probe = va_macro_probe, 1571 .remove = va_macro_remove, 1572 }; 1573 1574 module_platform_driver(va_macro_driver); 1575 MODULE_DESCRIPTION("VA macro driver"); 1576 MODULE_LICENSE("GPL"); 1577