1 // SPDX-License-Identifier: GPL-2.0-only 2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. 3 4 #include <linux/clk.h> 5 #include <linux/clk-provider.h> 6 #include <linux/init.h> 7 #include <linux/io.h> 8 #include <linux/module.h> 9 #include <linux/of_clk.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/regmap.h> 13 #include <linux/regulator/consumer.h> 14 #include <sound/soc.h> 15 #include <sound/soc-dapm.h> 16 #include <sound/tlv.h> 17 18 /* VA macro registers */ 19 #define CDC_VA_CLK_RST_CTRL_MCLK_CONTROL (0x0000) 20 #define CDC_VA_MCLK_CONTROL_EN BIT(0) 21 #define CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004) 22 #define CDC_VA_FS_CONTROL_EN BIT(0) 23 #define CDC_VA_CLK_RST_CTRL_SWR_CONTROL (0x0008) 24 #define CDC_VA_TOP_CSR_TOP_CFG0 (0x0080) 25 #define CDC_VA_FS_BROADCAST_EN BIT(1) 26 #define CDC_VA_TOP_CSR_DMIC0_CTL (0x0084) 27 #define CDC_VA_TOP_CSR_DMIC1_CTL (0x0088) 28 #define CDC_VA_TOP_CSR_DMIC2_CTL (0x008C) 29 #define CDC_VA_TOP_CSR_DMIC3_CTL (0x0090) 30 #define CDC_VA_DMIC_EN_MASK BIT(0) 31 #define CDC_VA_DMIC_ENABLE BIT(0) 32 #define CDC_VA_DMIC_CLK_SEL_MASK GENMASK(3, 1) 33 #define CDC_VA_DMIC_CLK_SEL_SHFT 1 34 #define CDC_VA_DMIC_CLK_SEL_DIV0 0x0 35 #define CDC_VA_DMIC_CLK_SEL_DIV1 0x2 36 #define CDC_VA_DMIC_CLK_SEL_DIV2 0x4 37 #define CDC_VA_DMIC_CLK_SEL_DIV3 0x6 38 #define CDC_VA_DMIC_CLK_SEL_DIV4 0x8 39 #define CDC_VA_DMIC_CLK_SEL_DIV5 0xa 40 #define CDC_VA_TOP_CSR_DMIC_CFG (0x0094) 41 #define CDC_VA_RESET_ALL_DMICS_MASK BIT(7) 42 #define CDC_VA_RESET_ALL_DMICS_RESET BIT(7) 43 #define CDC_VA_RESET_ALL_DMICS_DISABLE 0 44 #define CDC_VA_DMIC3_FREQ_CHANGE_MASK BIT(3) 45 #define CDC_VA_DMIC3_FREQ_CHANGE_EN BIT(3) 46 #define CDC_VA_DMIC2_FREQ_CHANGE_MASK BIT(2) 47 #define CDC_VA_DMIC2_FREQ_CHANGE_EN BIT(2) 48 #define CDC_VA_DMIC1_FREQ_CHANGE_MASK BIT(1) 49 #define CDC_VA_DMIC1_FREQ_CHANGE_EN BIT(1) 50 #define CDC_VA_DMIC0_FREQ_CHANGE_MASK BIT(0) 51 #define CDC_VA_DMIC0_FREQ_CHANGE_EN BIT(0) 52 #define CDC_VA_DMIC_FREQ_CHANGE_DISABLE 0 53 #define CDC_VA_TOP_CSR_DEBUG_BUS (0x009C) 54 #define CDC_VA_TOP_CSR_DEBUG_EN (0x00A0) 55 #define CDC_VA_TOP_CSR_TX_I2S_CTL (0x00A4) 56 #define CDC_VA_TOP_CSR_I2S_CLK (0x00A8) 57 #define CDC_VA_TOP_CSR_I2S_RESET (0x00AC) 58 #define CDC_VA_TOP_CSR_CORE_ID_0 (0x00C0) 59 #define CDC_VA_TOP_CSR_CORE_ID_1 (0x00C4) 60 #define CDC_VA_TOP_CSR_CORE_ID_2 (0x00C8) 61 #define CDC_VA_TOP_CSR_CORE_ID_3 (0x00CC) 62 #define CDC_VA_TOP_CSR_SWR_MIC_CTL0 (0x00D0) 63 #define CDC_VA_TOP_CSR_SWR_MIC_CTL1 (0x00D4) 64 #define CDC_VA_TOP_CSR_SWR_MIC_CTL2 (0x00D8) 65 #define CDC_VA_TOP_CSR_SWR_CTRL (0x00DC) 66 #define CDC_VA_INP_MUX_ADC_MUX0_CFG0 (0x0100) 67 #define CDC_VA_INP_MUX_ADC_MUX0_CFG1 (0x0104) 68 #define CDC_VA_INP_MUX_ADC_MUX1_CFG0 (0x0108) 69 #define CDC_VA_INP_MUX_ADC_MUX1_CFG1 (0x010C) 70 #define CDC_VA_INP_MUX_ADC_MUX2_CFG0 (0x0110) 71 #define CDC_VA_INP_MUX_ADC_MUX2_CFG1 (0x0114) 72 #define CDC_VA_INP_MUX_ADC_MUX3_CFG0 (0x0118) 73 #define CDC_VA_INP_MUX_ADC_MUX3_CFG1 (0x011C) 74 #define CDC_VA_TX0_TX_PATH_CTL (0x0400) 75 #define CDC_VA_TX_PATH_CLK_EN_MASK BIT(5) 76 #define CDC_VA_TX_PATH_CLK_EN BIT(5) 77 #define CDC_VA_TX_PATH_CLK_DISABLE 0 78 #define CDC_VA_TX_PATH_PGA_MUTE_EN_MASK BIT(4) 79 #define CDC_VA_TX_PATH_PGA_MUTE_EN BIT(4) 80 #define CDC_VA_TX_PATH_PGA_MUTE_DISABLE 0 81 #define CDC_VA_TX0_TX_PATH_CFG0 (0x0404) 82 #define CDC_VA_ADC_MODE_MASK GENMASK(2, 1) 83 #define CDC_VA_ADC_MODE_SHIFT 1 84 #define TX_HPF_CUT_OFF_FREQ_MASK GENMASK(6, 5) 85 #define CF_MIN_3DB_4HZ 0x0 86 #define CF_MIN_3DB_75HZ 0x1 87 #define CF_MIN_3DB_150HZ 0x2 88 #define CDC_VA_TX0_TX_PATH_CFG1 (0x0408) 89 #define CDC_VA_TX0_TX_VOL_CTL (0x040C) 90 #define CDC_VA_TX0_TX_PATH_SEC0 (0x0410) 91 #define CDC_VA_TX0_TX_PATH_SEC1 (0x0414) 92 #define CDC_VA_TX0_TX_PATH_SEC2 (0x0418) 93 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK BIT(1) 94 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ BIT(1) 95 #define CDC_VA_TX_HPF_ZERO_GATE_MASK BIT(0) 96 #define CDC_VA_TX_HPF_ZERO_NO_GATE BIT(0) 97 #define CDC_VA_TX_HPF_ZERO_GATE 0 98 #define CDC_VA_TX0_TX_PATH_SEC3 (0x041C) 99 #define CDC_VA_TX0_TX_PATH_SEC4 (0x0420) 100 #define CDC_VA_TX0_TX_PATH_SEC5 (0x0424) 101 #define CDC_VA_TX0_TX_PATH_SEC6 (0x0428) 102 #define CDC_VA_TX0_TX_PATH_SEC7 (0x042C) 103 #define CDC_VA_TX1_TX_PATH_CTL (0x0480) 104 #define CDC_VA_TX1_TX_PATH_CFG0 (0x0484) 105 #define CDC_VA_TX1_TX_PATH_CFG1 (0x0488) 106 #define CDC_VA_TX1_TX_VOL_CTL (0x048C) 107 #define CDC_VA_TX1_TX_PATH_SEC0 (0x0490) 108 #define CDC_VA_TX1_TX_PATH_SEC1 (0x0494) 109 #define CDC_VA_TX1_TX_PATH_SEC2 (0x0498) 110 #define CDC_VA_TX1_TX_PATH_SEC3 (0x049C) 111 #define CDC_VA_TX1_TX_PATH_SEC4 (0x04A0) 112 #define CDC_VA_TX1_TX_PATH_SEC5 (0x04A4) 113 #define CDC_VA_TX1_TX_PATH_SEC6 (0x04A8) 114 #define CDC_VA_TX2_TX_PATH_CTL (0x0500) 115 #define CDC_VA_TX2_TX_PATH_CFG0 (0x0504) 116 #define CDC_VA_TX2_TX_PATH_CFG1 (0x0508) 117 #define CDC_VA_TX2_TX_VOL_CTL (0x050C) 118 #define CDC_VA_TX2_TX_PATH_SEC0 (0x0510) 119 #define CDC_VA_TX2_TX_PATH_SEC1 (0x0514) 120 #define CDC_VA_TX2_TX_PATH_SEC2 (0x0518) 121 #define CDC_VA_TX2_TX_PATH_SEC3 (0x051C) 122 #define CDC_VA_TX2_TX_PATH_SEC4 (0x0520) 123 #define CDC_VA_TX2_TX_PATH_SEC5 (0x0524) 124 #define CDC_VA_TX2_TX_PATH_SEC6 (0x0528) 125 #define CDC_VA_TX3_TX_PATH_CTL (0x0580) 126 #define CDC_VA_TX3_TX_PATH_CFG0 (0x0584) 127 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK BIT(7) 128 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC BIT(7) 129 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_ADC 0 130 #define CDC_VA_TX3_TX_PATH_CFG1 (0x0588) 131 #define CDC_VA_TX3_TX_VOL_CTL (0x058C) 132 #define CDC_VA_TX3_TX_PATH_SEC0 (0x0590) 133 #define CDC_VA_TX3_TX_PATH_SEC1 (0x0594) 134 #define CDC_VA_TX3_TX_PATH_SEC2 (0x0598) 135 #define CDC_VA_TX3_TX_PATH_SEC3 (0x059C) 136 #define CDC_VA_TX3_TX_PATH_SEC4 (0x05A0) 137 #define CDC_VA_TX3_TX_PATH_SEC5 (0x05A4) 138 #define CDC_VA_TX3_TX_PATH_SEC6 (0x05A8) 139 140 #define VA_MAX_OFFSET (0x07A8) 141 142 #define VA_MACRO_NUM_DECIMATORS 4 143 #define VA_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ 144 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ 145 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) 146 #define VA_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 147 SNDRV_PCM_FMTBIT_S24_LE |\ 148 SNDRV_PCM_FMTBIT_S24_3LE) 149 150 #define VA_MACRO_MCLK_FREQ 9600000 151 #define VA_MACRO_TX_PATH_OFFSET 0x80 152 #define VA_MACRO_SWR_MIC_MUX_SEL_MASK 0xF 153 #define VA_MACRO_ADC_MUX_CFG_OFFSET 0x8 154 155 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400); 156 157 enum { 158 VA_MACRO_AIF_INVALID = 0, 159 VA_MACRO_AIF1_CAP, 160 VA_MACRO_AIF2_CAP, 161 VA_MACRO_AIF3_CAP, 162 VA_MACRO_MAX_DAIS, 163 }; 164 165 enum { 166 VA_MACRO_DEC0, 167 VA_MACRO_DEC1, 168 VA_MACRO_DEC2, 169 VA_MACRO_DEC3, 170 VA_MACRO_DEC4, 171 VA_MACRO_DEC5, 172 VA_MACRO_DEC6, 173 VA_MACRO_DEC7, 174 VA_MACRO_DEC_MAX, 175 }; 176 177 enum { 178 VA_MACRO_CLK_DIV_2, 179 VA_MACRO_CLK_DIV_3, 180 VA_MACRO_CLK_DIV_4, 181 VA_MACRO_CLK_DIV_6, 182 VA_MACRO_CLK_DIV_8, 183 VA_MACRO_CLK_DIV_16, 184 }; 185 186 #define VA_NUM_CLKS_MAX 3 187 188 struct va_macro { 189 struct device *dev; 190 unsigned long active_ch_mask[VA_MACRO_MAX_DAIS]; 191 unsigned long active_ch_cnt[VA_MACRO_MAX_DAIS]; 192 unsigned long active_decimator[VA_MACRO_MAX_DAIS]; 193 u16 dmic_clk_div; 194 195 int dec_mode[VA_MACRO_NUM_DECIMATORS]; 196 struct regmap *regmap; 197 struct clk_bulk_data clks[VA_NUM_CLKS_MAX]; 198 struct clk_hw hw; 199 200 s32 dmic_0_1_clk_cnt; 201 s32 dmic_2_3_clk_cnt; 202 s32 dmic_4_5_clk_cnt; 203 s32 dmic_6_7_clk_cnt; 204 u8 dmic_0_1_clk_div; 205 u8 dmic_2_3_clk_div; 206 u8 dmic_4_5_clk_div; 207 u8 dmic_6_7_clk_div; 208 }; 209 210 #define to_va_macro(_hw) container_of(_hw, struct va_macro, hw) 211 212 static bool va_is_volatile_register(struct device *dev, unsigned int reg) 213 { 214 switch (reg) { 215 case CDC_VA_TOP_CSR_CORE_ID_0: 216 case CDC_VA_TOP_CSR_CORE_ID_1: 217 case CDC_VA_TOP_CSR_CORE_ID_2: 218 case CDC_VA_TOP_CSR_CORE_ID_3: 219 case CDC_VA_TOP_CSR_DMIC0_CTL: 220 case CDC_VA_TOP_CSR_DMIC1_CTL: 221 case CDC_VA_TOP_CSR_DMIC2_CTL: 222 case CDC_VA_TOP_CSR_DMIC3_CTL: 223 return true; 224 } 225 return false; 226 } 227 228 static const struct reg_default va_defaults[] = { 229 /* VA macro */ 230 { CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 0x00}, 231 { CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00}, 232 { CDC_VA_CLK_RST_CTRL_SWR_CONTROL, 0x00}, 233 { CDC_VA_TOP_CSR_TOP_CFG0, 0x00}, 234 { CDC_VA_TOP_CSR_DMIC0_CTL, 0x00}, 235 { CDC_VA_TOP_CSR_DMIC1_CTL, 0x00}, 236 { CDC_VA_TOP_CSR_DMIC2_CTL, 0x00}, 237 { CDC_VA_TOP_CSR_DMIC3_CTL, 0x00}, 238 { CDC_VA_TOP_CSR_DMIC_CFG, 0x80}, 239 { CDC_VA_TOP_CSR_DEBUG_BUS, 0x00}, 240 { CDC_VA_TOP_CSR_DEBUG_EN, 0x00}, 241 { CDC_VA_TOP_CSR_TX_I2S_CTL, 0x0C}, 242 { CDC_VA_TOP_CSR_I2S_CLK, 0x00}, 243 { CDC_VA_TOP_CSR_I2S_RESET, 0x00}, 244 { CDC_VA_TOP_CSR_CORE_ID_0, 0x00}, 245 { CDC_VA_TOP_CSR_CORE_ID_1, 0x00}, 246 { CDC_VA_TOP_CSR_CORE_ID_2, 0x00}, 247 { CDC_VA_TOP_CSR_CORE_ID_3, 0x00}, 248 { CDC_VA_TOP_CSR_SWR_MIC_CTL0, 0xEE}, 249 { CDC_VA_TOP_CSR_SWR_MIC_CTL1, 0xEE}, 250 { CDC_VA_TOP_CSR_SWR_MIC_CTL2, 0xEE}, 251 { CDC_VA_TOP_CSR_SWR_CTRL, 0x06}, 252 253 /* VA core */ 254 { CDC_VA_INP_MUX_ADC_MUX0_CFG0, 0x00}, 255 { CDC_VA_INP_MUX_ADC_MUX0_CFG1, 0x00}, 256 { CDC_VA_INP_MUX_ADC_MUX1_CFG0, 0x00}, 257 { CDC_VA_INP_MUX_ADC_MUX1_CFG1, 0x00}, 258 { CDC_VA_INP_MUX_ADC_MUX2_CFG0, 0x00}, 259 { CDC_VA_INP_MUX_ADC_MUX2_CFG1, 0x00}, 260 { CDC_VA_INP_MUX_ADC_MUX3_CFG0, 0x00}, 261 { CDC_VA_INP_MUX_ADC_MUX3_CFG1, 0x00}, 262 { CDC_VA_TX0_TX_PATH_CTL, 0x04}, 263 { CDC_VA_TX0_TX_PATH_CFG0, 0x10}, 264 { CDC_VA_TX0_TX_PATH_CFG1, 0x0B}, 265 { CDC_VA_TX0_TX_VOL_CTL, 0x00}, 266 { CDC_VA_TX0_TX_PATH_SEC0, 0x00}, 267 { CDC_VA_TX0_TX_PATH_SEC1, 0x00}, 268 { CDC_VA_TX0_TX_PATH_SEC2, 0x01}, 269 { CDC_VA_TX0_TX_PATH_SEC3, 0x3C}, 270 { CDC_VA_TX0_TX_PATH_SEC4, 0x20}, 271 { CDC_VA_TX0_TX_PATH_SEC5, 0x00}, 272 { CDC_VA_TX0_TX_PATH_SEC6, 0x00}, 273 { CDC_VA_TX0_TX_PATH_SEC7, 0x25}, 274 { CDC_VA_TX1_TX_PATH_CTL, 0x04}, 275 { CDC_VA_TX1_TX_PATH_CFG0, 0x10}, 276 { CDC_VA_TX1_TX_PATH_CFG1, 0x0B}, 277 { CDC_VA_TX1_TX_VOL_CTL, 0x00}, 278 { CDC_VA_TX1_TX_PATH_SEC0, 0x00}, 279 { CDC_VA_TX1_TX_PATH_SEC1, 0x00}, 280 { CDC_VA_TX1_TX_PATH_SEC2, 0x01}, 281 { CDC_VA_TX1_TX_PATH_SEC3, 0x3C}, 282 { CDC_VA_TX1_TX_PATH_SEC4, 0x20}, 283 { CDC_VA_TX1_TX_PATH_SEC5, 0x00}, 284 { CDC_VA_TX1_TX_PATH_SEC6, 0x00}, 285 { CDC_VA_TX2_TX_PATH_CTL, 0x04}, 286 { CDC_VA_TX2_TX_PATH_CFG0, 0x10}, 287 { CDC_VA_TX2_TX_PATH_CFG1, 0x0B}, 288 { CDC_VA_TX2_TX_VOL_CTL, 0x00}, 289 { CDC_VA_TX2_TX_PATH_SEC0, 0x00}, 290 { CDC_VA_TX2_TX_PATH_SEC1, 0x00}, 291 { CDC_VA_TX2_TX_PATH_SEC2, 0x01}, 292 { CDC_VA_TX2_TX_PATH_SEC3, 0x3C}, 293 { CDC_VA_TX2_TX_PATH_SEC4, 0x20}, 294 { CDC_VA_TX2_TX_PATH_SEC5, 0x00}, 295 { CDC_VA_TX2_TX_PATH_SEC6, 0x00}, 296 { CDC_VA_TX3_TX_PATH_CTL, 0x04}, 297 { CDC_VA_TX3_TX_PATH_CFG0, 0x10}, 298 { CDC_VA_TX3_TX_PATH_CFG1, 0x0B}, 299 { CDC_VA_TX3_TX_VOL_CTL, 0x00}, 300 { CDC_VA_TX3_TX_PATH_SEC0, 0x00}, 301 { CDC_VA_TX3_TX_PATH_SEC1, 0x00}, 302 { CDC_VA_TX3_TX_PATH_SEC2, 0x01}, 303 { CDC_VA_TX3_TX_PATH_SEC3, 0x3C}, 304 { CDC_VA_TX3_TX_PATH_SEC4, 0x20}, 305 { CDC_VA_TX3_TX_PATH_SEC5, 0x00}, 306 { CDC_VA_TX3_TX_PATH_SEC6, 0x00}, 307 }; 308 309 static bool va_is_rw_register(struct device *dev, unsigned int reg) 310 { 311 switch (reg) { 312 case CDC_VA_CLK_RST_CTRL_MCLK_CONTROL: 313 case CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL: 314 case CDC_VA_CLK_RST_CTRL_SWR_CONTROL: 315 case CDC_VA_TOP_CSR_TOP_CFG0: 316 case CDC_VA_TOP_CSR_DMIC0_CTL: 317 case CDC_VA_TOP_CSR_DMIC1_CTL: 318 case CDC_VA_TOP_CSR_DMIC2_CTL: 319 case CDC_VA_TOP_CSR_DMIC3_CTL: 320 case CDC_VA_TOP_CSR_DMIC_CFG: 321 case CDC_VA_TOP_CSR_DEBUG_BUS: 322 case CDC_VA_TOP_CSR_DEBUG_EN: 323 case CDC_VA_TOP_CSR_TX_I2S_CTL: 324 case CDC_VA_TOP_CSR_I2S_CLK: 325 case CDC_VA_TOP_CSR_I2S_RESET: 326 case CDC_VA_INP_MUX_ADC_MUX0_CFG0: 327 case CDC_VA_INP_MUX_ADC_MUX0_CFG1: 328 case CDC_VA_INP_MUX_ADC_MUX1_CFG0: 329 case CDC_VA_INP_MUX_ADC_MUX1_CFG1: 330 case CDC_VA_INP_MUX_ADC_MUX2_CFG0: 331 case CDC_VA_INP_MUX_ADC_MUX2_CFG1: 332 case CDC_VA_INP_MUX_ADC_MUX3_CFG0: 333 case CDC_VA_INP_MUX_ADC_MUX3_CFG1: 334 case CDC_VA_TX0_TX_PATH_CTL: 335 case CDC_VA_TX0_TX_PATH_CFG0: 336 case CDC_VA_TX0_TX_PATH_CFG1: 337 case CDC_VA_TX0_TX_VOL_CTL: 338 case CDC_VA_TX0_TX_PATH_SEC0: 339 case CDC_VA_TX0_TX_PATH_SEC1: 340 case CDC_VA_TX0_TX_PATH_SEC2: 341 case CDC_VA_TX0_TX_PATH_SEC3: 342 case CDC_VA_TX0_TX_PATH_SEC4: 343 case CDC_VA_TX0_TX_PATH_SEC5: 344 case CDC_VA_TX0_TX_PATH_SEC6: 345 case CDC_VA_TX0_TX_PATH_SEC7: 346 case CDC_VA_TX1_TX_PATH_CTL: 347 case CDC_VA_TX1_TX_PATH_CFG0: 348 case CDC_VA_TX1_TX_PATH_CFG1: 349 case CDC_VA_TX1_TX_VOL_CTL: 350 case CDC_VA_TX1_TX_PATH_SEC0: 351 case CDC_VA_TX1_TX_PATH_SEC1: 352 case CDC_VA_TX1_TX_PATH_SEC2: 353 case CDC_VA_TX1_TX_PATH_SEC3: 354 case CDC_VA_TX1_TX_PATH_SEC4: 355 case CDC_VA_TX1_TX_PATH_SEC5: 356 case CDC_VA_TX1_TX_PATH_SEC6: 357 case CDC_VA_TX2_TX_PATH_CTL: 358 case CDC_VA_TX2_TX_PATH_CFG0: 359 case CDC_VA_TX2_TX_PATH_CFG1: 360 case CDC_VA_TX2_TX_VOL_CTL: 361 case CDC_VA_TX2_TX_PATH_SEC0: 362 case CDC_VA_TX2_TX_PATH_SEC1: 363 case CDC_VA_TX2_TX_PATH_SEC2: 364 case CDC_VA_TX2_TX_PATH_SEC3: 365 case CDC_VA_TX2_TX_PATH_SEC4: 366 case CDC_VA_TX2_TX_PATH_SEC5: 367 case CDC_VA_TX2_TX_PATH_SEC6: 368 case CDC_VA_TX3_TX_PATH_CTL: 369 case CDC_VA_TX3_TX_PATH_CFG0: 370 case CDC_VA_TX3_TX_PATH_CFG1: 371 case CDC_VA_TX3_TX_VOL_CTL: 372 case CDC_VA_TX3_TX_PATH_SEC0: 373 case CDC_VA_TX3_TX_PATH_SEC1: 374 case CDC_VA_TX3_TX_PATH_SEC2: 375 case CDC_VA_TX3_TX_PATH_SEC3: 376 case CDC_VA_TX3_TX_PATH_SEC4: 377 case CDC_VA_TX3_TX_PATH_SEC5: 378 case CDC_VA_TX3_TX_PATH_SEC6: 379 return true; 380 } 381 382 return false; 383 } 384 385 static bool va_is_readable_register(struct device *dev, unsigned int reg) 386 { 387 switch (reg) { 388 case CDC_VA_TOP_CSR_CORE_ID_0: 389 case CDC_VA_TOP_CSR_CORE_ID_1: 390 case CDC_VA_TOP_CSR_CORE_ID_2: 391 case CDC_VA_TOP_CSR_CORE_ID_3: 392 return true; 393 } 394 395 return va_is_rw_register(dev, reg); 396 } 397 398 static const struct regmap_config va_regmap_config = { 399 .name = "va_macro", 400 .reg_bits = 32, 401 .val_bits = 32, 402 .reg_stride = 4, 403 .cache_type = REGCACHE_FLAT, 404 .reg_defaults = va_defaults, 405 .num_reg_defaults = ARRAY_SIZE(va_defaults), 406 .max_register = VA_MAX_OFFSET, 407 .volatile_reg = va_is_volatile_register, 408 .readable_reg = va_is_readable_register, 409 .writeable_reg = va_is_rw_register, 410 }; 411 412 static int va_clk_rsc_fs_gen_request(struct va_macro *va, bool enable) 413 { 414 struct regmap *regmap = va->regmap; 415 416 if (enable) { 417 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 418 CDC_VA_MCLK_CONTROL_EN, 419 CDC_VA_MCLK_CONTROL_EN); 420 421 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 422 CDC_VA_FS_CONTROL_EN, 423 CDC_VA_FS_CONTROL_EN); 424 425 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0, 426 CDC_VA_FS_BROADCAST_EN, 427 CDC_VA_FS_BROADCAST_EN); 428 } else { 429 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_MCLK_CONTROL, 430 CDC_VA_MCLK_CONTROL_EN, 0x0); 431 432 regmap_update_bits(regmap, CDC_VA_CLK_RST_CTRL_FS_CNT_CONTROL, 433 CDC_VA_FS_CONTROL_EN, 0x0); 434 435 regmap_update_bits(regmap, CDC_VA_TOP_CSR_TOP_CFG0, 436 CDC_VA_FS_BROADCAST_EN, 0x0); 437 } 438 439 return 0; 440 } 441 442 static int va_macro_mclk_enable(struct va_macro *va, bool mclk_enable) 443 { 444 struct regmap *regmap = va->regmap; 445 446 if (mclk_enable) { 447 va_clk_rsc_fs_gen_request(va, true); 448 regcache_mark_dirty(regmap); 449 regcache_sync_region(regmap, 0x0, VA_MAX_OFFSET); 450 } else { 451 va_clk_rsc_fs_gen_request(va, false); 452 } 453 454 return 0; 455 } 456 457 static int va_macro_mclk_event(struct snd_soc_dapm_widget *w, 458 struct snd_kcontrol *kcontrol, int event) 459 { 460 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 461 struct va_macro *va = snd_soc_component_get_drvdata(comp); 462 463 switch (event) { 464 case SND_SOC_DAPM_PRE_PMU: 465 return va_macro_mclk_enable(va, true); 466 case SND_SOC_DAPM_POST_PMD: 467 return va_macro_mclk_enable(va, false); 468 } 469 470 return 0; 471 } 472 473 static int va_macro_put_dec_enum(struct snd_kcontrol *kcontrol, 474 struct snd_ctl_elem_value *ucontrol) 475 { 476 struct snd_soc_dapm_widget *widget = 477 snd_soc_dapm_kcontrol_widget(kcontrol); 478 struct snd_soc_component *component = 479 snd_soc_dapm_to_component(widget->dapm); 480 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 481 unsigned int val; 482 u16 mic_sel_reg; 483 484 val = ucontrol->value.enumerated.item[0]; 485 486 switch (e->reg) { 487 case CDC_VA_INP_MUX_ADC_MUX0_CFG0: 488 mic_sel_reg = CDC_VA_TX0_TX_PATH_CFG0; 489 break; 490 case CDC_VA_INP_MUX_ADC_MUX1_CFG0: 491 mic_sel_reg = CDC_VA_TX1_TX_PATH_CFG0; 492 break; 493 case CDC_VA_INP_MUX_ADC_MUX2_CFG0: 494 mic_sel_reg = CDC_VA_TX2_TX_PATH_CFG0; 495 break; 496 case CDC_VA_INP_MUX_ADC_MUX3_CFG0: 497 mic_sel_reg = CDC_VA_TX3_TX_PATH_CFG0; 498 break; 499 default: 500 dev_err(component->dev, "%s: e->reg: 0x%x not expected\n", 501 __func__, e->reg); 502 return -EINVAL; 503 } 504 505 if (val != 0) 506 snd_soc_component_update_bits(component, mic_sel_reg, 507 CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK, 508 CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC); 509 510 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 511 } 512 513 static int va_macro_tx_mixer_get(struct snd_kcontrol *kcontrol, 514 struct snd_ctl_elem_value *ucontrol) 515 { 516 struct snd_soc_dapm_widget *widget = 517 snd_soc_dapm_kcontrol_widget(kcontrol); 518 struct snd_soc_component *component = 519 snd_soc_dapm_to_component(widget->dapm); 520 struct soc_mixer_control *mc = 521 (struct soc_mixer_control *)kcontrol->private_value; 522 u32 dai_id = widget->shift; 523 u32 dec_id = mc->shift; 524 struct va_macro *va = snd_soc_component_get_drvdata(component); 525 526 if (test_bit(dec_id, &va->active_ch_mask[dai_id])) 527 ucontrol->value.integer.value[0] = 1; 528 else 529 ucontrol->value.integer.value[0] = 0; 530 531 return 0; 532 } 533 534 static int va_macro_tx_mixer_put(struct snd_kcontrol *kcontrol, 535 struct snd_ctl_elem_value *ucontrol) 536 { 537 struct snd_soc_dapm_widget *widget = 538 snd_soc_dapm_kcontrol_widget(kcontrol); 539 struct snd_soc_component *component = 540 snd_soc_dapm_to_component(widget->dapm); 541 struct snd_soc_dapm_update *update = NULL; 542 struct soc_mixer_control *mc = 543 (struct soc_mixer_control *)kcontrol->private_value; 544 u32 dai_id = widget->shift; 545 u32 dec_id = mc->shift; 546 u32 enable = ucontrol->value.integer.value[0]; 547 struct va_macro *va = snd_soc_component_get_drvdata(component); 548 549 if (enable) { 550 set_bit(dec_id, &va->active_ch_mask[dai_id]); 551 va->active_ch_cnt[dai_id]++; 552 va->active_decimator[dai_id] = dec_id; 553 } else { 554 clear_bit(dec_id, &va->active_ch_mask[dai_id]); 555 va->active_ch_cnt[dai_id]--; 556 va->active_decimator[dai_id] = -1; 557 } 558 559 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); 560 561 return 0; 562 } 563 564 static int va_dmic_clk_enable(struct snd_soc_component *component, 565 u32 dmic, bool enable) 566 { 567 struct va_macro *va = snd_soc_component_get_drvdata(component); 568 u16 dmic_clk_reg; 569 s32 *dmic_clk_cnt; 570 u8 *dmic_clk_div; 571 u8 freq_change_mask; 572 u8 clk_div; 573 574 switch (dmic) { 575 case 0: 576 case 1: 577 dmic_clk_cnt = &(va->dmic_0_1_clk_cnt); 578 dmic_clk_div = &(va->dmic_0_1_clk_div); 579 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC0_CTL; 580 freq_change_mask = CDC_VA_DMIC0_FREQ_CHANGE_MASK; 581 break; 582 case 2: 583 case 3: 584 dmic_clk_cnt = &(va->dmic_2_3_clk_cnt); 585 dmic_clk_div = &(va->dmic_2_3_clk_div); 586 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC1_CTL; 587 freq_change_mask = CDC_VA_DMIC1_FREQ_CHANGE_MASK; 588 break; 589 case 4: 590 case 5: 591 dmic_clk_cnt = &(va->dmic_4_5_clk_cnt); 592 dmic_clk_div = &(va->dmic_4_5_clk_div); 593 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC2_CTL; 594 freq_change_mask = CDC_VA_DMIC2_FREQ_CHANGE_MASK; 595 break; 596 case 6: 597 case 7: 598 dmic_clk_cnt = &(va->dmic_6_7_clk_cnt); 599 dmic_clk_div = &(va->dmic_6_7_clk_div); 600 dmic_clk_reg = CDC_VA_TOP_CSR_DMIC3_CTL; 601 freq_change_mask = CDC_VA_DMIC3_FREQ_CHANGE_MASK; 602 break; 603 default: 604 dev_err(component->dev, "%s: Invalid DMIC Selection\n", 605 __func__); 606 return -EINVAL; 607 } 608 609 if (enable) { 610 clk_div = va->dmic_clk_div; 611 (*dmic_clk_cnt)++; 612 if (*dmic_clk_cnt == 1) { 613 snd_soc_component_update_bits(component, 614 CDC_VA_TOP_CSR_DMIC_CFG, 615 CDC_VA_RESET_ALL_DMICS_MASK, 616 CDC_VA_RESET_ALL_DMICS_DISABLE); 617 snd_soc_component_update_bits(component, dmic_clk_reg, 618 CDC_VA_DMIC_CLK_SEL_MASK, 619 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 620 snd_soc_component_update_bits(component, dmic_clk_reg, 621 CDC_VA_DMIC_EN_MASK, 622 CDC_VA_DMIC_ENABLE); 623 } else { 624 if (*dmic_clk_div > clk_div) { 625 snd_soc_component_update_bits(component, 626 CDC_VA_TOP_CSR_DMIC_CFG, 627 freq_change_mask, 628 freq_change_mask); 629 snd_soc_component_update_bits(component, dmic_clk_reg, 630 CDC_VA_DMIC_CLK_SEL_MASK, 631 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 632 snd_soc_component_update_bits(component, 633 CDC_VA_TOP_CSR_DMIC_CFG, 634 freq_change_mask, 635 CDC_VA_DMIC_FREQ_CHANGE_DISABLE); 636 } else { 637 clk_div = *dmic_clk_div; 638 } 639 } 640 *dmic_clk_div = clk_div; 641 } else { 642 (*dmic_clk_cnt)--; 643 if (*dmic_clk_cnt == 0) { 644 snd_soc_component_update_bits(component, dmic_clk_reg, 645 CDC_VA_DMIC_EN_MASK, 0); 646 clk_div = 0; 647 snd_soc_component_update_bits(component, dmic_clk_reg, 648 CDC_VA_DMIC_CLK_SEL_MASK, 649 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 650 } else { 651 clk_div = va->dmic_clk_div; 652 if (*dmic_clk_div > clk_div) { 653 clk_div = va->dmic_clk_div; 654 snd_soc_component_update_bits(component, 655 CDC_VA_TOP_CSR_DMIC_CFG, 656 freq_change_mask, 657 freq_change_mask); 658 snd_soc_component_update_bits(component, dmic_clk_reg, 659 CDC_VA_DMIC_CLK_SEL_MASK, 660 clk_div << CDC_VA_DMIC_CLK_SEL_SHFT); 661 snd_soc_component_update_bits(component, 662 CDC_VA_TOP_CSR_DMIC_CFG, 663 freq_change_mask, 664 CDC_VA_DMIC_FREQ_CHANGE_DISABLE); 665 } else { 666 clk_div = *dmic_clk_div; 667 } 668 } 669 *dmic_clk_div = clk_div; 670 } 671 672 return 0; 673 } 674 675 static int va_macro_enable_dmic(struct snd_soc_dapm_widget *w, 676 struct snd_kcontrol *kcontrol, int event) 677 { 678 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 679 unsigned int dmic = w->shift; 680 681 switch (event) { 682 case SND_SOC_DAPM_PRE_PMU: 683 va_dmic_clk_enable(comp, dmic, true); 684 break; 685 case SND_SOC_DAPM_POST_PMD: 686 va_dmic_clk_enable(comp, dmic, false); 687 break; 688 } 689 690 return 0; 691 } 692 693 static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 694 struct snd_kcontrol *kcontrol, int event) 695 { 696 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); 697 unsigned int decimator; 698 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg; 699 u16 tx_gain_ctl_reg; 700 u8 hpf_cut_off_freq; 701 702 struct va_macro *va = snd_soc_component_get_drvdata(comp); 703 704 decimator = w->shift; 705 706 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL + 707 VA_MACRO_TX_PATH_OFFSET * decimator; 708 hpf_gate_reg = CDC_VA_TX0_TX_PATH_SEC2 + 709 VA_MACRO_TX_PATH_OFFSET * decimator; 710 dec_cfg_reg = CDC_VA_TX0_TX_PATH_CFG0 + 711 VA_MACRO_TX_PATH_OFFSET * decimator; 712 tx_gain_ctl_reg = CDC_VA_TX0_TX_VOL_CTL + 713 VA_MACRO_TX_PATH_OFFSET * decimator; 714 715 switch (event) { 716 case SND_SOC_DAPM_PRE_PMU: 717 snd_soc_component_update_bits(comp, 718 dec_cfg_reg, CDC_VA_ADC_MODE_MASK, 719 va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT); 720 /* Enable TX PGA Mute */ 721 break; 722 case SND_SOC_DAPM_POST_PMU: 723 /* Enable TX CLK */ 724 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 725 CDC_VA_TX_PATH_CLK_EN_MASK, 726 CDC_VA_TX_PATH_CLK_EN); 727 snd_soc_component_update_bits(comp, hpf_gate_reg, 728 CDC_VA_TX_HPF_ZERO_GATE_MASK, 729 CDC_VA_TX_HPF_ZERO_GATE); 730 731 usleep_range(1000, 1010); 732 hpf_cut_off_freq = (snd_soc_component_read(comp, dec_cfg_reg) & 733 TX_HPF_CUT_OFF_FREQ_MASK) >> 5; 734 735 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) { 736 snd_soc_component_update_bits(comp, dec_cfg_reg, 737 TX_HPF_CUT_OFF_FREQ_MASK, 738 CF_MIN_3DB_150HZ << 5); 739 740 snd_soc_component_update_bits(comp, hpf_gate_reg, 741 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK, 742 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ); 743 744 /* 745 * Minimum 1 clk cycle delay is required as per HW spec 746 */ 747 usleep_range(1000, 1010); 748 749 snd_soc_component_update_bits(comp, 750 hpf_gate_reg, 751 CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK, 752 0x0); 753 } 754 755 756 usleep_range(1000, 1010); 757 snd_soc_component_update_bits(comp, hpf_gate_reg, 758 CDC_VA_TX_HPF_ZERO_GATE_MASK, 759 CDC_VA_TX_HPF_ZERO_NO_GATE); 760 /* 761 * 6ms delay is required as per HW spec 762 */ 763 usleep_range(6000, 6010); 764 /* apply gain after decimator is enabled */ 765 snd_soc_component_write(comp, tx_gain_ctl_reg, 766 snd_soc_component_read(comp, tx_gain_ctl_reg)); 767 break; 768 case SND_SOC_DAPM_POST_PMD: 769 /* Disable TX CLK */ 770 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 771 CDC_VA_TX_PATH_CLK_EN_MASK, 772 CDC_VA_TX_PATH_CLK_DISABLE); 773 break; 774 } 775 return 0; 776 } 777 778 static int va_macro_dec_mode_get(struct snd_kcontrol *kcontrol, 779 struct snd_ctl_elem_value *ucontrol) 780 { 781 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 782 struct va_macro *va = snd_soc_component_get_drvdata(comp); 783 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 784 int path = e->shift_l; 785 786 ucontrol->value.integer.value[0] = va->dec_mode[path]; 787 788 return 0; 789 } 790 791 static int va_macro_dec_mode_put(struct snd_kcontrol *kcontrol, 792 struct snd_ctl_elem_value *ucontrol) 793 { 794 struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol); 795 int value = ucontrol->value.integer.value[0]; 796 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 797 int path = e->shift_l; 798 struct va_macro *va = snd_soc_component_get_drvdata(comp); 799 800 va->dec_mode[path] = value; 801 802 return 0; 803 } 804 805 static int va_macro_hw_params(struct snd_pcm_substream *substream, 806 struct snd_pcm_hw_params *params, 807 struct snd_soc_dai *dai) 808 { 809 int tx_fs_rate; 810 struct snd_soc_component *component = dai->component; 811 u32 decimator, sample_rate; 812 u16 tx_fs_reg; 813 struct device *va_dev = component->dev; 814 struct va_macro *va = snd_soc_component_get_drvdata(component); 815 816 sample_rate = params_rate(params); 817 switch (sample_rate) { 818 case 8000: 819 tx_fs_rate = 0; 820 break; 821 case 16000: 822 tx_fs_rate = 1; 823 break; 824 case 32000: 825 tx_fs_rate = 3; 826 break; 827 case 48000: 828 tx_fs_rate = 4; 829 break; 830 case 96000: 831 tx_fs_rate = 5; 832 break; 833 case 192000: 834 tx_fs_rate = 6; 835 break; 836 case 384000: 837 tx_fs_rate = 7; 838 break; 839 default: 840 dev_err(va_dev, "%s: Invalid TX sample rate: %d\n", 841 __func__, params_rate(params)); 842 return -EINVAL; 843 } 844 845 for_each_set_bit(decimator, &va->active_ch_mask[dai->id], 846 VA_MACRO_DEC_MAX) { 847 tx_fs_reg = CDC_VA_TX0_TX_PATH_CTL + 848 VA_MACRO_TX_PATH_OFFSET * decimator; 849 snd_soc_component_update_bits(component, tx_fs_reg, 0x0F, 850 tx_fs_rate); 851 } 852 return 0; 853 } 854 855 static int va_macro_get_channel_map(struct snd_soc_dai *dai, 856 unsigned int *tx_num, unsigned int *tx_slot, 857 unsigned int *rx_num, unsigned int *rx_slot) 858 { 859 struct snd_soc_component *component = dai->component; 860 struct device *va_dev = component->dev; 861 struct va_macro *va = snd_soc_component_get_drvdata(component); 862 863 switch (dai->id) { 864 case VA_MACRO_AIF1_CAP: 865 case VA_MACRO_AIF2_CAP: 866 case VA_MACRO_AIF3_CAP: 867 *tx_slot = va->active_ch_mask[dai->id]; 868 *tx_num = va->active_ch_cnt[dai->id]; 869 break; 870 default: 871 dev_err(va_dev, "%s: Invalid AIF\n", __func__); 872 break; 873 } 874 return 0; 875 } 876 877 static int va_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream) 878 { 879 struct snd_soc_component *component = dai->component; 880 struct va_macro *va = snd_soc_component_get_drvdata(component); 881 u16 tx_vol_ctl_reg, decimator; 882 883 decimator = va->active_decimator[dai->id]; 884 885 tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL + 886 VA_MACRO_TX_PATH_OFFSET * decimator; 887 if (mute) 888 snd_soc_component_update_bits(component, tx_vol_ctl_reg, 889 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK, 890 CDC_VA_TX_PATH_PGA_MUTE_EN); 891 else 892 snd_soc_component_update_bits(component, tx_vol_ctl_reg, 893 CDC_VA_TX_PATH_PGA_MUTE_EN_MASK, 894 CDC_VA_TX_PATH_PGA_MUTE_DISABLE); 895 896 return 0; 897 } 898 899 static struct snd_soc_dai_ops va_macro_dai_ops = { 900 .hw_params = va_macro_hw_params, 901 .get_channel_map = va_macro_get_channel_map, 902 .mute_stream = va_macro_digital_mute, 903 }; 904 905 static struct snd_soc_dai_driver va_macro_dais[] = { 906 { 907 .name = "va_macro_tx1", 908 .id = VA_MACRO_AIF1_CAP, 909 .capture = { 910 .stream_name = "VA_AIF1 Capture", 911 .rates = VA_MACRO_RATES, 912 .formats = VA_MACRO_FORMATS, 913 .rate_max = 192000, 914 .rate_min = 8000, 915 .channels_min = 1, 916 .channels_max = 8, 917 }, 918 .ops = &va_macro_dai_ops, 919 }, 920 { 921 .name = "va_macro_tx2", 922 .id = VA_MACRO_AIF2_CAP, 923 .capture = { 924 .stream_name = "VA_AIF2 Capture", 925 .rates = VA_MACRO_RATES, 926 .formats = VA_MACRO_FORMATS, 927 .rate_max = 192000, 928 .rate_min = 8000, 929 .channels_min = 1, 930 .channels_max = 8, 931 }, 932 .ops = &va_macro_dai_ops, 933 }, 934 { 935 .name = "va_macro_tx3", 936 .id = VA_MACRO_AIF3_CAP, 937 .capture = { 938 .stream_name = "VA_AIF3 Capture", 939 .rates = VA_MACRO_RATES, 940 .formats = VA_MACRO_FORMATS, 941 .rate_max = 192000, 942 .rate_min = 8000, 943 .channels_min = 1, 944 .channels_max = 8, 945 }, 946 .ops = &va_macro_dai_ops, 947 }, 948 }; 949 950 static const char * const adc_mux_text[] = { 951 "VA_DMIC", "SWR_MIC" 952 }; 953 954 static SOC_ENUM_SINGLE_DECL(va_dec0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG1, 955 0, adc_mux_text); 956 static SOC_ENUM_SINGLE_DECL(va_dec1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG1, 957 0, adc_mux_text); 958 static SOC_ENUM_SINGLE_DECL(va_dec2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG1, 959 0, adc_mux_text); 960 static SOC_ENUM_SINGLE_DECL(va_dec3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG1, 961 0, adc_mux_text); 962 963 static const struct snd_kcontrol_new va_dec0_mux = SOC_DAPM_ENUM("va_dec0", 964 va_dec0_enum); 965 static const struct snd_kcontrol_new va_dec1_mux = SOC_DAPM_ENUM("va_dec1", 966 va_dec1_enum); 967 static const struct snd_kcontrol_new va_dec2_mux = SOC_DAPM_ENUM("va_dec2", 968 va_dec2_enum); 969 static const struct snd_kcontrol_new va_dec3_mux = SOC_DAPM_ENUM("va_dec3", 970 va_dec3_enum); 971 972 static const char * const dmic_mux_text[] = { 973 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", 974 "DMIC4", "DMIC5", "DMIC6", "DMIC7" 975 }; 976 977 static SOC_ENUM_SINGLE_DECL(va_dmic0_enum, CDC_VA_INP_MUX_ADC_MUX0_CFG0, 978 4, dmic_mux_text); 979 980 static SOC_ENUM_SINGLE_DECL(va_dmic1_enum, CDC_VA_INP_MUX_ADC_MUX1_CFG0, 981 4, dmic_mux_text); 982 983 static SOC_ENUM_SINGLE_DECL(va_dmic2_enum, CDC_VA_INP_MUX_ADC_MUX2_CFG0, 984 4, dmic_mux_text); 985 986 static SOC_ENUM_SINGLE_DECL(va_dmic3_enum, CDC_VA_INP_MUX_ADC_MUX3_CFG0, 987 4, dmic_mux_text); 988 989 static const struct snd_kcontrol_new va_dmic0_mux = SOC_DAPM_ENUM_EXT("va_dmic0", 990 va_dmic0_enum, snd_soc_dapm_get_enum_double, 991 va_macro_put_dec_enum); 992 993 static const struct snd_kcontrol_new va_dmic1_mux = SOC_DAPM_ENUM_EXT("va_dmic1", 994 va_dmic1_enum, snd_soc_dapm_get_enum_double, 995 va_macro_put_dec_enum); 996 997 static const struct snd_kcontrol_new va_dmic2_mux = SOC_DAPM_ENUM_EXT("va_dmic2", 998 va_dmic2_enum, snd_soc_dapm_get_enum_double, 999 va_macro_put_dec_enum); 1000 1001 static const struct snd_kcontrol_new va_dmic3_mux = SOC_DAPM_ENUM_EXT("va_dmic3", 1002 va_dmic3_enum, snd_soc_dapm_get_enum_double, 1003 va_macro_put_dec_enum); 1004 1005 static const struct snd_kcontrol_new va_aif1_cap_mixer[] = { 1006 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0, 1007 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1008 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0, 1009 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1010 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0, 1011 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1012 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0, 1013 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1014 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0, 1015 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1016 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0, 1017 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1018 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0, 1019 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1020 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0, 1021 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1022 }; 1023 1024 static const struct snd_kcontrol_new va_aif2_cap_mixer[] = { 1025 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0, 1026 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1027 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0, 1028 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1029 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0, 1030 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1031 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0, 1032 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1033 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0, 1034 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1035 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0, 1036 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1037 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0, 1038 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1039 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0, 1040 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1041 }; 1042 1043 static const struct snd_kcontrol_new va_aif3_cap_mixer[] = { 1044 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, VA_MACRO_DEC0, 1, 0, 1045 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1046 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, VA_MACRO_DEC1, 1, 0, 1047 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1048 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, VA_MACRO_DEC2, 1, 0, 1049 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1050 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, VA_MACRO_DEC3, 1, 0, 1051 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1052 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, VA_MACRO_DEC4, 1, 0, 1053 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1054 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, VA_MACRO_DEC5, 1, 0, 1055 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1056 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, VA_MACRO_DEC6, 1, 0, 1057 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1058 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, VA_MACRO_DEC7, 1, 0, 1059 va_macro_tx_mixer_get, va_macro_tx_mixer_put), 1060 }; 1061 1062 static const struct snd_soc_dapm_widget va_macro_dapm_widgets[] = { 1063 SND_SOC_DAPM_AIF_OUT("VA_AIF1 CAP", "VA_AIF1 Capture", 0, 1064 SND_SOC_NOPM, VA_MACRO_AIF1_CAP, 0), 1065 1066 SND_SOC_DAPM_AIF_OUT("VA_AIF2 CAP", "VA_AIF2 Capture", 0, 1067 SND_SOC_NOPM, VA_MACRO_AIF2_CAP, 0), 1068 1069 SND_SOC_DAPM_AIF_OUT("VA_AIF3 CAP", "VA_AIF3 Capture", 0, 1070 SND_SOC_NOPM, VA_MACRO_AIF3_CAP, 0), 1071 1072 SND_SOC_DAPM_MIXER("VA_AIF1_CAP Mixer", SND_SOC_NOPM, 1073 VA_MACRO_AIF1_CAP, 0, 1074 va_aif1_cap_mixer, ARRAY_SIZE(va_aif1_cap_mixer)), 1075 1076 SND_SOC_DAPM_MIXER("VA_AIF2_CAP Mixer", SND_SOC_NOPM, 1077 VA_MACRO_AIF2_CAP, 0, 1078 va_aif2_cap_mixer, ARRAY_SIZE(va_aif2_cap_mixer)), 1079 1080 SND_SOC_DAPM_MIXER("VA_AIF3_CAP Mixer", SND_SOC_NOPM, 1081 VA_MACRO_AIF3_CAP, 0, 1082 va_aif3_cap_mixer, ARRAY_SIZE(va_aif3_cap_mixer)), 1083 1084 SND_SOC_DAPM_MUX("VA DMIC MUX0", SND_SOC_NOPM, 0, 0, &va_dmic0_mux), 1085 SND_SOC_DAPM_MUX("VA DMIC MUX1", SND_SOC_NOPM, 0, 0, &va_dmic1_mux), 1086 SND_SOC_DAPM_MUX("VA DMIC MUX2", SND_SOC_NOPM, 0, 0, &va_dmic2_mux), 1087 SND_SOC_DAPM_MUX("VA DMIC MUX3", SND_SOC_NOPM, 0, 0, &va_dmic3_mux), 1088 1089 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0), 1090 SND_SOC_DAPM_INPUT("DMIC0 Pin"), 1091 SND_SOC_DAPM_INPUT("DMIC1 Pin"), 1092 SND_SOC_DAPM_INPUT("DMIC2 Pin"), 1093 SND_SOC_DAPM_INPUT("DMIC3 Pin"), 1094 SND_SOC_DAPM_INPUT("DMIC4 Pin"), 1095 SND_SOC_DAPM_INPUT("DMIC5 Pin"), 1096 SND_SOC_DAPM_INPUT("DMIC6 Pin"), 1097 SND_SOC_DAPM_INPUT("DMIC7 Pin"), 1098 1099 SND_SOC_DAPM_ADC_E("VA DMIC0", NULL, SND_SOC_NOPM, 0, 0, 1100 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1101 SND_SOC_DAPM_POST_PMD), 1102 1103 SND_SOC_DAPM_ADC_E("VA DMIC1", NULL, SND_SOC_NOPM, 1, 0, 1104 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1105 SND_SOC_DAPM_POST_PMD), 1106 1107 SND_SOC_DAPM_ADC_E("VA DMIC2", NULL, SND_SOC_NOPM, 2, 0, 1108 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1109 SND_SOC_DAPM_POST_PMD), 1110 1111 SND_SOC_DAPM_ADC_E("VA DMIC3", NULL, SND_SOC_NOPM, 3, 0, 1112 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1113 SND_SOC_DAPM_POST_PMD), 1114 1115 SND_SOC_DAPM_ADC_E("VA DMIC4", NULL, SND_SOC_NOPM, 4, 0, 1116 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1117 SND_SOC_DAPM_POST_PMD), 1118 1119 SND_SOC_DAPM_ADC_E("VA DMIC5", NULL, SND_SOC_NOPM, 5, 0, 1120 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1121 SND_SOC_DAPM_POST_PMD), 1122 1123 SND_SOC_DAPM_ADC_E("VA DMIC6", NULL, SND_SOC_NOPM, 6, 0, 1124 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1125 SND_SOC_DAPM_POST_PMD), 1126 1127 SND_SOC_DAPM_ADC_E("VA DMIC7", NULL, SND_SOC_NOPM, 7, 0, 1128 va_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | 1129 SND_SOC_DAPM_POST_PMD), 1130 1131 SND_SOC_DAPM_INPUT("VA SWR_ADC0"), 1132 SND_SOC_DAPM_INPUT("VA SWR_ADC1"), 1133 SND_SOC_DAPM_INPUT("VA SWR_ADC2"), 1134 SND_SOC_DAPM_INPUT("VA SWR_ADC3"), 1135 SND_SOC_DAPM_INPUT("VA SWR_MIC0"), 1136 SND_SOC_DAPM_INPUT("VA SWR_MIC1"), 1137 SND_SOC_DAPM_INPUT("VA SWR_MIC2"), 1138 SND_SOC_DAPM_INPUT("VA SWR_MIC3"), 1139 SND_SOC_DAPM_INPUT("VA SWR_MIC4"), 1140 SND_SOC_DAPM_INPUT("VA SWR_MIC5"), 1141 SND_SOC_DAPM_INPUT("VA SWR_MIC6"), 1142 SND_SOC_DAPM_INPUT("VA SWR_MIC7"), 1143 1144 SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, VA_MACRO_DEC0, 0, 1145 &va_dec0_mux, va_macro_enable_dec, 1146 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1147 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1148 1149 SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, VA_MACRO_DEC1, 0, 1150 &va_dec1_mux, va_macro_enable_dec, 1151 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1152 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1153 1154 SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, VA_MACRO_DEC2, 0, 1155 &va_dec2_mux, va_macro_enable_dec, 1156 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1157 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1158 1159 SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, VA_MACRO_DEC3, 0, 1160 &va_dec3_mux, va_macro_enable_dec, 1161 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 1162 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), 1163 1164 SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0, 1165 va_macro_mclk_event, 1166 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1167 }; 1168 1169 static const struct snd_soc_dapm_route va_audio_map[] = { 1170 {"VA_AIF1 CAP", NULL, "VA_MCLK"}, 1171 {"VA_AIF2 CAP", NULL, "VA_MCLK"}, 1172 {"VA_AIF3 CAP", NULL, "VA_MCLK"}, 1173 1174 {"VA_AIF1 CAP", NULL, "VA_AIF1_CAP Mixer"}, 1175 {"VA_AIF2 CAP", NULL, "VA_AIF2_CAP Mixer"}, 1176 {"VA_AIF3 CAP", NULL, "VA_AIF3_CAP Mixer"}, 1177 1178 {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"}, 1179 {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"}, 1180 {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"}, 1181 {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"}, 1182 1183 {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"}, 1184 {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"}, 1185 {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"}, 1186 {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"}, 1187 1188 {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"}, 1189 {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"}, 1190 {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"}, 1191 {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"}, 1192 1193 {"VA DEC0 MUX", "VA_DMIC", "VA DMIC MUX0"}, 1194 {"VA DMIC MUX0", "DMIC0", "VA DMIC0"}, 1195 {"VA DMIC MUX0", "DMIC1", "VA DMIC1"}, 1196 {"VA DMIC MUX0", "DMIC2", "VA DMIC2"}, 1197 {"VA DMIC MUX0", "DMIC3", "VA DMIC3"}, 1198 {"VA DMIC MUX0", "DMIC4", "VA DMIC4"}, 1199 {"VA DMIC MUX0", "DMIC5", "VA DMIC5"}, 1200 {"VA DMIC MUX0", "DMIC6", "VA DMIC6"}, 1201 {"VA DMIC MUX0", "DMIC7", "VA DMIC7"}, 1202 1203 {"VA DEC1 MUX", "VA_DMIC", "VA DMIC MUX1"}, 1204 {"VA DMIC MUX1", "DMIC0", "VA DMIC0"}, 1205 {"VA DMIC MUX1", "DMIC1", "VA DMIC1"}, 1206 {"VA DMIC MUX1", "DMIC2", "VA DMIC2"}, 1207 {"VA DMIC MUX1", "DMIC3", "VA DMIC3"}, 1208 {"VA DMIC MUX1", "DMIC4", "VA DMIC4"}, 1209 {"VA DMIC MUX1", "DMIC5", "VA DMIC5"}, 1210 {"VA DMIC MUX1", "DMIC6", "VA DMIC6"}, 1211 {"VA DMIC MUX1", "DMIC7", "VA DMIC7"}, 1212 1213 {"VA DEC2 MUX", "VA_DMIC", "VA DMIC MUX2"}, 1214 {"VA DMIC MUX2", "DMIC0", "VA DMIC0"}, 1215 {"VA DMIC MUX2", "DMIC1", "VA DMIC1"}, 1216 {"VA DMIC MUX2", "DMIC2", "VA DMIC2"}, 1217 {"VA DMIC MUX2", "DMIC3", "VA DMIC3"}, 1218 {"VA DMIC MUX2", "DMIC4", "VA DMIC4"}, 1219 {"VA DMIC MUX2", "DMIC5", "VA DMIC5"}, 1220 {"VA DMIC MUX2", "DMIC6", "VA DMIC6"}, 1221 {"VA DMIC MUX2", "DMIC7", "VA DMIC7"}, 1222 1223 {"VA DEC3 MUX", "VA_DMIC", "VA DMIC MUX3"}, 1224 {"VA DMIC MUX3", "DMIC0", "VA DMIC0"}, 1225 {"VA DMIC MUX3", "DMIC1", "VA DMIC1"}, 1226 {"VA DMIC MUX3", "DMIC2", "VA DMIC2"}, 1227 {"VA DMIC MUX3", "DMIC3", "VA DMIC3"}, 1228 {"VA DMIC MUX3", "DMIC4", "VA DMIC4"}, 1229 {"VA DMIC MUX3", "DMIC5", "VA DMIC5"}, 1230 {"VA DMIC MUX3", "DMIC6", "VA DMIC6"}, 1231 {"VA DMIC MUX3", "DMIC7", "VA DMIC7"}, 1232 1233 { "VA DMIC0", NULL, "DMIC0 Pin" }, 1234 { "VA DMIC1", NULL, "DMIC1 Pin" }, 1235 { "VA DMIC2", NULL, "DMIC2 Pin" }, 1236 { "VA DMIC3", NULL, "DMIC3 Pin" }, 1237 { "VA DMIC4", NULL, "DMIC4 Pin" }, 1238 { "VA DMIC5", NULL, "DMIC5 Pin" }, 1239 { "VA DMIC6", NULL, "DMIC6 Pin" }, 1240 { "VA DMIC7", NULL, "DMIC7 Pin" }, 1241 }; 1242 1243 static const char * const dec_mode_mux_text[] = { 1244 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF", 1245 }; 1246 1247 static const struct soc_enum dec_mode_mux_enum[] = { 1248 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text), 1249 dec_mode_mux_text), 1250 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text), 1251 dec_mode_mux_text), 1252 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text), 1253 dec_mode_mux_text), 1254 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text), 1255 dec_mode_mux_text), 1256 }; 1257 1258 static const struct snd_kcontrol_new va_macro_snd_controls[] = { 1259 SOC_SINGLE_S8_TLV("VA_DEC0 Volume", CDC_VA_TX0_TX_VOL_CTL, 1260 -84, 40, digital_gain), 1261 SOC_SINGLE_S8_TLV("VA_DEC1 Volume", CDC_VA_TX1_TX_VOL_CTL, 1262 -84, 40, digital_gain), 1263 SOC_SINGLE_S8_TLV("VA_DEC2 Volume", CDC_VA_TX2_TX_VOL_CTL, 1264 -84, 40, digital_gain), 1265 SOC_SINGLE_S8_TLV("VA_DEC3 Volume", CDC_VA_TX3_TX_VOL_CTL, 1266 -84, 40, digital_gain), 1267 1268 SOC_ENUM_EXT("VA_DEC0 MODE", dec_mode_mux_enum[0], 1269 va_macro_dec_mode_get, va_macro_dec_mode_put), 1270 SOC_ENUM_EXT("VA_DEC1 MODE", dec_mode_mux_enum[1], 1271 va_macro_dec_mode_get, va_macro_dec_mode_put), 1272 SOC_ENUM_EXT("VA_DEC2 MODE", dec_mode_mux_enum[2], 1273 va_macro_dec_mode_get, va_macro_dec_mode_put), 1274 SOC_ENUM_EXT("VA_DEC3 MODE", dec_mode_mux_enum[3], 1275 va_macro_dec_mode_get, va_macro_dec_mode_put), 1276 }; 1277 1278 static int va_macro_component_probe(struct snd_soc_component *component) 1279 { 1280 struct va_macro *va = snd_soc_component_get_drvdata(component); 1281 1282 snd_soc_component_init_regmap(component, va->regmap); 1283 1284 return 0; 1285 } 1286 1287 static const struct snd_soc_component_driver va_macro_component_drv = { 1288 .name = "VA MACRO", 1289 .probe = va_macro_component_probe, 1290 .controls = va_macro_snd_controls, 1291 .num_controls = ARRAY_SIZE(va_macro_snd_controls), 1292 .dapm_widgets = va_macro_dapm_widgets, 1293 .num_dapm_widgets = ARRAY_SIZE(va_macro_dapm_widgets), 1294 .dapm_routes = va_audio_map, 1295 .num_dapm_routes = ARRAY_SIZE(va_audio_map), 1296 }; 1297 1298 static int fsgen_gate_enable(struct clk_hw *hw) 1299 { 1300 return va_macro_mclk_enable(to_va_macro(hw), true); 1301 } 1302 1303 static void fsgen_gate_disable(struct clk_hw *hw) 1304 { 1305 va_macro_mclk_enable(to_va_macro(hw), false); 1306 } 1307 1308 static int fsgen_gate_is_enabled(struct clk_hw *hw) 1309 { 1310 struct va_macro *va = to_va_macro(hw); 1311 int val; 1312 1313 regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val); 1314 1315 return !!(val & CDC_VA_FS_BROADCAST_EN); 1316 } 1317 1318 static const struct clk_ops fsgen_gate_ops = { 1319 .prepare = fsgen_gate_enable, 1320 .unprepare = fsgen_gate_disable, 1321 .is_enabled = fsgen_gate_is_enabled, 1322 }; 1323 1324 static int va_macro_register_fsgen_output(struct va_macro *va) 1325 { 1326 struct clk *parent = va->clks[2].clk; 1327 struct device *dev = va->dev; 1328 struct device_node *np = dev->of_node; 1329 const char *parent_clk_name; 1330 const char *clk_name = "fsgen"; 1331 struct clk_init_data init; 1332 int ret; 1333 1334 parent_clk_name = __clk_get_name(parent); 1335 1336 of_property_read_string(np, "clock-output-names", &clk_name); 1337 1338 init.name = clk_name; 1339 init.ops = &fsgen_gate_ops; 1340 init.flags = 0; 1341 init.parent_names = &parent_clk_name; 1342 init.num_parents = 1; 1343 va->hw.init = &init; 1344 ret = devm_clk_hw_register(va->dev, &va->hw); 1345 if (ret) 1346 return ret; 1347 1348 return of_clk_add_provider(np, of_clk_src_simple_get, va->hw.clk); 1349 } 1350 1351 static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate, 1352 struct va_macro *va) 1353 { 1354 u32 div_factor; 1355 u32 mclk_rate = VA_MACRO_MCLK_FREQ; 1356 1357 if (!dmic_sample_rate || mclk_rate % dmic_sample_rate != 0) 1358 goto undefined_rate; 1359 1360 div_factor = mclk_rate / dmic_sample_rate; 1361 1362 switch (div_factor) { 1363 case 2: 1364 va->dmic_clk_div = VA_MACRO_CLK_DIV_2; 1365 break; 1366 case 3: 1367 va->dmic_clk_div = VA_MACRO_CLK_DIV_3; 1368 break; 1369 case 4: 1370 va->dmic_clk_div = VA_MACRO_CLK_DIV_4; 1371 break; 1372 case 6: 1373 va->dmic_clk_div = VA_MACRO_CLK_DIV_6; 1374 break; 1375 case 8: 1376 va->dmic_clk_div = VA_MACRO_CLK_DIV_8; 1377 break; 1378 case 16: 1379 va->dmic_clk_div = VA_MACRO_CLK_DIV_16; 1380 break; 1381 default: 1382 /* Any other DIV factor is invalid */ 1383 goto undefined_rate; 1384 } 1385 1386 return dmic_sample_rate; 1387 1388 undefined_rate: 1389 dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n", 1390 __func__, dmic_sample_rate, mclk_rate); 1391 dmic_sample_rate = 0; 1392 1393 return dmic_sample_rate; 1394 } 1395 1396 static int va_macro_probe(struct platform_device *pdev) 1397 { 1398 struct device *dev = &pdev->dev; 1399 struct va_macro *va; 1400 void __iomem *base; 1401 u32 sample_rate = 0; 1402 int ret; 1403 1404 va = devm_kzalloc(dev, sizeof(*va), GFP_KERNEL); 1405 if (!va) 1406 return -ENOMEM; 1407 1408 va->dev = dev; 1409 va->clks[0].id = "macro"; 1410 va->clks[1].id = "dcodec"; 1411 va->clks[2].id = "mclk"; 1412 1413 ret = devm_clk_bulk_get(dev, VA_NUM_CLKS_MAX, va->clks); 1414 if (ret) { 1415 dev_err(dev, "Error getting VA Clocks (%d)\n", ret); 1416 return ret; 1417 } 1418 1419 ret = of_property_read_u32(dev->of_node, "qcom,dmic-sample-rate", 1420 &sample_rate); 1421 if (ret) { 1422 dev_err(dev, "qcom,dmic-sample-rate dt entry missing\n"); 1423 va->dmic_clk_div = VA_MACRO_CLK_DIV_2; 1424 } else { 1425 ret = va_macro_validate_dmic_sample_rate(sample_rate, va); 1426 if (!ret) 1427 return -EINVAL; 1428 } 1429 1430 /* mclk rate */ 1431 clk_set_rate(va->clks[1].clk, VA_MACRO_MCLK_FREQ); 1432 ret = clk_bulk_prepare_enable(VA_NUM_CLKS_MAX, va->clks); 1433 if (ret) 1434 return ret; 1435 1436 base = devm_platform_ioremap_resource(pdev, 0); 1437 if (IS_ERR(base)) { 1438 ret = PTR_ERR(base); 1439 goto err; 1440 } 1441 1442 va->regmap = devm_regmap_init_mmio(dev, base, &va_regmap_config); 1443 if (IS_ERR(va->regmap)) { 1444 ret = -EINVAL; 1445 goto err; 1446 } 1447 1448 dev_set_drvdata(dev, va); 1449 ret = va_macro_register_fsgen_output(va); 1450 if (ret) 1451 goto err; 1452 1453 ret = devm_snd_soc_register_component(dev, &va_macro_component_drv, 1454 va_macro_dais, 1455 ARRAY_SIZE(va_macro_dais)); 1456 if (ret) 1457 goto soc_err; 1458 1459 return ret; 1460 1461 soc_err: 1462 of_clk_del_provider(pdev->dev.of_node); 1463 err: 1464 clk_bulk_disable_unprepare(VA_NUM_CLKS_MAX, va->clks); 1465 1466 return ret; 1467 } 1468 1469 static int va_macro_remove(struct platform_device *pdev) 1470 { 1471 struct va_macro *va = dev_get_drvdata(&pdev->dev); 1472 1473 of_clk_del_provider(pdev->dev.of_node); 1474 clk_bulk_disable_unprepare(VA_NUM_CLKS_MAX, va->clks); 1475 1476 return 0; 1477 } 1478 1479 static const struct of_device_id va_macro_dt_match[] = { 1480 { .compatible = "qcom,sm8250-lpass-va-macro" }, 1481 {} 1482 }; 1483 MODULE_DEVICE_TABLE(of, va_macro_dt_match); 1484 1485 static struct platform_driver va_macro_driver = { 1486 .driver = { 1487 .name = "va_macro", 1488 .of_match_table = va_macro_dt_match, 1489 .suppress_bind_attrs = true, 1490 }, 1491 .probe = va_macro_probe, 1492 .remove = va_macro_remove, 1493 }; 1494 1495 module_platform_driver(va_macro_driver); 1496 MODULE_DESCRIPTION("VA macro driver"); 1497 MODULE_LICENSE("GPL"); 1498