1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3 
4 #include <linux/module.h>
5 #include <linux/init.h>
6 #include <linux/clk.h>
7 #include <linux/io.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_runtime.h>
10 #include <linux/regmap.h>
11 #include <sound/soc.h>
12 #include <sound/soc-dapm.h>
13 #include <sound/tlv.h>
14 #include <linux/of_clk.h>
15 #include <linux/clk-provider.h>
16 
17 #include "lpass-macro-common.h"
18 
19 #define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
20 #define CDC_TX_MCLK_EN_MASK		BIT(0)
21 #define CDC_TX_MCLK_ENABLE		BIT(0)
22 #define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
23 #define CDC_TX_FS_CNT_EN_MASK		BIT(0)
24 #define CDC_TX_FS_CNT_ENABLE		BIT(0)
25 #define CDC_TX_CLK_RST_CTRL_SWR_CONTROL	(0x0008)
26 #define CDC_TX_SWR_RESET_MASK		BIT(1)
27 #define CDC_TX_SWR_RESET_ENABLE		BIT(1)
28 #define CDC_TX_SWR_CLK_EN_MASK		BIT(0)
29 #define CDC_TX_SWR_CLK_ENABLE		BIT(0)
30 #define CDC_TX_TOP_CSR_TOP_CFG0		(0x0080)
31 #define CDC_TX_TOP_CSR_ANC_CFG		(0x0084)
32 #define CDC_TX_TOP_CSR_SWR_CTRL		(0x0088)
33 #define CDC_TX_TOP_CSR_FREQ_MCLK	(0x0090)
34 #define CDC_TX_TOP_CSR_DEBUG_BUS	(0x0094)
35 #define CDC_TX_TOP_CSR_DEBUG_EN		(0x0098)
36 #define CDC_TX_TOP_CSR_TX_I2S_CTL	(0x00A4)
37 #define CDC_TX_TOP_CSR_I2S_CLK		(0x00A8)
38 #define CDC_TX_TOP_CSR_I2S_RESET	(0x00AC)
39 #define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n)	(0x00C0 + n * 0x4)
40 #define CDC_TX_TOP_CSR_SWR_DMIC0_CTL	(0x00C0)
41 #define CDC_TX_SWR_DMIC_CLK_SEL_MASK	GENMASK(3, 1)
42 #define CDC_TX_TOP_CSR_SWR_DMIC1_CTL	(0x00C4)
43 #define CDC_TX_TOP_CSR_SWR_DMIC2_CTL	(0x00C8)
44 #define CDC_TX_TOP_CSR_SWR_DMIC3_CTL	(0x00CC)
45 #define CDC_TX_TOP_CSR_SWR_AMIC0_CTL	(0x00D0)
46 #define CDC_TX_TOP_CSR_SWR_AMIC1_CTL	(0x00D4)
47 #define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n)	(0x0100 + 0x8 * n)
48 #define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0)
49 #define CDC_TX_MACRO_DMIC_MUX_SEL_MASK GENMASK(7, 4)
50 #define CDC_TX_INP_MUX_ADC_MUX0_CFG0	(0x0100)
51 #define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n)	(0x0104 + 0x8 * n)
52 #define CDC_TX_INP_MUX_ADC_MUX0_CFG1	(0x0104)
53 #define CDC_TX_INP_MUX_ADC_MUX1_CFG0	(0x0108)
54 #define CDC_TX_INP_MUX_ADC_MUX1_CFG1	(0x010C)
55 #define CDC_TX_INP_MUX_ADC_MUX2_CFG0	(0x0110)
56 #define CDC_TX_INP_MUX_ADC_MUX2_CFG1	(0x0114)
57 #define CDC_TX_INP_MUX_ADC_MUX3_CFG0	(0x0118)
58 #define CDC_TX_INP_MUX_ADC_MUX3_CFG1	(0x011C)
59 #define CDC_TX_INP_MUX_ADC_MUX4_CFG0	(0x0120)
60 #define CDC_TX_INP_MUX_ADC_MUX4_CFG1	(0x0124)
61 #define CDC_TX_INP_MUX_ADC_MUX5_CFG0	(0x0128)
62 #define CDC_TX_INP_MUX_ADC_MUX5_CFG1	(0x012C)
63 #define CDC_TX_INP_MUX_ADC_MUX6_CFG0	(0x0130)
64 #define CDC_TX_INP_MUX_ADC_MUX6_CFG1	(0x0134)
65 #define CDC_TX_INP_MUX_ADC_MUX7_CFG0	(0x0138)
66 #define CDC_TX_INP_MUX_ADC_MUX7_CFG1	(0x013C)
67 #define CDC_TX_ANC0_CLK_RESET_CTL	(0x0200)
68 #define CDC_TX_ANC0_MODE_1_CTL		(0x0204)
69 #define CDC_TX_ANC0_MODE_2_CTL		(0x0208)
70 #define CDC_TX_ANC0_FF_SHIFT		(0x020C)
71 #define CDC_TX_ANC0_FB_SHIFT		(0x0210)
72 #define CDC_TX_ANC0_LPF_FF_A_CTL	(0x0214)
73 #define CDC_TX_ANC0_LPF_FF_B_CTL	(0x0218)
74 #define CDC_TX_ANC0_LPF_FB_CTL		(0x021C)
75 #define CDC_TX_ANC0_SMLPF_CTL		(0x0220)
76 #define CDC_TX_ANC0_DCFLT_SHIFT_CTL	(0x0224)
77 #define CDC_TX_ANC0_IIR_ADAPT_CTL	(0x0228)
78 #define CDC_TX_ANC0_IIR_COEFF_1_CTL	(0x022C)
79 #define CDC_TX_ANC0_IIR_COEFF_2_CTL	(0x0230)
80 #define CDC_TX_ANC0_FF_A_GAIN_CTL	(0x0234)
81 #define CDC_TX_ANC0_FF_B_GAIN_CTL	(0x0238)
82 #define CDC_TX_ANC0_FB_GAIN_CTL		(0x023C)
83 #define CDC_TXn_TX_PATH_CTL(n)		(0x0400 + 0x80 * n)
84 #define CDC_TXn_PCM_RATE_MASK		GENMASK(3, 0)
85 #define CDC_TXn_PGA_MUTE_MASK		BIT(4)
86 #define CDC_TXn_CLK_EN_MASK		BIT(5)
87 #define CDC_TX0_TX_PATH_CTL		(0x0400)
88 #define CDC_TXn_TX_PATH_CFG0(n)		(0x0404 + 0x80 * n)
89 #define CDC_TX0_TX_PATH_CFG0		(0x0404)
90 #define CDC_TXn_PH_EN_MASK		BIT(0)
91 #define CDC_TXn_ADC_MODE_MASK		GENMASK(2, 1)
92 #define CDC_TXn_HPF_CUT_FREQ_MASK	GENMASK(6, 5)
93 #define CDC_TXn_ADC_DMIC_SEL_MASK	BIT(7)
94 #define CDC_TX0_TX_PATH_CFG1		(0x0408)
95 #define CDC_TXn_TX_VOL_CTL(n)		(0x040C + 0x80 * n)
96 #define CDC_TX0_TX_VOL_CTL		(0x040C)
97 #define CDC_TX0_TX_PATH_SEC0		(0x0410)
98 #define CDC_TX0_TX_PATH_SEC1		(0x0414)
99 #define CDC_TXn_TX_PATH_SEC2(n)		(0x0418 + 0x80 * n)
100 #define CDC_TXn_HPF_F_CHANGE_MASK	 BIT(1)
101 #define CDC_TXn_HPF_ZERO_GATE_MASK	 BIT(0)
102 #define CDC_TX0_TX_PATH_SEC2		(0x0418)
103 #define CDC_TX0_TX_PATH_SEC3		(0x041C)
104 #define CDC_TX0_TX_PATH_SEC4		(0x0420)
105 #define CDC_TX0_TX_PATH_SEC5		(0x0424)
106 #define CDC_TX0_TX_PATH_SEC6		(0x0428)
107 #define CDC_TX0_TX_PATH_SEC7		(0x042C)
108 #define CDC_TX0_MBHC_CTL_EN_MASK	BIT(6)
109 #define CDC_TX1_TX_PATH_CTL		(0x0480)
110 #define CDC_TX1_TX_PATH_CFG0		(0x0484)
111 #define CDC_TX1_TX_PATH_CFG1		(0x0488)
112 #define CDC_TX1_TX_VOL_CTL		(0x048C)
113 #define CDC_TX1_TX_PATH_SEC0		(0x0490)
114 #define CDC_TX1_TX_PATH_SEC1		(0x0494)
115 #define CDC_TX1_TX_PATH_SEC2		(0x0498)
116 #define CDC_TX1_TX_PATH_SEC3		(0x049C)
117 #define CDC_TX1_TX_PATH_SEC4		(0x04A0)
118 #define CDC_TX1_TX_PATH_SEC5		(0x04A4)
119 #define CDC_TX1_TX_PATH_SEC6		(0x04A8)
120 #define CDC_TX2_TX_PATH_CTL		(0x0500)
121 #define CDC_TX2_TX_PATH_CFG0		(0x0504)
122 #define CDC_TX2_TX_PATH_CFG1		(0x0508)
123 #define CDC_TX2_TX_VOL_CTL		(0x050C)
124 #define CDC_TX2_TX_PATH_SEC0		(0x0510)
125 #define CDC_TX2_TX_PATH_SEC1		(0x0514)
126 #define CDC_TX2_TX_PATH_SEC2		(0x0518)
127 #define CDC_TX2_TX_PATH_SEC3		(0x051C)
128 #define CDC_TX2_TX_PATH_SEC4		(0x0520)
129 #define CDC_TX2_TX_PATH_SEC5		(0x0524)
130 #define CDC_TX2_TX_PATH_SEC6		(0x0528)
131 #define CDC_TX3_TX_PATH_CTL		(0x0580)
132 #define CDC_TX3_TX_PATH_CFG0		(0x0584)
133 #define CDC_TX3_TX_PATH_CFG1		(0x0588)
134 #define CDC_TX3_TX_VOL_CTL		(0x058C)
135 #define CDC_TX3_TX_PATH_SEC0		(0x0590)
136 #define CDC_TX3_TX_PATH_SEC1		(0x0594)
137 #define CDC_TX3_TX_PATH_SEC2		(0x0598)
138 #define CDC_TX3_TX_PATH_SEC3		(0x059C)
139 #define CDC_TX3_TX_PATH_SEC4		(0x05A0)
140 #define CDC_TX3_TX_PATH_SEC5		(0x05A4)
141 #define CDC_TX3_TX_PATH_SEC6		(0x05A8)
142 #define CDC_TX4_TX_PATH_CTL		(0x0600)
143 #define CDC_TX4_TX_PATH_CFG0		(0x0604)
144 #define CDC_TX4_TX_PATH_CFG1		(0x0608)
145 #define CDC_TX4_TX_VOL_CTL		(0x060C)
146 #define CDC_TX4_TX_PATH_SEC0		(0x0610)
147 #define CDC_TX4_TX_PATH_SEC1		(0x0614)
148 #define CDC_TX4_TX_PATH_SEC2		(0x0618)
149 #define CDC_TX4_TX_PATH_SEC3		(0x061C)
150 #define CDC_TX4_TX_PATH_SEC4		(0x0620)
151 #define CDC_TX4_TX_PATH_SEC5		(0x0624)
152 #define CDC_TX4_TX_PATH_SEC6		(0x0628)
153 #define CDC_TX5_TX_PATH_CTL		(0x0680)
154 #define CDC_TX5_TX_PATH_CFG0		(0x0684)
155 #define CDC_TX5_TX_PATH_CFG1		(0x0688)
156 #define CDC_TX5_TX_VOL_CTL		(0x068C)
157 #define CDC_TX5_TX_PATH_SEC0		(0x0690)
158 #define CDC_TX5_TX_PATH_SEC1		(0x0694)
159 #define CDC_TX5_TX_PATH_SEC2		(0x0698)
160 #define CDC_TX5_TX_PATH_SEC3		(0x069C)
161 #define CDC_TX5_TX_PATH_SEC4		(0x06A0)
162 #define CDC_TX5_TX_PATH_SEC5		(0x06A4)
163 #define CDC_TX5_TX_PATH_SEC6		(0x06A8)
164 #define CDC_TX6_TX_PATH_CTL		(0x0700)
165 #define CDC_TX6_TX_PATH_CFG0		(0x0704)
166 #define CDC_TX6_TX_PATH_CFG1		(0x0708)
167 #define CDC_TX6_TX_VOL_CTL		(0x070C)
168 #define CDC_TX6_TX_PATH_SEC0		(0x0710)
169 #define CDC_TX6_TX_PATH_SEC1		(0x0714)
170 #define CDC_TX6_TX_PATH_SEC2		(0x0718)
171 #define CDC_TX6_TX_PATH_SEC3		(0x071C)
172 #define CDC_TX6_TX_PATH_SEC4		(0x0720)
173 #define CDC_TX6_TX_PATH_SEC5		(0x0724)
174 #define CDC_TX6_TX_PATH_SEC6		(0x0728)
175 #define CDC_TX7_TX_PATH_CTL		(0x0780)
176 #define CDC_TX7_TX_PATH_CFG0		(0x0784)
177 #define CDC_TX7_TX_PATH_CFG1		(0x0788)
178 #define CDC_TX7_TX_VOL_CTL		(0x078C)
179 #define CDC_TX7_TX_PATH_SEC0		(0x0790)
180 #define CDC_TX7_TX_PATH_SEC1		(0x0794)
181 #define CDC_TX7_TX_PATH_SEC2		(0x0798)
182 #define CDC_TX7_TX_PATH_SEC3		(0x079C)
183 #define CDC_TX7_TX_PATH_SEC4		(0x07A0)
184 #define CDC_TX7_TX_PATH_SEC5		(0x07A4)
185 #define CDC_TX7_TX_PATH_SEC6		(0x07A8)
186 #define TX_MAX_OFFSET			(0x07A8)
187 
188 #define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
189 			SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
190 			SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
191 #define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
192 			SNDRV_PCM_FMTBIT_S24_LE |\
193 			SNDRV_PCM_FMTBIT_S24_3LE)
194 
195 #define  CF_MIN_3DB_4HZ			0x0
196 #define  CF_MIN_3DB_75HZ		0x1
197 #define  CF_MIN_3DB_150HZ		0x2
198 #define	TX_ADC_MAX	5
199 #define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2)
200 #define NUM_DECIMATORS 8
201 #define TX_NUM_CLKS_MAX	5
202 #define TX_MACRO_DMIC_UNMUTE_DELAY_MS	40
203 #define TX_MACRO_AMIC_UNMUTE_DELAY_MS	100
204 #define TX_MACRO_DMIC_HPF_DELAY_MS	300
205 #define TX_MACRO_AMIC_HPF_DELAY_MS	300
206 #define MCLK_FREQ		19200000
207 
208 enum {
209 	TX_MACRO_AIF_INVALID = 0,
210 	TX_MACRO_AIF1_CAP,
211 	TX_MACRO_AIF2_CAP,
212 	TX_MACRO_AIF3_CAP,
213 	TX_MACRO_MAX_DAIS
214 };
215 
216 enum {
217 	TX_MACRO_DEC0,
218 	TX_MACRO_DEC1,
219 	TX_MACRO_DEC2,
220 	TX_MACRO_DEC3,
221 	TX_MACRO_DEC4,
222 	TX_MACRO_DEC5,
223 	TX_MACRO_DEC6,
224 	TX_MACRO_DEC7,
225 	TX_MACRO_DEC_MAX,
226 };
227 
228 enum {
229 	TX_MACRO_CLK_DIV_2,
230 	TX_MACRO_CLK_DIV_3,
231 	TX_MACRO_CLK_DIV_4,
232 	TX_MACRO_CLK_DIV_6,
233 	TX_MACRO_CLK_DIV_8,
234 	TX_MACRO_CLK_DIV_16,
235 };
236 
237 enum {
238 	MSM_DMIC,
239 	SWR_MIC,
240 	ANC_FB_TUNE1
241 };
242 
243 struct tx_mute_work {
244 	struct tx_macro *tx;
245 	u8 decimator;
246 	struct delayed_work dwork;
247 };
248 
249 struct hpf_work {
250 	struct tx_macro *tx;
251 	u8 decimator;
252 	u8 hpf_cut_off_freq;
253 	struct delayed_work dwork;
254 };
255 
256 struct tx_macro {
257 	struct device *dev;
258 	struct snd_soc_component *component;
259 	struct hpf_work tx_hpf_work[NUM_DECIMATORS];
260 	struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS];
261 	unsigned long active_ch_mask[TX_MACRO_MAX_DAIS];
262 	unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS];
263 	int active_decimator[TX_MACRO_MAX_DAIS];
264 	struct regmap *regmap;
265 	struct clk *mclk;
266 	struct clk *npl;
267 	struct clk *macro;
268 	struct clk *dcodec;
269 	struct clk *fsgen;
270 	struct clk_hw hw;
271 	bool dec_active[NUM_DECIMATORS];
272 	int tx_mclk_users;
273 	u16 dmic_clk_div;
274 	bool bcs_enable;
275 	int dec_mode[NUM_DECIMATORS];
276 	struct lpass_macro *pds;
277 	bool bcs_clk_en;
278 };
279 #define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw)
280 
281 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
282 
283 static struct reg_default tx_defaults[] = {
284 	/* TX Macro */
285 	{ CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
286 	{ CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
287 	{ CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
288 	{ CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
289 	{ CDC_TX_TOP_CSR_ANC_CFG, 0x00},
290 	{ CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
291 	{ CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
292 	{ CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
293 	{ CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
294 	{ CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
295 	{ CDC_TX_TOP_CSR_I2S_CLK, 0x00},
296 	{ CDC_TX_TOP_CSR_I2S_RESET, 0x00},
297 	{ CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
298 	{ CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
299 	{ CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
300 	{ CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
301 	{ CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
302 	{ CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
303 	{ CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
304 	{ CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
305 	{ CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
306 	{ CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00},
307 	{ CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00},
308 	{ CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00},
309 	{ CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00},
310 	{ CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00},
311 	{ CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00},
312 	{ CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00},
313 	{ CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00},
314 	{ CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00},
315 	{ CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00},
316 	{ CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00},
317 	{ CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00},
318 	{ CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00},
319 	{ CDC_TX_ANC0_CLK_RESET_CTL, 0x00},
320 	{ CDC_TX_ANC0_MODE_1_CTL, 0x00},
321 	{ CDC_TX_ANC0_MODE_2_CTL, 0x00},
322 	{ CDC_TX_ANC0_FF_SHIFT, 0x00},
323 	{ CDC_TX_ANC0_FB_SHIFT, 0x00},
324 	{ CDC_TX_ANC0_LPF_FF_A_CTL, 0x00},
325 	{ CDC_TX_ANC0_LPF_FF_B_CTL, 0x00},
326 	{ CDC_TX_ANC0_LPF_FB_CTL, 0x00},
327 	{ CDC_TX_ANC0_SMLPF_CTL, 0x00},
328 	{ CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00},
329 	{ CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00},
330 	{ CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00},
331 	{ CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00},
332 	{ CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00},
333 	{ CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00},
334 	{ CDC_TX_ANC0_FB_GAIN_CTL, 0x00},
335 	{ CDC_TX0_TX_PATH_CTL, 0x04},
336 	{ CDC_TX0_TX_PATH_CFG0, 0x10},
337 	{ CDC_TX0_TX_PATH_CFG1, 0x0B},
338 	{ CDC_TX0_TX_VOL_CTL, 0x00},
339 	{ CDC_TX0_TX_PATH_SEC0, 0x00},
340 	{ CDC_TX0_TX_PATH_SEC1, 0x00},
341 	{ CDC_TX0_TX_PATH_SEC2, 0x01},
342 	{ CDC_TX0_TX_PATH_SEC3, 0x3C},
343 	{ CDC_TX0_TX_PATH_SEC4, 0x20},
344 	{ CDC_TX0_TX_PATH_SEC5, 0x00},
345 	{ CDC_TX0_TX_PATH_SEC6, 0x00},
346 	{ CDC_TX0_TX_PATH_SEC7, 0x25},
347 	{ CDC_TX1_TX_PATH_CTL, 0x04},
348 	{ CDC_TX1_TX_PATH_CFG0, 0x10},
349 	{ CDC_TX1_TX_PATH_CFG1, 0x0B},
350 	{ CDC_TX1_TX_VOL_CTL, 0x00},
351 	{ CDC_TX1_TX_PATH_SEC0, 0x00},
352 	{ CDC_TX1_TX_PATH_SEC1, 0x00},
353 	{ CDC_TX1_TX_PATH_SEC2, 0x01},
354 	{ CDC_TX1_TX_PATH_SEC3, 0x3C},
355 	{ CDC_TX1_TX_PATH_SEC4, 0x20},
356 	{ CDC_TX1_TX_PATH_SEC5, 0x00},
357 	{ CDC_TX1_TX_PATH_SEC6, 0x00},
358 	{ CDC_TX2_TX_PATH_CTL, 0x04},
359 	{ CDC_TX2_TX_PATH_CFG0, 0x10},
360 	{ CDC_TX2_TX_PATH_CFG1, 0x0B},
361 	{ CDC_TX2_TX_VOL_CTL, 0x00},
362 	{ CDC_TX2_TX_PATH_SEC0, 0x00},
363 	{ CDC_TX2_TX_PATH_SEC1, 0x00},
364 	{ CDC_TX2_TX_PATH_SEC2, 0x01},
365 	{ CDC_TX2_TX_PATH_SEC3, 0x3C},
366 	{ CDC_TX2_TX_PATH_SEC4, 0x20},
367 	{ CDC_TX2_TX_PATH_SEC5, 0x00},
368 	{ CDC_TX2_TX_PATH_SEC6, 0x00},
369 	{ CDC_TX3_TX_PATH_CTL, 0x04},
370 	{ CDC_TX3_TX_PATH_CFG0, 0x10},
371 	{ CDC_TX3_TX_PATH_CFG1, 0x0B},
372 	{ CDC_TX3_TX_VOL_CTL, 0x00},
373 	{ CDC_TX3_TX_PATH_SEC0, 0x00},
374 	{ CDC_TX3_TX_PATH_SEC1, 0x00},
375 	{ CDC_TX3_TX_PATH_SEC2, 0x01},
376 	{ CDC_TX3_TX_PATH_SEC3, 0x3C},
377 	{ CDC_TX3_TX_PATH_SEC4, 0x20},
378 	{ CDC_TX3_TX_PATH_SEC5, 0x00},
379 	{ CDC_TX3_TX_PATH_SEC6, 0x00},
380 	{ CDC_TX4_TX_PATH_CTL, 0x04},
381 	{ CDC_TX4_TX_PATH_CFG0, 0x10},
382 	{ CDC_TX4_TX_PATH_CFG1, 0x0B},
383 	{ CDC_TX4_TX_VOL_CTL, 0x00},
384 	{ CDC_TX4_TX_PATH_SEC0, 0x00},
385 	{ CDC_TX4_TX_PATH_SEC1, 0x00},
386 	{ CDC_TX4_TX_PATH_SEC2, 0x01},
387 	{ CDC_TX4_TX_PATH_SEC3, 0x3C},
388 	{ CDC_TX4_TX_PATH_SEC4, 0x20},
389 	{ CDC_TX4_TX_PATH_SEC5, 0x00},
390 	{ CDC_TX4_TX_PATH_SEC6, 0x00},
391 	{ CDC_TX5_TX_PATH_CTL, 0x04},
392 	{ CDC_TX5_TX_PATH_CFG0, 0x10},
393 	{ CDC_TX5_TX_PATH_CFG1, 0x0B},
394 	{ CDC_TX5_TX_VOL_CTL, 0x00},
395 	{ CDC_TX5_TX_PATH_SEC0, 0x00},
396 	{ CDC_TX5_TX_PATH_SEC1, 0x00},
397 	{ CDC_TX5_TX_PATH_SEC2, 0x01},
398 	{ CDC_TX5_TX_PATH_SEC3, 0x3C},
399 	{ CDC_TX5_TX_PATH_SEC4, 0x20},
400 	{ CDC_TX5_TX_PATH_SEC5, 0x00},
401 	{ CDC_TX5_TX_PATH_SEC6, 0x00},
402 	{ CDC_TX6_TX_PATH_CTL, 0x04},
403 	{ CDC_TX6_TX_PATH_CFG0, 0x10},
404 	{ CDC_TX6_TX_PATH_CFG1, 0x0B},
405 	{ CDC_TX6_TX_VOL_CTL, 0x00},
406 	{ CDC_TX6_TX_PATH_SEC0, 0x00},
407 	{ CDC_TX6_TX_PATH_SEC1, 0x00},
408 	{ CDC_TX6_TX_PATH_SEC2, 0x01},
409 	{ CDC_TX6_TX_PATH_SEC3, 0x3C},
410 	{ CDC_TX6_TX_PATH_SEC4, 0x20},
411 	{ CDC_TX6_TX_PATH_SEC5, 0x00},
412 	{ CDC_TX6_TX_PATH_SEC6, 0x00},
413 	{ CDC_TX7_TX_PATH_CTL, 0x04},
414 	{ CDC_TX7_TX_PATH_CFG0, 0x10},
415 	{ CDC_TX7_TX_PATH_CFG1, 0x0B},
416 	{ CDC_TX7_TX_VOL_CTL, 0x00},
417 	{ CDC_TX7_TX_PATH_SEC0, 0x00},
418 	{ CDC_TX7_TX_PATH_SEC1, 0x00},
419 	{ CDC_TX7_TX_PATH_SEC2, 0x01},
420 	{ CDC_TX7_TX_PATH_SEC3, 0x3C},
421 	{ CDC_TX7_TX_PATH_SEC4, 0x20},
422 	{ CDC_TX7_TX_PATH_SEC5, 0x00},
423 	{ CDC_TX7_TX_PATH_SEC6, 0x00},
424 };
425 
426 static bool tx_is_volatile_register(struct device *dev, unsigned int reg)
427 {
428 	/* Update volatile list for tx/tx macros */
429 	switch (reg) {
430 	case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
431 	case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
432 	case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
433 	case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
434 		return true;
435 	}
436 	return false;
437 }
438 
439 static bool tx_is_rw_register(struct device *dev, unsigned int reg)
440 {
441 	switch (reg) {
442 	case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL:
443 	case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL:
444 	case CDC_TX_CLK_RST_CTRL_SWR_CONTROL:
445 	case CDC_TX_TOP_CSR_TOP_CFG0:
446 	case CDC_TX_TOP_CSR_ANC_CFG:
447 	case CDC_TX_TOP_CSR_SWR_CTRL:
448 	case CDC_TX_TOP_CSR_FREQ_MCLK:
449 	case CDC_TX_TOP_CSR_DEBUG_BUS:
450 	case CDC_TX_TOP_CSR_DEBUG_EN:
451 	case CDC_TX_TOP_CSR_TX_I2S_CTL:
452 	case CDC_TX_TOP_CSR_I2S_CLK:
453 	case CDC_TX_TOP_CSR_I2S_RESET:
454 	case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
455 	case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
456 	case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
457 	case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
458 	case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
459 	case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
460 	case CDC_TX_ANC0_CLK_RESET_CTL:
461 	case CDC_TX_ANC0_MODE_1_CTL:
462 	case CDC_TX_ANC0_MODE_2_CTL:
463 	case CDC_TX_ANC0_FF_SHIFT:
464 	case CDC_TX_ANC0_FB_SHIFT:
465 	case CDC_TX_ANC0_LPF_FF_A_CTL:
466 	case CDC_TX_ANC0_LPF_FF_B_CTL:
467 	case CDC_TX_ANC0_LPF_FB_CTL:
468 	case CDC_TX_ANC0_SMLPF_CTL:
469 	case CDC_TX_ANC0_DCFLT_SHIFT_CTL:
470 	case CDC_TX_ANC0_IIR_ADAPT_CTL:
471 	case CDC_TX_ANC0_IIR_COEFF_1_CTL:
472 	case CDC_TX_ANC0_IIR_COEFF_2_CTL:
473 	case CDC_TX_ANC0_FF_A_GAIN_CTL:
474 	case CDC_TX_ANC0_FF_B_GAIN_CTL:
475 	case CDC_TX_ANC0_FB_GAIN_CTL:
476 	case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
477 	case CDC_TX_INP_MUX_ADC_MUX0_CFG1:
478 	case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
479 	case CDC_TX_INP_MUX_ADC_MUX1_CFG1:
480 	case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
481 	case CDC_TX_INP_MUX_ADC_MUX2_CFG1:
482 	case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
483 	case CDC_TX_INP_MUX_ADC_MUX3_CFG1:
484 	case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
485 	case CDC_TX_INP_MUX_ADC_MUX4_CFG1:
486 	case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
487 	case CDC_TX_INP_MUX_ADC_MUX5_CFG1:
488 	case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
489 	case CDC_TX_INP_MUX_ADC_MUX6_CFG1:
490 	case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
491 	case CDC_TX_INP_MUX_ADC_MUX7_CFG1:
492 	case CDC_TX0_TX_PATH_CTL:
493 	case CDC_TX0_TX_PATH_CFG0:
494 	case CDC_TX0_TX_PATH_CFG1:
495 	case CDC_TX0_TX_VOL_CTL:
496 	case CDC_TX0_TX_PATH_SEC0:
497 	case CDC_TX0_TX_PATH_SEC1:
498 	case CDC_TX0_TX_PATH_SEC2:
499 	case CDC_TX0_TX_PATH_SEC3:
500 	case CDC_TX0_TX_PATH_SEC4:
501 	case CDC_TX0_TX_PATH_SEC5:
502 	case CDC_TX0_TX_PATH_SEC6:
503 	case CDC_TX0_TX_PATH_SEC7:
504 	case CDC_TX1_TX_PATH_CTL:
505 	case CDC_TX1_TX_PATH_CFG0:
506 	case CDC_TX1_TX_PATH_CFG1:
507 	case CDC_TX1_TX_VOL_CTL:
508 	case CDC_TX1_TX_PATH_SEC0:
509 	case CDC_TX1_TX_PATH_SEC1:
510 	case CDC_TX1_TX_PATH_SEC2:
511 	case CDC_TX1_TX_PATH_SEC3:
512 	case CDC_TX1_TX_PATH_SEC4:
513 	case CDC_TX1_TX_PATH_SEC5:
514 	case CDC_TX1_TX_PATH_SEC6:
515 	case CDC_TX2_TX_PATH_CTL:
516 	case CDC_TX2_TX_PATH_CFG0:
517 	case CDC_TX2_TX_PATH_CFG1:
518 	case CDC_TX2_TX_VOL_CTL:
519 	case CDC_TX2_TX_PATH_SEC0:
520 	case CDC_TX2_TX_PATH_SEC1:
521 	case CDC_TX2_TX_PATH_SEC2:
522 	case CDC_TX2_TX_PATH_SEC3:
523 	case CDC_TX2_TX_PATH_SEC4:
524 	case CDC_TX2_TX_PATH_SEC5:
525 	case CDC_TX2_TX_PATH_SEC6:
526 	case CDC_TX3_TX_PATH_CTL:
527 	case CDC_TX3_TX_PATH_CFG0:
528 	case CDC_TX3_TX_PATH_CFG1:
529 	case CDC_TX3_TX_VOL_CTL:
530 	case CDC_TX3_TX_PATH_SEC0:
531 	case CDC_TX3_TX_PATH_SEC1:
532 	case CDC_TX3_TX_PATH_SEC2:
533 	case CDC_TX3_TX_PATH_SEC3:
534 	case CDC_TX3_TX_PATH_SEC4:
535 	case CDC_TX3_TX_PATH_SEC5:
536 	case CDC_TX3_TX_PATH_SEC6:
537 	case CDC_TX4_TX_PATH_CTL:
538 	case CDC_TX4_TX_PATH_CFG0:
539 	case CDC_TX4_TX_PATH_CFG1:
540 	case CDC_TX4_TX_VOL_CTL:
541 	case CDC_TX4_TX_PATH_SEC0:
542 	case CDC_TX4_TX_PATH_SEC1:
543 	case CDC_TX4_TX_PATH_SEC2:
544 	case CDC_TX4_TX_PATH_SEC3:
545 	case CDC_TX4_TX_PATH_SEC4:
546 	case CDC_TX4_TX_PATH_SEC5:
547 	case CDC_TX4_TX_PATH_SEC6:
548 	case CDC_TX5_TX_PATH_CTL:
549 	case CDC_TX5_TX_PATH_CFG0:
550 	case CDC_TX5_TX_PATH_CFG1:
551 	case CDC_TX5_TX_VOL_CTL:
552 	case CDC_TX5_TX_PATH_SEC0:
553 	case CDC_TX5_TX_PATH_SEC1:
554 	case CDC_TX5_TX_PATH_SEC2:
555 	case CDC_TX5_TX_PATH_SEC3:
556 	case CDC_TX5_TX_PATH_SEC4:
557 	case CDC_TX5_TX_PATH_SEC5:
558 	case CDC_TX5_TX_PATH_SEC6:
559 	case CDC_TX6_TX_PATH_CTL:
560 	case CDC_TX6_TX_PATH_CFG0:
561 	case CDC_TX6_TX_PATH_CFG1:
562 	case CDC_TX6_TX_VOL_CTL:
563 	case CDC_TX6_TX_PATH_SEC0:
564 	case CDC_TX6_TX_PATH_SEC1:
565 	case CDC_TX6_TX_PATH_SEC2:
566 	case CDC_TX6_TX_PATH_SEC3:
567 	case CDC_TX6_TX_PATH_SEC4:
568 	case CDC_TX6_TX_PATH_SEC5:
569 	case CDC_TX6_TX_PATH_SEC6:
570 	case CDC_TX7_TX_PATH_CTL:
571 	case CDC_TX7_TX_PATH_CFG0:
572 	case CDC_TX7_TX_PATH_CFG1:
573 	case CDC_TX7_TX_VOL_CTL:
574 	case CDC_TX7_TX_PATH_SEC0:
575 	case CDC_TX7_TX_PATH_SEC1:
576 	case CDC_TX7_TX_PATH_SEC2:
577 	case CDC_TX7_TX_PATH_SEC3:
578 	case CDC_TX7_TX_PATH_SEC4:
579 	case CDC_TX7_TX_PATH_SEC5:
580 	case CDC_TX7_TX_PATH_SEC6:
581 		return true;
582 	}
583 
584 	return false;
585 }
586 
587 static const struct regmap_config tx_regmap_config = {
588 	.name = "tx_macro",
589 	.reg_bits = 16,
590 	.val_bits = 32,
591 	.reg_stride = 4,
592 	.cache_type = REGCACHE_FLAT,
593 	.max_register = TX_MAX_OFFSET,
594 	.reg_defaults = tx_defaults,
595 	.num_reg_defaults = ARRAY_SIZE(tx_defaults),
596 	.writeable_reg = tx_is_rw_register,
597 	.volatile_reg = tx_is_volatile_register,
598 	.readable_reg = tx_is_rw_register,
599 };
600 
601 static int tx_macro_mclk_enable(struct tx_macro *tx,
602 				bool mclk_enable)
603 {
604 	struct regmap *regmap = tx->regmap;
605 
606 	if (mclk_enable) {
607 		if (tx->tx_mclk_users == 0) {
608 			/* 9.6MHz MCLK, set value 0x00 if other frequency */
609 			regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01);
610 			regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
611 					   CDC_TX_MCLK_EN_MASK,
612 					   CDC_TX_MCLK_ENABLE);
613 			regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
614 					   CDC_TX_FS_CNT_EN_MASK,
615 					   CDC_TX_FS_CNT_ENABLE);
616 			regcache_mark_dirty(regmap);
617 			regcache_sync(regmap);
618 		}
619 		tx->tx_mclk_users++;
620 	} else {
621 		if (tx->tx_mclk_users <= 0) {
622 			dev_err(tx->dev, "clock already disabled\n");
623 			tx->tx_mclk_users = 0;
624 			goto exit;
625 		}
626 		tx->tx_mclk_users--;
627 		if (tx->tx_mclk_users == 0) {
628 			regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
629 					   CDC_TX_FS_CNT_EN_MASK, 0x0);
630 			regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
631 					   CDC_TX_MCLK_EN_MASK, 0x0);
632 		}
633 	}
634 exit:
635 	return 0;
636 }
637 
638 static bool is_amic_enabled(struct snd_soc_component *component, u8 decimator)
639 {
640 	u16 adc_mux_reg, adc_reg, adc_n;
641 
642 	adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
643 
644 	if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
645 		adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
646 		adc_n = snd_soc_component_read_field(component, adc_reg,
647 					     CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK);
648 		if (adc_n < TX_ADC_MAX)
649 			return true;
650 	}
651 
652 	return false;
653 }
654 
655 static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work)
656 {
657 	struct delayed_work *hpf_delayed_work;
658 	struct hpf_work *hpf_work;
659 	struct tx_macro *tx;
660 	struct snd_soc_component *component;
661 	u16 dec_cfg_reg, hpf_gate_reg;
662 	u8 hpf_cut_off_freq;
663 
664 	hpf_delayed_work = to_delayed_work(work);
665 	hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
666 	tx = hpf_work->tx;
667 	component = tx->component;
668 	hpf_cut_off_freq = hpf_work->hpf_cut_off_freq;
669 
670 	dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator);
671 	hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator);
672 
673 	if (is_amic_enabled(component, hpf_work->decimator)) {
674 		snd_soc_component_write_field(component,
675 				dec_cfg_reg,
676 				CDC_TXn_HPF_CUT_FREQ_MASK,
677 				hpf_cut_off_freq);
678 		snd_soc_component_update_bits(component, hpf_gate_reg,
679 					      CDC_TXn_HPF_F_CHANGE_MASK |
680 					      CDC_TXn_HPF_ZERO_GATE_MASK,
681 					      0x02);
682 		snd_soc_component_update_bits(component, hpf_gate_reg,
683 					      CDC_TXn_HPF_F_CHANGE_MASK |
684 					      CDC_TXn_HPF_ZERO_GATE_MASK,
685 					      0x01);
686 	} else {
687 		snd_soc_component_write_field(component, dec_cfg_reg,
688 					      CDC_TXn_HPF_CUT_FREQ_MASK,
689 					      hpf_cut_off_freq);
690 		snd_soc_component_write_field(component, hpf_gate_reg,
691 					      CDC_TXn_HPF_F_CHANGE_MASK, 0x1);
692 		/* Minimum 1 clk cycle delay is required as per HW spec */
693 		usleep_range(1000, 1010);
694 		snd_soc_component_write_field(component, hpf_gate_reg,
695 					      CDC_TXn_HPF_F_CHANGE_MASK, 0x0);
696 	}
697 }
698 
699 static void tx_macro_mute_update_callback(struct work_struct *work)
700 {
701 	struct tx_mute_work *tx_mute_dwork;
702 	struct snd_soc_component *component;
703 	struct tx_macro *tx;
704 	struct delayed_work *delayed_work;
705 	u8 decimator;
706 
707 	delayed_work = to_delayed_work(work);
708 	tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork);
709 	tx = tx_mute_dwork->tx;
710 	component = tx->component;
711 	decimator = tx_mute_dwork->decimator;
712 
713 	snd_soc_component_write_field(component, CDC_TXn_TX_PATH_CTL(decimator),
714 				      CDC_TXn_PGA_MUTE_MASK, 0x0);
715 }
716 
717 static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w,
718 			       struct snd_kcontrol *kcontrol, int event)
719 {
720 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
721 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);
722 
723 	switch (event) {
724 	case SND_SOC_DAPM_PRE_PMU:
725 		tx_macro_mclk_enable(tx, true);
726 		break;
727 	case SND_SOC_DAPM_POST_PMD:
728 		tx_macro_mclk_enable(tx, false);
729 		break;
730 	default:
731 		break;
732 	}
733 
734 	return 0;
735 }
736 
737 static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
738 				 struct snd_ctl_elem_value *ucontrol)
739 {
740 	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
741 	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
742 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
743 	unsigned int val, dmic;
744 	u16 mic_sel_reg;
745 	u16 dmic_clk_reg;
746 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);
747 
748 	val = ucontrol->value.enumerated.item[0];
749 	if (val >= e->items)
750 		return -EINVAL;
751 
752 	switch (e->reg) {
753 	case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
754 		mic_sel_reg = CDC_TX0_TX_PATH_CFG0;
755 		break;
756 	case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
757 		mic_sel_reg = CDC_TX1_TX_PATH_CFG0;
758 		break;
759 	case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
760 		mic_sel_reg = CDC_TX2_TX_PATH_CFG0;
761 		break;
762 	case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
763 		mic_sel_reg = CDC_TX3_TX_PATH_CFG0;
764 		break;
765 	case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
766 		mic_sel_reg = CDC_TX4_TX_PATH_CFG0;
767 		break;
768 	case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
769 		mic_sel_reg = CDC_TX5_TX_PATH_CFG0;
770 		break;
771 	case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
772 		mic_sel_reg = CDC_TX6_TX_PATH_CFG0;
773 		break;
774 	case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
775 		mic_sel_reg = CDC_TX7_TX_PATH_CFG0;
776 		break;
777 	default:
778 		dev_err(component->dev, "Error in configuration!!\n");
779 		return -EINVAL;
780 	}
781 
782 	if (val != 0) {
783 		if (widget->shift) { /* MSM DMIC */
784 			snd_soc_component_write_field(component, mic_sel_reg,
785 						      CDC_TXn_ADC_DMIC_SEL_MASK, 1);
786 		} else if (val < 5) {
787 			snd_soc_component_write_field(component, mic_sel_reg,
788 						      CDC_TXn_ADC_DMIC_SEL_MASK, 0);
789 		} else {
790 			snd_soc_component_write_field(component, mic_sel_reg,
791 						      CDC_TXn_ADC_DMIC_SEL_MASK, 1);
792 			dmic = TX_ADC_TO_DMIC(val);
793 			dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
794 			snd_soc_component_write_field(component, dmic_clk_reg,
795 						CDC_TX_SWR_DMIC_CLK_SEL_MASK,
796 						tx->dmic_clk_div);
797 		}
798 	}
799 
800 	return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
801 }
802 
803 static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
804 				 struct snd_ctl_elem_value *ucontrol)
805 {
806 	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
807 	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
808 	struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
809 	u32 dai_id = widget->shift;
810 	u32 dec_id = mc->shift;
811 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);
812 
813 	if (test_bit(dec_id, &tx->active_ch_mask[dai_id]))
814 		ucontrol->value.integer.value[0] = 1;
815 	else
816 		ucontrol->value.integer.value[0] = 0;
817 
818 	return 0;
819 }
820 
821 static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
822 				 struct snd_ctl_elem_value *ucontrol)
823 {
824 	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
825 	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
826 	struct snd_soc_dapm_update *update = NULL;
827 	struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
828 	u32 dai_id = widget->shift;
829 	u32 dec_id = mc->shift;
830 	u32 enable = ucontrol->value.integer.value[0];
831 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);
832 
833 	if (enable) {
834 		if (tx->active_decimator[dai_id] == dec_id)
835 			return 0;
836 
837 		set_bit(dec_id, &tx->active_ch_mask[dai_id]);
838 		tx->active_ch_cnt[dai_id]++;
839 		tx->active_decimator[dai_id] = dec_id;
840 	} else {
841 		if (tx->active_decimator[dai_id] == -1)
842 			return 0;
843 
844 		tx->active_ch_cnt[dai_id]--;
845 		clear_bit(dec_id, &tx->active_ch_mask[dai_id]);
846 		tx->active_decimator[dai_id] = -1;
847 	}
848 	snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
849 
850 	return 1;
851 }
852 
853 static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
854 			       struct snd_kcontrol *kcontrol, int event)
855 {
856 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
857 	u8 decimator;
858 	u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg, tx_gain_ctl_reg;
859 	u8 hpf_cut_off_freq;
860 	int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS;
861 	int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS;
862 	u16 adc_mux_reg, adc_reg, adc_n, dmic;
863 	u16 dmic_clk_reg;
864 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);
865 
866 	decimator = w->shift;
867 	tx_vol_ctl_reg = CDC_TXn_TX_PATH_CTL(decimator);
868 	hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(decimator);
869 	dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(decimator);
870 	tx_gain_ctl_reg = CDC_TXn_TX_VOL_CTL(decimator);
871 
872 	switch (event) {
873 	case SND_SOC_DAPM_PRE_PMU:
874 		adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
875 		if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
876 			adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
877 			adc_n = snd_soc_component_read(component, adc_reg) &
878 				CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK;
879 			if (adc_n >= TX_ADC_MAX) {
880 				dmic = TX_ADC_TO_DMIC(adc_n);
881 				dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
882 
883 				snd_soc_component_write_field(component, dmic_clk_reg,
884 							CDC_TX_SWR_DMIC_CLK_SEL_MASK,
885 							tx->dmic_clk_div);
886 			}
887 		}
888 		snd_soc_component_write_field(component, dec_cfg_reg,
889 					      CDC_TXn_ADC_MODE_MASK,
890 					      tx->dec_mode[decimator]);
891 		/* Enable TX PGA Mute */
892 		snd_soc_component_write_field(component, tx_vol_ctl_reg,
893 					      CDC_TXn_PGA_MUTE_MASK, 0x1);
894 		break;
895 	case SND_SOC_DAPM_POST_PMU:
896 		snd_soc_component_write_field(component, tx_vol_ctl_reg,
897 					     CDC_TXn_CLK_EN_MASK, 0x1);
898 		if (!is_amic_enabled(component, decimator)) {
899 			snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00);
900 			/* Minimum 1 clk cycle delay is required as per HW spec */
901 			usleep_range(1000, 1010);
902 		}
903 		hpf_cut_off_freq = snd_soc_component_read_field(component, dec_cfg_reg,
904 								CDC_TXn_HPF_CUT_FREQ_MASK);
905 
906 		tx->tx_hpf_work[decimator].hpf_cut_off_freq =
907 						hpf_cut_off_freq;
908 
909 		if (hpf_cut_off_freq != CF_MIN_3DB_150HZ)
910 			snd_soc_component_write_field(component, dec_cfg_reg,
911 						      CDC_TXn_HPF_CUT_FREQ_MASK,
912 						      CF_MIN_3DB_150HZ);
913 
914 		if (is_amic_enabled(component, decimator)) {
915 			hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS;
916 			unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS;
917 		}
918 		/* schedule work queue to Remove Mute */
919 		queue_delayed_work(system_freezable_wq,
920 				   &tx->tx_mute_dwork[decimator].dwork,
921 				   msecs_to_jiffies(unmute_delay));
922 		if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
923 			queue_delayed_work(system_freezable_wq,
924 				&tx->tx_hpf_work[decimator].dwork,
925 				msecs_to_jiffies(hpf_delay));
926 			snd_soc_component_update_bits(component, hpf_gate_reg,
927 					      CDC_TXn_HPF_F_CHANGE_MASK |
928 					      CDC_TXn_HPF_ZERO_GATE_MASK,
929 					      0x02);
930 			if (!is_amic_enabled(component, decimator))
931 				snd_soc_component_update_bits(component, hpf_gate_reg,
932 						      CDC_TXn_HPF_F_CHANGE_MASK |
933 						      CDC_TXn_HPF_ZERO_GATE_MASK,
934 						      0x00);
935 			snd_soc_component_update_bits(component, hpf_gate_reg,
936 					      CDC_TXn_HPF_F_CHANGE_MASK |
937 					      CDC_TXn_HPF_ZERO_GATE_MASK,
938 					      0x01);
939 
940 			/*
941 			 * 6ms delay is required as per HW spec
942 			 */
943 			usleep_range(6000, 6010);
944 		}
945 		/* apply gain after decimator is enabled */
946 		snd_soc_component_write(component, tx_gain_ctl_reg,
947 			      snd_soc_component_read(component,
948 					tx_gain_ctl_reg));
949 		if (tx->bcs_enable) {
950 			snd_soc_component_update_bits(component, dec_cfg_reg,
951 					0x01, 0x01);
952 			tx->bcs_clk_en = true;
953 		}
954 		break;
955 	case SND_SOC_DAPM_PRE_PMD:
956 		hpf_cut_off_freq =
957 			tx->tx_hpf_work[decimator].hpf_cut_off_freq;
958 		snd_soc_component_write_field(component, tx_vol_ctl_reg,
959 					      CDC_TXn_PGA_MUTE_MASK, 0x1);
960 		if (cancel_delayed_work_sync(
961 		    &tx->tx_hpf_work[decimator].dwork)) {
962 			if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
963 				snd_soc_component_write_field(
964 						component, dec_cfg_reg,
965 						CDC_TXn_HPF_CUT_FREQ_MASK,
966 						hpf_cut_off_freq);
967 				if (is_amic_enabled(component, decimator))
968 					snd_soc_component_update_bits(component,
969 					      hpf_gate_reg,
970 					      CDC_TXn_HPF_F_CHANGE_MASK |
971 					      CDC_TXn_HPF_ZERO_GATE_MASK,
972 					      0x02);
973 				else
974 					snd_soc_component_update_bits(component,
975 					      hpf_gate_reg,
976 					      CDC_TXn_HPF_F_CHANGE_MASK |
977 					      CDC_TXn_HPF_ZERO_GATE_MASK,
978 					      0x03);
979 
980 				/*
981 				 * Minimum 1 clk cycle delay is required
982 				 * as per HW spec
983 				 */
984 				usleep_range(1000, 1010);
985 				snd_soc_component_update_bits(component, hpf_gate_reg,
986 					      CDC_TXn_HPF_F_CHANGE_MASK |
987 					      CDC_TXn_HPF_ZERO_GATE_MASK,
988 					      0x1);
989 			}
990 		}
991 		cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork);
992 		break;
993 	case SND_SOC_DAPM_POST_PMD:
994 		snd_soc_component_write_field(component, tx_vol_ctl_reg,
995 					      CDC_TXn_CLK_EN_MASK, 0x0);
996 		snd_soc_component_write_field(component, dec_cfg_reg,
997 					      CDC_TXn_ADC_MODE_MASK, 0x0);
998 		snd_soc_component_write_field(component, tx_vol_ctl_reg,
999 					      CDC_TXn_PGA_MUTE_MASK, 0x0);
1000 		if (tx->bcs_enable) {
1001 			snd_soc_component_write_field(component, dec_cfg_reg,
1002 						      CDC_TXn_PH_EN_MASK, 0x0);
1003 			snd_soc_component_write_field(component,
1004 						      CDC_TX0_TX_PATH_SEC7,
1005 						      CDC_TX0_MBHC_CTL_EN_MASK,
1006 						      0x0);
1007 			tx->bcs_clk_en = false;
1008 		}
1009 		break;
1010 	}
1011 	return 0;
1012 }
1013 
1014 static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
1015 				 struct snd_ctl_elem_value *ucontrol)
1016 {
1017 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1018 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1019 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1020 	int path = e->shift_l;
1021 
1022 	ucontrol->value.integer.value[0] = tx->dec_mode[path];
1023 
1024 	return 0;
1025 }
1026 
1027 static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
1028 				 struct snd_ctl_elem_value *ucontrol)
1029 {
1030 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1031 	int value = ucontrol->value.integer.value[0];
1032 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1033 	int path = e->shift_l;
1034 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1035 
1036 	if (tx->dec_mode[path] == value)
1037 		return 0;
1038 
1039 	tx->dec_mode[path] = value;
1040 
1041 	return 1;
1042 }
1043 
1044 static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol,
1045 			    struct snd_ctl_elem_value *ucontrol)
1046 {
1047 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1048 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1049 
1050 	ucontrol->value.integer.value[0] = tx->bcs_enable;
1051 
1052 	return 0;
1053 }
1054 
1055 static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol,
1056 			    struct snd_ctl_elem_value *ucontrol)
1057 {
1058 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1059 	int value = ucontrol->value.integer.value[0];
1060 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1061 
1062 	tx->bcs_enable = value;
1063 
1064 	return 0;
1065 }
1066 
1067 static int tx_macro_hw_params(struct snd_pcm_substream *substream,
1068 			      struct snd_pcm_hw_params *params,
1069 			      struct snd_soc_dai *dai)
1070 {
1071 	struct snd_soc_component *component = dai->component;
1072 	u32 sample_rate;
1073 	u8 decimator;
1074 	int tx_fs_rate;
1075 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1076 
1077 	sample_rate = params_rate(params);
1078 	switch (sample_rate) {
1079 	case 8000:
1080 		tx_fs_rate = 0;
1081 		break;
1082 	case 16000:
1083 		tx_fs_rate = 1;
1084 		break;
1085 	case 32000:
1086 		tx_fs_rate = 3;
1087 		break;
1088 	case 48000:
1089 		tx_fs_rate = 4;
1090 		break;
1091 	case 96000:
1092 		tx_fs_rate = 5;
1093 		break;
1094 	case 192000:
1095 		tx_fs_rate = 6;
1096 		break;
1097 	case 384000:
1098 		tx_fs_rate = 7;
1099 		break;
1100 	default:
1101 		dev_err(component->dev, "%s: Invalid TX sample rate: %d\n",
1102 			__func__, params_rate(params));
1103 		return -EINVAL;
1104 	}
1105 
1106 	for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX)
1107 		snd_soc_component_update_bits(component, CDC_TXn_TX_PATH_CTL(decimator),
1108 					      CDC_TXn_PCM_RATE_MASK,
1109 					      tx_fs_rate);
1110 	return 0;
1111 }
1112 
1113 static int tx_macro_get_channel_map(struct snd_soc_dai *dai,
1114 				    unsigned int *tx_num, unsigned int *tx_slot,
1115 				    unsigned int *rx_num, unsigned int *rx_slot)
1116 {
1117 	struct snd_soc_component *component = dai->component;
1118 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1119 
1120 	switch (dai->id) {
1121 	case TX_MACRO_AIF1_CAP:
1122 	case TX_MACRO_AIF2_CAP:
1123 	case TX_MACRO_AIF3_CAP:
1124 		*tx_slot = tx->active_ch_mask[dai->id];
1125 		*tx_num = tx->active_ch_cnt[dai->id];
1126 		break;
1127 	default:
1128 		break;
1129 	}
1130 	return 0;
1131 }
1132 
1133 static int tx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1134 {
1135 	struct snd_soc_component *component = dai->component;
1136 	struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1137 	u8 decimator;
1138 
1139 	/* active decimator not set yet */
1140 	if (tx->active_decimator[dai->id] == -1)
1141 		return 0;
1142 
1143 	decimator = tx->active_decimator[dai->id];
1144 
1145 	if (mute)
1146 		snd_soc_component_write_field(component,
1147 					      CDC_TXn_TX_PATH_CTL(decimator),
1148 					      CDC_TXn_PGA_MUTE_MASK, 0x1);
1149 	else
1150 		snd_soc_component_update_bits(component,
1151 					      CDC_TXn_TX_PATH_CTL(decimator),
1152 					      CDC_TXn_PGA_MUTE_MASK, 0x0);
1153 
1154 	return 0;
1155 }
1156 
1157 static const struct snd_soc_dai_ops tx_macro_dai_ops = {
1158 	.hw_params = tx_macro_hw_params,
1159 	.get_channel_map = tx_macro_get_channel_map,
1160 	.mute_stream = tx_macro_digital_mute,
1161 };
1162 
1163 static struct snd_soc_dai_driver tx_macro_dai[] = {
1164 	{
1165 		.name = "tx_macro_tx1",
1166 		.id = TX_MACRO_AIF1_CAP,
1167 		.capture = {
1168 			.stream_name = "TX_AIF1 Capture",
1169 			.rates = TX_MACRO_RATES,
1170 			.formats = TX_MACRO_FORMATS,
1171 			.rate_max = 192000,
1172 			.rate_min = 8000,
1173 			.channels_min = 1,
1174 			.channels_max = 8,
1175 		},
1176 		.ops = &tx_macro_dai_ops,
1177 	},
1178 	{
1179 		.name = "tx_macro_tx2",
1180 		.id = TX_MACRO_AIF2_CAP,
1181 		.capture = {
1182 			.stream_name = "TX_AIF2 Capture",
1183 			.rates = TX_MACRO_RATES,
1184 			.formats = TX_MACRO_FORMATS,
1185 			.rate_max = 192000,
1186 			.rate_min = 8000,
1187 			.channels_min = 1,
1188 			.channels_max = 8,
1189 		},
1190 		.ops = &tx_macro_dai_ops,
1191 	},
1192 	{
1193 		.name = "tx_macro_tx3",
1194 		.id = TX_MACRO_AIF3_CAP,
1195 		.capture = {
1196 			.stream_name = "TX_AIF3 Capture",
1197 			.rates = TX_MACRO_RATES,
1198 			.formats = TX_MACRO_FORMATS,
1199 			.rate_max = 192000,
1200 			.rate_min = 8000,
1201 			.channels_min = 1,
1202 			.channels_max = 8,
1203 		},
1204 		.ops = &tx_macro_dai_ops,
1205 	},
1206 };
1207 
1208 static const char * const adc_mux_text[] = {
1209 	"MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1"
1210 };
1211 
1212 static SOC_ENUM_SINGLE_DECL(tx_dec0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1,
1213 		   0, adc_mux_text);
1214 static SOC_ENUM_SINGLE_DECL(tx_dec1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1,
1215 		   0, adc_mux_text);
1216 static SOC_ENUM_SINGLE_DECL(tx_dec2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1,
1217 		   0, adc_mux_text);
1218 static SOC_ENUM_SINGLE_DECL(tx_dec3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1,
1219 		   0, adc_mux_text);
1220 static SOC_ENUM_SINGLE_DECL(tx_dec4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1,
1221 		   0, adc_mux_text);
1222 static SOC_ENUM_SINGLE_DECL(tx_dec5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1,
1223 		   0, adc_mux_text);
1224 static SOC_ENUM_SINGLE_DECL(tx_dec6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1,
1225 		   0, adc_mux_text);
1226 static SOC_ENUM_SINGLE_DECL(tx_dec7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1,
1227 		   0, adc_mux_text);
1228 
1229 static const struct snd_kcontrol_new tx_dec0_mux = SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum);
1230 static const struct snd_kcontrol_new tx_dec1_mux = SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum);
1231 static const struct snd_kcontrol_new tx_dec2_mux = SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum);
1232 static const struct snd_kcontrol_new tx_dec3_mux = SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum);
1233 static const struct snd_kcontrol_new tx_dec4_mux = SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum);
1234 static const struct snd_kcontrol_new tx_dec5_mux = SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum);
1235 static const struct snd_kcontrol_new tx_dec6_mux = SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum);
1236 static const struct snd_kcontrol_new tx_dec7_mux = SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum);
1237 
1238 static const char * const smic_mux_text[] = {
1239 	"ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0",
1240 	"SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4",
1241 	"SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7"
1242 };
1243 
1244 static SOC_ENUM_SINGLE_DECL(tx_smic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
1245 			0, smic_mux_text);
1246 
1247 static SOC_ENUM_SINGLE_DECL(tx_smic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
1248 			0, smic_mux_text);
1249 
1250 static SOC_ENUM_SINGLE_DECL(tx_smic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
1251 			0, smic_mux_text);
1252 
1253 static SOC_ENUM_SINGLE_DECL(tx_smic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
1254 			0, smic_mux_text);
1255 
1256 static SOC_ENUM_SINGLE_DECL(tx_smic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
1257 			0, smic_mux_text);
1258 
1259 static SOC_ENUM_SINGLE_DECL(tx_smic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
1260 			0, smic_mux_text);
1261 
1262 static SOC_ENUM_SINGLE_DECL(tx_smic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
1263 			0, smic_mux_text);
1264 
1265 static SOC_ENUM_SINGLE_DECL(tx_smic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
1266 			0, smic_mux_text);
1267 
1268 static const struct snd_kcontrol_new tx_smic0_mux = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum,
1269 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1270 static const struct snd_kcontrol_new tx_smic1_mux = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum,
1271 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1272 static const struct snd_kcontrol_new tx_smic2_mux = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum,
1273 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1274 static const struct snd_kcontrol_new tx_smic3_mux = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum,
1275 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1276 static const struct snd_kcontrol_new tx_smic4_mux = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum,
1277 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1278 static const struct snd_kcontrol_new tx_smic5_mux = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum,
1279 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1280 static const struct snd_kcontrol_new tx_smic6_mux = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum,
1281 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1282 static const struct snd_kcontrol_new tx_smic7_mux = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum,
1283 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1284 
1285 static const char * const dmic_mux_text[] = {
1286 	"ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
1287 	"DMIC4", "DMIC5", "DMIC6", "DMIC7"
1288 };
1289 
1290 static SOC_ENUM_SINGLE_DECL(tx_dmic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
1291 			4, dmic_mux_text);
1292 
1293 static SOC_ENUM_SINGLE_DECL(tx_dmic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
1294 			4, dmic_mux_text);
1295 
1296 static SOC_ENUM_SINGLE_DECL(tx_dmic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
1297 			4, dmic_mux_text);
1298 
1299 static SOC_ENUM_SINGLE_DECL(tx_dmic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
1300 			4, dmic_mux_text);
1301 
1302 static SOC_ENUM_SINGLE_DECL(tx_dmic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
1303 			4, dmic_mux_text);
1304 
1305 static SOC_ENUM_SINGLE_DECL(tx_dmic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
1306 			4, dmic_mux_text);
1307 
1308 static SOC_ENUM_SINGLE_DECL(tx_dmic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
1309 			4, dmic_mux_text);
1310 
1311 static SOC_ENUM_SINGLE_DECL(tx_dmic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
1312 			4, dmic_mux_text);
1313 
1314 static const struct snd_kcontrol_new tx_dmic0_mux = SOC_DAPM_ENUM_EXT("tx_dmic0", tx_dmic0_enum,
1315 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1316 static const struct snd_kcontrol_new tx_dmic1_mux = SOC_DAPM_ENUM_EXT("tx_dmic1", tx_dmic1_enum,
1317 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1318 static const struct snd_kcontrol_new tx_dmic2_mux = SOC_DAPM_ENUM_EXT("tx_dmic2", tx_dmic2_enum,
1319 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1320 static const struct snd_kcontrol_new tx_dmic3_mux = SOC_DAPM_ENUM_EXT("tx_dmic3", tx_dmic3_enum,
1321 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1322 static const struct snd_kcontrol_new tx_dmic4_mux = SOC_DAPM_ENUM_EXT("tx_dmic4", tx_dmic4_enum,
1323 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1324 static const struct snd_kcontrol_new tx_dmic5_mux = SOC_DAPM_ENUM_EXT("tx_dmic5", tx_dmic5_enum,
1325 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1326 static const struct snd_kcontrol_new tx_dmic6_mux = SOC_DAPM_ENUM_EXT("tx_dmic6", tx_dmic6_enum,
1327 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1328 static const struct snd_kcontrol_new tx_dmic7_mux = SOC_DAPM_ENUM_EXT("tx_dmic7", tx_dmic7_enum,
1329 			snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1330 
1331 static const char * const dec_mode_mux_text[] = {
1332 	"ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
1333 };
1334 
1335 static const struct soc_enum dec_mode_mux_enum[] = {
1336 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1337 			dec_mode_mux_text),
1338 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
1339 			dec_mode_mux_text),
1340 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 2,  ARRAY_SIZE(dec_mode_mux_text),
1341 			dec_mode_mux_text),
1342 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
1343 			dec_mode_mux_text),
1344 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 4, ARRAY_SIZE(dec_mode_mux_text),
1345 			dec_mode_mux_text),
1346 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 5, ARRAY_SIZE(dec_mode_mux_text),
1347 			dec_mode_mux_text),
1348 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 6, ARRAY_SIZE(dec_mode_mux_text),
1349 			dec_mode_mux_text),
1350 	SOC_ENUM_SINGLE(SND_SOC_NOPM, 7, ARRAY_SIZE(dec_mode_mux_text),
1351 			dec_mode_mux_text),
1352 };
1353 
1354 static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = {
1355 	SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1356 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1357 	SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1358 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1359 	SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1360 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1361 	SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1362 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1363 	SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1364 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1365 	SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1366 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1367 	SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1368 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1369 	SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1370 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1371 };
1372 
1373 static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = {
1374 	SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1375 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1376 	SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1377 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1378 	SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1379 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1380 	SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1381 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1382 	SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1383 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1384 	SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1385 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1386 	SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1387 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1388 	SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1389 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1390 };
1391 
1392 static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = {
1393 	SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1394 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1395 	SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1396 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1397 	SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1398 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1399 	SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1400 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1401 	SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1402 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1403 	SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1404 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1405 	SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1406 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1407 	SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1408 			tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1409 };
1410 
1411 static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = {
1412 	SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0,
1413 		SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0),
1414 
1415 	SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0,
1416 		SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0),
1417 
1418 	SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0,
1419 		SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0),
1420 
1421 	SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0,
1422 		tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)),
1423 
1424 	SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0,
1425 		tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)),
1426 
1427 	SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0,
1428 		tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)),
1429 
1430 	SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux),
1431 	SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux),
1432 	SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux),
1433 	SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux),
1434 	SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux),
1435 	SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux),
1436 	SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux),
1437 	SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux),
1438 
1439 	SND_SOC_DAPM_MUX("TX DMIC MUX0", SND_SOC_NOPM, 4, 0, &tx_dmic0_mux),
1440 	SND_SOC_DAPM_MUX("TX DMIC MUX1", SND_SOC_NOPM, 4, 0, &tx_dmic1_mux),
1441 	SND_SOC_DAPM_MUX("TX DMIC MUX2", SND_SOC_NOPM, 4, 0, &tx_dmic2_mux),
1442 	SND_SOC_DAPM_MUX("TX DMIC MUX3", SND_SOC_NOPM, 4, 0, &tx_dmic3_mux),
1443 	SND_SOC_DAPM_MUX("TX DMIC MUX4", SND_SOC_NOPM, 4, 0, &tx_dmic4_mux),
1444 	SND_SOC_DAPM_MUX("TX DMIC MUX5", SND_SOC_NOPM, 4, 0, &tx_dmic5_mux),
1445 	SND_SOC_DAPM_MUX("TX DMIC MUX6", SND_SOC_NOPM, 4, 0, &tx_dmic6_mux),
1446 	SND_SOC_DAPM_MUX("TX DMIC MUX7", SND_SOC_NOPM, 4, 0, &tx_dmic7_mux),
1447 
1448 	SND_SOC_DAPM_INPUT("TX SWR_ADC0"),
1449 	SND_SOC_DAPM_INPUT("TX SWR_ADC1"),
1450 	SND_SOC_DAPM_INPUT("TX SWR_ADC2"),
1451 	SND_SOC_DAPM_INPUT("TX SWR_ADC3"),
1452 	SND_SOC_DAPM_INPUT("TX SWR_DMIC0"),
1453 	SND_SOC_DAPM_INPUT("TX SWR_DMIC1"),
1454 	SND_SOC_DAPM_INPUT("TX SWR_DMIC2"),
1455 	SND_SOC_DAPM_INPUT("TX SWR_DMIC3"),
1456 	SND_SOC_DAPM_INPUT("TX SWR_DMIC4"),
1457 	SND_SOC_DAPM_INPUT("TX SWR_DMIC5"),
1458 	SND_SOC_DAPM_INPUT("TX SWR_DMIC6"),
1459 	SND_SOC_DAPM_INPUT("TX SWR_DMIC7"),
1460 	SND_SOC_DAPM_INPUT("TX DMIC0"),
1461 	SND_SOC_DAPM_INPUT("TX DMIC1"),
1462 	SND_SOC_DAPM_INPUT("TX DMIC2"),
1463 	SND_SOC_DAPM_INPUT("TX DMIC3"),
1464 	SND_SOC_DAPM_INPUT("TX DMIC4"),
1465 	SND_SOC_DAPM_INPUT("TX DMIC5"),
1466 	SND_SOC_DAPM_INPUT("TX DMIC6"),
1467 	SND_SOC_DAPM_INPUT("TX DMIC7"),
1468 
1469 	SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
1470 			   TX_MACRO_DEC0, 0,
1471 			   &tx_dec0_mux, tx_macro_enable_dec,
1472 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1473 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1474 
1475 	SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
1476 			   TX_MACRO_DEC1, 0,
1477 			   &tx_dec1_mux, tx_macro_enable_dec,
1478 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1479 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1480 
1481 	SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
1482 			   TX_MACRO_DEC2, 0,
1483 			   &tx_dec2_mux, tx_macro_enable_dec,
1484 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1485 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1486 
1487 	SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
1488 			   TX_MACRO_DEC3, 0,
1489 			   &tx_dec3_mux, tx_macro_enable_dec,
1490 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1491 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1492 
1493 	SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
1494 			   TX_MACRO_DEC4, 0,
1495 			   &tx_dec4_mux, tx_macro_enable_dec,
1496 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1497 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1498 
1499 	SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
1500 			   TX_MACRO_DEC5, 0,
1501 			   &tx_dec5_mux, tx_macro_enable_dec,
1502 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1503 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1504 
1505 	SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
1506 			   TX_MACRO_DEC6, 0,
1507 			   &tx_dec6_mux, tx_macro_enable_dec,
1508 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1509 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1510 
1511 	SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
1512 			   TX_MACRO_DEC7, 0,
1513 			   &tx_dec7_mux, tx_macro_enable_dec,
1514 			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1515 			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1516 
1517 	SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0,
1518 	tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1519 
1520 	SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
1521 
1522 	SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0,
1523 			NULL, 0),
1524 };
1525 
1526 static const struct snd_soc_dapm_route tx_audio_map[] = {
1527 	{"TX_AIF1 CAP", NULL, "TX_MCLK"},
1528 	{"TX_AIF2 CAP", NULL, "TX_MCLK"},
1529 	{"TX_AIF3 CAP", NULL, "TX_MCLK"},
1530 
1531 	{"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"},
1532 	{"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"},
1533 	{"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"},
1534 
1535 	{"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1536 	{"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1537 	{"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1538 	{"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1539 	{"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1540 	{"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1541 	{"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1542 	{"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1543 
1544 	{"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1545 	{"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1546 	{"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1547 	{"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1548 	{"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1549 	{"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1550 	{"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1551 	{"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1552 
1553 	{"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1554 	{"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1555 	{"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1556 	{"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1557 	{"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1558 	{"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1559 	{"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1560 	{"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1561 
1562 	{"TX DEC0 MUX", NULL, "TX_MCLK"},
1563 	{"TX DEC1 MUX", NULL, "TX_MCLK"},
1564 	{"TX DEC2 MUX", NULL, "TX_MCLK"},
1565 	{"TX DEC3 MUX", NULL, "TX_MCLK"},
1566 	{"TX DEC4 MUX", NULL, "TX_MCLK"},
1567 	{"TX DEC5 MUX", NULL, "TX_MCLK"},
1568 	{"TX DEC6 MUX", NULL, "TX_MCLK"},
1569 	{"TX DEC7 MUX", NULL, "TX_MCLK"},
1570 
1571 	{"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"},
1572 	{"TX DMIC MUX0", "DMIC0", "TX DMIC0"},
1573 	{"TX DMIC MUX0", "DMIC1", "TX DMIC1"},
1574 	{"TX DMIC MUX0", "DMIC2", "TX DMIC2"},
1575 	{"TX DMIC MUX0", "DMIC3", "TX DMIC3"},
1576 	{"TX DMIC MUX0", "DMIC4", "TX DMIC4"},
1577 	{"TX DMIC MUX0", "DMIC5", "TX DMIC5"},
1578 	{"TX DMIC MUX0", "DMIC6", "TX DMIC6"},
1579 	{"TX DMIC MUX0", "DMIC7", "TX DMIC7"},
1580 
1581 	{"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1582 	{"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
1583 	{"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"},
1584 	{"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"},
1585 	{"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"},
1586 	{"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"},
1587 	{"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"},
1588 	{"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"},
1589 	{"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"},
1590 	{"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"},
1591 	{"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"},
1592 	{"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"},
1593 	{"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"},
1594 	{"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"},
1595 
1596 	{"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"},
1597 	{"TX DMIC MUX1", "DMIC0", "TX DMIC0"},
1598 	{"TX DMIC MUX1", "DMIC1", "TX DMIC1"},
1599 	{"TX DMIC MUX1", "DMIC2", "TX DMIC2"},
1600 	{"TX DMIC MUX1", "DMIC3", "TX DMIC3"},
1601 	{"TX DMIC MUX1", "DMIC4", "TX DMIC4"},
1602 	{"TX DMIC MUX1", "DMIC5", "TX DMIC5"},
1603 	{"TX DMIC MUX1", "DMIC6", "TX DMIC6"},
1604 	{"TX DMIC MUX1", "DMIC7", "TX DMIC7"},
1605 
1606 	{"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1607 	{"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
1608 	{"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"},
1609 	{"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"},
1610 	{"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"},
1611 	{"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"},
1612 	{"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"},
1613 	{"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"},
1614 	{"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"},
1615 	{"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"},
1616 	{"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"},
1617 	{"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"},
1618 	{"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"},
1619 	{"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"},
1620 
1621 	{"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"},
1622 	{"TX DMIC MUX2", "DMIC0", "TX DMIC0"},
1623 	{"TX DMIC MUX2", "DMIC1", "TX DMIC1"},
1624 	{"TX DMIC MUX2", "DMIC2", "TX DMIC2"},
1625 	{"TX DMIC MUX2", "DMIC3", "TX DMIC3"},
1626 	{"TX DMIC MUX2", "DMIC4", "TX DMIC4"},
1627 	{"TX DMIC MUX2", "DMIC5", "TX DMIC5"},
1628 	{"TX DMIC MUX2", "DMIC6", "TX DMIC6"},
1629 	{"TX DMIC MUX2", "DMIC7", "TX DMIC7"},
1630 
1631 	{"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1632 	{"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
1633 	{"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"},
1634 	{"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"},
1635 	{"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"},
1636 	{"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"},
1637 	{"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"},
1638 	{"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"},
1639 	{"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"},
1640 	{"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"},
1641 	{"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"},
1642 	{"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"},
1643 	{"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"},
1644 	{"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"},
1645 
1646 	{"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"},
1647 	{"TX DMIC MUX3", "DMIC0", "TX DMIC0"},
1648 	{"TX DMIC MUX3", "DMIC1", "TX DMIC1"},
1649 	{"TX DMIC MUX3", "DMIC2", "TX DMIC2"},
1650 	{"TX DMIC MUX3", "DMIC3", "TX DMIC3"},
1651 	{"TX DMIC MUX3", "DMIC4", "TX DMIC4"},
1652 	{"TX DMIC MUX3", "DMIC5", "TX DMIC5"},
1653 	{"TX DMIC MUX3", "DMIC6", "TX DMIC6"},
1654 	{"TX DMIC MUX3", "DMIC7", "TX DMIC7"},
1655 
1656 	{"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1657 	{"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
1658 	{"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"},
1659 	{"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"},
1660 	{"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"},
1661 	{"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"},
1662 	{"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"},
1663 	{"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"},
1664 	{"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"},
1665 	{"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"},
1666 	{"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"},
1667 	{"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"},
1668 	{"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"},
1669 	{"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"},
1670 
1671 	{"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"},
1672 	{"TX DMIC MUX4", "DMIC0", "TX DMIC0"},
1673 	{"TX DMIC MUX4", "DMIC1", "TX DMIC1"},
1674 	{"TX DMIC MUX4", "DMIC2", "TX DMIC2"},
1675 	{"TX DMIC MUX4", "DMIC3", "TX DMIC3"},
1676 	{"TX DMIC MUX4", "DMIC4", "TX DMIC4"},
1677 	{"TX DMIC MUX4", "DMIC5", "TX DMIC5"},
1678 	{"TX DMIC MUX4", "DMIC6", "TX DMIC6"},
1679 	{"TX DMIC MUX4", "DMIC7", "TX DMIC7"},
1680 
1681 	{"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1682 	{"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
1683 	{"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"},
1684 	{"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"},
1685 	{"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"},
1686 	{"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"},
1687 	{"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"},
1688 	{"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"},
1689 	{"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"},
1690 	{"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"},
1691 	{"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"},
1692 	{"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"},
1693 	{"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"},
1694 	{"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"},
1695 
1696 	{"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"},
1697 	{"TX DMIC MUX5", "DMIC0", "TX DMIC0"},
1698 	{"TX DMIC MUX5", "DMIC1", "TX DMIC1"},
1699 	{"TX DMIC MUX5", "DMIC2", "TX DMIC2"},
1700 	{"TX DMIC MUX5", "DMIC3", "TX DMIC3"},
1701 	{"TX DMIC MUX5", "DMIC4", "TX DMIC4"},
1702 	{"TX DMIC MUX5", "DMIC5", "TX DMIC5"},
1703 	{"TX DMIC MUX5", "DMIC6", "TX DMIC6"},
1704 	{"TX DMIC MUX5", "DMIC7", "TX DMIC7"},
1705 
1706 	{"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1707 	{"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
1708 	{"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"},
1709 	{"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"},
1710 	{"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"},
1711 	{"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"},
1712 	{"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"},
1713 	{"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"},
1714 	{"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"},
1715 	{"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"},
1716 	{"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"},
1717 	{"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"},
1718 	{"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"},
1719 	{"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"},
1720 
1721 	{"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"},
1722 	{"TX DMIC MUX6", "DMIC0", "TX DMIC0"},
1723 	{"TX DMIC MUX6", "DMIC1", "TX DMIC1"},
1724 	{"TX DMIC MUX6", "DMIC2", "TX DMIC2"},
1725 	{"TX DMIC MUX6", "DMIC3", "TX DMIC3"},
1726 	{"TX DMIC MUX6", "DMIC4", "TX DMIC4"},
1727 	{"TX DMIC MUX6", "DMIC5", "TX DMIC5"},
1728 	{"TX DMIC MUX6", "DMIC6", "TX DMIC6"},
1729 	{"TX DMIC MUX6", "DMIC7", "TX DMIC7"},
1730 
1731 	{"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
1732 	{"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
1733 	{"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"},
1734 	{"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"},
1735 	{"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"},
1736 	{"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"},
1737 	{"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"},
1738 	{"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"},
1739 	{"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"},
1740 	{"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"},
1741 	{"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"},
1742 	{"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"},
1743 	{"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"},
1744 	{"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"},
1745 
1746 	{"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"},
1747 	{"TX DMIC MUX7", "DMIC0", "TX DMIC0"},
1748 	{"TX DMIC MUX7", "DMIC1", "TX DMIC1"},
1749 	{"TX DMIC MUX7", "DMIC2", "TX DMIC2"},
1750 	{"TX DMIC MUX7", "DMIC3", "TX DMIC3"},
1751 	{"TX DMIC MUX7", "DMIC4", "TX DMIC4"},
1752 	{"TX DMIC MUX7", "DMIC5", "TX DMIC5"},
1753 	{"TX DMIC MUX7", "DMIC6", "TX DMIC6"},
1754 	{"TX DMIC MUX7", "DMIC7", "TX DMIC7"},
1755 
1756 	{"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
1757 	{"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
1758 	{"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"},
1759 	{"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"},
1760 	{"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"},
1761 	{"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"},
1762 	{"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"},
1763 	{"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"},
1764 	{"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"},
1765 	{"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"},
1766 	{"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"},
1767 	{"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"},
1768 	{"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"},
1769 	{"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"},
1770 };
1771 
1772 static const struct snd_kcontrol_new tx_macro_snd_controls[] = {
1773 	SOC_SINGLE_S8_TLV("TX_DEC0 Volume",
1774 			  CDC_TX0_TX_VOL_CTL,
1775 			  -84, 40, digital_gain),
1776 	SOC_SINGLE_S8_TLV("TX_DEC1 Volume",
1777 			  CDC_TX1_TX_VOL_CTL,
1778 			  -84, 40, digital_gain),
1779 	SOC_SINGLE_S8_TLV("TX_DEC2 Volume",
1780 			  CDC_TX2_TX_VOL_CTL,
1781 			  -84, 40, digital_gain),
1782 	SOC_SINGLE_S8_TLV("TX_DEC3 Volume",
1783 			  CDC_TX3_TX_VOL_CTL,
1784 			  -84, 40, digital_gain),
1785 	SOC_SINGLE_S8_TLV("TX_DEC4 Volume",
1786 			  CDC_TX4_TX_VOL_CTL,
1787 			  -84, 40, digital_gain),
1788 	SOC_SINGLE_S8_TLV("TX_DEC5 Volume",
1789 			  CDC_TX5_TX_VOL_CTL,
1790 			  -84, 40, digital_gain),
1791 	SOC_SINGLE_S8_TLV("TX_DEC6 Volume",
1792 			  CDC_TX6_TX_VOL_CTL,
1793 			  -84, 40, digital_gain),
1794 	SOC_SINGLE_S8_TLV("TX_DEC7 Volume",
1795 			  CDC_TX7_TX_VOL_CTL,
1796 			  -84, 40, digital_gain),
1797 
1798 	SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0],
1799 			tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1800 
1801 	SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum[1],
1802 			tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1803 
1804 	SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum[2],
1805 			tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1806 
1807 	SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum[3],
1808 			tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1809 
1810 	SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum[4],
1811 			tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1812 
1813 	SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum[5],
1814 			tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1815 
1816 	SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum[6],
1817 			tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1818 
1819 	SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum[7],
1820 			tx_macro_dec_mode_get, tx_macro_dec_mode_put),
1821 
1822 	SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0,
1823 		       tx_macro_get_bcs, tx_macro_set_bcs),
1824 };
1825 
1826 static int tx_macro_component_probe(struct snd_soc_component *comp)
1827 {
1828 	struct tx_macro *tx = snd_soc_component_get_drvdata(comp);
1829 	int i;
1830 
1831 	snd_soc_component_init_regmap(comp, tx->regmap);
1832 
1833 	for (i = 0; i < NUM_DECIMATORS; i++) {
1834 		tx->tx_hpf_work[i].tx = tx;
1835 		tx->tx_hpf_work[i].decimator = i;
1836 		INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork,
1837 			tx_macro_tx_hpf_corner_freq_callback);
1838 	}
1839 
1840 	for (i = 0; i < NUM_DECIMATORS; i++) {
1841 		tx->tx_mute_dwork[i].tx = tx;
1842 		tx->tx_mute_dwork[i].decimator = i;
1843 		INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork,
1844 			  tx_macro_mute_update_callback);
1845 	}
1846 	tx->component = comp;
1847 
1848 	snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F,
1849 				      0x0A);
1850 	/* Enable swr mic0 and mic1 clock */
1851 	snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0xFF, 0x00);
1852 	snd_soc_component_update_bits(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0xFF, 0x00);
1853 
1854 	return 0;
1855 }
1856 
1857 static int swclk_gate_enable(struct clk_hw *hw)
1858 {
1859 	struct tx_macro *tx = to_tx_macro(hw);
1860 	struct regmap *regmap = tx->regmap;
1861 	int ret;
1862 
1863 	ret = clk_prepare_enable(tx->mclk);
1864 	if (ret) {
1865 		dev_err(tx->dev, "failed to enable mclk\n");
1866 		return ret;
1867 	}
1868 
1869 	tx_macro_mclk_enable(tx, true);
1870 
1871 	regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1872 			   CDC_TX_SWR_CLK_EN_MASK,
1873 			   CDC_TX_SWR_CLK_ENABLE);
1874 	return 0;
1875 }
1876 
1877 static void swclk_gate_disable(struct clk_hw *hw)
1878 {
1879 	struct tx_macro *tx = to_tx_macro(hw);
1880 	struct regmap *regmap = tx->regmap;
1881 
1882 	regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
1883 			   CDC_TX_SWR_CLK_EN_MASK, 0x0);
1884 
1885 	tx_macro_mclk_enable(tx, false);
1886 	clk_disable_unprepare(tx->mclk);
1887 }
1888 
1889 static int swclk_gate_is_enabled(struct clk_hw *hw)
1890 {
1891 	struct tx_macro *tx = to_tx_macro(hw);
1892 	int ret, val;
1893 
1894 	regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val);
1895 	ret = val & BIT(0);
1896 
1897 	return ret;
1898 }
1899 
1900 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
1901 				       unsigned long parent_rate)
1902 {
1903 	return parent_rate / 2;
1904 }
1905 
1906 static const struct clk_ops swclk_gate_ops = {
1907 	.prepare = swclk_gate_enable,
1908 	.unprepare = swclk_gate_disable,
1909 	.is_enabled = swclk_gate_is_enabled,
1910 	.recalc_rate = swclk_recalc_rate,
1911 
1912 };
1913 
1914 static int tx_macro_register_mclk_output(struct tx_macro *tx)
1915 {
1916 	struct device *dev = tx->dev;
1917 	const char *parent_clk_name = NULL;
1918 	const char *clk_name = "lpass-tx-mclk";
1919 	struct clk_hw *hw;
1920 	struct clk_init_data init;
1921 	int ret;
1922 
1923 	if (tx->npl)
1924 		parent_clk_name = __clk_get_name(tx->npl);
1925 	else
1926 		parent_clk_name = __clk_get_name(tx->mclk);
1927 
1928 	init.name = clk_name;
1929 	init.ops = &swclk_gate_ops;
1930 	init.flags = 0;
1931 	init.parent_names = &parent_clk_name;
1932 	init.num_parents = 1;
1933 	tx->hw.init = &init;
1934 	hw = &tx->hw;
1935 	ret = devm_clk_hw_register(dev, hw);
1936 	if (ret)
1937 		return ret;
1938 
1939 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
1940 }
1941 
1942 static const struct snd_soc_component_driver tx_macro_component_drv = {
1943 	.name = "RX-MACRO",
1944 	.probe = tx_macro_component_probe,
1945 	.controls = tx_macro_snd_controls,
1946 	.num_controls = ARRAY_SIZE(tx_macro_snd_controls),
1947 	.dapm_widgets = tx_macro_dapm_widgets,
1948 	.num_dapm_widgets = ARRAY_SIZE(tx_macro_dapm_widgets),
1949 	.dapm_routes = tx_audio_map,
1950 	.num_dapm_routes = ARRAY_SIZE(tx_audio_map),
1951 };
1952 
1953 static int tx_macro_probe(struct platform_device *pdev)
1954 {
1955 	struct device *dev = &pdev->dev;
1956 	struct device_node *np = dev->of_node;
1957 	kernel_ulong_t flags;
1958 	struct tx_macro *tx;
1959 	void __iomem *base;
1960 	int ret, reg;
1961 
1962 	flags = (kernel_ulong_t)device_get_match_data(dev);
1963 
1964 	tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL);
1965 	if (!tx)
1966 		return -ENOMEM;
1967 
1968 	tx->macro = devm_clk_get_optional(dev, "macro");
1969 	if (IS_ERR(tx->macro))
1970 		return dev_err_probe(dev, PTR_ERR(tx->macro), "unable to get macro clock\n");
1971 
1972 	tx->dcodec = devm_clk_get_optional(dev, "dcodec");
1973 	if (IS_ERR(tx->dcodec))
1974 		return dev_err_probe(dev, PTR_ERR(tx->dcodec), "unable to get dcodec clock\n");
1975 
1976 	tx->mclk = devm_clk_get(dev, "mclk");
1977 	if (IS_ERR(tx->mclk))
1978 		return dev_err_probe(dev, PTR_ERR(tx->mclk), "unable to get mclk clock\n");
1979 
1980 	if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) {
1981 		tx->npl = devm_clk_get(dev, "npl");
1982 		if (IS_ERR(tx->npl))
1983 			return dev_err_probe(dev, PTR_ERR(tx->npl), "unable to get npl clock\n");
1984 	}
1985 
1986 	tx->fsgen = devm_clk_get(dev, "fsgen");
1987 	if (IS_ERR(tx->fsgen))
1988 		return dev_err_probe(dev, PTR_ERR(tx->fsgen), "unable to get fsgen clock\n");
1989 
1990 	tx->pds = lpass_macro_pds_init(dev);
1991 	if (IS_ERR(tx->pds))
1992 		return PTR_ERR(tx->pds);
1993 
1994 	base = devm_platform_ioremap_resource(pdev, 0);
1995 	if (IS_ERR(base)) {
1996 		ret = PTR_ERR(base);
1997 		goto err;
1998 	}
1999 
2000 	/* Update defaults for lpass sc7280 */
2001 	if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) {
2002 		for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) {
2003 			switch (tx_defaults[reg].reg) {
2004 			case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
2005 			case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
2006 				tx_defaults[reg].def = 0x0E;
2007 				break;
2008 			default:
2009 				break;
2010 			}
2011 		}
2012 	}
2013 
2014 	tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config);
2015 	if (IS_ERR(tx->regmap)) {
2016 		ret = PTR_ERR(tx->regmap);
2017 		goto err;
2018 	}
2019 
2020 	dev_set_drvdata(dev, tx);
2021 
2022 	tx->dev = dev;
2023 
2024 	/* set MCLK and NPL rates */
2025 	clk_set_rate(tx->mclk, MCLK_FREQ);
2026 	clk_set_rate(tx->npl, MCLK_FREQ);
2027 
2028 	ret = clk_prepare_enable(tx->macro);
2029 	if (ret)
2030 		goto err;
2031 
2032 	ret = clk_prepare_enable(tx->dcodec);
2033 	if (ret)
2034 		goto err_dcodec;
2035 
2036 	ret = clk_prepare_enable(tx->mclk);
2037 	if (ret)
2038 		goto err_mclk;
2039 
2040 	ret = clk_prepare_enable(tx->npl);
2041 	if (ret)
2042 		goto err_npl;
2043 
2044 	ret = clk_prepare_enable(tx->fsgen);
2045 	if (ret)
2046 		goto err_fsgen;
2047 
2048 	/* reset soundwire block */
2049 	regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
2050 			   CDC_TX_SWR_RESET_MASK, CDC_TX_SWR_RESET_ENABLE);
2051 
2052 	regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
2053 			   CDC_TX_SWR_CLK_EN_MASK,
2054 			   CDC_TX_SWR_CLK_ENABLE);
2055 	regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
2056 			   CDC_TX_SWR_RESET_MASK, 0x0);
2057 
2058 	ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv,
2059 					      tx_macro_dai,
2060 					      ARRAY_SIZE(tx_macro_dai));
2061 	if (ret)
2062 		goto err_clkout;
2063 
2064 	pm_runtime_set_autosuspend_delay(dev, 3000);
2065 	pm_runtime_use_autosuspend(dev);
2066 	pm_runtime_mark_last_busy(dev);
2067 	pm_runtime_set_active(dev);
2068 	pm_runtime_enable(dev);
2069 
2070 	ret = tx_macro_register_mclk_output(tx);
2071 	if (ret)
2072 		goto err_clkout;
2073 
2074 	return 0;
2075 
2076 err_clkout:
2077 	clk_disable_unprepare(tx->fsgen);
2078 err_fsgen:
2079 	clk_disable_unprepare(tx->npl);
2080 err_npl:
2081 	clk_disable_unprepare(tx->mclk);
2082 err_mclk:
2083 	clk_disable_unprepare(tx->dcodec);
2084 err_dcodec:
2085 	clk_disable_unprepare(tx->macro);
2086 err:
2087 	lpass_macro_pds_exit(tx->pds);
2088 
2089 	return ret;
2090 }
2091 
2092 static void tx_macro_remove(struct platform_device *pdev)
2093 {
2094 	struct tx_macro *tx = dev_get_drvdata(&pdev->dev);
2095 
2096 	clk_disable_unprepare(tx->macro);
2097 	clk_disable_unprepare(tx->dcodec);
2098 	clk_disable_unprepare(tx->mclk);
2099 	clk_disable_unprepare(tx->npl);
2100 	clk_disable_unprepare(tx->fsgen);
2101 
2102 	lpass_macro_pds_exit(tx->pds);
2103 }
2104 
2105 static int __maybe_unused tx_macro_runtime_suspend(struct device *dev)
2106 {
2107 	struct tx_macro *tx = dev_get_drvdata(dev);
2108 
2109 	regcache_cache_only(tx->regmap, true);
2110 	regcache_mark_dirty(tx->regmap);
2111 
2112 	clk_disable_unprepare(tx->fsgen);
2113 	clk_disable_unprepare(tx->npl);
2114 	clk_disable_unprepare(tx->mclk);
2115 
2116 	return 0;
2117 }
2118 
2119 static int __maybe_unused tx_macro_runtime_resume(struct device *dev)
2120 {
2121 	struct tx_macro *tx = dev_get_drvdata(dev);
2122 	int ret;
2123 
2124 	ret = clk_prepare_enable(tx->mclk);
2125 	if (ret) {
2126 		dev_err(dev, "unable to prepare mclk\n");
2127 		return ret;
2128 	}
2129 
2130 	ret = clk_prepare_enable(tx->npl);
2131 	if (ret) {
2132 		dev_err(dev, "unable to prepare npl\n");
2133 		goto err_npl;
2134 	}
2135 
2136 	ret = clk_prepare_enable(tx->fsgen);
2137 	if (ret) {
2138 		dev_err(dev, "unable to prepare fsgen\n");
2139 		goto err_fsgen;
2140 	}
2141 
2142 	regcache_cache_only(tx->regmap, false);
2143 	regcache_sync(tx->regmap);
2144 
2145 	return 0;
2146 err_fsgen:
2147 	clk_disable_unprepare(tx->npl);
2148 err_npl:
2149 	clk_disable_unprepare(tx->mclk);
2150 
2151 	return ret;
2152 }
2153 
2154 static const struct dev_pm_ops tx_macro_pm_ops = {
2155 	SET_RUNTIME_PM_OPS(tx_macro_runtime_suspend, tx_macro_runtime_resume, NULL)
2156 };
2157 
2158 static const struct of_device_id tx_macro_dt_match[] = {
2159 	{
2160 		.compatible = "qcom,sc7280-lpass-tx-macro",
2161 		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
2162 	}, {
2163 		.compatible = "qcom,sm8250-lpass-tx-macro",
2164 		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
2165 	}, {
2166 		.compatible = "qcom,sm8450-lpass-tx-macro",
2167 		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
2168 	}, {
2169 		.compatible = "qcom,sm8550-lpass-tx-macro",
2170 	}, {
2171 		.compatible = "qcom,sc8280xp-lpass-tx-macro",
2172 		.data = (void *)LPASS_MACRO_FLAG_HAS_NPL_CLOCK,
2173 	},
2174 	{ }
2175 };
2176 MODULE_DEVICE_TABLE(of, tx_macro_dt_match);
2177 static struct platform_driver tx_macro_driver = {
2178 	.driver = {
2179 		.name = "tx_macro",
2180 		.of_match_table = tx_macro_dt_match,
2181 		.suppress_bind_attrs = true,
2182 		.pm = &tx_macro_pm_ops,
2183 	},
2184 	.probe = tx_macro_probe,
2185 	.remove_new = tx_macro_remove,
2186 };
2187 
2188 module_platform_driver(tx_macro_driver);
2189 
2190 MODULE_DESCRIPTION("TX macro driver");
2191 MODULE_LICENSE("GPL");
2192