1b886d83cSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2dbf7a733SM R Swami Reddy /* 3dbf7a733SM R Swami Reddy * lm49453.h - LM49453 ALSA Soc Audio drive 4dbf7a733SM R Swami Reddy * 5dbf7a733SM R Swami Reddy * Copyright (c) 2012 Texas Instruments, Inc 6dbf7a733SM R Swami Reddy */ 7dbf7a733SM R Swami Reddy 8dbf7a733SM R Swami Reddy #ifndef _LM49453_H 9dbf7a733SM R Swami Reddy #define _LM49453_H 10dbf7a733SM R Swami Reddy 11dbf7a733SM R Swami Reddy #include <linux/bitops.h> 12dbf7a733SM R Swami Reddy 13dbf7a733SM R Swami Reddy /* LM49453_P0 register space for page0 */ 14dbf7a733SM R Swami Reddy #define LM49453_P0_PMC_SETUP_REG 0x00 15dbf7a733SM R Swami Reddy #define LM49453_P0_PLL_CLK_SEL1_REG 0x01 16dbf7a733SM R Swami Reddy #define LM49453_P0_PLL_CLK_SEL2_REG 0x02 17dbf7a733SM R Swami Reddy #define LM49453_P0_PMC_CLK_DIV_REG 0x03 18dbf7a733SM R Swami Reddy #define LM49453_P0_HSDET_CLK_DIV_REG 0x04 19dbf7a733SM R Swami Reddy #define LM49453_P0_DMIC_CLK_DIV_REG 0x05 20dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_CLK_DIV_REG 0x06 21dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_OT_CLK_DIV_REG 0x07 22dbf7a733SM R Swami Reddy #define LM49453_P0_PLL_HF_M_REG 0x08 23dbf7a733SM R Swami Reddy #define LM49453_P0_PLL_LF_M_REG 0x09 24dbf7a733SM R Swami Reddy #define LM49453_P0_PLL_NL_REG 0x0A 25dbf7a733SM R Swami Reddy #define LM49453_P0_PLL_N_MODL_REG 0x0B 26dbf7a733SM R Swami Reddy #define LM49453_P0_PLL_N_MODH_REG 0x0C 27dbf7a733SM R Swami Reddy #define LM49453_P0_PLL_P1_REG 0x0D 28dbf7a733SM R Swami Reddy #define LM49453_P0_PLL_P2_REG 0x0E 29dbf7a733SM R Swami Reddy #define LM49453_P0_FLL_REF_FREQL_REG 0x0F 30dbf7a733SM R Swami Reddy #define LM49453_P0_FLL_REF_FREQH_REG 0x10 31dbf7a733SM R Swami Reddy #define LM49453_P0_VCO_TARGETLL_REG 0x11 32dbf7a733SM R Swami Reddy #define LM49453_P0_VCO_TARGETLH_REG 0x12 33dbf7a733SM R Swami Reddy #define LM49453_P0_VCO_TARGETHL_REG 0x13 34dbf7a733SM R Swami Reddy #define LM49453_P0_VCO_TARGETHH_REG 0x14 35dbf7a733SM R Swami Reddy #define LM49453_P0_PLL_CONFIG_REG 0x15 36dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_CLK_SEL_REG 0x16 37dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_HP_CLK_DIV_REG 0x17 38dbf7a733SM R Swami Reddy 39dbf7a733SM R Swami Reddy /* Analog Mixer Input Stages */ 40dbf7a733SM R Swami Reddy #define LM49453_P0_MICL_REG 0x20 41dbf7a733SM R Swami Reddy #define LM49453_P0_MICR_REG 0x21 42dbf7a733SM R Swami Reddy #define LM49453_P0_EP_REG 0x24 43dbf7a733SM R Swami Reddy #define LM49453_P0_DIS_PKVL_FB_REG 0x25 44dbf7a733SM R Swami Reddy 45dbf7a733SM R Swami Reddy /* Analog Mixer Output Stages */ 46dbf7a733SM R Swami Reddy #define LM49453_P0_ANALOG_MIXER_ADC_REG 0x2E 47dbf7a733SM R Swami Reddy 48dbf7a733SM R Swami Reddy /*ADC or DAC */ 49dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_DSP_REG 0x30 50dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_DSP_REG 0x31 51dbf7a733SM R Swami Reddy 52dbf7a733SM R Swami Reddy /* EFFECTS ENABLES */ 53dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_FX_ENABLES_REG 0x33 54dbf7a733SM R Swami Reddy 55dbf7a733SM R Swami Reddy /* GPIO */ 56dbf7a733SM R Swami Reddy #define LM49453_P0_GPIO1_REG 0x38 57dbf7a733SM R Swami Reddy #define LM49453_P0_GPIO2_REG 0x39 58dbf7a733SM R Swami Reddy #define LM49453_P0_GPIO3_REG 0x3A 59dbf7a733SM R Swami Reddy #define LM49453_P0_HAP_CTL_REG 0x3B 60dbf7a733SM R Swami Reddy #define LM49453_P0_HAP_FREQ_PROG_LEFTL_REG 0x3C 61dbf7a733SM R Swami Reddy #define LM49453_P0_HAP_FREQ_PROG_LEFTH_REG 0x3D 62dbf7a733SM R Swami Reddy #define LM49453_P0_HAP_FREQ_PROG_RIGHTL_REG 0x3E 63dbf7a733SM R Swami Reddy #define LM49453_P0_HAP_FREQ_PROG_RIGHTH_REG 0x3F 64dbf7a733SM R Swami Reddy 65dbf7a733SM R Swami Reddy /* DIGITAL MIXER */ 66dbf7a733SM R Swami Reddy #define LM49453_P0_DMIX_CLK_SEL_REG 0x40 67dbf7a733SM R Swami Reddy #define LM49453_P0_PORT1_RX_LVL1_REG 0x41 68dbf7a733SM R Swami Reddy #define LM49453_P0_PORT1_RX_LVL2_REG 0x42 69dbf7a733SM R Swami Reddy #define LM49453_P0_PORT2_RX_LVL_REG 0x43 70dbf7a733SM R Swami Reddy #define LM49453_P0_PORT1_TX1_REG 0x44 71dbf7a733SM R Swami Reddy #define LM49453_P0_PORT1_TX2_REG 0x45 72dbf7a733SM R Swami Reddy #define LM49453_P0_PORT1_TX3_REG 0x46 73dbf7a733SM R Swami Reddy #define LM49453_P0_PORT1_TX4_REG 0x47 74dbf7a733SM R Swami Reddy #define LM49453_P0_PORT1_TX5_REG 0x48 75dbf7a733SM R Swami Reddy #define LM49453_P0_PORT1_TX6_REG 0x49 76dbf7a733SM R Swami Reddy #define LM49453_P0_PORT1_TX7_REG 0x4A 77dbf7a733SM R Swami Reddy #define LM49453_P0_PORT1_TX8_REG 0x4B 78dbf7a733SM R Swami Reddy #define LM49453_P0_PORT2_TX1_REG 0x4C 79dbf7a733SM R Swami Reddy #define LM49453_P0_PORT2_TX2_REG 0x4D 80dbf7a733SM R Swami Reddy #define LM49453_P0_STN_SEL_REG 0x4F 81dbf7a733SM R Swami Reddy #define LM49453_P0_DACHPL1_REG 0x50 82dbf7a733SM R Swami Reddy #define LM49453_P0_DACHPL2_REG 0x51 83dbf7a733SM R Swami Reddy #define LM49453_P0_DACHPR1_REG 0x52 84dbf7a733SM R Swami Reddy #define LM49453_P0_DACHPR2_REG 0x53 85dbf7a733SM R Swami Reddy #define LM49453_P0_DACLOL1_REG 0x54 86dbf7a733SM R Swami Reddy #define LM49453_P0_DACLOL2_REG 0x55 87dbf7a733SM R Swami Reddy #define LM49453_P0_DACLOR1_REG 0x56 88dbf7a733SM R Swami Reddy #define LM49453_P0_DACLOR2_REG 0x57 89dbf7a733SM R Swami Reddy #define LM49453_P0_DACLSL1_REG 0x58 90dbf7a733SM R Swami Reddy #define LM49453_P0_DACLSL2_REG 0x59 91dbf7a733SM R Swami Reddy #define LM49453_P0_DACLSR1_REG 0x5A 92dbf7a733SM R Swami Reddy #define LM49453_P0_DACLSR2_REG 0x5B 93dbf7a733SM R Swami Reddy #define LM49453_P0_DACHAL1_REG 0x5C 94dbf7a733SM R Swami Reddy #define LM49453_P0_DACHAL2_REG 0x5D 95dbf7a733SM R Swami Reddy #define LM49453_P0_DACHAR1_REG 0x5E 96dbf7a733SM R Swami Reddy #define LM49453_P0_DACHAR2_REG 0x5F 97dbf7a733SM R Swami Reddy 98dbf7a733SM R Swami Reddy /* AUDIO PORT 1 (TDM) */ 99dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT1_BASIC_REG 0x60 100dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT1_CLK_GEN1_REG 0x61 101dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT1_CLK_GEN2_REG 0x62 102dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT1_CLK_GEN3_REG 0x63 103dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT1_SYNC_RATE_REG 0x64 104dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT1_SYNC_SDO_SETUP_REG 0x65 105dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT1_DATA_WIDTH_REG 0x66 106dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT1_RX_MSB_REG 0x67 107dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT1_TX_MSB_REG 0x68 108dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT1_TDM_CHANNELS_REG 0x69 109dbf7a733SM R Swami Reddy 110dbf7a733SM R Swami Reddy /* AUDIO PORT 2 */ 111dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT2_BASIC_REG 0x6A 112dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT2_CLK_GEN1_REG 0x6B 113dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT2_CLK_GEN2_REG 0x6C 114dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT2_SYNC_GEN_REG 0x6D 115dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT2_DATA_WIDTH_REG 0x6E 116dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT2_RX_MODE_REG 0x6F 117dbf7a733SM R Swami Reddy #define LM49453_P0_AUDIO_PORT2_TX_MODE_REG 0x70 118dbf7a733SM R Swami Reddy 119dbf7a733SM R Swami Reddy /* SAMPLE RATE */ 120dbf7a733SM R Swami Reddy #define LM49453_P0_PORT1_SR_LSB_REG 0x79 121dbf7a733SM R Swami Reddy #define LM49453_P0_PORT1_SR_MSB_REG 0x7A 122dbf7a733SM R Swami Reddy #define LM49453_P0_PORT2_SR_LSB_REG 0x7B 123dbf7a733SM R Swami Reddy #define LM49453_P0_PORT2_SR_MSB_REG 0x7C 124dbf7a733SM R Swami Reddy 125dbf7a733SM R Swami Reddy /* EFFECTS - HPFs */ 126dbf7a733SM R Swami Reddy #define LM49453_P0_HPF_REG 0x80 127dbf7a733SM R Swami Reddy 128dbf7a733SM R Swami Reddy /* EFFECTS ADC ALC */ 129dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_ALC1_REG 0x82 130dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_ALC2_REG 0x83 131dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_ALC3_REG 0x84 132dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_ALC4_REG 0x85 133dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_ALC5_REG 0x86 134dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_ALC6_REG 0x87 135dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_ALC7_REG 0x88 136dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_ALC8_REG 0x89 137dbf7a733SM R Swami Reddy #define LM49453_P0_DMIC1_LEVELL_REG 0x8A 138dbf7a733SM R Swami Reddy #define LM49453_P0_DMIC1_LEVELR_REG 0x8B 139dbf7a733SM R Swami Reddy #define LM49453_P0_DMIC2_LEVELL_REG 0x8C 140dbf7a733SM R Swami Reddy #define LM49453_P0_DMIC2_LEVELR_REG 0x8D 141dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_LEVELL_REG 0x8E 142dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_LEVELR_REG 0x8F 143dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_HP_LEVELL_REG 0x90 144dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_HP_LEVELR_REG 0x91 145dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_LO_LEVELL_REG 0x92 146dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_LO_LEVELR_REG 0x93 147dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_LS_LEVELL_REG 0x94 148dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_LS_LEVELR_REG 0x95 149dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_HA_LEVELL_REG 0x96 150dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_HA_LEVELR_REG 0x97 151dbf7a733SM R Swami Reddy #define LM49453_P0_SOFT_MUTE_REG 0x98 152dbf7a733SM R Swami Reddy #define LM49453_P0_DMIC_MUTE_CFG_REG 0x99 153dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_MUTE_CFG_REG 0x9A 154dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_MUTE_CFG_REG 0x9B 155dbf7a733SM R Swami Reddy 156dbf7a733SM R Swami Reddy /*DIGITAL MIC1 */ 157dbf7a733SM R Swami Reddy #define LM49453_P0_DIGITAL_MIC1_CONFIG_REG 0xB0 158dbf7a733SM R Swami Reddy #define LM49453_P0_DIGITAL_MIC1_DATA_DELAYL_REG 0xB1 159dbf7a733SM R Swami Reddy #define LM49453_P0_DIGITAL_MIC1_DATA_DELAYR_REG 0xB2 160dbf7a733SM R Swami Reddy 161dbf7a733SM R Swami Reddy /*DIGITAL MIC2 */ 162dbf7a733SM R Swami Reddy #define LM49453_P0_DIGITAL_MIC2_CONFIG_REG 0xB3 163dbf7a733SM R Swami Reddy #define LM49453_P0_DIGITAL_MIC2_DATA_DELAYL_REG 0xB4 164dbf7a733SM R Swami Reddy #define LM49453_P0_DIGITAL_MIC2_DATA_DELAYR_REG 0xB5 165dbf7a733SM R Swami Reddy 166dbf7a733SM R Swami Reddy /* ADC DECIMATOR */ 167dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_DECIMATOR_REG 0xB6 168dbf7a733SM R Swami Reddy 169dbf7a733SM R Swami Reddy /* DAC CONFIGURE */ 170dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_CONFIG_REG 0xB7 171dbf7a733SM R Swami Reddy 172dbf7a733SM R Swami Reddy /* SIDETONE */ 173dbf7a733SM R Swami Reddy #define LM49453_P0_STN_VOL_ADCL_REG 0xB8 174dbf7a733SM R Swami Reddy #define LM49453_P0_STN_VOL_ADCR_REG 0xB9 175dbf7a733SM R Swami Reddy #define LM49453_P0_STN_VOL_DMIC1L_REG 0xBA 176dbf7a733SM R Swami Reddy #define LM49453_P0_STN_VOL_DMIC1R_REG 0xBB 177dbf7a733SM R Swami Reddy #define LM49453_P0_STN_VOL_DMIC2L_REG 0xBC 178dbf7a733SM R Swami Reddy #define LM49453_P0_STN_VOL_DMIC2R_REG 0xBD 179dbf7a733SM R Swami Reddy 180dbf7a733SM R Swami Reddy /* ADC/DAC CLIPPING MONITORS (Read Only/Write to Clear) */ 181dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_DEC_CLIP_REG 0xC2 182dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_HPF_CLIP_REG 0xC3 183dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_LVL_CLIP_REG 0xC4 184dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_LVL_CLIP_REG 0xC5 185dbf7a733SM R Swami Reddy 186dbf7a733SM R Swami Reddy /* ADC ALC EFFECT MONITORS (Read Only) */ 187dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_LVLMONL_REG 0xC8 188dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_LVLMONR_REG 0xC9 189dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_ALCMONL_REG 0xCA 190dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_ALCMONR_REG 0xCB 191dbf7a733SM R Swami Reddy #define LM49453_P0_ADC_MUTED_REG 0xCC 192dbf7a733SM R Swami Reddy #define LM49453_P0_DAC_MUTED_REG 0xCD 193dbf7a733SM R Swami Reddy 194dbf7a733SM R Swami Reddy /* HEADSET DETECT */ 195dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_PPB_LONG_CNT_LIMITL_REG 0xD0 196dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_PPB_LONG_CNT_LIMITR_REG 0xD1 197dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITL_REG 0xD2 198dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_PIN3_4_EX_LOOP_CNT_LIMITH_REG 0xD3 199dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_TIMEOUT1_REG 0xD4 200dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_TIMEOUT2_REG 0xD5 201dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_TIMEOUT3_REG 0xD6 202dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_PIN3_4_CFG_REG 0xD7 203dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_IRQ1_REG 0xD8 204dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_IRQ2_REG 0xD9 205dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_IRQ3_REG 0xDA 206dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_IRQ4_REG 0xDB 207dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_IRQ_MASK1_REG 0xDC 208dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_IRQ_MASK2_REG 0xDD 209dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_IRQ_MASK3_REG 0xDE 210dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_R_HPLL_REG 0xE0 211dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_R_HPLH_REG 0xE1 212dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_R_HPLU_REG 0xE2 213dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_R_HPRL_REG 0xE3 214dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_R_HPRH_REG 0xE4 215dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_R_HPRU_REG 0xE5 216dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_VEL_L_FINALL_REG 0xE6 217dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_VEL_L_FINALH_REG 0xE7 218dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_VEL_L_FINALU_REG 0xE8 219dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_RO_FINALL_REG 0xE9 220dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_RO_FINALH_REG 0xEA 221dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_RO_FINALU_REG 0xEB 222dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_VMIC_BIAS_FINALL_REG 0xEC 223dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_VMIC_BIAS_FINALH_REG 0xED 224dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_VMIC_BIAS_FINALU_REG 0xEE 225dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_PIN_CONFIG_REG 0xEF 226dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS1_REG 0xF1 227dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS2_REG 0xF2 228dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATUS3_REG 0xF3 229dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEL_REG 0xF4 230dbf7a733SM R Swami Reddy #define LM49453_P0_HSD_PLUG_DETECT_BB_IRQ_STATEH_REG 0xF5 231dbf7a733SM R Swami Reddy 232dbf7a733SM R Swami Reddy /* I/O PULLDOWN CONFIG */ 233dbf7a733SM R Swami Reddy #define LM49453_P0_PULL_CONFIG1_REG 0xF8 234dbf7a733SM R Swami Reddy #define LM49453_P0_PULL_CONFIG2_REG 0xF9 235dbf7a733SM R Swami Reddy #define LM49453_P0_PULL_CONFIG3_REG 0xFA 236dbf7a733SM R Swami Reddy 237dbf7a733SM R Swami Reddy /* RESET */ 238dbf7a733SM R Swami Reddy #define LM49453_P0_RESET_REG 0xFE 239dbf7a733SM R Swami Reddy 240dbf7a733SM R Swami Reddy /* PAGE */ 241dbf7a733SM R Swami Reddy #define LM49453_PAGE_REG 0xFF 242dbf7a733SM R Swami Reddy 243dbf7a733SM R Swami Reddy #define LM49453_MAX_REGISTER (0xFF+1) 244dbf7a733SM R Swami Reddy 245dbf7a733SM R Swami Reddy /* LM49453_P0_PMC_SETUP_REG (0x00h) */ 246dbf7a733SM R Swami Reddy #define LM49453_PMC_SETUP_CHIP_EN (BIT(1)|BIT(0)) 247dbf7a733SM R Swami Reddy #define LM49453_PMC_SETUP_PLL_EN BIT(2) 248dbf7a733SM R Swami Reddy #define LM49453_PMC_SETUP_PLL_P2_EN BIT(3) 249dbf7a733SM R Swami Reddy #define LM49453_PMC_SETUP_PLL_FLL BIT(4) 250dbf7a733SM R Swami Reddy #define LM49453_PMC_SETUP_MCLK_OVER BIT(5) 251dbf7a733SM R Swami Reddy #define LM49453_PMC_SETUP_RTC_CLK_OVER BIT(6) 252dbf7a733SM R Swami Reddy #define LM49453_PMC_SETUP_CHIP_ACTIVE BIT(7) 253dbf7a733SM R Swami Reddy 254dbf7a733SM R Swami Reddy /* Chip Enable bits */ 255dbf7a733SM R Swami Reddy #define LM49453_CHIP_EN_SHUTDOWN 0x00 256dbf7a733SM R Swami Reddy #define LM49453_CHIP_EN 0x01 257dbf7a733SM R Swami Reddy #define LM49453_CHIP_EN_HSD_DETECT 0x02 258dbf7a733SM R Swami Reddy #define LM49453_CHIP_EN_INVALID_HSD 0x03 259dbf7a733SM R Swami Reddy 260dbf7a733SM R Swami Reddy /* LM49453_P0_PLL_CLK_SEL1_REG (0x01h) */ 261dbf7a733SM R Swami Reddy #define LM49453_CLK_SEL1_MCLK_SEL 0x11 262dbf7a733SM R Swami Reddy #define LM49453_CLK_SEL1_RTC_SEL 0x11 263dbf7a733SM R Swami Reddy #define LM49453_CLK_SEL1_PORT1_SEL 0x10 264dbf7a733SM R Swami Reddy #define LM49453_CLK_SEL1_PORT2_SEL 0x11 265dbf7a733SM R Swami Reddy 266dbf7a733SM R Swami Reddy /* LM49453_P0_PLL_CLK_SEL2_REG (0x02h) */ 267dbf7a733SM R Swami Reddy #define LM49453_CLK_SEL2_ADC_CLK_SEL 0x38 268dbf7a733SM R Swami Reddy 269dbf7a733SM R Swami Reddy /* LM49453_P0_FLL_REF_FREQL_REG (0x0F) */ 270dbf7a733SM R Swami Reddy #define LM49453_FLL_REF_FREQ_VAL 0x8ca0001 271dbf7a733SM R Swami Reddy 272dbf7a733SM R Swami Reddy /* LM49453_P0_VCO_TARGETLL_REG (0x11) */ 273dbf7a733SM R Swami Reddy #define LM49453_VCO_TARGET_VAL 0x8ca0001 274dbf7a733SM R Swami Reddy 275dbf7a733SM R Swami Reddy /* LM49453_P0_ADC_DSP_REG (0x30h) */ 276dbf7a733SM R Swami Reddy #define LM49453_ADC_DSP_ADC_MUTEL BIT(0) 277dbf7a733SM R Swami Reddy #define LM49453_ADC_DSP_ADC_MUTER BIT(1) 278dbf7a733SM R Swami Reddy #define LM49453_ADC_DSP_DMIC1_MUTEL BIT(2) 279dbf7a733SM R Swami Reddy #define LM49453_ADC_DSP_DMIC1_MUTER BIT(3) 280dbf7a733SM R Swami Reddy #define LM49453_ADC_DSP_DMIC2_MUTEL BIT(4) 281dbf7a733SM R Swami Reddy #define LM49453_ADC_DSP_DMIC2_MUTER BIT(5) 282dbf7a733SM R Swami Reddy #define LM49453_ADC_DSP_MUTE_ALL 0x3F 283dbf7a733SM R Swami Reddy 284dbf7a733SM R Swami Reddy /* LM49453_P0_DAC_DSP_REG (0x31h) */ 285dbf7a733SM R Swami Reddy #define LM49453_DAC_DSP_MUTE_ALL 0xFF 286dbf7a733SM R Swami Reddy 287dbf7a733SM R Swami Reddy /* LM49453_P0_AUDIO_PORT1_BASIC_REG (0x60h) */ 288dbf7a733SM R Swami Reddy #define LM49453_AUDIO_PORT1_BASIC_FMT_MASK (BIT(4)|BIT(3)) 289dbf7a733SM R Swami Reddy #define LM49453_AUDIO_PORT1_BASIC_CLK_MS BIT(3) 290dbf7a733SM R Swami Reddy #define LM49453_AUDIO_PORT1_BASIC_SYNC_MS BIT(4) 291dbf7a733SM R Swami Reddy 292dbf7a733SM R Swami Reddy /* LM49453_P0_RESET_REG (0xFEh) */ 293dbf7a733SM R Swami Reddy #define LM49453_RESET_REG_RST BIT(0) 294dbf7a733SM R Swami Reddy 295dbf7a733SM R Swami Reddy /* Page select register bits (0xFF) */ 296dbf7a733SM R Swami Reddy #define LM49453_PAGE0_SELECT 0x0 297dbf7a733SM R Swami Reddy #define LM49453_PAGE1_SELECT 0x1 298dbf7a733SM R Swami Reddy 299dbf7a733SM R Swami Reddy /* LM49453_P0_HSD_PIN3_4_CFG_REG (Jack Pin config - 0xD7) */ 300dbf7a733SM R Swami Reddy #define LM49453_JACK_DISABLE 0x00 301dbf7a733SM R Swami Reddy #define LM49453_JACK_CONFIG1 0x01 302dbf7a733SM R Swami Reddy #define LM49453_JACK_CONFIG2 0x02 303dbf7a733SM R Swami Reddy #define LM49453_JACK_CONFIG3 0x03 304dbf7a733SM R Swami Reddy #define LM49453_JACK_CONFIG4 0x04 305dbf7a733SM R Swami Reddy #define LM49453_JACK_CONFIG5 0x05 306dbf7a733SM R Swami Reddy 307dbf7a733SM R Swami Reddy /* Page 1 REGISTERS */ 308dbf7a733SM R Swami Reddy 309dbf7a733SM R Swami Reddy /* SIDETONE */ 310dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SA0L_REG 0x80 311dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SA0H_REG 0x81 312dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SAB0U_REG 0x82 313dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SB0L_REG 0x83 314dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SB0H_REG 0x84 315dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH0L_REG 0x85 316dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH0H_REG 0x86 317dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH0U_REG 0x87 318dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SA1L_REG 0x88 319dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SA1H_REG 0x89 320dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SAB1U_REG 0x8A 321dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SB1L_REG 0x8B 322dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SB1H_REG 0x8C 323dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH1L_REG 0x8D 324dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH1H_REG 0x8E 325dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH1U_REG 0x8F 326dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SA2L_REG 0x90 327dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SA2H_REG 0x91 328dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SAB2U_REG 0x92 329dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SB2L_REG 0x93 330dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SB2H_REG 0x94 331dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH2L_REG 0x95 332dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH2H_REG 0x96 333dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH2U_REG 0x97 334dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SA3L_REG 0x98 335dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SA3H_REG 0x99 336dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SAB3U_REG 0x9A 337dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SB3L_REG 0x9B 338dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SB3H_REG 0x9C 339dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH3L_REG 0x9D 340dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH3H_REG 0x9E 341dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH3U_REG 0x9F 342dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SA4L_REG 0xA0 343dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SA4H_REG 0xA1 344dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SAB4U_REG 0xA2 345dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SB4L_REG 0xA3 346dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SB4H_REG 0xA4 347dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH4L_REG 0xA5 348dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH4H_REG 0xA6 349dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH4U_REG 0xA7 350dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SA5L_REG 0xA8 351dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SA5H_REG 0xA9 352dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SAB5U_REG 0xAA 353dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SB5L_REG 0xAB 354dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SB5H_REG 0xAC 355dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH5L_REG 0xAD 356dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH5H_REG 0xAE 357dbf7a733SM R Swami Reddy #define LM49453_P1_SIDETONE_SH5U_REG 0xAF 358dbf7a733SM R Swami Reddy 359dbf7a733SM R Swami Reddy /* CHARGE PUMP CONFIG */ 360dbf7a733SM R Swami Reddy #define LM49453_P1_CP_CONFIG1_REG 0xB0 361dbf7a733SM R Swami Reddy #define LM49453_P1_CP_CONFIG2_REG 0xB1 362dbf7a733SM R Swami Reddy #define LM49453_P1_CP_CONFIG3_REG 0xB2 363dbf7a733SM R Swami Reddy #define LM49453_P1_CP_CONFIG4_REG 0xB3 364dbf7a733SM R Swami Reddy #define LM49453_P1_CP_LA_VTH1L_REG 0xB4 365dbf7a733SM R Swami Reddy #define LM49453_P1_CP_LA_VTH1M_REG 0xB5 366dbf7a733SM R Swami Reddy #define LM49453_P1_CP_LA_VTH2L_REG 0xB6 367dbf7a733SM R Swami Reddy #define LM49453_P1_CP_LA_VTH2M_REG 0xB7 368dbf7a733SM R Swami Reddy #define LM49453_P1_CP_LA_VTH3L_REG 0xB8 369dbf7a733SM R Swami Reddy #define LM49453_P1_CP_LA_VTH3H_REG 0xB9 370dbf7a733SM R Swami Reddy #define LM49453_P1_CP_CLK_DIV_REG 0xBA 371dbf7a733SM R Swami Reddy 372dbf7a733SM R Swami Reddy /* DAC */ 373dbf7a733SM R Swami Reddy #define LM49453_P1_DAC_CHOP_REG 0xC0 374dbf7a733SM R Swami Reddy 375dbf7a733SM R Swami Reddy #define LM49453_CLK_SRC_MCLK 1 376dbf7a733SM R Swami Reddy #endif 377