1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Ingenic JZ4770 CODEC driver 4 // 5 // Copyright (C) 2012, Maarten ter Huurne <maarten@treewalker.org> 6 // Copyright (C) 2019, Paul Cercueil <paul@crapouillou.net> 7 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/iopoll.h> 11 #include <linux/module.h> 12 #include <linux/regmap.h> 13 #include <linux/time64.h> 14 15 #include <sound/pcm_params.h> 16 #include <sound/soc.h> 17 #include <sound/soc-dai.h> 18 #include <sound/soc-dapm.h> 19 #include <sound/tlv.h> 20 21 #define ICDC_RGADW_OFFSET 0x00 22 #define ICDC_RGDATA_OFFSET 0x04 23 24 /* ICDC internal register access control register(RGADW) */ 25 #define ICDC_RGADW_RGWR BIT(16) 26 27 #define ICDC_RGADW_RGADDR_OFFSET 8 28 #define ICDC_RGADW_RGADDR_MASK GENMASK(14, ICDC_RGADW_RGADDR_OFFSET) 29 30 #define ICDC_RGADW_RGDIN_OFFSET 0 31 #define ICDC_RGADW_RGDIN_MASK GENMASK(7, ICDC_RGADW_RGDIN_OFFSET) 32 33 /* ICDC internal register data output register (RGDATA)*/ 34 #define ICDC_RGDATA_IRQ BIT(8) 35 36 #define ICDC_RGDATA_RGDOUT_OFFSET 0 37 #define ICDC_RGDATA_RGDOUT_MASK GENMASK(7, ICDC_RGDATA_RGDOUT_OFFSET) 38 39 /* Internal register space, accessed through regmap */ 40 enum { 41 JZ4770_CODEC_REG_SR, 42 JZ4770_CODEC_REG_AICR_DAC, 43 JZ4770_CODEC_REG_AICR_ADC, 44 JZ4770_CODEC_REG_CR_LO, 45 JZ4770_CODEC_REG_CR_HP, 46 47 JZ4770_CODEC_REG_MISSING_REG1, 48 49 JZ4770_CODEC_REG_CR_DAC, 50 JZ4770_CODEC_REG_CR_MIC, 51 JZ4770_CODEC_REG_CR_LI, 52 JZ4770_CODEC_REG_CR_ADC, 53 JZ4770_CODEC_REG_CR_MIX, 54 JZ4770_CODEC_REG_CR_VIC, 55 JZ4770_CODEC_REG_CCR, 56 JZ4770_CODEC_REG_FCR_DAC, 57 JZ4770_CODEC_REG_FCR_ADC, 58 JZ4770_CODEC_REG_ICR, 59 JZ4770_CODEC_REG_IMR, 60 JZ4770_CODEC_REG_IFR, 61 JZ4770_CODEC_REG_GCR_HPL, 62 JZ4770_CODEC_REG_GCR_HPR, 63 JZ4770_CODEC_REG_GCR_LIBYL, 64 JZ4770_CODEC_REG_GCR_LIBYR, 65 JZ4770_CODEC_REG_GCR_DACL, 66 JZ4770_CODEC_REG_GCR_DACR, 67 JZ4770_CODEC_REG_GCR_MIC1, 68 JZ4770_CODEC_REG_GCR_MIC2, 69 JZ4770_CODEC_REG_GCR_ADCL, 70 JZ4770_CODEC_REG_GCR_ADCR, 71 72 JZ4770_CODEC_REG_MISSING_REG2, 73 74 JZ4770_CODEC_REG_GCR_MIXADC, 75 JZ4770_CODEC_REG_GCR_MIXDAC, 76 JZ4770_CODEC_REG_AGC1, 77 JZ4770_CODEC_REG_AGC2, 78 JZ4770_CODEC_REG_AGC3, 79 JZ4770_CODEC_REG_AGC4, 80 JZ4770_CODEC_REG_AGC5, 81 }; 82 83 #define REG_AICR_DAC_ADWL_OFFSET 6 84 #define REG_AICR_DAC_ADWL_MASK (0x3 << REG_AICR_DAC_ADWL_OFFSET) 85 #define REG_AICR_DAC_SERIAL BIT(1) 86 #define REG_AICR_DAC_I2S BIT(0) 87 88 #define REG_AICR_ADC_ADWL_OFFSET 6 89 #define REG_AICR_ADC_ADWL_MASK (0x3 << REG_AICR_ADC_ADWL_OFFSET) 90 #define REG_AICR_ADC_SERIAL BIT(1) 91 #define REG_AICR_ADC_I2S BIT(0) 92 93 #define REG_CR_LO_MUTE_OFFSET 7 94 #define REG_CR_LO_SB_OFFSET 4 95 #define REG_CR_LO_SEL_OFFSET 0 96 #define REG_CR_LO_SEL_MASK (0x3 << REG_CR_LO_SEL_OFFSET) 97 98 #define REG_CR_HP_MUTE BIT(7) 99 #define REG_CR_HP_LOAD BIT(6) 100 #define REG_CR_HP_SB_OFFSET 4 101 #define REG_CR_HP_SB_HPCM BIT(3) 102 #define REG_CR_HP_SEL_OFFSET 0 103 #define REG_CR_HP_SEL_MASK (0x3 << REG_CR_HP_SEL_OFFSET) 104 105 #define REG_CR_DAC_MUTE BIT(7) 106 #define REG_CR_DAC_MONO BIT(6) 107 #define REG_CR_DAC_LEFT_ONLY BIT(5) 108 #define REG_CR_DAC_SB_OFFSET 4 109 #define REG_CR_DAC_LRSWAP BIT(3) 110 111 #define REG_CR_MIC_STEREO_OFFSET 7 112 #define REG_CR_MIC_IDIFF_OFFSET 6 113 #define REG_CR_MIC_SB_MIC2_OFFSET 5 114 #define REG_CR_MIC_SB_MIC1_OFFSET 4 115 #define REG_CR_MIC_BIAS_V0_OFFSET 1 116 #define REG_CR_MIC_BIAS_SB_OFFSET 0 117 118 #define REG_CR_LI_LIBY_OFFSET 4 119 #define REG_CR_LI_SB_OFFSET 0 120 121 #define REG_CR_ADC_DMIC_SEL BIT(7) 122 #define REG_CR_ADC_MONO BIT(6) 123 #define REG_CR_ADC_LEFT_ONLY BIT(5) 124 #define REG_CR_ADC_SB_OFFSET 4 125 #define REG_CR_ADC_LRSWAP BIT(3) 126 #define REG_CR_ADC_IN_SEL_OFFSET 0 127 #define REG_CR_ADC_IN_SEL_MASK (0x3 << REG_CR_ADC_IN_SEL_OFFSET) 128 129 #define REG_CR_VIC_SB_SLEEP BIT(1) 130 #define REG_CR_VIC_SB BIT(0) 131 132 #define REG_CCR_CRYSTAL_OFFSET 0 133 #define REG_CCR_CRYSTAL_MASK (0xf << REG_CCR_CRYSTAL_OFFSET) 134 135 #define REG_FCR_DAC_FREQ_OFFSET 0 136 #define REG_FCR_DAC_FREQ_MASK (0xf << REG_FCR_DAC_FREQ_OFFSET) 137 138 #define REG_FCR_ADC_FREQ_OFFSET 0 139 #define REG_FCR_ADC_FREQ_MASK (0xf << REG_FCR_ADC_FREQ_OFFSET) 140 141 #define REG_ICR_INT_FORM_OFFSET 6 142 #define REG_ICR_INT_FORM_MASK (0x3 << REG_ICR_INT_FORM_OFFSET) 143 144 #define REG_IMR_ALL_MASK (0x7f) 145 #define REG_IMR_SCLR_MASK BIT(6) 146 #define REG_IMR_JACK_MASK BIT(5) 147 #define REG_IMR_SCMC_MASK BIT(4) 148 #define REG_IMR_RUP_MASK BIT(3) 149 #define REG_IMR_RDO_MASK BIT(2) 150 #define REG_IMR_GUP_MASK BIT(1) 151 #define REG_IMR_GDO_MASK BIT(0) 152 153 #define REG_IFR_ALL_MASK (0x7f) 154 #define REG_IFR_SCLR BIT(6) 155 #define REG_IFR_JACK BIT(5) 156 #define REG_IFR_SCMC BIT(4) 157 #define REG_IFR_RUP BIT(3) 158 #define REG_IFR_RDO BIT(2) 159 #define REG_IFR_GUP BIT(1) 160 #define REG_IFR_GDO BIT(0) 161 162 #define REG_GCR_HPL_LRGO BIT(7) 163 164 #define REG_GCR_DACL_RLGOD BIT(7) 165 166 #define REG_GCR_GAIN_OFFSET 0 167 #define REG_GCR_GAIN_MAX 0x1f 168 169 #define REG_GCR_MIC_GAIN_OFFSET 0 170 #define REG_GCR_MIC_GAIN_MAX 5 171 172 #define REG_GCR_ADC_GAIN_OFFSET 0 173 #define REG_GCR_ADC_GAIN_MAX 23 174 175 #define REG_AGC1_EN BIT(7) 176 177 /* codec private data */ 178 struct jz_codec { 179 struct device *dev; 180 struct regmap *regmap; 181 void __iomem *base; 182 struct clk *clk; 183 }; 184 185 static int jz4770_codec_set_bias_level(struct snd_soc_component *codec, 186 enum snd_soc_bias_level level) 187 { 188 struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec); 189 struct regmap *regmap = jz_codec->regmap; 190 191 switch (level) { 192 case SND_SOC_BIAS_PREPARE: 193 /* Reset all interrupt flags. */ 194 regmap_write(regmap, JZ4770_CODEC_REG_IFR, REG_IFR_ALL_MASK); 195 196 regmap_clear_bits(regmap, JZ4770_CODEC_REG_CR_VIC, 197 REG_CR_VIC_SB); 198 msleep(250); 199 regmap_clear_bits(regmap, JZ4770_CODEC_REG_CR_VIC, 200 REG_CR_VIC_SB_SLEEP); 201 msleep(400); 202 break; 203 case SND_SOC_BIAS_STANDBY: 204 regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_VIC, 205 REG_CR_VIC_SB_SLEEP); 206 regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_VIC, 207 REG_CR_VIC_SB); 208 fallthrough; 209 default: 210 break; 211 } 212 213 return 0; 214 } 215 216 static int jz4770_codec_startup(struct snd_pcm_substream *substream, 217 struct snd_soc_dai *dai) 218 { 219 struct snd_soc_component *codec = dai->component; 220 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(codec); 221 222 /* 223 * SYSCLK output from the codec to the AIC is required to keep the 224 * DMA transfer going during playback when all audible outputs have 225 * been disabled. 226 */ 227 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 228 snd_soc_dapm_force_enable_pin(dapm, "SYSCLK"); 229 230 return 0; 231 } 232 233 static void jz4770_codec_shutdown(struct snd_pcm_substream *substream, 234 struct snd_soc_dai *dai) 235 { 236 struct snd_soc_component *codec = dai->component; 237 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(codec); 238 239 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 240 snd_soc_dapm_disable_pin(dapm, "SYSCLK"); 241 } 242 243 244 static int jz4770_codec_pcm_trigger(struct snd_pcm_substream *substream, 245 int cmd, struct snd_soc_dai *dai) 246 { 247 struct snd_soc_component *codec = dai->component; 248 int ret = 0; 249 250 switch (cmd) { 251 case SNDRV_PCM_TRIGGER_START: 252 case SNDRV_PCM_TRIGGER_RESUME: 253 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 254 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) 255 snd_soc_component_force_bias_level(codec, 256 SND_SOC_BIAS_ON); 257 break; 258 case SNDRV_PCM_TRIGGER_STOP: 259 case SNDRV_PCM_TRIGGER_SUSPEND: 260 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 261 /* do nothing */ 262 break; 263 default: 264 ret = -EINVAL; 265 } 266 267 return ret; 268 } 269 270 static int jz4770_codec_mute_stream(struct snd_soc_dai *dai, int mute, int direction) 271 { 272 struct snd_soc_component *codec = dai->component; 273 struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec); 274 unsigned int gain_bit = mute ? REG_IFR_GDO : REG_IFR_GUP; 275 unsigned int val; 276 int change, err; 277 278 change = snd_soc_component_update_bits(codec, JZ4770_CODEC_REG_CR_DAC, 279 REG_CR_DAC_MUTE, 280 mute ? REG_CR_DAC_MUTE : 0); 281 if (change == 1) { 282 regmap_read(jz_codec->regmap, JZ4770_CODEC_REG_CR_DAC, &val); 283 284 if (val & BIT(REG_CR_DAC_SB_OFFSET)) 285 return 1; 286 287 err = regmap_read_poll_timeout(jz_codec->regmap, 288 JZ4770_CODEC_REG_IFR, 289 val, val & gain_bit, 290 1000, 100 * USEC_PER_MSEC); 291 if (err) { 292 dev_err(jz_codec->dev, 293 "Timeout while setting digital mute: %d", err); 294 return err; 295 } 296 297 /* clear GUP/GDO flag */ 298 regmap_set_bits(jz_codec->regmap, JZ4770_CODEC_REG_IFR, 299 gain_bit); 300 } 301 302 return 0; 303 } 304 305 /* unit: 0.01dB */ 306 static const DECLARE_TLV_DB_MINMAX_MUTE(dac_tlv, -3100, 0); 307 static const DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0); 308 static const DECLARE_TLV_DB_MINMAX(out_tlv, -2500, 600); 309 static const DECLARE_TLV_DB_SCALE(linein_tlv, -2500, 100, 0); 310 311 /* Unconditional controls. */ 312 static const struct snd_kcontrol_new jz4770_codec_snd_controls[] = { 313 /* record gain control */ 314 SOC_DOUBLE_R_TLV("PCM Capture Volume", 315 JZ4770_CODEC_REG_GCR_ADCL, JZ4770_CODEC_REG_GCR_ADCR, 316 REG_GCR_ADC_GAIN_OFFSET, REG_GCR_ADC_GAIN_MAX, 317 0, adc_tlv), 318 319 SOC_DOUBLE_R_TLV("Line In Bypass Playback Volume", 320 JZ4770_CODEC_REG_GCR_LIBYL, JZ4770_CODEC_REG_GCR_LIBYR, 321 REG_GCR_GAIN_OFFSET, REG_GCR_GAIN_MAX, 1, linein_tlv), 322 }; 323 324 static const struct snd_kcontrol_new jz4770_codec_pcm_playback_controls[] = { 325 { 326 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 327 .name = "Volume", 328 .info = snd_soc_info_volsw, 329 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ 330 | SNDRV_CTL_ELEM_ACCESS_READWRITE, 331 .tlv.p = dac_tlv, 332 .get = snd_soc_dapm_get_volsw, 333 .put = snd_soc_dapm_put_volsw, 334 /* 335 * NOTE: DACR/DACL are inversed; the gain value written to DACR 336 * seems to affect the left channel, and the gain value written 337 * to DACL seems to affect the right channel. 338 */ 339 .private_value = SOC_DOUBLE_R_VALUE(JZ4770_CODEC_REG_GCR_DACR, 340 JZ4770_CODEC_REG_GCR_DACL, 341 REG_GCR_GAIN_OFFSET, 342 REG_GCR_GAIN_MAX, 1), 343 }, 344 }; 345 346 static const struct snd_kcontrol_new jz4770_codec_hp_playback_controls[] = { 347 { 348 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 349 .name = "Volume", 350 .info = snd_soc_info_volsw, 351 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ 352 | SNDRV_CTL_ELEM_ACCESS_READWRITE, 353 .tlv.p = out_tlv, 354 .get = snd_soc_dapm_get_volsw, 355 .put = snd_soc_dapm_put_volsw, 356 /* HPR/HPL inversed for the same reason as above */ 357 .private_value = SOC_DOUBLE_R_VALUE(JZ4770_CODEC_REG_GCR_HPR, 358 JZ4770_CODEC_REG_GCR_HPL, 359 REG_GCR_GAIN_OFFSET, 360 REG_GCR_GAIN_MAX, 1), 361 }, 362 }; 363 364 static int hpout_event(struct snd_soc_dapm_widget *w, 365 struct snd_kcontrol *kcontrol, int event) 366 { 367 struct snd_soc_component *codec = snd_soc_dapm_to_component(w->dapm); 368 struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec); 369 unsigned int val; 370 int err; 371 372 switch (event) { 373 case SND_SOC_DAPM_PRE_PMU: 374 /* set cap-less, unmute HP */ 375 regmap_clear_bits(jz_codec->regmap, JZ4770_CODEC_REG_CR_HP, 376 REG_CR_HP_SB_HPCM | REG_CR_HP_MUTE); 377 break; 378 379 case SND_SOC_DAPM_POST_PMU: 380 /* wait for ramp-up complete (RUP) */ 381 err = regmap_read_poll_timeout(jz_codec->regmap, 382 JZ4770_CODEC_REG_IFR, 383 val, val & REG_IFR_RUP, 384 1000, 100 * USEC_PER_MSEC); 385 if (err) { 386 dev_err(jz_codec->dev, "RUP timeout: %d", err); 387 return err; 388 } 389 390 /* clear RUP flag */ 391 regmap_set_bits(jz_codec->regmap, JZ4770_CODEC_REG_IFR, 392 REG_IFR_RUP); 393 394 break; 395 396 case SND_SOC_DAPM_POST_PMD: 397 /* set cap-couple, mute HP */ 398 regmap_set_bits(jz_codec->regmap, JZ4770_CODEC_REG_CR_HP, 399 REG_CR_HP_SB_HPCM | REG_CR_HP_MUTE); 400 401 err = regmap_read_poll_timeout(jz_codec->regmap, 402 JZ4770_CODEC_REG_IFR, 403 val, val & REG_IFR_RDO, 404 1000, 100 * USEC_PER_MSEC); 405 if (err) { 406 dev_err(jz_codec->dev, "RDO timeout: %d", err); 407 return err; 408 } 409 410 /* clear RDO flag */ 411 regmap_set_bits(jz_codec->regmap, JZ4770_CODEC_REG_IFR, 412 REG_IFR_RDO); 413 414 break; 415 } 416 417 return 0; 418 } 419 420 static int adc_poweron_event(struct snd_soc_dapm_widget *w, 421 struct snd_kcontrol *kcontrol, int event) 422 { 423 if (event == SND_SOC_DAPM_POST_PMU) 424 msleep(1000); 425 426 return 0; 427 } 428 429 static const char * const jz4770_codec_hp_texts[] = { 430 "PCM", "Line In", "Mic 1", "Mic 2" 431 }; 432 static const unsigned int jz4770_codec_hp_values[] = { 3, 2, 0, 1 }; 433 static SOC_VALUE_ENUM_SINGLE_DECL(jz4770_codec_hp_enum, 434 JZ4770_CODEC_REG_CR_HP, 435 REG_CR_HP_SEL_OFFSET, 436 REG_CR_HP_SEL_MASK, 437 jz4770_codec_hp_texts, 438 jz4770_codec_hp_values); 439 static const struct snd_kcontrol_new jz4770_codec_hp_source = 440 SOC_DAPM_ENUM("Route", jz4770_codec_hp_enum); 441 442 static SOC_VALUE_ENUM_SINGLE_DECL(jz4770_codec_lo_enum, 443 JZ4770_CODEC_REG_CR_LO, 444 REG_CR_LO_SEL_OFFSET, 445 REG_CR_LO_SEL_MASK, 446 jz4770_codec_hp_texts, 447 jz4770_codec_hp_values); 448 static const struct snd_kcontrol_new jz4770_codec_lo_source = 449 SOC_DAPM_ENUM("Route", jz4770_codec_lo_enum); 450 451 static const char * const jz4770_codec_cap_texts[] = { 452 "Line In", "Mic 1", "Mic 2" 453 }; 454 static const unsigned int jz4770_codec_cap_values[] = { 2, 0, 1 }; 455 static SOC_VALUE_ENUM_SINGLE_DECL(jz4770_codec_cap_enum, 456 JZ4770_CODEC_REG_CR_ADC, 457 REG_CR_ADC_IN_SEL_OFFSET, 458 REG_CR_ADC_IN_SEL_MASK, 459 jz4770_codec_cap_texts, 460 jz4770_codec_cap_values); 461 static const struct snd_kcontrol_new jz4770_codec_cap_source = 462 SOC_DAPM_ENUM("Route", jz4770_codec_cap_enum); 463 464 static const struct snd_kcontrol_new jz4770_codec_mic_controls[] = { 465 SOC_DAPM_SINGLE("Stereo Capture Switch", JZ4770_CODEC_REG_CR_MIC, 466 REG_CR_MIC_STEREO_OFFSET, 1, 0), 467 }; 468 469 static const struct snd_soc_dapm_widget jz4770_codec_dapm_widgets[] = { 470 SND_SOC_DAPM_PGA_E("HP Out", JZ4770_CODEC_REG_CR_HP, 471 REG_CR_HP_SB_OFFSET, 1, NULL, 0, hpout_event, 472 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | 473 SND_SOC_DAPM_POST_PMD), 474 475 SND_SOC_DAPM_PGA("Line Out", JZ4770_CODEC_REG_CR_LO, 476 REG_CR_LO_SB_OFFSET, 1, NULL, 0), 477 478 SND_SOC_DAPM_PGA("Line Out Switch 2", JZ4770_CODEC_REG_CR_LO, 479 REG_CR_LO_MUTE_OFFSET, 1, NULL, 0), 480 481 SND_SOC_DAPM_PGA("Line In", JZ4770_CODEC_REG_CR_LI, 482 REG_CR_LI_SB_OFFSET, 1, NULL, 0), 483 484 SND_SOC_DAPM_MUX("Headphones Source", SND_SOC_NOPM, 0, 0, 485 &jz4770_codec_hp_source), 486 SND_SOC_DAPM_MUX("Capture Source", SND_SOC_NOPM, 0, 0, 487 &jz4770_codec_cap_source), 488 SND_SOC_DAPM_MUX("Line Out Source", SND_SOC_NOPM, 0, 0, 489 &jz4770_codec_lo_source), 490 491 SND_SOC_DAPM_PGA("Mic 1", JZ4770_CODEC_REG_CR_MIC, 492 REG_CR_MIC_SB_MIC1_OFFSET, 1, NULL, 0), 493 SND_SOC_DAPM_PGA("Mic 2", JZ4770_CODEC_REG_CR_MIC, 494 REG_CR_MIC_SB_MIC2_OFFSET, 1, NULL, 0), 495 496 SND_SOC_DAPM_PGA("Mic Diff", JZ4770_CODEC_REG_CR_MIC, 497 REG_CR_MIC_IDIFF_OFFSET, 0, NULL, 0), 498 499 SND_SOC_DAPM_MIXER("Mic", SND_SOC_NOPM, 0, 0, 500 jz4770_codec_mic_controls, 501 ARRAY_SIZE(jz4770_codec_mic_controls)), 502 503 SND_SOC_DAPM_PGA("Line In Bypass", JZ4770_CODEC_REG_CR_LI, 504 REG_CR_LI_LIBY_OFFSET, 1, NULL, 0), 505 506 SND_SOC_DAPM_ADC_E("ADC", "HiFi Capture", JZ4770_CODEC_REG_CR_ADC, 507 REG_CR_ADC_SB_OFFSET, 1, adc_poweron_event, 508 SND_SOC_DAPM_POST_PMU), 509 SND_SOC_DAPM_DAC("DAC", "HiFi Playback", JZ4770_CODEC_REG_CR_DAC, 510 REG_CR_DAC_SB_OFFSET, 1), 511 512 SND_SOC_DAPM_MIXER("PCM Playback", SND_SOC_NOPM, 0, 0, 513 jz4770_codec_pcm_playback_controls, 514 ARRAY_SIZE(jz4770_codec_pcm_playback_controls)), 515 SND_SOC_DAPM_MIXER("Headphones Playback", SND_SOC_NOPM, 0, 0, 516 jz4770_codec_hp_playback_controls, 517 ARRAY_SIZE(jz4770_codec_hp_playback_controls)), 518 519 SND_SOC_DAPM_SUPPLY("MICBIAS", JZ4770_CODEC_REG_CR_MIC, 520 REG_CR_MIC_BIAS_SB_OFFSET, 1, NULL, 0), 521 522 SND_SOC_DAPM_INPUT("MIC1P"), 523 SND_SOC_DAPM_INPUT("MIC1N"), 524 SND_SOC_DAPM_INPUT("MIC2P"), 525 SND_SOC_DAPM_INPUT("MIC2N"), 526 527 SND_SOC_DAPM_OUTPUT("LOUT"), 528 SND_SOC_DAPM_OUTPUT("ROUT"), 529 530 SND_SOC_DAPM_OUTPUT("LHPOUT"), 531 SND_SOC_DAPM_OUTPUT("RHPOUT"), 532 533 SND_SOC_DAPM_INPUT("LLINEIN"), 534 SND_SOC_DAPM_INPUT("RLINEIN"), 535 536 SND_SOC_DAPM_OUTPUT("SYSCLK"), 537 }; 538 539 /* Unconditional routes. */ 540 static const struct snd_soc_dapm_route jz4770_codec_dapm_routes[] = { 541 { "Mic 1", NULL, "MIC1P" }, 542 { "Mic Diff", NULL, "MIC1N" }, 543 { "Mic 1", NULL, "Mic Diff" }, 544 { "Mic 2", NULL, "MIC2P" }, 545 { "Mic Diff", NULL, "MIC2N" }, 546 { "Mic 2", NULL, "Mic Diff" }, 547 548 { "Line In", NULL, "LLINEIN" }, 549 { "Line In", NULL, "RLINEIN" }, 550 551 { "Mic", "Stereo Capture Switch", "Mic 1" }, 552 { "Mic", "Stereo Capture Switch", "Mic 2" }, 553 { "Headphones Source", "Mic 1", "Mic" }, 554 { "Headphones Source", "Mic 2", "Mic" }, 555 { "Capture Source", "Mic 1", "Mic" }, 556 { "Capture Source", "Mic 2", "Mic" }, 557 558 { "Headphones Source", "Mic 1", "Mic 1" }, 559 { "Headphones Source", "Mic 2", "Mic 2" }, 560 { "Headphones Source", "Line In", "Line In Bypass" }, 561 { "Headphones Source", "PCM", "Headphones Playback" }, 562 { "HP Out", NULL, "Headphones Source" }, 563 564 { "Capture Source", "Line In", "Line In" }, 565 { "Capture Source", "Mic 1", "Mic 1" }, 566 { "Capture Source", "Mic 2", "Mic 2" }, 567 { "ADC", NULL, "Capture Source" }, 568 569 { "Line In Bypass", NULL, "Line In" }, 570 { "Line Out Source", "Line In", "Line In Bypass" }, 571 { "Line Out Source", "PCM", "PCM Playback" }, 572 573 { "LHPOUT", NULL, "HP Out"}, 574 { "RHPOUT", NULL, "HP Out"}, 575 576 { "Line Out", NULL, "Line Out Source" }, 577 { "Line Out Switch 2", NULL, "Line Out" }, 578 579 { "LOUT", NULL, "Line Out Switch 2"}, 580 { "ROUT", NULL, "Line Out Switch 2"}, 581 582 { "PCM Playback", "Volume", "DAC" }, 583 { "Headphones Playback", "Volume", "PCM Playback" }, 584 585 { "SYSCLK", NULL, "DAC" }, 586 }; 587 588 static void jz4770_codec_codec_init_regs(struct snd_soc_component *codec) 589 { 590 struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec); 591 struct regmap *regmap = jz_codec->regmap; 592 593 /* Collect updates for later sending. */ 594 regcache_cache_only(regmap, true); 595 596 /* default HP output to PCM */ 597 regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_HP, REG_CR_HP_SEL_MASK); 598 599 /* default line output to PCM */ 600 regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_LO, REG_CR_LO_SEL_MASK); 601 602 /* Disable stereo mic */ 603 regmap_clear_bits(regmap, JZ4770_CODEC_REG_CR_MIC, 604 BIT(REG_CR_MIC_STEREO_OFFSET)); 605 606 /* Set mic 1 as default source for ADC */ 607 regmap_clear_bits(regmap, JZ4770_CODEC_REG_CR_ADC, 608 REG_CR_ADC_IN_SEL_MASK); 609 610 /* ADC/DAC: serial + i2s */ 611 regmap_set_bits(regmap, JZ4770_CODEC_REG_AICR_ADC, 612 REG_AICR_ADC_SERIAL | REG_AICR_ADC_I2S); 613 regmap_set_bits(regmap, JZ4770_CODEC_REG_AICR_DAC, 614 REG_AICR_DAC_SERIAL | REG_AICR_DAC_I2S); 615 616 /* The generated IRQ is a high level */ 617 regmap_clear_bits(regmap, JZ4770_CODEC_REG_ICR, REG_ICR_INT_FORM_MASK); 618 regmap_update_bits(regmap, JZ4770_CODEC_REG_IMR, REG_IMR_ALL_MASK, 619 REG_IMR_JACK_MASK | REG_IMR_RUP_MASK | 620 REG_IMR_RDO_MASK | REG_IMR_GUP_MASK | 621 REG_IMR_GDO_MASK); 622 623 /* 12M oscillator */ 624 regmap_clear_bits(regmap, JZ4770_CODEC_REG_CCR, REG_CCR_CRYSTAL_MASK); 625 626 /* 0: 16ohm/220uF, 1: 10kohm/1uF */ 627 regmap_clear_bits(regmap, JZ4770_CODEC_REG_CR_HP, REG_CR_HP_LOAD); 628 629 /* disable automatic gain */ 630 regmap_clear_bits(regmap, JZ4770_CODEC_REG_AGC1, REG_AGC1_EN); 631 632 /* Disable DAC lrswap */ 633 regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_DAC, REG_CR_DAC_LRSWAP); 634 635 /* Independent L/R DAC gain control */ 636 regmap_clear_bits(regmap, JZ4770_CODEC_REG_GCR_DACL, 637 REG_GCR_DACL_RLGOD); 638 639 /* Disable ADC lrswap */ 640 regmap_set_bits(regmap, JZ4770_CODEC_REG_CR_ADC, REG_CR_ADC_LRSWAP); 641 642 /* default to cap-less mode(0) */ 643 regmap_clear_bits(regmap, JZ4770_CODEC_REG_CR_HP, REG_CR_HP_SB_HPCM); 644 645 /* Send collected updates. */ 646 regcache_cache_only(regmap, false); 647 regcache_sync(regmap); 648 } 649 650 static int jz4770_codec_codec_probe(struct snd_soc_component *codec) 651 { 652 struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec); 653 654 clk_prepare_enable(jz_codec->clk); 655 656 jz4770_codec_codec_init_regs(codec); 657 658 return 0; 659 } 660 661 static void jz4770_codec_codec_remove(struct snd_soc_component *codec) 662 { 663 struct jz_codec *jz_codec = snd_soc_component_get_drvdata(codec); 664 665 clk_disable_unprepare(jz_codec->clk); 666 } 667 668 static const struct snd_soc_component_driver jz4770_codec_soc_codec_dev = { 669 .probe = jz4770_codec_codec_probe, 670 .remove = jz4770_codec_codec_remove, 671 .set_bias_level = jz4770_codec_set_bias_level, 672 .controls = jz4770_codec_snd_controls, 673 .num_controls = ARRAY_SIZE(jz4770_codec_snd_controls), 674 .dapm_widgets = jz4770_codec_dapm_widgets, 675 .num_dapm_widgets = ARRAY_SIZE(jz4770_codec_dapm_widgets), 676 .dapm_routes = jz4770_codec_dapm_routes, 677 .num_dapm_routes = ARRAY_SIZE(jz4770_codec_dapm_routes), 678 .suspend_bias_off = 1, 679 .use_pmdown_time = 1, 680 }; 681 682 static const unsigned int jz4770_codec_sample_rates[] = { 683 96000, 48000, 44100, 32000, 684 24000, 22050, 16000, 12000, 685 11025, 9600, 8000, 686 }; 687 688 static int jz4770_codec_hw_params(struct snd_pcm_substream *substream, 689 struct snd_pcm_hw_params *params, 690 struct snd_soc_dai *dai) 691 { 692 struct jz_codec *codec = snd_soc_component_get_drvdata(dai->component); 693 unsigned int rate, bit_width; 694 695 switch (params_format(params)) { 696 case SNDRV_PCM_FORMAT_S16_LE: 697 bit_width = 0; 698 break; 699 case SNDRV_PCM_FORMAT_S18_3LE: 700 bit_width = 1; 701 break; 702 case SNDRV_PCM_FORMAT_S20_3LE: 703 bit_width = 2; 704 break; 705 case SNDRV_PCM_FORMAT_S24_3LE: 706 bit_width = 3; 707 break; 708 default: 709 return -EINVAL; 710 } 711 712 for (rate = 0; rate < ARRAY_SIZE(jz4770_codec_sample_rates); rate++) { 713 if (jz4770_codec_sample_rates[rate] == params_rate(params)) 714 break; 715 } 716 717 if (rate == ARRAY_SIZE(jz4770_codec_sample_rates)) 718 return -EINVAL; 719 720 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 721 regmap_update_bits(codec->regmap, JZ4770_CODEC_REG_AICR_DAC, 722 REG_AICR_DAC_ADWL_MASK, 723 bit_width << REG_AICR_DAC_ADWL_OFFSET); 724 regmap_update_bits(codec->regmap, JZ4770_CODEC_REG_FCR_DAC, 725 REG_FCR_DAC_FREQ_MASK, 726 rate << REG_FCR_DAC_FREQ_OFFSET); 727 } else { 728 regmap_update_bits(codec->regmap, JZ4770_CODEC_REG_AICR_ADC, 729 REG_AICR_ADC_ADWL_MASK, 730 bit_width << REG_AICR_ADC_ADWL_OFFSET); 731 regmap_update_bits(codec->regmap, JZ4770_CODEC_REG_FCR_ADC, 732 REG_FCR_ADC_FREQ_MASK, 733 rate << REG_FCR_ADC_FREQ_OFFSET); 734 } 735 736 return 0; 737 } 738 739 static const struct snd_soc_dai_ops jz4770_codec_dai_ops = { 740 .startup = jz4770_codec_startup, 741 .shutdown = jz4770_codec_shutdown, 742 .hw_params = jz4770_codec_hw_params, 743 .trigger = jz4770_codec_pcm_trigger, 744 .mute_stream = jz4770_codec_mute_stream, 745 .no_capture_mute = 1, 746 }; 747 748 #define JZ_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 749 SNDRV_PCM_FMTBIT_S18_3LE | \ 750 SNDRV_PCM_FMTBIT_S20_3LE | \ 751 SNDRV_PCM_FMTBIT_S24_3LE) 752 753 static struct snd_soc_dai_driver jz4770_codec_dai = { 754 .name = "jz4770-hifi", 755 .playback = { 756 .stream_name = "Playback", 757 .channels_min = 2, 758 .channels_max = 2, 759 .rates = SNDRV_PCM_RATE_8000_96000, 760 .formats = JZ_CODEC_FORMATS, 761 }, 762 .capture = { 763 .stream_name = "Capture", 764 .channels_min = 2, 765 .channels_max = 2, 766 .rates = SNDRV_PCM_RATE_8000_96000, 767 .formats = JZ_CODEC_FORMATS, 768 }, 769 .ops = &jz4770_codec_dai_ops, 770 }; 771 772 static bool jz4770_codec_volatile(struct device *dev, unsigned int reg) 773 { 774 return reg == JZ4770_CODEC_REG_SR || reg == JZ4770_CODEC_REG_IFR; 775 } 776 777 static bool jz4770_codec_readable(struct device *dev, unsigned int reg) 778 { 779 switch (reg) { 780 case JZ4770_CODEC_REG_MISSING_REG1: 781 case JZ4770_CODEC_REG_MISSING_REG2: 782 return false; 783 default: 784 return true; 785 } 786 } 787 788 static bool jz4770_codec_writeable(struct device *dev, unsigned int reg) 789 { 790 switch (reg) { 791 case JZ4770_CODEC_REG_SR: 792 case JZ4770_CODEC_REG_MISSING_REG1: 793 case JZ4770_CODEC_REG_MISSING_REG2: 794 return false; 795 default: 796 return true; 797 } 798 } 799 800 static int jz4770_codec_io_wait(struct jz_codec *codec) 801 { 802 u32 reg; 803 804 return readl_poll_timeout(codec->base + ICDC_RGADW_OFFSET, reg, 805 !(reg & ICDC_RGADW_RGWR), 806 1000, 10 * USEC_PER_MSEC); 807 } 808 809 static int jz4770_codec_reg_read(void *context, unsigned int reg, 810 unsigned int *val) 811 { 812 struct jz_codec *codec = context; 813 unsigned int i; 814 u32 tmp; 815 int ret; 816 817 ret = jz4770_codec_io_wait(codec); 818 if (ret) 819 return ret; 820 821 tmp = readl(codec->base + ICDC_RGADW_OFFSET); 822 tmp = (tmp & ~ICDC_RGADW_RGADDR_MASK) 823 | (reg << ICDC_RGADW_RGADDR_OFFSET); 824 writel(tmp, codec->base + ICDC_RGADW_OFFSET); 825 826 /* wait 6+ cycles */ 827 for (i = 0; i < 6; i++) 828 *val = readl(codec->base + ICDC_RGDATA_OFFSET) & 829 ICDC_RGDATA_RGDOUT_MASK; 830 831 return 0; 832 } 833 834 static int jz4770_codec_reg_write(void *context, unsigned int reg, 835 unsigned int val) 836 { 837 struct jz_codec *codec = context; 838 int ret; 839 840 ret = jz4770_codec_io_wait(codec); 841 if (ret) 842 return ret; 843 844 writel(ICDC_RGADW_RGWR | (reg << ICDC_RGADW_RGADDR_OFFSET) | val, 845 codec->base + ICDC_RGADW_OFFSET); 846 847 ret = jz4770_codec_io_wait(codec); 848 if (ret) 849 return ret; 850 851 return 0; 852 } 853 854 static const u8 jz4770_codec_reg_defaults[] = { 855 0x00, 0xC3, 0xC3, 0x90, 0x98, 0xFF, 0x90, 0xB1, 856 0x11, 0x10, 0x00, 0x03, 0x00, 0x00, 0x40, 0x00, 857 0xFF, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 858 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x34, 859 0x07, 0x44, 0x1F, 0x00 860 }; 861 862 static struct regmap_config jz4770_codec_regmap_config = { 863 .reg_bits = 7, 864 .val_bits = 8, 865 866 .max_register = JZ4770_CODEC_REG_AGC5, 867 .volatile_reg = jz4770_codec_volatile, 868 .readable_reg = jz4770_codec_readable, 869 .writeable_reg = jz4770_codec_writeable, 870 871 .reg_read = jz4770_codec_reg_read, 872 .reg_write = jz4770_codec_reg_write, 873 874 .reg_defaults_raw = jz4770_codec_reg_defaults, 875 .num_reg_defaults_raw = ARRAY_SIZE(jz4770_codec_reg_defaults), 876 .cache_type = REGCACHE_FLAT, 877 }; 878 879 static int jz4770_codec_probe(struct platform_device *pdev) 880 { 881 struct device *dev = &pdev->dev; 882 struct jz_codec *codec; 883 int ret; 884 885 codec = devm_kzalloc(dev, sizeof(*codec), GFP_KERNEL); 886 if (!codec) 887 return -ENOMEM; 888 889 codec->dev = dev; 890 891 codec->base = devm_platform_ioremap_resource(pdev, 0); 892 if (IS_ERR(codec->base)) { 893 ret = PTR_ERR(codec->base); 894 dev_err(dev, "Failed to ioremap mmio memory: %d\n", ret); 895 return ret; 896 } 897 898 codec->regmap = devm_regmap_init(dev, NULL, codec, 899 &jz4770_codec_regmap_config); 900 if (IS_ERR(codec->regmap)) 901 return PTR_ERR(codec->regmap); 902 903 codec->clk = devm_clk_get(dev, "aic"); 904 if (IS_ERR(codec->clk)) 905 return PTR_ERR(codec->clk); 906 907 platform_set_drvdata(pdev, codec); 908 909 ret = devm_snd_soc_register_component(dev, &jz4770_codec_soc_codec_dev, 910 &jz4770_codec_dai, 1); 911 if (ret) { 912 dev_err(dev, "Failed to register codec: %d\n", ret); 913 return ret; 914 } 915 916 return 0; 917 } 918 919 static const struct of_device_id jz4770_codec_of_matches[] = { 920 { .compatible = "ingenic,jz4770-codec", }, 921 { /* sentinel */ } 922 }; 923 MODULE_DEVICE_TABLE(of, jz4770_codec_of_matches); 924 925 static struct platform_driver jz4770_codec_driver = { 926 .probe = jz4770_codec_probe, 927 .driver = { 928 .name = "jz4770-codec", 929 .of_match_table = jz4770_codec_of_matches, 930 }, 931 }; 932 module_platform_driver(jz4770_codec_driver); 933 934 MODULE_DESCRIPTION("JZ4770 SoC internal codec driver"); 935 MODULE_AUTHOR("Maarten ter Huurne <maarten@treewalker.org>"); 936 MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>"); 937 MODULE_LICENSE("GPL v2"); 938