1 /* 2 * Driver of Inno codec for rk3036 by Rockchip Inc. 3 * 4 * Author: Rockchip Inc. 5 * Author: Zheng ShunQian<zhengsq@rock-chips.com> 6 */ 7 8 #include <sound/soc.h> 9 #include <sound/tlv.h> 10 #include <sound/soc-dapm.h> 11 #include <sound/soc-dai.h> 12 #include <sound/pcm.h> 13 #include <sound/pcm_params.h> 14 15 #include <linux/platform_device.h> 16 #include <linux/of.h> 17 #include <linux/clk.h> 18 #include <linux/regmap.h> 19 #include <linux/device.h> 20 #include <linux/mfd/syscon.h> 21 #include <linux/module.h> 22 #include <linux/io.h> 23 24 #include "inno_rk3036.h" 25 26 struct rk3036_codec_priv { 27 void __iomem *base; 28 struct clk *pclk; 29 struct regmap *regmap; 30 struct device *dev; 31 }; 32 33 static const DECLARE_TLV_DB_MINMAX(rk3036_codec_hp_tlv, -39, 0); 34 35 static int rk3036_codec_antipop_info(struct snd_kcontrol *kcontrol, 36 struct snd_ctl_elem_info *uinfo) 37 { 38 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 39 uinfo->count = 2; 40 uinfo->value.integer.min = 0; 41 uinfo->value.integer.max = 1; 42 43 return 0; 44 } 45 46 static int rk3036_codec_antipop_get(struct snd_kcontrol *kcontrol, 47 struct snd_ctl_elem_value *ucontrol) 48 { 49 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 50 int val, ret, regval; 51 52 ret = snd_soc_component_read(component, INNO_R09, ®val); 53 if (ret) 54 return ret; 55 val = ((regval >> INNO_R09_HPL_ANITPOP_SHIFT) & 56 INNO_R09_HP_ANTIPOP_MSK) == INNO_R09_HP_ANTIPOP_ON; 57 ucontrol->value.integer.value[0] = val; 58 59 val = ((regval >> INNO_R09_HPR_ANITPOP_SHIFT) & 60 INNO_R09_HP_ANTIPOP_MSK) == INNO_R09_HP_ANTIPOP_ON; 61 ucontrol->value.integer.value[1] = val; 62 63 return 0; 64 } 65 66 static int rk3036_codec_antipop_put(struct snd_kcontrol *kcontrol, 67 struct snd_ctl_elem_value *ucontrol) 68 { 69 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 70 int val, ret, regmsk; 71 72 val = (ucontrol->value.integer.value[0] ? 73 INNO_R09_HP_ANTIPOP_ON : INNO_R09_HP_ANTIPOP_OFF) << 74 INNO_R09_HPL_ANITPOP_SHIFT; 75 val |= (ucontrol->value.integer.value[1] ? 76 INNO_R09_HP_ANTIPOP_ON : INNO_R09_HP_ANTIPOP_OFF) << 77 INNO_R09_HPR_ANITPOP_SHIFT; 78 79 regmsk = INNO_R09_HP_ANTIPOP_MSK << INNO_R09_HPL_ANITPOP_SHIFT | 80 INNO_R09_HP_ANTIPOP_MSK << INNO_R09_HPR_ANITPOP_SHIFT; 81 82 ret = snd_soc_component_update_bits(component, INNO_R09, 83 regmsk, val); 84 if (ret < 0) 85 return ret; 86 87 return 0; 88 } 89 90 #define SOC_RK3036_CODEC_ANTIPOP_DECL(xname) \ 91 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 92 .info = rk3036_codec_antipop_info, .get = rk3036_codec_antipop_get, \ 93 .put = rk3036_codec_antipop_put, } 94 95 static const struct snd_kcontrol_new rk3036_codec_dapm_controls[] = { 96 SOC_DOUBLE_R_RANGE_TLV("Headphone Volume", INNO_R07, INNO_R08, 97 INNO_HP_GAIN_SHIFT, INNO_HP_GAIN_N39DB, 98 INNO_HP_GAIN_0DB, 0, rk3036_codec_hp_tlv), 99 SOC_DOUBLE("Zero Cross Switch", INNO_R06, INNO_R06_VOUTL_CZ_SHIFT, 100 INNO_R06_VOUTR_CZ_SHIFT, 1, 0), 101 SOC_DOUBLE("Headphone Switch", INNO_R09, INNO_R09_HPL_MUTE_SHIFT, 102 INNO_R09_HPR_MUTE_SHIFT, 1, 0), 103 SOC_RK3036_CODEC_ANTIPOP_DECL("Anti-pop Switch"), 104 }; 105 106 static const struct snd_kcontrol_new rk3036_codec_hpl_mixer_controls[] = { 107 SOC_DAPM_SINGLE("DAC Left Out Switch", INNO_R09, 108 INNO_R09_DACL_SWITCH_SHIFT, 1, 0), 109 }; 110 111 static const struct snd_kcontrol_new rk3036_codec_hpr_mixer_controls[] = { 112 SOC_DAPM_SINGLE("DAC Right Out Switch", INNO_R09, 113 INNO_R09_DACR_SWITCH_SHIFT, 1, 0), 114 }; 115 116 static const struct snd_kcontrol_new rk3036_codec_hpl_switch_controls[] = { 117 SOC_DAPM_SINGLE("HP Left Out Switch", INNO_R05, 118 INNO_R05_HPL_WORK_SHIFT, 1, 0), 119 }; 120 121 static const struct snd_kcontrol_new rk3036_codec_hpr_switch_controls[] = { 122 SOC_DAPM_SINGLE("HP Right Out Switch", INNO_R05, 123 INNO_R05_HPR_WORK_SHIFT, 1, 0), 124 }; 125 126 static const struct snd_soc_dapm_widget rk3036_codec_dapm_widgets[] = { 127 SND_SOC_DAPM_SUPPLY_S("DAC PWR", 1, INNO_R06, 128 INNO_R06_DAC_EN_SHIFT, 0, NULL, 0), 129 SND_SOC_DAPM_SUPPLY_S("DACL VREF", 2, INNO_R04, 130 INNO_R04_DACL_VREF_SHIFT, 0, NULL, 0), 131 SND_SOC_DAPM_SUPPLY_S("DACR VREF", 2, INNO_R04, 132 INNO_R04_DACR_VREF_SHIFT, 0, NULL, 0), 133 SND_SOC_DAPM_SUPPLY_S("DACL HiLo VREF", 3, INNO_R06, 134 INNO_R06_DACL_HILO_VREF_SHIFT, 0, NULL, 0), 135 SND_SOC_DAPM_SUPPLY_S("DACR HiLo VREF", 3, INNO_R06, 136 INNO_R06_DACR_HILO_VREF_SHIFT, 0, NULL, 0), 137 SND_SOC_DAPM_SUPPLY_S("DACR CLK", 3, INNO_R04, 138 INNO_R04_DACR_CLK_SHIFT, 0, NULL, 0), 139 SND_SOC_DAPM_SUPPLY_S("DACL CLK", 3, INNO_R04, 140 INNO_R04_DACL_CLK_SHIFT, 0, NULL, 0), 141 142 SND_SOC_DAPM_DAC("DACL", "Left Playback", INNO_R04, 143 INNO_R04_DACL_SW_SHIFT, 0), 144 SND_SOC_DAPM_DAC("DACR", "Right Playback", INNO_R04, 145 INNO_R04_DACR_SW_SHIFT, 0), 146 147 SND_SOC_DAPM_MIXER("Left Headphone Mixer", SND_SOC_NOPM, 0, 0, 148 rk3036_codec_hpl_mixer_controls, 149 ARRAY_SIZE(rk3036_codec_hpl_mixer_controls)), 150 SND_SOC_DAPM_MIXER("Right Headphone Mixer", SND_SOC_NOPM, 0, 0, 151 rk3036_codec_hpr_mixer_controls, 152 ARRAY_SIZE(rk3036_codec_hpr_mixer_controls)), 153 154 SND_SOC_DAPM_PGA("HP Left Out", INNO_R05, 155 INNO_R05_HPL_EN_SHIFT, 0, NULL, 0), 156 SND_SOC_DAPM_PGA("HP Right Out", INNO_R05, 157 INNO_R05_HPR_EN_SHIFT, 0, NULL, 0), 158 159 SND_SOC_DAPM_MIXER("HP Left Switch", SND_SOC_NOPM, 0, 0, 160 rk3036_codec_hpl_switch_controls, 161 ARRAY_SIZE(rk3036_codec_hpl_switch_controls)), 162 SND_SOC_DAPM_MIXER("HP Right Switch", SND_SOC_NOPM, 0, 0, 163 rk3036_codec_hpr_switch_controls, 164 ARRAY_SIZE(rk3036_codec_hpr_switch_controls)), 165 166 SND_SOC_DAPM_OUTPUT("HPL"), 167 SND_SOC_DAPM_OUTPUT("HPR"), 168 }; 169 170 static const struct snd_soc_dapm_route rk3036_codec_dapm_routes[] = { 171 {"DACL VREF", NULL, "DAC PWR"}, 172 {"DACR VREF", NULL, "DAC PWR"}, 173 {"DACL HiLo VREF", NULL, "DAC PWR"}, 174 {"DACR HiLo VREF", NULL, "DAC PWR"}, 175 {"DACL CLK", NULL, "DAC PWR"}, 176 {"DACR CLK", NULL, "DAC PWR"}, 177 178 {"DACL", NULL, "DACL VREF"}, 179 {"DACL", NULL, "DACL HiLo VREF"}, 180 {"DACL", NULL, "DACL CLK"}, 181 {"DACR", NULL, "DACR VREF"}, 182 {"DACR", NULL, "DACR HiLo VREF"}, 183 {"DACR", NULL, "DACR CLK"}, 184 185 {"Left Headphone Mixer", "DAC Left Out Switch", "DACL"}, 186 {"Right Headphone Mixer", "DAC Right Out Switch", "DACR"}, 187 {"HP Left Out", NULL, "Left Headphone Mixer"}, 188 {"HP Right Out", NULL, "Right Headphone Mixer"}, 189 190 {"HP Left Switch", "HP Left Out Switch", "HP Left Out"}, 191 {"HP Right Switch", "HP Right Out Switch", "HP Right Out"}, 192 193 {"HPL", NULL, "HP Left Switch"}, 194 {"HPR", NULL, "HP Right Switch"}, 195 }; 196 197 static int rk3036_codec_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 198 { 199 struct snd_soc_codec *codec = dai->codec; 200 unsigned int reg01_val = 0, reg02_val = 0, reg03_val = 0; 201 202 dev_dbg(codec->dev, "rk3036_codec dai set fmt : %08x\n", fmt); 203 204 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 205 case SND_SOC_DAIFMT_CBS_CFS: 206 reg01_val |= INNO_R01_PINDIR_IN_SLAVE | 207 INNO_R01_I2SMODE_SLAVE; 208 break; 209 case SND_SOC_DAIFMT_CBM_CFM: 210 reg01_val |= INNO_R01_PINDIR_OUT_MASTER | 211 INNO_R01_I2SMODE_MASTER; 212 break; 213 default: 214 dev_err(codec->dev, "invalid fmt\n"); 215 return -EINVAL; 216 } 217 218 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 219 case SND_SOC_DAIFMT_DSP_A: 220 reg02_val |= INNO_R02_DACM_PCM; 221 break; 222 case SND_SOC_DAIFMT_I2S: 223 reg02_val |= INNO_R02_DACM_I2S; 224 break; 225 case SND_SOC_DAIFMT_RIGHT_J: 226 reg02_val |= INNO_R02_DACM_RJM; 227 break; 228 case SND_SOC_DAIFMT_LEFT_J: 229 reg02_val |= INNO_R02_DACM_LJM; 230 break; 231 default: 232 dev_err(codec->dev, "set dai format failed\n"); 233 return -EINVAL; 234 } 235 236 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 237 case SND_SOC_DAIFMT_NB_NF: 238 reg02_val |= INNO_R02_LRCP_NORMAL; 239 reg03_val |= INNO_R03_BCP_NORMAL; 240 break; 241 case SND_SOC_DAIFMT_IB_IF: 242 reg02_val |= INNO_R02_LRCP_REVERSAL; 243 reg03_val |= INNO_R03_BCP_REVERSAL; 244 break; 245 case SND_SOC_DAIFMT_IB_NF: 246 reg02_val |= INNO_R02_LRCP_REVERSAL; 247 reg03_val |= INNO_R03_BCP_NORMAL; 248 break; 249 case SND_SOC_DAIFMT_NB_IF: 250 reg02_val |= INNO_R02_LRCP_NORMAL; 251 reg03_val |= INNO_R03_BCP_REVERSAL; 252 break; 253 default: 254 dev_err(codec->dev, "set dai format failed\n"); 255 return -EINVAL; 256 } 257 258 snd_soc_update_bits(codec, INNO_R01, INNO_R01_I2SMODE_MSK | 259 INNO_R01_PINDIR_MSK, reg01_val); 260 snd_soc_update_bits(codec, INNO_R02, INNO_R02_LRCP_MSK | 261 INNO_R02_DACM_MSK, reg02_val); 262 snd_soc_update_bits(codec, INNO_R03, INNO_R03_BCP_MSK, reg03_val); 263 264 return 0; 265 } 266 267 static int rk3036_codec_dai_hw_params(struct snd_pcm_substream *substream, 268 struct snd_pcm_hw_params *hw_params, 269 struct snd_soc_dai *dai) 270 { 271 struct snd_soc_codec *codec = dai->codec; 272 unsigned int reg02_val = 0, reg03_val = 0; 273 274 switch (params_format(hw_params)) { 275 case SNDRV_PCM_FORMAT_S16_LE: 276 reg02_val |= INNO_R02_VWL_16BIT; 277 break; 278 case SNDRV_PCM_FORMAT_S20_3LE: 279 reg02_val |= INNO_R02_VWL_20BIT; 280 break; 281 case SNDRV_PCM_FORMAT_S24_LE: 282 reg02_val |= INNO_R02_VWL_24BIT; 283 break; 284 case SNDRV_PCM_FORMAT_S32_LE: 285 reg02_val |= INNO_R02_VWL_32BIT; 286 break; 287 default: 288 return -EINVAL; 289 } 290 291 reg02_val |= INNO_R02_LRCP_NORMAL; 292 reg03_val |= INNO_R03_FWL_32BIT | INNO_R03_DACR_WORK; 293 294 snd_soc_update_bits(codec, INNO_R02, INNO_R02_LRCP_MSK | 295 INNO_R02_VWL_MSK, reg02_val); 296 snd_soc_update_bits(codec, INNO_R03, INNO_R03_DACR_MSK | 297 INNO_R03_FWL_MSK, reg03_val); 298 return 0; 299 } 300 301 #define RK3036_CODEC_RATES (SNDRV_PCM_RATE_8000 | \ 302 SNDRV_PCM_RATE_16000 | \ 303 SNDRV_PCM_RATE_32000 | \ 304 SNDRV_PCM_RATE_44100 | \ 305 SNDRV_PCM_RATE_48000 | \ 306 SNDRV_PCM_RATE_96000) 307 308 #define RK3036_CODEC_FMTS (SNDRV_PCM_FMTBIT_S16_LE | \ 309 SNDRV_PCM_FMTBIT_S20_3LE | \ 310 SNDRV_PCM_FMTBIT_S24_LE | \ 311 SNDRV_PCM_FMTBIT_S32_LE) 312 313 static struct snd_soc_dai_ops rk3036_codec_dai_ops = { 314 .set_fmt = rk3036_codec_dai_set_fmt, 315 .hw_params = rk3036_codec_dai_hw_params, 316 }; 317 318 static struct snd_soc_dai_driver rk3036_codec_dai_driver[] = { 319 { 320 .name = "rk3036-codec-dai", 321 .playback = { 322 .stream_name = "Playback", 323 .channels_min = 1, 324 .channels_max = 2, 325 .rates = RK3036_CODEC_RATES, 326 .formats = RK3036_CODEC_FMTS, 327 }, 328 .ops = &rk3036_codec_dai_ops, 329 .symmetric_rates = 1, 330 }, 331 }; 332 333 static void rk3036_codec_reset(struct snd_soc_codec *codec) 334 { 335 snd_soc_write(codec, INNO_R00, 336 INNO_R00_CSR_RESET | INNO_R00_CDCR_RESET); 337 snd_soc_write(codec, INNO_R00, 338 INNO_R00_CSR_WORK | INNO_R00_CDCR_WORK); 339 } 340 341 static int rk3036_codec_probe(struct snd_soc_codec *codec) 342 { 343 rk3036_codec_reset(codec); 344 return 0; 345 } 346 347 static int rk3036_codec_remove(struct snd_soc_codec *codec) 348 { 349 rk3036_codec_reset(codec); 350 return 0; 351 } 352 353 static int rk3036_codec_set_bias_level(struct snd_soc_codec *codec, 354 enum snd_soc_bias_level level) 355 { 356 switch (level) { 357 case SND_SOC_BIAS_STANDBY: 358 /* set a big current for capacitor charging. */ 359 snd_soc_write(codec, INNO_R10, INNO_R10_MAX_CUR); 360 /* start precharge */ 361 snd_soc_write(codec, INNO_R06, INNO_R06_DAC_PRECHARGE); 362 363 break; 364 365 case SND_SOC_BIAS_OFF: 366 /* set a big current for capacitor discharging. */ 367 snd_soc_write(codec, INNO_R10, INNO_R10_MAX_CUR); 368 /* start discharge. */ 369 snd_soc_write(codec, INNO_R06, INNO_R06_DAC_DISCHARGE); 370 371 break; 372 default: 373 break; 374 } 375 376 return 0; 377 } 378 379 static struct snd_soc_codec_driver rk3036_codec_driver = { 380 .probe = rk3036_codec_probe, 381 .remove = rk3036_codec_remove, 382 .set_bias_level = rk3036_codec_set_bias_level, 383 .component_driver = { 384 .controls = rk3036_codec_dapm_controls, 385 .num_controls = ARRAY_SIZE(rk3036_codec_dapm_controls), 386 .dapm_routes = rk3036_codec_dapm_routes, 387 .num_dapm_routes = ARRAY_SIZE(rk3036_codec_dapm_routes), 388 .dapm_widgets = rk3036_codec_dapm_widgets, 389 .num_dapm_widgets = ARRAY_SIZE(rk3036_codec_dapm_widgets), 390 }, 391 }; 392 393 static const struct regmap_config rk3036_codec_regmap_config = { 394 .reg_bits = 32, 395 .reg_stride = 4, 396 .val_bits = 32, 397 }; 398 399 #define GRF_SOC_CON0 0x00140 400 #define GRF_ACODEC_SEL (BIT(10) | BIT(16 + 10)) 401 402 static int rk3036_codec_platform_probe(struct platform_device *pdev) 403 { 404 struct rk3036_codec_priv *priv; 405 struct device_node *of_node = pdev->dev.of_node; 406 struct resource *res; 407 void __iomem *base; 408 struct regmap *grf; 409 int ret; 410 411 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 412 if (!priv) 413 return -ENOMEM; 414 415 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 416 base = devm_ioremap_resource(&pdev->dev, res); 417 if (IS_ERR(base)) 418 return PTR_ERR(base); 419 420 priv->base = base; 421 priv->regmap = devm_regmap_init_mmio(&pdev->dev, priv->base, 422 &rk3036_codec_regmap_config); 423 if (IS_ERR(priv->regmap)) { 424 dev_err(&pdev->dev, "init regmap failed\n"); 425 return PTR_ERR(priv->regmap); 426 } 427 428 grf = syscon_regmap_lookup_by_phandle(of_node, "rockchip,grf"); 429 if (IS_ERR(grf)) { 430 dev_err(&pdev->dev, "needs 'rockchip,grf' property\n"); 431 return PTR_ERR(grf); 432 } 433 ret = regmap_write(grf, GRF_SOC_CON0, GRF_ACODEC_SEL); 434 if (ret) { 435 dev_err(&pdev->dev, "Could not write to GRF: %d\n", ret); 436 return ret; 437 } 438 439 priv->pclk = devm_clk_get(&pdev->dev, "acodec_pclk"); 440 if (IS_ERR(priv->pclk)) 441 return PTR_ERR(priv->pclk); 442 443 ret = clk_prepare_enable(priv->pclk); 444 if (ret < 0) { 445 dev_err(&pdev->dev, "failed to enable clk\n"); 446 return ret; 447 } 448 449 priv->dev = &pdev->dev; 450 dev_set_drvdata(&pdev->dev, priv); 451 452 ret = snd_soc_register_codec(&pdev->dev, &rk3036_codec_driver, 453 rk3036_codec_dai_driver, 454 ARRAY_SIZE(rk3036_codec_dai_driver)); 455 if (ret) { 456 clk_disable_unprepare(priv->pclk); 457 dev_set_drvdata(&pdev->dev, NULL); 458 } 459 460 return ret; 461 } 462 463 static int rk3036_codec_platform_remove(struct platform_device *pdev) 464 { 465 struct rk3036_codec_priv *priv = dev_get_drvdata(&pdev->dev); 466 467 snd_soc_unregister_codec(&pdev->dev); 468 clk_disable_unprepare(priv->pclk); 469 470 return 0; 471 } 472 473 static const struct of_device_id rk3036_codec_of_match[] = { 474 { .compatible = "rockchip,rk3036-codec", }, 475 {} 476 }; 477 MODULE_DEVICE_TABLE(of, rk3036_codec_of_match); 478 479 static struct platform_driver rk3036_codec_platform_driver = { 480 .driver = { 481 .name = "rk3036-codec-platform", 482 .of_match_table = of_match_ptr(rk3036_codec_of_match), 483 }, 484 .probe = rk3036_codec_platform_probe, 485 .remove = rk3036_codec_platform_remove, 486 }; 487 488 module_platform_driver(rk3036_codec_platform_driver); 489 490 MODULE_AUTHOR("Rockchip Inc."); 491 MODULE_DESCRIPTION("Rockchip rk3036 codec driver"); 492 MODULE_LICENSE("GPL"); 493