1 /* 2 * DA9055 ALSA Soc codec driver 3 * 4 * Copyright (c) 2012 Dialog Semiconductor 5 * 6 * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C 7 * Written by David Chen <david.chen@diasemi.com> and 8 * Ashish Chavan <ashish.chavan@kpitcummins.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/soc.h> 26 #include <sound/initval.h> 27 #include <sound/tlv.h> 28 #include <sound/da9055.h> 29 30 /* DA9055 register space */ 31 32 /* Status Registers */ 33 #define DA9055_STATUS1 0x02 34 #define DA9055_PLL_STATUS 0x03 35 #define DA9055_AUX_L_GAIN_STATUS 0x04 36 #define DA9055_AUX_R_GAIN_STATUS 0x05 37 #define DA9055_MIC_L_GAIN_STATUS 0x06 38 #define DA9055_MIC_R_GAIN_STATUS 0x07 39 #define DA9055_MIXIN_L_GAIN_STATUS 0x08 40 #define DA9055_MIXIN_R_GAIN_STATUS 0x09 41 #define DA9055_ADC_L_GAIN_STATUS 0x0A 42 #define DA9055_ADC_R_GAIN_STATUS 0x0B 43 #define DA9055_DAC_L_GAIN_STATUS 0x0C 44 #define DA9055_DAC_R_GAIN_STATUS 0x0D 45 #define DA9055_HP_L_GAIN_STATUS 0x0E 46 #define DA9055_HP_R_GAIN_STATUS 0x0F 47 #define DA9055_LINE_GAIN_STATUS 0x10 48 49 /* System Initialisation Registers */ 50 #define DA9055_CIF_CTRL 0x20 51 #define DA9055_DIG_ROUTING_AIF 0X21 52 #define DA9055_SR 0x22 53 #define DA9055_REFERENCES 0x23 54 #define DA9055_PLL_FRAC_TOP 0x24 55 #define DA9055_PLL_FRAC_BOT 0x25 56 #define DA9055_PLL_INTEGER 0x26 57 #define DA9055_PLL_CTRL 0x27 58 #define DA9055_AIF_CLK_MODE 0x28 59 #define DA9055_AIF_CTRL 0x29 60 #define DA9055_DIG_ROUTING_DAC 0x2A 61 #define DA9055_ALC_CTRL1 0x2B 62 63 /* Input - Gain, Select and Filter Registers */ 64 #define DA9055_AUX_L_GAIN 0x30 65 #define DA9055_AUX_R_GAIN 0x31 66 #define DA9055_MIXIN_L_SELECT 0x32 67 #define DA9055_MIXIN_R_SELECT 0x33 68 #define DA9055_MIXIN_L_GAIN 0x34 69 #define DA9055_MIXIN_R_GAIN 0x35 70 #define DA9055_ADC_L_GAIN 0x36 71 #define DA9055_ADC_R_GAIN 0x37 72 #define DA9055_ADC_FILTERS1 0x38 73 #define DA9055_MIC_L_GAIN 0x39 74 #define DA9055_MIC_R_GAIN 0x3A 75 76 /* Output - Gain, Select and Filter Registers */ 77 #define DA9055_DAC_FILTERS5 0x40 78 #define DA9055_DAC_FILTERS2 0x41 79 #define DA9055_DAC_FILTERS3 0x42 80 #define DA9055_DAC_FILTERS4 0x43 81 #define DA9055_DAC_FILTERS1 0x44 82 #define DA9055_DAC_L_GAIN 0x45 83 #define DA9055_DAC_R_GAIN 0x46 84 #define DA9055_CP_CTRL 0x47 85 #define DA9055_HP_L_GAIN 0x48 86 #define DA9055_HP_R_GAIN 0x49 87 #define DA9055_LINE_GAIN 0x4A 88 #define DA9055_MIXOUT_L_SELECT 0x4B 89 #define DA9055_MIXOUT_R_SELECT 0x4C 90 91 /* System Controller Registers */ 92 #define DA9055_SYSTEM_MODES_INPUT 0x50 93 #define DA9055_SYSTEM_MODES_OUTPUT 0x51 94 95 /* Control Registers */ 96 #define DA9055_AUX_L_CTRL 0x60 97 #define DA9055_AUX_R_CTRL 0x61 98 #define DA9055_MIC_BIAS_CTRL 0x62 99 #define DA9055_MIC_L_CTRL 0x63 100 #define DA9055_MIC_R_CTRL 0x64 101 #define DA9055_MIXIN_L_CTRL 0x65 102 #define DA9055_MIXIN_R_CTRL 0x66 103 #define DA9055_ADC_L_CTRL 0x67 104 #define DA9055_ADC_R_CTRL 0x68 105 #define DA9055_DAC_L_CTRL 0x69 106 #define DA9055_DAC_R_CTRL 0x6A 107 #define DA9055_HP_L_CTRL 0x6B 108 #define DA9055_HP_R_CTRL 0x6C 109 #define DA9055_LINE_CTRL 0x6D 110 #define DA9055_MIXOUT_L_CTRL 0x6E 111 #define DA9055_MIXOUT_R_CTRL 0x6F 112 113 /* Configuration Registers */ 114 #define DA9055_LDO_CTRL 0x90 115 #define DA9055_IO_CTRL 0x91 116 #define DA9055_GAIN_RAMP_CTRL 0x92 117 #define DA9055_MIC_CONFIG 0x93 118 #define DA9055_PC_COUNT 0x94 119 #define DA9055_CP_VOL_THRESHOLD1 0x95 120 #define DA9055_CP_DELAY 0x96 121 #define DA9055_CP_DETECTOR 0x97 122 #define DA9055_AIF_OFFSET 0x98 123 #define DA9055_DIG_CTRL 0x99 124 #define DA9055_ALC_CTRL2 0x9A 125 #define DA9055_ALC_CTRL3 0x9B 126 #define DA9055_ALC_NOISE 0x9C 127 #define DA9055_ALC_TARGET_MIN 0x9D 128 #define DA9055_ALC_TARGET_MAX 0x9E 129 #define DA9055_ALC_GAIN_LIMITS 0x9F 130 #define DA9055_ALC_ANA_GAIN_LIMITS 0xA0 131 #define DA9055_ALC_ANTICLIP_CTRL 0xA1 132 #define DA9055_ALC_ANTICLIP_LEVEL 0xA2 133 #define DA9055_ALC_OFFSET_OP2M_L 0xA6 134 #define DA9055_ALC_OFFSET_OP2U_L 0xA7 135 #define DA9055_ALC_OFFSET_OP2M_R 0xAB 136 #define DA9055_ALC_OFFSET_OP2U_R 0xAC 137 #define DA9055_ALC_CIC_OP_LVL_CTRL 0xAD 138 #define DA9055_ALC_CIC_OP_LVL_DATA 0xAE 139 #define DA9055_DAC_NG_SETUP_TIME 0xAF 140 #define DA9055_DAC_NG_OFF_THRESHOLD 0xB0 141 #define DA9055_DAC_NG_ON_THRESHOLD 0xB1 142 #define DA9055_DAC_NG_CTRL 0xB2 143 144 /* SR bit fields */ 145 #define DA9055_SR_8000 (0x1 << 0) 146 #define DA9055_SR_11025 (0x2 << 0) 147 #define DA9055_SR_12000 (0x3 << 0) 148 #define DA9055_SR_16000 (0x5 << 0) 149 #define DA9055_SR_22050 (0x6 << 0) 150 #define DA9055_SR_24000 (0x7 << 0) 151 #define DA9055_SR_32000 (0x9 << 0) 152 #define DA9055_SR_44100 (0xA << 0) 153 #define DA9055_SR_48000 (0xB << 0) 154 #define DA9055_SR_88200 (0xE << 0) 155 #define DA9055_SR_96000 (0xF << 0) 156 157 /* REFERENCES bit fields */ 158 #define DA9055_BIAS_EN (1 << 3) 159 #define DA9055_VMID_EN (1 << 7) 160 161 /* PLL_CTRL bit fields */ 162 #define DA9055_PLL_INDIV_10_20_MHZ (1 << 2) 163 #define DA9055_PLL_SRM_EN (1 << 6) 164 #define DA9055_PLL_EN (1 << 7) 165 166 /* AIF_CLK_MODE bit fields */ 167 #define DA9055_AIF_BCLKS_PER_WCLK_32 (0 << 0) 168 #define DA9055_AIF_BCLKS_PER_WCLK_64 (1 << 0) 169 #define DA9055_AIF_BCLKS_PER_WCLK_128 (2 << 0) 170 #define DA9055_AIF_BCLKS_PER_WCLK_256 (3 << 0) 171 #define DA9055_AIF_CLK_EN_SLAVE_MODE (0 << 7) 172 #define DA9055_AIF_CLK_EN_MASTER_MODE (1 << 7) 173 174 /* AIF_CTRL bit fields */ 175 #define DA9055_AIF_FORMAT_I2S_MODE (0 << 0) 176 #define DA9055_AIF_FORMAT_LEFT_J (1 << 0) 177 #define DA9055_AIF_FORMAT_RIGHT_J (2 << 0) 178 #define DA9055_AIF_FORMAT_DSP (3 << 0) 179 #define DA9055_AIF_WORD_S16_LE (0 << 2) 180 #define DA9055_AIF_WORD_S20_3LE (1 << 2) 181 #define DA9055_AIF_WORD_S24_LE (2 << 2) 182 #define DA9055_AIF_WORD_S32_LE (3 << 2) 183 184 /* MIC_L_CTRL bit fields */ 185 #define DA9055_MIC_L_MUTE_EN (1 << 6) 186 187 /* MIC_R_CTRL bit fields */ 188 #define DA9055_MIC_R_MUTE_EN (1 << 6) 189 190 /* MIXIN_L_CTRL bit fields */ 191 #define DA9055_MIXIN_L_MIX_EN (1 << 3) 192 193 /* MIXIN_R_CTRL bit fields */ 194 #define DA9055_MIXIN_R_MIX_EN (1 << 3) 195 196 /* ADC_L_CTRL bit fields */ 197 #define DA9055_ADC_L_EN (1 << 7) 198 199 /* ADC_R_CTRL bit fields */ 200 #define DA9055_ADC_R_EN (1 << 7) 201 202 /* DAC_L_CTRL bit fields */ 203 #define DA9055_DAC_L_MUTE_EN (1 << 6) 204 205 /* DAC_R_CTRL bit fields */ 206 #define DA9055_DAC_R_MUTE_EN (1 << 6) 207 208 /* HP_L_CTRL bit fields */ 209 #define DA9055_HP_L_AMP_OE (1 << 3) 210 211 /* HP_R_CTRL bit fields */ 212 #define DA9055_HP_R_AMP_OE (1 << 3) 213 214 /* LINE_CTRL bit fields */ 215 #define DA9055_LINE_AMP_OE (1 << 3) 216 217 /* MIXOUT_L_CTRL bit fields */ 218 #define DA9055_MIXOUT_L_MIX_EN (1 << 3) 219 220 /* MIXOUT_R_CTRL bit fields */ 221 #define DA9055_MIXOUT_R_MIX_EN (1 << 3) 222 223 /* MIC bias select bit fields */ 224 #define DA9055_MICBIAS2_EN (1 << 6) 225 226 /* ALC_CIC_OP_LEVEL_CTRL bit fields */ 227 #define DA9055_ALC_DATA_MIDDLE (2 << 0) 228 #define DA9055_ALC_DATA_TOP (3 << 0) 229 #define DA9055_ALC_CIC_OP_CHANNEL_LEFT (0 << 7) 230 #define DA9055_ALC_CIC_OP_CHANNEL_RIGHT (1 << 7) 231 232 #define DA9055_AIF_BCLK_MASK (3 << 0) 233 #define DA9055_AIF_CLK_MODE_MASK (1 << 7) 234 #define DA9055_AIF_FORMAT_MASK (3 << 0) 235 #define DA9055_AIF_WORD_LENGTH_MASK (3 << 2) 236 #define DA9055_GAIN_RAMPING_EN (1 << 5) 237 #define DA9055_MICBIAS_LEVEL_MASK (3 << 4) 238 239 #define DA9055_ALC_OFFSET_15_8 0x00FF00 240 #define DA9055_ALC_OFFSET_17_16 0x030000 241 #define DA9055_ALC_AVG_ITERATIONS 5 242 243 struct pll_div { 244 int fref; 245 int fout; 246 u8 frac_top; 247 u8 frac_bot; 248 u8 integer; 249 u8 mode; /* 0 = slave, 1 = master */ 250 }; 251 252 /* PLL divisor table */ 253 static const struct pll_div da9055_pll_div[] = { 254 /* for MASTER mode, fs = 44.1Khz and its harmonics */ 255 {11289600, 2822400, 0x00, 0x00, 0x20, 1}, /* MCLK=11.2896Mhz */ 256 {12000000, 2822400, 0x03, 0x61, 0x1E, 1}, /* MCLK=12Mhz */ 257 {12288000, 2822400, 0x0C, 0xCC, 0x1D, 1}, /* MCLK=12.288Mhz */ 258 {13000000, 2822400, 0x19, 0x45, 0x1B, 1}, /* MCLK=13Mhz */ 259 {13500000, 2822400, 0x18, 0x56, 0x1A, 1}, /* MCLK=13.5Mhz */ 260 {14400000, 2822400, 0x02, 0xD0, 0x19, 1}, /* MCLK=14.4Mhz */ 261 {19200000, 2822400, 0x1A, 0x1C, 0x12, 1}, /* MCLK=19.2Mhz */ 262 {19680000, 2822400, 0x0B, 0x6D, 0x12, 1}, /* MCLK=19.68Mhz */ 263 {19800000, 2822400, 0x07, 0xDD, 0x12, 1}, /* MCLK=19.8Mhz */ 264 /* for MASTER mode, fs = 48Khz and its harmonics */ 265 {11289600, 3072000, 0x1A, 0x8E, 0x22, 1}, /* MCLK=11.2896Mhz */ 266 {12000000, 3072000, 0x18, 0x93, 0x20, 1}, /* MCLK=12Mhz */ 267 {12288000, 3072000, 0x00, 0x00, 0x20, 1}, /* MCLK=12.288Mhz */ 268 {13000000, 3072000, 0x07, 0xEA, 0x1E, 1}, /* MCLK=13Mhz */ 269 {13500000, 3072000, 0x04, 0x11, 0x1D, 1}, /* MCLK=13.5Mhz */ 270 {14400000, 3072000, 0x09, 0xD0, 0x1B, 1}, /* MCLK=14.4Mhz */ 271 {19200000, 3072000, 0x0F, 0x5C, 0x14, 1}, /* MCLK=19.2Mhz */ 272 {19680000, 3072000, 0x1F, 0x60, 0x13, 1}, /* MCLK=19.68Mhz */ 273 {19800000, 3072000, 0x1B, 0x80, 0x13, 1}, /* MCLK=19.8Mhz */ 274 /* for SLAVE mode with SRM */ 275 {11289600, 2822400, 0x0D, 0x47, 0x21, 0}, /* MCLK=11.2896Mhz */ 276 {12000000, 2822400, 0x0D, 0xFA, 0x1F, 0}, /* MCLK=12Mhz */ 277 {12288000, 2822400, 0x16, 0x66, 0x1E, 0}, /* MCLK=12.288Mhz */ 278 {13000000, 2822400, 0x00, 0x98, 0x1D, 0}, /* MCLK=13Mhz */ 279 {13500000, 2822400, 0x1E, 0x33, 0x1B, 0}, /* MCLK=13.5Mhz */ 280 {14400000, 2822400, 0x06, 0x50, 0x1A, 0}, /* MCLK=14.4Mhz */ 281 {19200000, 2822400, 0x14, 0xBC, 0x13, 0}, /* MCLK=19.2Mhz */ 282 {19680000, 2822400, 0x05, 0x66, 0x13, 0}, /* MCLK=19.68Mhz */ 283 {19800000, 2822400, 0x01, 0xAE, 0x13, 0}, /* MCLK=19.8Mhz */ 284 }; 285 286 enum clk_src { 287 DA9055_CLKSRC_MCLK 288 }; 289 290 /* Gain and Volume */ 291 292 static const unsigned int aux_vol_tlv[] = { 293 TLV_DB_RANGE_HEAD(2), 294 0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0), 295 /* -54dB to 15dB */ 296 0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0) 297 }; 298 299 static const unsigned int digital_gain_tlv[] = { 300 TLV_DB_RANGE_HEAD(2), 301 0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 302 /* -78dB to 12dB */ 303 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0) 304 }; 305 306 static const unsigned int alc_analog_gain_tlv[] = { 307 TLV_DB_RANGE_HEAD(2), 308 0x0, 0x0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 309 /* 0dB to 36dB */ 310 0x01, 0x07, TLV_DB_SCALE_ITEM(0, 600, 0) 311 }; 312 313 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0); 314 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0); 315 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0); 316 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0); 317 static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0); 318 static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0); 319 static const DECLARE_TLV_DB_SCALE(alc_gain_tlv, 0, 600, 0); 320 321 /* ADC and DAC high pass filter cutoff value */ 322 static const char * const da9055_hpf_cutoff_txt[] = { 323 "Fs/24000", "Fs/12000", "Fs/6000", "Fs/3000" 324 }; 325 326 static SOC_ENUM_SINGLE_DECL(da9055_dac_hpf_cutoff, 327 DA9055_DAC_FILTERS1, 4, da9055_hpf_cutoff_txt); 328 329 static SOC_ENUM_SINGLE_DECL(da9055_adc_hpf_cutoff, 330 DA9055_ADC_FILTERS1, 4, da9055_hpf_cutoff_txt); 331 332 /* ADC and DAC voice mode (8kHz) high pass cutoff value */ 333 static const char * const da9055_vf_cutoff_txt[] = { 334 "2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz" 335 }; 336 337 static SOC_ENUM_SINGLE_DECL(da9055_dac_vf_cutoff, 338 DA9055_DAC_FILTERS1, 0, da9055_vf_cutoff_txt); 339 340 static SOC_ENUM_SINGLE_DECL(da9055_adc_vf_cutoff, 341 DA9055_ADC_FILTERS1, 0, da9055_vf_cutoff_txt); 342 343 /* Gain ramping rate value */ 344 static const char * const da9055_gain_ramping_txt[] = { 345 "nominal rate", "nominal rate * 4", "nominal rate * 8", 346 "nominal rate / 8" 347 }; 348 349 static SOC_ENUM_SINGLE_DECL(da9055_gain_ramping_rate, 350 DA9055_GAIN_RAMP_CTRL, 0, da9055_gain_ramping_txt); 351 352 /* DAC noise gate setup time value */ 353 static const char * const da9055_dac_ng_setup_time_txt[] = { 354 "256 samples", "512 samples", "1024 samples", "2048 samples" 355 }; 356 357 static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_setup_time, 358 DA9055_DAC_NG_SETUP_TIME, 0, 359 da9055_dac_ng_setup_time_txt); 360 361 /* DAC noise gate rampup rate value */ 362 static const char * const da9055_dac_ng_rampup_txt[] = { 363 "0.02 ms/dB", "0.16 ms/dB" 364 }; 365 366 static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_rampup_rate, 367 DA9055_DAC_NG_SETUP_TIME, 2, 368 da9055_dac_ng_rampup_txt); 369 370 /* DAC noise gate rampdown rate value */ 371 static const char * const da9055_dac_ng_rampdown_txt[] = { 372 "0.64 ms/dB", "20.48 ms/dB" 373 }; 374 375 static SOC_ENUM_SINGLE_DECL(da9055_dac_ng_rampdown_rate, 376 DA9055_DAC_NG_SETUP_TIME, 3, 377 da9055_dac_ng_rampdown_txt); 378 379 /* DAC soft mute rate value */ 380 static const char * const da9055_dac_soft_mute_rate_txt[] = { 381 "1", "2", "4", "8", "16", "32", "64" 382 }; 383 384 static SOC_ENUM_SINGLE_DECL(da9055_dac_soft_mute_rate, 385 DA9055_DAC_FILTERS5, 4, 386 da9055_dac_soft_mute_rate_txt); 387 388 /* DAC routing select */ 389 static const char * const da9055_dac_src_txt[] = { 390 "ADC output left", "ADC output right", "AIF input left", 391 "AIF input right" 392 }; 393 394 static SOC_ENUM_SINGLE_DECL(da9055_dac_l_src, 395 DA9055_DIG_ROUTING_DAC, 0, da9055_dac_src_txt); 396 397 static SOC_ENUM_SINGLE_DECL(da9055_dac_r_src, 398 DA9055_DIG_ROUTING_DAC, 4, da9055_dac_src_txt); 399 400 /* MIC PGA Left source select */ 401 static const char * const da9055_mic_l_src_txt[] = { 402 "MIC1_P_N", "MIC1_P", "MIC1_N", "MIC2_L" 403 }; 404 405 static SOC_ENUM_SINGLE_DECL(da9055_mic_l_src, 406 DA9055_MIXIN_L_SELECT, 4, da9055_mic_l_src_txt); 407 408 /* MIC PGA Right source select */ 409 static const char * const da9055_mic_r_src_txt[] = { 410 "MIC2_R_L", "MIC2_R", "MIC2_L" 411 }; 412 413 static SOC_ENUM_SINGLE_DECL(da9055_mic_r_src, 414 DA9055_MIXIN_R_SELECT, 4, da9055_mic_r_src_txt); 415 416 /* ALC Input Signal Tracking rate select */ 417 static const char * const da9055_signal_tracking_rate_txt[] = { 418 "1/4", "1/16", "1/256", "1/65536" 419 }; 420 421 static SOC_ENUM_SINGLE_DECL(da9055_integ_attack_rate, 422 DA9055_ALC_CTRL3, 4, 423 da9055_signal_tracking_rate_txt); 424 425 static SOC_ENUM_SINGLE_DECL(da9055_integ_release_rate, 426 DA9055_ALC_CTRL3, 6, 427 da9055_signal_tracking_rate_txt); 428 429 /* ALC Attack Rate select */ 430 static const char * const da9055_attack_rate_txt[] = { 431 "44/fs", "88/fs", "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", 432 "5632/fs", "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs" 433 }; 434 435 static SOC_ENUM_SINGLE_DECL(da9055_attack_rate, 436 DA9055_ALC_CTRL2, 0, da9055_attack_rate_txt); 437 438 /* ALC Release Rate select */ 439 static const char * const da9055_release_rate_txt[] = { 440 "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", "5632/fs", 441 "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs" 442 }; 443 444 static SOC_ENUM_SINGLE_DECL(da9055_release_rate, 445 DA9055_ALC_CTRL2, 4, da9055_release_rate_txt); 446 447 /* ALC Hold Time select */ 448 static const char * const da9055_hold_time_txt[] = { 449 "62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs", 450 "7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs", 451 "253952/fs", "507904/fs", "1015808/fs", "2031616/fs" 452 }; 453 454 static SOC_ENUM_SINGLE_DECL(da9055_hold_time, 455 DA9055_ALC_CTRL3, 0, da9055_hold_time_txt); 456 457 static int da9055_get_alc_data(struct snd_soc_codec *codec, u8 reg_val) 458 { 459 int mid_data, top_data; 460 int sum = 0; 461 u8 iteration; 462 463 for (iteration = 0; iteration < DA9055_ALC_AVG_ITERATIONS; 464 iteration++) { 465 /* Select the left or right channel and capture data */ 466 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL, reg_val); 467 468 /* Select middle 8 bits for read back from data register */ 469 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL, 470 reg_val | DA9055_ALC_DATA_MIDDLE); 471 mid_data = snd_soc_read(codec, DA9055_ALC_CIC_OP_LVL_DATA); 472 473 /* Select top 8 bits for read back from data register */ 474 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL, 475 reg_val | DA9055_ALC_DATA_TOP); 476 top_data = snd_soc_read(codec, DA9055_ALC_CIC_OP_LVL_DATA); 477 478 sum += ((mid_data << 8) | (top_data << 16)); 479 } 480 481 return sum / DA9055_ALC_AVG_ITERATIONS; 482 } 483 484 static int da9055_put_alc_sw(struct snd_kcontrol *kcontrol, 485 struct snd_ctl_elem_value *ucontrol) 486 { 487 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); 488 u8 reg_val, adc_left, adc_right, mic_left, mic_right; 489 int avg_left_data, avg_right_data, offset_l, offset_r; 490 491 if (ucontrol->value.integer.value[0]) { 492 /* 493 * While enabling ALC (or ALC sync mode), calibration of the DC 494 * offsets must be done first 495 */ 496 497 /* Save current values from Mic control registers */ 498 mic_left = snd_soc_read(codec, DA9055_MIC_L_CTRL); 499 mic_right = snd_soc_read(codec, DA9055_MIC_R_CTRL); 500 501 /* Mute Mic PGA Left and Right */ 502 snd_soc_update_bits(codec, DA9055_MIC_L_CTRL, 503 DA9055_MIC_L_MUTE_EN, DA9055_MIC_L_MUTE_EN); 504 snd_soc_update_bits(codec, DA9055_MIC_R_CTRL, 505 DA9055_MIC_R_MUTE_EN, DA9055_MIC_R_MUTE_EN); 506 507 /* Save current values from ADC control registers */ 508 adc_left = snd_soc_read(codec, DA9055_ADC_L_CTRL); 509 adc_right = snd_soc_read(codec, DA9055_ADC_R_CTRL); 510 511 /* Enable ADC Left and Right */ 512 snd_soc_update_bits(codec, DA9055_ADC_L_CTRL, 513 DA9055_ADC_L_EN, DA9055_ADC_L_EN); 514 snd_soc_update_bits(codec, DA9055_ADC_R_CTRL, 515 DA9055_ADC_R_EN, DA9055_ADC_R_EN); 516 517 /* Calculate average for Left and Right data */ 518 /* Left Data */ 519 avg_left_data = da9055_get_alc_data(codec, 520 DA9055_ALC_CIC_OP_CHANNEL_LEFT); 521 /* Right Data */ 522 avg_right_data = da9055_get_alc_data(codec, 523 DA9055_ALC_CIC_OP_CHANNEL_RIGHT); 524 525 /* Calculate DC offset */ 526 offset_l = -avg_left_data; 527 offset_r = -avg_right_data; 528 529 reg_val = (offset_l & DA9055_ALC_OFFSET_15_8) >> 8; 530 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2M_L, reg_val); 531 reg_val = (offset_l & DA9055_ALC_OFFSET_17_16) >> 16; 532 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2U_L, reg_val); 533 534 reg_val = (offset_r & DA9055_ALC_OFFSET_15_8) >> 8; 535 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2M_R, reg_val); 536 reg_val = (offset_r & DA9055_ALC_OFFSET_17_16) >> 16; 537 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2U_R, reg_val); 538 539 /* Restore original values of ADC control registers */ 540 snd_soc_write(codec, DA9055_ADC_L_CTRL, adc_left); 541 snd_soc_write(codec, DA9055_ADC_R_CTRL, adc_right); 542 543 /* Restore original values of Mic control registers */ 544 snd_soc_write(codec, DA9055_MIC_L_CTRL, mic_left); 545 snd_soc_write(codec, DA9055_MIC_R_CTRL, mic_right); 546 } 547 548 return snd_soc_put_volsw(kcontrol, ucontrol); 549 } 550 551 static const struct snd_kcontrol_new da9055_snd_controls[] = { 552 553 /* Volume controls */ 554 SOC_DOUBLE_R_TLV("Mic Volume", 555 DA9055_MIC_L_GAIN, DA9055_MIC_R_GAIN, 556 0, 0x7, 0, mic_vol_tlv), 557 SOC_DOUBLE_R_TLV("Aux Volume", 558 DA9055_AUX_L_GAIN, DA9055_AUX_R_GAIN, 559 0, 0x3f, 0, aux_vol_tlv), 560 SOC_DOUBLE_R_TLV("Mixin PGA Volume", 561 DA9055_MIXIN_L_GAIN, DA9055_MIXIN_R_GAIN, 562 0, 0xf, 0, mixin_gain_tlv), 563 SOC_DOUBLE_R_TLV("ADC Volume", 564 DA9055_ADC_L_GAIN, DA9055_ADC_R_GAIN, 565 0, 0x7f, 0, digital_gain_tlv), 566 567 SOC_DOUBLE_R_TLV("DAC Volume", 568 DA9055_DAC_L_GAIN, DA9055_DAC_R_GAIN, 569 0, 0x7f, 0, digital_gain_tlv), 570 SOC_DOUBLE_R_TLV("Headphone Volume", 571 DA9055_HP_L_GAIN, DA9055_HP_R_GAIN, 572 0, 0x3f, 0, hp_vol_tlv), 573 SOC_SINGLE_TLV("Lineout Volume", DA9055_LINE_GAIN, 0, 0x3f, 0, 574 lineout_vol_tlv), 575 576 /* DAC Equalizer controls */ 577 SOC_SINGLE("DAC EQ Switch", DA9055_DAC_FILTERS4, 7, 1, 0), 578 SOC_SINGLE_TLV("DAC EQ1 Volume", DA9055_DAC_FILTERS2, 0, 0xf, 0, 579 eq_gain_tlv), 580 SOC_SINGLE_TLV("DAC EQ2 Volume", DA9055_DAC_FILTERS2, 4, 0xf, 0, 581 eq_gain_tlv), 582 SOC_SINGLE_TLV("DAC EQ3 Volume", DA9055_DAC_FILTERS3, 0, 0xf, 0, 583 eq_gain_tlv), 584 SOC_SINGLE_TLV("DAC EQ4 Volume", DA9055_DAC_FILTERS3, 4, 0xf, 0, 585 eq_gain_tlv), 586 SOC_SINGLE_TLV("DAC EQ5 Volume", DA9055_DAC_FILTERS4, 0, 0xf, 0, 587 eq_gain_tlv), 588 589 /* High Pass Filter and Voice Mode controls */ 590 SOC_SINGLE("ADC HPF Switch", DA9055_ADC_FILTERS1, 7, 1, 0), 591 SOC_ENUM("ADC HPF Cutoff", da9055_adc_hpf_cutoff), 592 SOC_SINGLE("ADC Voice Mode Switch", DA9055_ADC_FILTERS1, 3, 1, 0), 593 SOC_ENUM("ADC Voice Cutoff", da9055_adc_vf_cutoff), 594 595 SOC_SINGLE("DAC HPF Switch", DA9055_DAC_FILTERS1, 7, 1, 0), 596 SOC_ENUM("DAC HPF Cutoff", da9055_dac_hpf_cutoff), 597 SOC_SINGLE("DAC Voice Mode Switch", DA9055_DAC_FILTERS1, 3, 1, 0), 598 SOC_ENUM("DAC Voice Cutoff", da9055_dac_vf_cutoff), 599 600 /* Mute controls */ 601 SOC_DOUBLE_R("Mic Switch", DA9055_MIC_L_CTRL, 602 DA9055_MIC_R_CTRL, 6, 1, 0), 603 SOC_DOUBLE_R("Aux Switch", DA9055_AUX_L_CTRL, 604 DA9055_AUX_R_CTRL, 6, 1, 0), 605 SOC_DOUBLE_R("Mixin PGA Switch", DA9055_MIXIN_L_CTRL, 606 DA9055_MIXIN_R_CTRL, 6, 1, 0), 607 SOC_DOUBLE_R("ADC Switch", DA9055_ADC_L_CTRL, 608 DA9055_ADC_R_CTRL, 6, 1, 0), 609 SOC_DOUBLE_R("Headphone Switch", DA9055_HP_L_CTRL, 610 DA9055_HP_R_CTRL, 6, 1, 0), 611 SOC_SINGLE("Lineout Switch", DA9055_LINE_CTRL, 6, 1, 0), 612 SOC_SINGLE("DAC Soft Mute Switch", DA9055_DAC_FILTERS5, 7, 1, 0), 613 SOC_ENUM("DAC Soft Mute Rate", da9055_dac_soft_mute_rate), 614 615 /* Zero Cross controls */ 616 SOC_DOUBLE_R("Aux ZC Switch", DA9055_AUX_L_CTRL, 617 DA9055_AUX_R_CTRL, 4, 1, 0), 618 SOC_DOUBLE_R("Mixin PGA ZC Switch", DA9055_MIXIN_L_CTRL, 619 DA9055_MIXIN_R_CTRL, 4, 1, 0), 620 SOC_DOUBLE_R("Headphone ZC Switch", DA9055_HP_L_CTRL, 621 DA9055_HP_R_CTRL, 4, 1, 0), 622 SOC_SINGLE("Lineout ZC Switch", DA9055_LINE_CTRL, 4, 1, 0), 623 624 /* Gain Ramping controls */ 625 SOC_DOUBLE_R("Aux Gain Ramping Switch", DA9055_AUX_L_CTRL, 626 DA9055_AUX_R_CTRL, 5, 1, 0), 627 SOC_DOUBLE_R("Mixin Gain Ramping Switch", DA9055_MIXIN_L_CTRL, 628 DA9055_MIXIN_R_CTRL, 5, 1, 0), 629 SOC_DOUBLE_R("ADC Gain Ramping Switch", DA9055_ADC_L_CTRL, 630 DA9055_ADC_R_CTRL, 5, 1, 0), 631 SOC_DOUBLE_R("DAC Gain Ramping Switch", DA9055_DAC_L_CTRL, 632 DA9055_DAC_R_CTRL, 5, 1, 0), 633 SOC_DOUBLE_R("Headphone Gain Ramping Switch", DA9055_HP_L_CTRL, 634 DA9055_HP_R_CTRL, 5, 1, 0), 635 SOC_SINGLE("Lineout Gain Ramping Switch", DA9055_LINE_CTRL, 5, 1, 0), 636 SOC_ENUM("Gain Ramping Rate", da9055_gain_ramping_rate), 637 638 /* DAC Noise Gate controls */ 639 SOC_SINGLE("DAC NG Switch", DA9055_DAC_NG_CTRL, 7, 1, 0), 640 SOC_SINGLE("DAC NG ON Threshold", DA9055_DAC_NG_ON_THRESHOLD, 641 0, 0x7, 0), 642 SOC_SINGLE("DAC NG OFF Threshold", DA9055_DAC_NG_OFF_THRESHOLD, 643 0, 0x7, 0), 644 SOC_ENUM("DAC NG Setup Time", da9055_dac_ng_setup_time), 645 SOC_ENUM("DAC NG Rampup Rate", da9055_dac_ng_rampup_rate), 646 SOC_ENUM("DAC NG Rampdown Rate", da9055_dac_ng_rampdown_rate), 647 648 /* DAC Invertion control */ 649 SOC_SINGLE("DAC Left Invert", DA9055_DIG_CTRL, 3, 1, 0), 650 SOC_SINGLE("DAC Right Invert", DA9055_DIG_CTRL, 7, 1, 0), 651 652 /* DMIC controls */ 653 SOC_DOUBLE_R("DMIC Switch", DA9055_MIXIN_L_SELECT, 654 DA9055_MIXIN_R_SELECT, 7, 1, 0), 655 656 /* ALC Controls */ 657 SOC_DOUBLE_EXT("ALC Switch", DA9055_ALC_CTRL1, 3, 7, 1, 0, 658 snd_soc_get_volsw, da9055_put_alc_sw), 659 SOC_SINGLE_EXT("ALC Sync Mode Switch", DA9055_ALC_CTRL1, 1, 1, 0, 660 snd_soc_get_volsw, da9055_put_alc_sw), 661 SOC_SINGLE("ALC Offset Switch", DA9055_ALC_CTRL1, 0, 1, 0), 662 SOC_SINGLE("ALC Anticlip Mode Switch", DA9055_ALC_ANTICLIP_CTRL, 663 7, 1, 0), 664 SOC_SINGLE("ALC Anticlip Level", DA9055_ALC_ANTICLIP_LEVEL, 665 0, 0x7f, 0), 666 SOC_SINGLE_TLV("ALC Min Threshold Volume", DA9055_ALC_TARGET_MIN, 667 0, 0x3f, 1, alc_threshold_tlv), 668 SOC_SINGLE_TLV("ALC Max Threshold Volume", DA9055_ALC_TARGET_MAX, 669 0, 0x3f, 1, alc_threshold_tlv), 670 SOC_SINGLE_TLV("ALC Noise Threshold Volume", DA9055_ALC_NOISE, 671 0, 0x3f, 1, alc_threshold_tlv), 672 SOC_SINGLE_TLV("ALC Max Gain Volume", DA9055_ALC_GAIN_LIMITS, 673 4, 0xf, 0, alc_gain_tlv), 674 SOC_SINGLE_TLV("ALC Max Attenuation Volume", DA9055_ALC_GAIN_LIMITS, 675 0, 0xf, 0, alc_gain_tlv), 676 SOC_SINGLE_TLV("ALC Min Analog Gain Volume", 677 DA9055_ALC_ANA_GAIN_LIMITS, 678 0, 0x7, 0, alc_analog_gain_tlv), 679 SOC_SINGLE_TLV("ALC Max Analog Gain Volume", 680 DA9055_ALC_ANA_GAIN_LIMITS, 681 4, 0x7, 0, alc_analog_gain_tlv), 682 SOC_ENUM("ALC Attack Rate", da9055_attack_rate), 683 SOC_ENUM("ALC Release Rate", da9055_release_rate), 684 SOC_ENUM("ALC Hold Time", da9055_hold_time), 685 /* 686 * Rate at which input signal envelope is tracked as the signal gets 687 * larger 688 */ 689 SOC_ENUM("ALC Integ Attack Rate", da9055_integ_attack_rate), 690 /* 691 * Rate at which input signal envelope is tracked as the signal gets 692 * smaller 693 */ 694 SOC_ENUM("ALC Integ Release Rate", da9055_integ_release_rate), 695 }; 696 697 /* DAPM Controls */ 698 699 /* Mic PGA Left Source */ 700 static const struct snd_kcontrol_new da9055_mic_l_mux_controls = 701 SOC_DAPM_ENUM("Route", da9055_mic_l_src); 702 703 /* Mic PGA Right Source */ 704 static const struct snd_kcontrol_new da9055_mic_r_mux_controls = 705 SOC_DAPM_ENUM("Route", da9055_mic_r_src); 706 707 /* In Mixer Left */ 708 static const struct snd_kcontrol_new da9055_dapm_mixinl_controls[] = { 709 SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXIN_L_SELECT, 0, 1, 0), 710 SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_L_SELECT, 1, 1, 0), 711 SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_L_SELECT, 2, 1, 0), 712 }; 713 714 /* In Mixer Right */ 715 static const struct snd_kcontrol_new da9055_dapm_mixinr_controls[] = { 716 SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXIN_R_SELECT, 0, 1, 0), 717 SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_R_SELECT, 1, 1, 0), 718 SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_R_SELECT, 2, 1, 0), 719 SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXIN_R_SELECT, 3, 1, 0), 720 }; 721 722 /* DAC Left Source */ 723 static const struct snd_kcontrol_new da9055_dac_l_mux_controls = 724 SOC_DAPM_ENUM("Route", da9055_dac_l_src); 725 726 /* DAC Right Source */ 727 static const struct snd_kcontrol_new da9055_dac_r_mux_controls = 728 SOC_DAPM_ENUM("Route", da9055_dac_r_src); 729 730 /* Out Mixer Left */ 731 static const struct snd_kcontrol_new da9055_dapm_mixoutl_controls[] = { 732 SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXOUT_L_SELECT, 0, 1, 0), 733 SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_L_SELECT, 1, 1, 0), 734 SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_L_SELECT, 2, 1, 0), 735 SOC_DAPM_SINGLE("DAC Left Switch", DA9055_MIXOUT_L_SELECT, 3, 1, 0), 736 SOC_DAPM_SINGLE("Aux Left Invert Switch", DA9055_MIXOUT_L_SELECT, 737 4, 1, 0), 738 SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_L_SELECT, 739 5, 1, 0), 740 SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_L_SELECT, 741 6, 1, 0), 742 }; 743 744 /* Out Mixer Right */ 745 static const struct snd_kcontrol_new da9055_dapm_mixoutr_controls[] = { 746 SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXOUT_R_SELECT, 0, 1, 0), 747 SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_R_SELECT, 1, 1, 0), 748 SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_R_SELECT, 2, 1, 0), 749 SOC_DAPM_SINGLE("DAC Right Switch", DA9055_MIXOUT_R_SELECT, 3, 1, 0), 750 SOC_DAPM_SINGLE("Aux Right Invert Switch", DA9055_MIXOUT_R_SELECT, 751 4, 1, 0), 752 SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_R_SELECT, 753 5, 1, 0), 754 SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_R_SELECT, 755 6, 1, 0), 756 }; 757 758 /* Headphone Output Enable */ 759 static const struct snd_kcontrol_new da9055_dapm_hp_l_control = 760 SOC_DAPM_SINGLE("Switch", DA9055_HP_L_CTRL, 3, 1, 0); 761 762 static const struct snd_kcontrol_new da9055_dapm_hp_r_control = 763 SOC_DAPM_SINGLE("Switch", DA9055_HP_R_CTRL, 3, 1, 0); 764 765 /* Lineout Output Enable */ 766 static const struct snd_kcontrol_new da9055_dapm_lineout_control = 767 SOC_DAPM_SINGLE("Switch", DA9055_LINE_CTRL, 3, 1, 0); 768 769 /* DAPM widgets */ 770 static const struct snd_soc_dapm_widget da9055_dapm_widgets[] = { 771 /* Input Side */ 772 773 /* Input Lines */ 774 SND_SOC_DAPM_INPUT("MIC1"), 775 SND_SOC_DAPM_INPUT("MIC2"), 776 SND_SOC_DAPM_INPUT("AUXL"), 777 SND_SOC_DAPM_INPUT("AUXR"), 778 779 /* MUXs for Mic PGA source selection */ 780 SND_SOC_DAPM_MUX("Mic Left Source", SND_SOC_NOPM, 0, 0, 781 &da9055_mic_l_mux_controls), 782 SND_SOC_DAPM_MUX("Mic Right Source", SND_SOC_NOPM, 0, 0, 783 &da9055_mic_r_mux_controls), 784 785 /* Input PGAs */ 786 SND_SOC_DAPM_PGA("Mic Left", DA9055_MIC_L_CTRL, 7, 0, NULL, 0), 787 SND_SOC_DAPM_PGA("Mic Right", DA9055_MIC_R_CTRL, 7, 0, NULL, 0), 788 SND_SOC_DAPM_PGA("Aux Left", DA9055_AUX_L_CTRL, 7, 0, NULL, 0), 789 SND_SOC_DAPM_PGA("Aux Right", DA9055_AUX_R_CTRL, 7, 0, NULL, 0), 790 SND_SOC_DAPM_PGA("MIXIN Left", DA9055_MIXIN_L_CTRL, 7, 0, NULL, 0), 791 SND_SOC_DAPM_PGA("MIXIN Right", DA9055_MIXIN_R_CTRL, 7, 0, NULL, 0), 792 793 SND_SOC_DAPM_SUPPLY("Mic Bias", DA9055_MIC_BIAS_CTRL, 7, 0, NULL, 0), 794 SND_SOC_DAPM_SUPPLY("AIF", DA9055_AIF_CTRL, 7, 0, NULL, 0), 795 SND_SOC_DAPM_SUPPLY("Charge Pump", DA9055_CP_CTRL, 7, 0, NULL, 0), 796 797 /* Input Mixers */ 798 SND_SOC_DAPM_MIXER("In Mixer Left", SND_SOC_NOPM, 0, 0, 799 &da9055_dapm_mixinl_controls[0], 800 ARRAY_SIZE(da9055_dapm_mixinl_controls)), 801 SND_SOC_DAPM_MIXER("In Mixer Right", SND_SOC_NOPM, 0, 0, 802 &da9055_dapm_mixinr_controls[0], 803 ARRAY_SIZE(da9055_dapm_mixinr_controls)), 804 805 /* ADCs */ 806 SND_SOC_DAPM_ADC("ADC Left", "Capture", DA9055_ADC_L_CTRL, 7, 0), 807 SND_SOC_DAPM_ADC("ADC Right", "Capture", DA9055_ADC_R_CTRL, 7, 0), 808 809 /* Output Side */ 810 811 /* MUXs for DAC source selection */ 812 SND_SOC_DAPM_MUX("DAC Left Source", SND_SOC_NOPM, 0, 0, 813 &da9055_dac_l_mux_controls), 814 SND_SOC_DAPM_MUX("DAC Right Source", SND_SOC_NOPM, 0, 0, 815 &da9055_dac_r_mux_controls), 816 817 /* AIF input */ 818 SND_SOC_DAPM_AIF_IN("AIFIN Left", "Playback", 0, SND_SOC_NOPM, 0, 0), 819 SND_SOC_DAPM_AIF_IN("AIFIN Right", "Playback", 0, SND_SOC_NOPM, 0, 0), 820 821 /* DACs */ 822 SND_SOC_DAPM_DAC("DAC Left", "Playback", DA9055_DAC_L_CTRL, 7, 0), 823 SND_SOC_DAPM_DAC("DAC Right", "Playback", DA9055_DAC_R_CTRL, 7, 0), 824 825 /* Output Mixers */ 826 SND_SOC_DAPM_MIXER("Out Mixer Left", SND_SOC_NOPM, 0, 0, 827 &da9055_dapm_mixoutl_controls[0], 828 ARRAY_SIZE(da9055_dapm_mixoutl_controls)), 829 SND_SOC_DAPM_MIXER("Out Mixer Right", SND_SOC_NOPM, 0, 0, 830 &da9055_dapm_mixoutr_controls[0], 831 ARRAY_SIZE(da9055_dapm_mixoutr_controls)), 832 833 /* Output Enable Switches */ 834 SND_SOC_DAPM_SWITCH("Headphone Left Enable", SND_SOC_NOPM, 0, 0, 835 &da9055_dapm_hp_l_control), 836 SND_SOC_DAPM_SWITCH("Headphone Right Enable", SND_SOC_NOPM, 0, 0, 837 &da9055_dapm_hp_r_control), 838 SND_SOC_DAPM_SWITCH("Lineout Enable", SND_SOC_NOPM, 0, 0, 839 &da9055_dapm_lineout_control), 840 841 /* Output PGAs */ 842 SND_SOC_DAPM_PGA("MIXOUT Left", DA9055_MIXOUT_L_CTRL, 7, 0, NULL, 0), 843 SND_SOC_DAPM_PGA("MIXOUT Right", DA9055_MIXOUT_R_CTRL, 7, 0, NULL, 0), 844 SND_SOC_DAPM_PGA("Lineout", DA9055_LINE_CTRL, 7, 0, NULL, 0), 845 SND_SOC_DAPM_PGA("Headphone Left", DA9055_HP_L_CTRL, 7, 0, NULL, 0), 846 SND_SOC_DAPM_PGA("Headphone Right", DA9055_HP_R_CTRL, 7, 0, NULL, 0), 847 848 /* Output Lines */ 849 SND_SOC_DAPM_OUTPUT("HPL"), 850 SND_SOC_DAPM_OUTPUT("HPR"), 851 SND_SOC_DAPM_OUTPUT("LINE"), 852 }; 853 854 /* DAPM audio route definition */ 855 static const struct snd_soc_dapm_route da9055_audio_map[] = { 856 /* Dest Connecting Widget source */ 857 858 /* Input path */ 859 {"Mic Left Source", "MIC1_P_N", "MIC1"}, 860 {"Mic Left Source", "MIC1_P", "MIC1"}, 861 {"Mic Left Source", "MIC1_N", "MIC1"}, 862 {"Mic Left Source", "MIC2_L", "MIC2"}, 863 864 {"Mic Right Source", "MIC2_R_L", "MIC2"}, 865 {"Mic Right Source", "MIC2_R", "MIC2"}, 866 {"Mic Right Source", "MIC2_L", "MIC2"}, 867 868 {"Mic Left", NULL, "Mic Left Source"}, 869 {"Mic Right", NULL, "Mic Right Source"}, 870 871 {"Aux Left", NULL, "AUXL"}, 872 {"Aux Right", NULL, "AUXR"}, 873 874 {"In Mixer Left", "Mic Left Switch", "Mic Left"}, 875 {"In Mixer Left", "Mic Right Switch", "Mic Right"}, 876 {"In Mixer Left", "Aux Left Switch", "Aux Left"}, 877 878 {"In Mixer Right", "Mic Right Switch", "Mic Right"}, 879 {"In Mixer Right", "Mic Left Switch", "Mic Left"}, 880 {"In Mixer Right", "Aux Right Switch", "Aux Right"}, 881 {"In Mixer Right", "Mixin Left Switch", "MIXIN Left"}, 882 883 {"MIXIN Left", NULL, "In Mixer Left"}, 884 {"ADC Left", NULL, "MIXIN Left"}, 885 886 {"MIXIN Right", NULL, "In Mixer Right"}, 887 {"ADC Right", NULL, "MIXIN Right"}, 888 889 {"ADC Left", NULL, "AIF"}, 890 {"ADC Right", NULL, "AIF"}, 891 892 /* Output path */ 893 {"AIFIN Left", NULL, "AIF"}, 894 {"AIFIN Right", NULL, "AIF"}, 895 896 {"DAC Left Source", "ADC output left", "ADC Left"}, 897 {"DAC Left Source", "ADC output right", "ADC Right"}, 898 {"DAC Left Source", "AIF input left", "AIFIN Left"}, 899 {"DAC Left Source", "AIF input right", "AIFIN Right"}, 900 901 {"DAC Right Source", "ADC output left", "ADC Left"}, 902 {"DAC Right Source", "ADC output right", "ADC Right"}, 903 {"DAC Right Source", "AIF input left", "AIFIN Left"}, 904 {"DAC Right Source", "AIF input right", "AIFIN Right"}, 905 906 {"DAC Left", NULL, "DAC Left Source"}, 907 {"DAC Right", NULL, "DAC Right Source"}, 908 909 {"Out Mixer Left", "Aux Left Switch", "Aux Left"}, 910 {"Out Mixer Left", "Mixin Left Switch", "MIXIN Left"}, 911 {"Out Mixer Left", "Mixin Right Switch", "MIXIN Right"}, 912 {"Out Mixer Left", "Aux Left Invert Switch", "Aux Left"}, 913 {"Out Mixer Left", "Mixin Left Invert Switch", "MIXIN Left"}, 914 {"Out Mixer Left", "Mixin Right Invert Switch", "MIXIN Right"}, 915 {"Out Mixer Left", "DAC Left Switch", "DAC Left"}, 916 917 {"Out Mixer Right", "Aux Right Switch", "Aux Right"}, 918 {"Out Mixer Right", "Mixin Right Switch", "MIXIN Right"}, 919 {"Out Mixer Right", "Mixin Left Switch", "MIXIN Left"}, 920 {"Out Mixer Right", "Aux Right Invert Switch", "Aux Right"}, 921 {"Out Mixer Right", "Mixin Right Invert Switch", "MIXIN Right"}, 922 {"Out Mixer Right", "Mixin Left Invert Switch", "MIXIN Left"}, 923 {"Out Mixer Right", "DAC Right Switch", "DAC Right"}, 924 925 {"MIXOUT Left", NULL, "Out Mixer Left"}, 926 {"Headphone Left Enable", "Switch", "MIXOUT Left"}, 927 {"Headphone Left", NULL, "Headphone Left Enable"}, 928 {"Headphone Left", NULL, "Charge Pump"}, 929 {"HPL", NULL, "Headphone Left"}, 930 931 {"MIXOUT Right", NULL, "Out Mixer Right"}, 932 {"Headphone Right Enable", "Switch", "MIXOUT Right"}, 933 {"Headphone Right", NULL, "Headphone Right Enable"}, 934 {"Headphone Right", NULL, "Charge Pump"}, 935 {"HPR", NULL, "Headphone Right"}, 936 937 {"MIXOUT Right", NULL, "Out Mixer Right"}, 938 {"Lineout Enable", "Switch", "MIXOUT Right"}, 939 {"Lineout", NULL, "Lineout Enable"}, 940 {"LINE", NULL, "Lineout"}, 941 }; 942 943 /* Codec private data */ 944 struct da9055_priv { 945 struct regmap *regmap; 946 unsigned int mclk_rate; 947 int master; 948 struct da9055_platform_data *pdata; 949 }; 950 951 static struct reg_default da9055_reg_defaults[] = { 952 { 0x21, 0x10 }, 953 { 0x22, 0x0A }, 954 { 0x23, 0x00 }, 955 { 0x24, 0x00 }, 956 { 0x25, 0x00 }, 957 { 0x26, 0x00 }, 958 { 0x27, 0x0C }, 959 { 0x28, 0x01 }, 960 { 0x29, 0x08 }, 961 { 0x2A, 0x32 }, 962 { 0x2B, 0x00 }, 963 { 0x30, 0x35 }, 964 { 0x31, 0x35 }, 965 { 0x32, 0x00 }, 966 { 0x33, 0x00 }, 967 { 0x34, 0x03 }, 968 { 0x35, 0x03 }, 969 { 0x36, 0x6F }, 970 { 0x37, 0x6F }, 971 { 0x38, 0x80 }, 972 { 0x39, 0x01 }, 973 { 0x3A, 0x01 }, 974 { 0x40, 0x00 }, 975 { 0x41, 0x88 }, 976 { 0x42, 0x88 }, 977 { 0x43, 0x08 }, 978 { 0x44, 0x80 }, 979 { 0x45, 0x6F }, 980 { 0x46, 0x6F }, 981 { 0x47, 0x61 }, 982 { 0x48, 0x35 }, 983 { 0x49, 0x35 }, 984 { 0x4A, 0x35 }, 985 { 0x4B, 0x00 }, 986 { 0x4C, 0x00 }, 987 { 0x60, 0x44 }, 988 { 0x61, 0x44 }, 989 { 0x62, 0x00 }, 990 { 0x63, 0x40 }, 991 { 0x64, 0x40 }, 992 { 0x65, 0x40 }, 993 { 0x66, 0x40 }, 994 { 0x67, 0x40 }, 995 { 0x68, 0x40 }, 996 { 0x69, 0x48 }, 997 { 0x6A, 0x40 }, 998 { 0x6B, 0x41 }, 999 { 0x6C, 0x40 }, 1000 { 0x6D, 0x40 }, 1001 { 0x6E, 0x10 }, 1002 { 0x6F, 0x10 }, 1003 { 0x90, 0x80 }, 1004 { 0x92, 0x02 }, 1005 { 0x93, 0x00 }, 1006 { 0x99, 0x00 }, 1007 { 0x9A, 0x00 }, 1008 { 0x9B, 0x00 }, 1009 { 0x9C, 0x3F }, 1010 { 0x9D, 0x00 }, 1011 { 0x9E, 0x3F }, 1012 { 0x9F, 0xFF }, 1013 { 0xA0, 0x71 }, 1014 { 0xA1, 0x00 }, 1015 { 0xA2, 0x00 }, 1016 { 0xA6, 0x00 }, 1017 { 0xA7, 0x00 }, 1018 { 0xAB, 0x00 }, 1019 { 0xAC, 0x00 }, 1020 { 0xAD, 0x00 }, 1021 { 0xAF, 0x08 }, 1022 { 0xB0, 0x00 }, 1023 { 0xB1, 0x00 }, 1024 { 0xB2, 0x00 }, 1025 }; 1026 1027 static bool da9055_volatile_register(struct device *dev, 1028 unsigned int reg) 1029 { 1030 switch (reg) { 1031 case DA9055_STATUS1: 1032 case DA9055_PLL_STATUS: 1033 case DA9055_AUX_L_GAIN_STATUS: 1034 case DA9055_AUX_R_GAIN_STATUS: 1035 case DA9055_MIC_L_GAIN_STATUS: 1036 case DA9055_MIC_R_GAIN_STATUS: 1037 case DA9055_MIXIN_L_GAIN_STATUS: 1038 case DA9055_MIXIN_R_GAIN_STATUS: 1039 case DA9055_ADC_L_GAIN_STATUS: 1040 case DA9055_ADC_R_GAIN_STATUS: 1041 case DA9055_DAC_L_GAIN_STATUS: 1042 case DA9055_DAC_R_GAIN_STATUS: 1043 case DA9055_HP_L_GAIN_STATUS: 1044 case DA9055_HP_R_GAIN_STATUS: 1045 case DA9055_LINE_GAIN_STATUS: 1046 case DA9055_ALC_CIC_OP_LVL_DATA: 1047 return 1; 1048 default: 1049 return 0; 1050 } 1051 } 1052 1053 /* Set DAI word length */ 1054 static int da9055_hw_params(struct snd_pcm_substream *substream, 1055 struct snd_pcm_hw_params *params, 1056 struct snd_soc_dai *dai) 1057 { 1058 struct snd_soc_codec *codec = dai->codec; 1059 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec); 1060 u8 aif_ctrl, fs; 1061 u32 sysclk; 1062 1063 switch (params_width(params)) { 1064 case 16: 1065 aif_ctrl = DA9055_AIF_WORD_S16_LE; 1066 break; 1067 case 20: 1068 aif_ctrl = DA9055_AIF_WORD_S20_3LE; 1069 break; 1070 case 24: 1071 aif_ctrl = DA9055_AIF_WORD_S24_LE; 1072 break; 1073 case 32: 1074 aif_ctrl = DA9055_AIF_WORD_S32_LE; 1075 break; 1076 default: 1077 return -EINVAL; 1078 } 1079 1080 /* Set AIF format */ 1081 snd_soc_update_bits(codec, DA9055_AIF_CTRL, DA9055_AIF_WORD_LENGTH_MASK, 1082 aif_ctrl); 1083 1084 switch (params_rate(params)) { 1085 case 8000: 1086 fs = DA9055_SR_8000; 1087 sysclk = 3072000; 1088 break; 1089 case 11025: 1090 fs = DA9055_SR_11025; 1091 sysclk = 2822400; 1092 break; 1093 case 12000: 1094 fs = DA9055_SR_12000; 1095 sysclk = 3072000; 1096 break; 1097 case 16000: 1098 fs = DA9055_SR_16000; 1099 sysclk = 3072000; 1100 break; 1101 case 22050: 1102 fs = DA9055_SR_22050; 1103 sysclk = 2822400; 1104 break; 1105 case 32000: 1106 fs = DA9055_SR_32000; 1107 sysclk = 3072000; 1108 break; 1109 case 44100: 1110 fs = DA9055_SR_44100; 1111 sysclk = 2822400; 1112 break; 1113 case 48000: 1114 fs = DA9055_SR_48000; 1115 sysclk = 3072000; 1116 break; 1117 case 88200: 1118 fs = DA9055_SR_88200; 1119 sysclk = 2822400; 1120 break; 1121 case 96000: 1122 fs = DA9055_SR_96000; 1123 sysclk = 3072000; 1124 break; 1125 default: 1126 return -EINVAL; 1127 } 1128 1129 if (da9055->mclk_rate) { 1130 /* PLL Mode, Write actual FS */ 1131 snd_soc_write(codec, DA9055_SR, fs); 1132 } else { 1133 /* 1134 * Non-PLL Mode 1135 * When PLL is bypassed, chip assumes constant MCLK of 1136 * 12.288MHz and uses sample rate value to divide this MCLK 1137 * to derive its sys clk. As sys clk has to be 256 * Fs, we 1138 * need to write constant sample rate i.e. 48KHz. 1139 */ 1140 snd_soc_write(codec, DA9055_SR, DA9055_SR_48000); 1141 } 1142 1143 if (da9055->mclk_rate && (da9055->mclk_rate != sysclk)) { 1144 /* PLL Mode */ 1145 if (!da9055->master) { 1146 /* PLL slave mode, enable PLL and also SRM */ 1147 snd_soc_update_bits(codec, DA9055_PLL_CTRL, 1148 DA9055_PLL_EN | DA9055_PLL_SRM_EN, 1149 DA9055_PLL_EN | DA9055_PLL_SRM_EN); 1150 } else { 1151 /* PLL master mode, only enable PLL */ 1152 snd_soc_update_bits(codec, DA9055_PLL_CTRL, 1153 DA9055_PLL_EN, DA9055_PLL_EN); 1154 } 1155 } else { 1156 /* Non PLL Mode, disable PLL */ 1157 snd_soc_update_bits(codec, DA9055_PLL_CTRL, DA9055_PLL_EN, 0); 1158 } 1159 1160 return 0; 1161 } 1162 1163 /* Set DAI mode and Format */ 1164 static int da9055_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1165 { 1166 struct snd_soc_codec *codec = codec_dai->codec; 1167 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec); 1168 u8 aif_clk_mode, aif_ctrl, mode; 1169 1170 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1171 case SND_SOC_DAIFMT_CBM_CFM: 1172 /* DA9055 in I2S Master Mode */ 1173 mode = 1; 1174 aif_clk_mode = DA9055_AIF_CLK_EN_MASTER_MODE; 1175 break; 1176 case SND_SOC_DAIFMT_CBS_CFS: 1177 /* DA9055 in I2S Slave Mode */ 1178 mode = 0; 1179 aif_clk_mode = DA9055_AIF_CLK_EN_SLAVE_MODE; 1180 break; 1181 default: 1182 return -EINVAL; 1183 } 1184 1185 /* Don't allow change of mode if PLL is enabled */ 1186 if ((snd_soc_read(codec, DA9055_PLL_CTRL) & DA9055_PLL_EN) && 1187 (da9055->master != mode)) 1188 return -EINVAL; 1189 1190 da9055->master = mode; 1191 1192 /* Only I2S is supported */ 1193 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1194 case SND_SOC_DAIFMT_I2S: 1195 aif_ctrl = DA9055_AIF_FORMAT_I2S_MODE; 1196 break; 1197 case SND_SOC_DAIFMT_LEFT_J: 1198 aif_ctrl = DA9055_AIF_FORMAT_LEFT_J; 1199 break; 1200 case SND_SOC_DAIFMT_RIGHT_J: 1201 aif_ctrl = DA9055_AIF_FORMAT_RIGHT_J; 1202 break; 1203 case SND_SOC_DAIFMT_DSP_A: 1204 aif_ctrl = DA9055_AIF_FORMAT_DSP; 1205 break; 1206 default: 1207 return -EINVAL; 1208 } 1209 1210 /* By default only 32 BCLK per WCLK is supported */ 1211 aif_clk_mode |= DA9055_AIF_BCLKS_PER_WCLK_32; 1212 1213 snd_soc_update_bits(codec, DA9055_AIF_CLK_MODE, 1214 (DA9055_AIF_CLK_MODE_MASK | DA9055_AIF_BCLK_MASK), 1215 aif_clk_mode); 1216 snd_soc_update_bits(codec, DA9055_AIF_CTRL, DA9055_AIF_FORMAT_MASK, 1217 aif_ctrl); 1218 return 0; 1219 } 1220 1221 static int da9055_mute(struct snd_soc_dai *dai, int mute) 1222 { 1223 struct snd_soc_codec *codec = dai->codec; 1224 1225 if (mute) { 1226 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL, 1227 DA9055_DAC_L_MUTE_EN, DA9055_DAC_L_MUTE_EN); 1228 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL, 1229 DA9055_DAC_R_MUTE_EN, DA9055_DAC_R_MUTE_EN); 1230 } else { 1231 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL, 1232 DA9055_DAC_L_MUTE_EN, 0); 1233 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL, 1234 DA9055_DAC_R_MUTE_EN, 0); 1235 } 1236 1237 return 0; 1238 } 1239 1240 #define DA9055_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1241 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1242 1243 static int da9055_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1244 int clk_id, unsigned int freq, int dir) 1245 { 1246 struct snd_soc_codec *codec = codec_dai->codec; 1247 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec); 1248 1249 switch (clk_id) { 1250 case DA9055_CLKSRC_MCLK: 1251 switch (freq) { 1252 case 11289600: 1253 case 12000000: 1254 case 12288000: 1255 case 13000000: 1256 case 13500000: 1257 case 14400000: 1258 case 19200000: 1259 case 19680000: 1260 case 19800000: 1261 da9055->mclk_rate = freq; 1262 return 0; 1263 default: 1264 dev_err(codec_dai->dev, "Unsupported MCLK value %d\n", 1265 freq); 1266 return -EINVAL; 1267 } 1268 break; 1269 default: 1270 dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id); 1271 return -EINVAL; 1272 } 1273 } 1274 1275 /* 1276 * da9055_set_dai_pll : Configure the codec PLL 1277 * @param codec_dai : Pointer to codec DAI 1278 * @param pll_id : da9055 has only one pll, so pll_id is always zero 1279 * @param fref : Input MCLK frequency 1280 * @param fout : FsDM value 1281 * @return int : Zero for success, negative error code for error 1282 * 1283 * Note: Supported PLL input frequencies are 11.2896MHz, 12MHz, 12.288MHz, 1284 * 13MHz, 13.5MHz, 14.4MHz, 19.2MHz, 19.6MHz and 19.8MHz 1285 */ 1286 static int da9055_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, 1287 int source, unsigned int fref, unsigned int fout) 1288 { 1289 struct snd_soc_codec *codec = codec_dai->codec; 1290 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec); 1291 1292 u8 pll_frac_top, pll_frac_bot, pll_integer, cnt; 1293 1294 /* Disable PLL before setting the divisors */ 1295 snd_soc_update_bits(codec, DA9055_PLL_CTRL, DA9055_PLL_EN, 0); 1296 1297 /* In slave mode, there is only one set of divisors */ 1298 if (!da9055->master && (fout != 2822400)) 1299 goto pll_err; 1300 1301 /* Search pll div array for correct divisors */ 1302 for (cnt = 0; cnt < ARRAY_SIZE(da9055_pll_div); cnt++) { 1303 /* Check fref, mode and fout */ 1304 if ((fref == da9055_pll_div[cnt].fref) && 1305 (da9055->master == da9055_pll_div[cnt].mode) && 1306 (fout == da9055_pll_div[cnt].fout)) { 1307 /* All match, pick up divisors */ 1308 pll_frac_top = da9055_pll_div[cnt].frac_top; 1309 pll_frac_bot = da9055_pll_div[cnt].frac_bot; 1310 pll_integer = da9055_pll_div[cnt].integer; 1311 break; 1312 } 1313 } 1314 if (cnt >= ARRAY_SIZE(da9055_pll_div)) 1315 goto pll_err; 1316 1317 /* Write PLL dividers */ 1318 snd_soc_write(codec, DA9055_PLL_FRAC_TOP, pll_frac_top); 1319 snd_soc_write(codec, DA9055_PLL_FRAC_BOT, pll_frac_bot); 1320 snd_soc_write(codec, DA9055_PLL_INTEGER, pll_integer); 1321 1322 return 0; 1323 pll_err: 1324 dev_err(codec_dai->dev, "Error in setting up PLL\n"); 1325 return -EINVAL; 1326 } 1327 1328 /* DAI operations */ 1329 static const struct snd_soc_dai_ops da9055_dai_ops = { 1330 .hw_params = da9055_hw_params, 1331 .set_fmt = da9055_set_dai_fmt, 1332 .set_sysclk = da9055_set_dai_sysclk, 1333 .set_pll = da9055_set_dai_pll, 1334 .digital_mute = da9055_mute, 1335 }; 1336 1337 static struct snd_soc_dai_driver da9055_dai = { 1338 .name = "da9055-hifi", 1339 /* Playback Capabilities */ 1340 .playback = { 1341 .stream_name = "Playback", 1342 .channels_min = 1, 1343 .channels_max = 2, 1344 .rates = SNDRV_PCM_RATE_8000_96000, 1345 .formats = DA9055_FORMATS, 1346 }, 1347 /* Capture Capabilities */ 1348 .capture = { 1349 .stream_name = "Capture", 1350 .channels_min = 1, 1351 .channels_max = 2, 1352 .rates = SNDRV_PCM_RATE_8000_96000, 1353 .formats = DA9055_FORMATS, 1354 }, 1355 .ops = &da9055_dai_ops, 1356 .symmetric_rates = 1, 1357 }; 1358 1359 static int da9055_set_bias_level(struct snd_soc_codec *codec, 1360 enum snd_soc_bias_level level) 1361 { 1362 switch (level) { 1363 case SND_SOC_BIAS_ON: 1364 case SND_SOC_BIAS_PREPARE: 1365 break; 1366 case SND_SOC_BIAS_STANDBY: 1367 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { 1368 /* Enable VMID reference & master bias */ 1369 snd_soc_update_bits(codec, DA9055_REFERENCES, 1370 DA9055_VMID_EN | DA9055_BIAS_EN, 1371 DA9055_VMID_EN | DA9055_BIAS_EN); 1372 } 1373 break; 1374 case SND_SOC_BIAS_OFF: 1375 /* Disable VMID reference & master bias */ 1376 snd_soc_update_bits(codec, DA9055_REFERENCES, 1377 DA9055_VMID_EN | DA9055_BIAS_EN, 0); 1378 break; 1379 } 1380 return 0; 1381 } 1382 1383 static int da9055_probe(struct snd_soc_codec *codec) 1384 { 1385 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec); 1386 1387 /* Enable all Gain Ramps */ 1388 snd_soc_update_bits(codec, DA9055_AUX_L_CTRL, 1389 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1390 snd_soc_update_bits(codec, DA9055_AUX_R_CTRL, 1391 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1392 snd_soc_update_bits(codec, DA9055_MIXIN_L_CTRL, 1393 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1394 snd_soc_update_bits(codec, DA9055_MIXIN_R_CTRL, 1395 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1396 snd_soc_update_bits(codec, DA9055_ADC_L_CTRL, 1397 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1398 snd_soc_update_bits(codec, DA9055_ADC_R_CTRL, 1399 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1400 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL, 1401 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1402 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL, 1403 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1404 snd_soc_update_bits(codec, DA9055_HP_L_CTRL, 1405 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1406 snd_soc_update_bits(codec, DA9055_HP_R_CTRL, 1407 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1408 snd_soc_update_bits(codec, DA9055_LINE_CTRL, 1409 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1410 1411 /* 1412 * There are two separate control bits for input and output mixers. 1413 * One to enable corresponding amplifier and other to enable its 1414 * output. As amplifier bits are related to power control, they are 1415 * being managed by DAPM while other (non power related) bits are 1416 * enabled here 1417 */ 1418 snd_soc_update_bits(codec, DA9055_MIXIN_L_CTRL, 1419 DA9055_MIXIN_L_MIX_EN, DA9055_MIXIN_L_MIX_EN); 1420 snd_soc_update_bits(codec, DA9055_MIXIN_R_CTRL, 1421 DA9055_MIXIN_R_MIX_EN, DA9055_MIXIN_R_MIX_EN); 1422 1423 snd_soc_update_bits(codec, DA9055_MIXOUT_L_CTRL, 1424 DA9055_MIXOUT_L_MIX_EN, DA9055_MIXOUT_L_MIX_EN); 1425 snd_soc_update_bits(codec, DA9055_MIXOUT_R_CTRL, 1426 DA9055_MIXOUT_R_MIX_EN, DA9055_MIXOUT_R_MIX_EN); 1427 1428 /* Set this as per your system configuration */ 1429 snd_soc_write(codec, DA9055_PLL_CTRL, DA9055_PLL_INDIV_10_20_MHZ); 1430 1431 /* Set platform data values */ 1432 if (da9055->pdata) { 1433 /* set mic bias source */ 1434 if (da9055->pdata->micbias_source) { 1435 snd_soc_update_bits(codec, DA9055_MIXIN_R_SELECT, 1436 DA9055_MICBIAS2_EN, 1437 DA9055_MICBIAS2_EN); 1438 } else { 1439 snd_soc_update_bits(codec, DA9055_MIXIN_R_SELECT, 1440 DA9055_MICBIAS2_EN, 0); 1441 } 1442 /* set mic bias voltage */ 1443 switch (da9055->pdata->micbias) { 1444 case DA9055_MICBIAS_2_2V: 1445 case DA9055_MICBIAS_2_1V: 1446 case DA9055_MICBIAS_1_8V: 1447 case DA9055_MICBIAS_1_6V: 1448 snd_soc_update_bits(codec, DA9055_MIC_CONFIG, 1449 DA9055_MICBIAS_LEVEL_MASK, 1450 (da9055->pdata->micbias) << 4); 1451 break; 1452 } 1453 } 1454 return 0; 1455 } 1456 1457 static struct snd_soc_codec_driver soc_codec_dev_da9055 = { 1458 .probe = da9055_probe, 1459 .set_bias_level = da9055_set_bias_level, 1460 1461 .controls = da9055_snd_controls, 1462 .num_controls = ARRAY_SIZE(da9055_snd_controls), 1463 1464 .dapm_widgets = da9055_dapm_widgets, 1465 .num_dapm_widgets = ARRAY_SIZE(da9055_dapm_widgets), 1466 .dapm_routes = da9055_audio_map, 1467 .num_dapm_routes = ARRAY_SIZE(da9055_audio_map), 1468 }; 1469 1470 static const struct regmap_config da9055_regmap_config = { 1471 .reg_bits = 8, 1472 .val_bits = 8, 1473 1474 .reg_defaults = da9055_reg_defaults, 1475 .num_reg_defaults = ARRAY_SIZE(da9055_reg_defaults), 1476 .volatile_reg = da9055_volatile_register, 1477 .cache_type = REGCACHE_RBTREE, 1478 }; 1479 1480 static int da9055_i2c_probe(struct i2c_client *i2c, 1481 const struct i2c_device_id *id) 1482 { 1483 struct da9055_priv *da9055; 1484 struct da9055_platform_data *pdata = dev_get_platdata(&i2c->dev); 1485 int ret; 1486 1487 da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055_priv), 1488 GFP_KERNEL); 1489 if (!da9055) 1490 return -ENOMEM; 1491 1492 if (pdata) 1493 da9055->pdata = pdata; 1494 1495 i2c_set_clientdata(i2c, da9055); 1496 1497 da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config); 1498 if (IS_ERR(da9055->regmap)) { 1499 ret = PTR_ERR(da9055->regmap); 1500 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret); 1501 return ret; 1502 } 1503 1504 ret = snd_soc_register_codec(&i2c->dev, 1505 &soc_codec_dev_da9055, &da9055_dai, 1); 1506 if (ret < 0) { 1507 dev_err(&i2c->dev, "Failed to register da9055 codec: %d\n", 1508 ret); 1509 } 1510 return ret; 1511 } 1512 1513 static int da9055_remove(struct i2c_client *client) 1514 { 1515 snd_soc_unregister_codec(&client->dev); 1516 return 0; 1517 } 1518 1519 /* 1520 * DO NOT change the device Ids. The naming is intentionally specific as both 1521 * the CODEC and PMIC parts of this chip are instantiated separately as I2C 1522 * devices (both have configurable I2C addresses, and are to all intents and 1523 * purposes separate). As a result there are specific DA9055 Ids for CODEC 1524 * and PMIC, which must be different to operate together. 1525 */ 1526 static const struct i2c_device_id da9055_i2c_id[] = { 1527 { "da9055-codec", 0 }, 1528 { } 1529 }; 1530 MODULE_DEVICE_TABLE(i2c, da9055_i2c_id); 1531 1532 static const struct of_device_id da9055_of_match[] = { 1533 { .compatible = "dlg,da9055-codec", }, 1534 { } 1535 }; 1536 1537 /* I2C codec control layer */ 1538 static struct i2c_driver da9055_i2c_driver = { 1539 .driver = { 1540 .name = "da9055-codec", 1541 .owner = THIS_MODULE, 1542 .of_match_table = of_match_ptr(da9055_of_match), 1543 }, 1544 .probe = da9055_i2c_probe, 1545 .remove = da9055_remove, 1546 .id_table = da9055_i2c_id, 1547 }; 1548 1549 module_i2c_driver(da9055_i2c_driver); 1550 1551 MODULE_DESCRIPTION("ASoC DA9055 Codec driver"); 1552 MODULE_AUTHOR("David Chen, Ashish Chavan"); 1553 MODULE_LICENSE("GPL"); 1554