1 /* 2 * DA9055 ALSA Soc codec driver 3 * 4 * Copyright (c) 2012 Dialog Semiconductor 5 * 6 * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C 7 * Written by David Chen <david.chen@diasemi.com> and 8 * Ashish Chavan <ashish.chavan@kpitcummins.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or (at your 13 * option) any later version. 14 */ 15 16 #include <linux/delay.h> 17 #include <linux/i2c.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include <sound/soc.h> 24 #include <sound/initval.h> 25 #include <sound/tlv.h> 26 #include <sound/da9055.h> 27 28 /* DA9055 register space */ 29 30 /* Status Registers */ 31 #define DA9055_STATUS1 0x02 32 #define DA9055_PLL_STATUS 0x03 33 #define DA9055_AUX_L_GAIN_STATUS 0x04 34 #define DA9055_AUX_R_GAIN_STATUS 0x05 35 #define DA9055_MIC_L_GAIN_STATUS 0x06 36 #define DA9055_MIC_R_GAIN_STATUS 0x07 37 #define DA9055_MIXIN_L_GAIN_STATUS 0x08 38 #define DA9055_MIXIN_R_GAIN_STATUS 0x09 39 #define DA9055_ADC_L_GAIN_STATUS 0x0A 40 #define DA9055_ADC_R_GAIN_STATUS 0x0B 41 #define DA9055_DAC_L_GAIN_STATUS 0x0C 42 #define DA9055_DAC_R_GAIN_STATUS 0x0D 43 #define DA9055_HP_L_GAIN_STATUS 0x0E 44 #define DA9055_HP_R_GAIN_STATUS 0x0F 45 #define DA9055_LINE_GAIN_STATUS 0x10 46 47 /* System Initialisation Registers */ 48 #define DA9055_CIF_CTRL 0x20 49 #define DA9055_DIG_ROUTING_AIF 0X21 50 #define DA9055_SR 0x22 51 #define DA9055_REFERENCES 0x23 52 #define DA9055_PLL_FRAC_TOP 0x24 53 #define DA9055_PLL_FRAC_BOT 0x25 54 #define DA9055_PLL_INTEGER 0x26 55 #define DA9055_PLL_CTRL 0x27 56 #define DA9055_AIF_CLK_MODE 0x28 57 #define DA9055_AIF_CTRL 0x29 58 #define DA9055_DIG_ROUTING_DAC 0x2A 59 #define DA9055_ALC_CTRL1 0x2B 60 61 /* Input - Gain, Select and Filter Registers */ 62 #define DA9055_AUX_L_GAIN 0x30 63 #define DA9055_AUX_R_GAIN 0x31 64 #define DA9055_MIXIN_L_SELECT 0x32 65 #define DA9055_MIXIN_R_SELECT 0x33 66 #define DA9055_MIXIN_L_GAIN 0x34 67 #define DA9055_MIXIN_R_GAIN 0x35 68 #define DA9055_ADC_L_GAIN 0x36 69 #define DA9055_ADC_R_GAIN 0x37 70 #define DA9055_ADC_FILTERS1 0x38 71 #define DA9055_MIC_L_GAIN 0x39 72 #define DA9055_MIC_R_GAIN 0x3A 73 74 /* Output - Gain, Select and Filter Registers */ 75 #define DA9055_DAC_FILTERS5 0x40 76 #define DA9055_DAC_FILTERS2 0x41 77 #define DA9055_DAC_FILTERS3 0x42 78 #define DA9055_DAC_FILTERS4 0x43 79 #define DA9055_DAC_FILTERS1 0x44 80 #define DA9055_DAC_L_GAIN 0x45 81 #define DA9055_DAC_R_GAIN 0x46 82 #define DA9055_CP_CTRL 0x47 83 #define DA9055_HP_L_GAIN 0x48 84 #define DA9055_HP_R_GAIN 0x49 85 #define DA9055_LINE_GAIN 0x4A 86 #define DA9055_MIXOUT_L_SELECT 0x4B 87 #define DA9055_MIXOUT_R_SELECT 0x4C 88 89 /* System Controller Registers */ 90 #define DA9055_SYSTEM_MODES_INPUT 0x50 91 #define DA9055_SYSTEM_MODES_OUTPUT 0x51 92 93 /* Control Registers */ 94 #define DA9055_AUX_L_CTRL 0x60 95 #define DA9055_AUX_R_CTRL 0x61 96 #define DA9055_MIC_BIAS_CTRL 0x62 97 #define DA9055_MIC_L_CTRL 0x63 98 #define DA9055_MIC_R_CTRL 0x64 99 #define DA9055_MIXIN_L_CTRL 0x65 100 #define DA9055_MIXIN_R_CTRL 0x66 101 #define DA9055_ADC_L_CTRL 0x67 102 #define DA9055_ADC_R_CTRL 0x68 103 #define DA9055_DAC_L_CTRL 0x69 104 #define DA9055_DAC_R_CTRL 0x6A 105 #define DA9055_HP_L_CTRL 0x6B 106 #define DA9055_HP_R_CTRL 0x6C 107 #define DA9055_LINE_CTRL 0x6D 108 #define DA9055_MIXOUT_L_CTRL 0x6E 109 #define DA9055_MIXOUT_R_CTRL 0x6F 110 111 /* Configuration Registers */ 112 #define DA9055_LDO_CTRL 0x90 113 #define DA9055_IO_CTRL 0x91 114 #define DA9055_GAIN_RAMP_CTRL 0x92 115 #define DA9055_MIC_CONFIG 0x93 116 #define DA9055_PC_COUNT 0x94 117 #define DA9055_CP_VOL_THRESHOLD1 0x95 118 #define DA9055_CP_DELAY 0x96 119 #define DA9055_CP_DETECTOR 0x97 120 #define DA9055_AIF_OFFSET 0x98 121 #define DA9055_DIG_CTRL 0x99 122 #define DA9055_ALC_CTRL2 0x9A 123 #define DA9055_ALC_CTRL3 0x9B 124 #define DA9055_ALC_NOISE 0x9C 125 #define DA9055_ALC_TARGET_MIN 0x9D 126 #define DA9055_ALC_TARGET_MAX 0x9E 127 #define DA9055_ALC_GAIN_LIMITS 0x9F 128 #define DA9055_ALC_ANA_GAIN_LIMITS 0xA0 129 #define DA9055_ALC_ANTICLIP_CTRL 0xA1 130 #define DA9055_ALC_ANTICLIP_LEVEL 0xA2 131 #define DA9055_ALC_OFFSET_OP2M_L 0xA6 132 #define DA9055_ALC_OFFSET_OP2U_L 0xA7 133 #define DA9055_ALC_OFFSET_OP2M_R 0xAB 134 #define DA9055_ALC_OFFSET_OP2U_R 0xAC 135 #define DA9055_ALC_CIC_OP_LVL_CTRL 0xAD 136 #define DA9055_ALC_CIC_OP_LVL_DATA 0xAE 137 #define DA9055_DAC_NG_SETUP_TIME 0xAF 138 #define DA9055_DAC_NG_OFF_THRESHOLD 0xB0 139 #define DA9055_DAC_NG_ON_THRESHOLD 0xB1 140 #define DA9055_DAC_NG_CTRL 0xB2 141 142 /* SR bit fields */ 143 #define DA9055_SR_8000 (0x1 << 0) 144 #define DA9055_SR_11025 (0x2 << 0) 145 #define DA9055_SR_12000 (0x3 << 0) 146 #define DA9055_SR_16000 (0x5 << 0) 147 #define DA9055_SR_22050 (0x6 << 0) 148 #define DA9055_SR_24000 (0x7 << 0) 149 #define DA9055_SR_32000 (0x9 << 0) 150 #define DA9055_SR_44100 (0xA << 0) 151 #define DA9055_SR_48000 (0xB << 0) 152 #define DA9055_SR_88200 (0xE << 0) 153 #define DA9055_SR_96000 (0xF << 0) 154 155 /* REFERENCES bit fields */ 156 #define DA9055_BIAS_EN (1 << 3) 157 #define DA9055_VMID_EN (1 << 7) 158 159 /* PLL_CTRL bit fields */ 160 #define DA9055_PLL_INDIV_10_20_MHZ (1 << 2) 161 #define DA9055_PLL_SRM_EN (1 << 6) 162 #define DA9055_PLL_EN (1 << 7) 163 164 /* AIF_CLK_MODE bit fields */ 165 #define DA9055_AIF_BCLKS_PER_WCLK_32 (0 << 0) 166 #define DA9055_AIF_BCLKS_PER_WCLK_64 (1 << 0) 167 #define DA9055_AIF_BCLKS_PER_WCLK_128 (2 << 0) 168 #define DA9055_AIF_BCLKS_PER_WCLK_256 (3 << 0) 169 #define DA9055_AIF_CLK_EN_SLAVE_MODE (0 << 7) 170 #define DA9055_AIF_CLK_EN_MASTER_MODE (1 << 7) 171 172 /* AIF_CTRL bit fields */ 173 #define DA9055_AIF_FORMAT_I2S_MODE (0 << 0) 174 #define DA9055_AIF_FORMAT_LEFT_J (1 << 0) 175 #define DA9055_AIF_FORMAT_RIGHT_J (2 << 0) 176 #define DA9055_AIF_FORMAT_DSP (3 << 0) 177 #define DA9055_AIF_WORD_S16_LE (0 << 2) 178 #define DA9055_AIF_WORD_S20_3LE (1 << 2) 179 #define DA9055_AIF_WORD_S24_LE (2 << 2) 180 #define DA9055_AIF_WORD_S32_LE (3 << 2) 181 182 /* MIC_L_CTRL bit fields */ 183 #define DA9055_MIC_L_MUTE_EN (1 << 6) 184 185 /* MIC_R_CTRL bit fields */ 186 #define DA9055_MIC_R_MUTE_EN (1 << 6) 187 188 /* MIXIN_L_CTRL bit fields */ 189 #define DA9055_MIXIN_L_MIX_EN (1 << 3) 190 191 /* MIXIN_R_CTRL bit fields */ 192 #define DA9055_MIXIN_R_MIX_EN (1 << 3) 193 194 /* ADC_L_CTRL bit fields */ 195 #define DA9055_ADC_L_EN (1 << 7) 196 197 /* ADC_R_CTRL bit fields */ 198 #define DA9055_ADC_R_EN (1 << 7) 199 200 /* DAC_L_CTRL bit fields */ 201 #define DA9055_DAC_L_MUTE_EN (1 << 6) 202 203 /* DAC_R_CTRL bit fields */ 204 #define DA9055_DAC_R_MUTE_EN (1 << 6) 205 206 /* HP_L_CTRL bit fields */ 207 #define DA9055_HP_L_AMP_OE (1 << 3) 208 209 /* HP_R_CTRL bit fields */ 210 #define DA9055_HP_R_AMP_OE (1 << 3) 211 212 /* LINE_CTRL bit fields */ 213 #define DA9055_LINE_AMP_OE (1 << 3) 214 215 /* MIXOUT_L_CTRL bit fields */ 216 #define DA9055_MIXOUT_L_MIX_EN (1 << 3) 217 218 /* MIXOUT_R_CTRL bit fields */ 219 #define DA9055_MIXOUT_R_MIX_EN (1 << 3) 220 221 /* MIC bias select bit fields */ 222 #define DA9055_MICBIAS2_EN (1 << 6) 223 224 /* ALC_CIC_OP_LEVEL_CTRL bit fields */ 225 #define DA9055_ALC_DATA_MIDDLE (2 << 0) 226 #define DA9055_ALC_DATA_TOP (3 << 0) 227 #define DA9055_ALC_CIC_OP_CHANNEL_LEFT (0 << 7) 228 #define DA9055_ALC_CIC_OP_CHANNEL_RIGHT (1 << 7) 229 230 #define DA9055_AIF_BCLK_MASK (3 << 0) 231 #define DA9055_AIF_CLK_MODE_MASK (1 << 7) 232 #define DA9055_AIF_FORMAT_MASK (3 << 0) 233 #define DA9055_AIF_WORD_LENGTH_MASK (3 << 2) 234 #define DA9055_GAIN_RAMPING_EN (1 << 5) 235 #define DA9055_MICBIAS_LEVEL_MASK (3 << 4) 236 237 #define DA9055_ALC_OFFSET_15_8 0x00FF00 238 #define DA9055_ALC_OFFSET_17_16 0x030000 239 #define DA9055_ALC_AVG_ITERATIONS 5 240 241 struct pll_div { 242 int fref; 243 int fout; 244 u8 frac_top; 245 u8 frac_bot; 246 u8 integer; 247 u8 mode; /* 0 = slave, 1 = master */ 248 }; 249 250 /* PLL divisor table */ 251 static const struct pll_div da9055_pll_div[] = { 252 /* for MASTER mode, fs = 44.1Khz and its harmonics */ 253 {11289600, 2822400, 0x00, 0x00, 0x20, 1}, /* MCLK=11.2896Mhz */ 254 {12000000, 2822400, 0x03, 0x61, 0x1E, 1}, /* MCLK=12Mhz */ 255 {12288000, 2822400, 0x0C, 0xCC, 0x1D, 1}, /* MCLK=12.288Mhz */ 256 {13000000, 2822400, 0x19, 0x45, 0x1B, 1}, /* MCLK=13Mhz */ 257 {13500000, 2822400, 0x18, 0x56, 0x1A, 1}, /* MCLK=13.5Mhz */ 258 {14400000, 2822400, 0x02, 0xD0, 0x19, 1}, /* MCLK=14.4Mhz */ 259 {19200000, 2822400, 0x1A, 0x1C, 0x12, 1}, /* MCLK=19.2Mhz */ 260 {19680000, 2822400, 0x0B, 0x6D, 0x12, 1}, /* MCLK=19.68Mhz */ 261 {19800000, 2822400, 0x07, 0xDD, 0x12, 1}, /* MCLK=19.8Mhz */ 262 /* for MASTER mode, fs = 48Khz and its harmonics */ 263 {11289600, 3072000, 0x1A, 0x8E, 0x22, 1}, /* MCLK=11.2896Mhz */ 264 {12000000, 3072000, 0x18, 0x93, 0x20, 1}, /* MCLK=12Mhz */ 265 {12288000, 3072000, 0x00, 0x00, 0x20, 1}, /* MCLK=12.288Mhz */ 266 {13000000, 3072000, 0x07, 0xEA, 0x1E, 1}, /* MCLK=13Mhz */ 267 {13500000, 3072000, 0x04, 0x11, 0x1D, 1}, /* MCLK=13.5Mhz */ 268 {14400000, 3072000, 0x09, 0xD0, 0x1B, 1}, /* MCLK=14.4Mhz */ 269 {19200000, 3072000, 0x0F, 0x5C, 0x14, 1}, /* MCLK=19.2Mhz */ 270 {19680000, 3072000, 0x1F, 0x60, 0x13, 1}, /* MCLK=19.68Mhz */ 271 {19800000, 3072000, 0x1B, 0x80, 0x13, 1}, /* MCLK=19.8Mhz */ 272 /* for SLAVE mode with SRM */ 273 {11289600, 2822400, 0x0D, 0x47, 0x21, 0}, /* MCLK=11.2896Mhz */ 274 {12000000, 2822400, 0x0D, 0xFA, 0x1F, 0}, /* MCLK=12Mhz */ 275 {12288000, 2822400, 0x16, 0x66, 0x1E, 0}, /* MCLK=12.288Mhz */ 276 {13000000, 2822400, 0x00, 0x98, 0x1D, 0}, /* MCLK=13Mhz */ 277 {13500000, 2822400, 0x1E, 0x33, 0x1B, 0}, /* MCLK=13.5Mhz */ 278 {14400000, 2822400, 0x06, 0x50, 0x1A, 0}, /* MCLK=14.4Mhz */ 279 {19200000, 2822400, 0x14, 0xBC, 0x13, 0}, /* MCLK=19.2Mhz */ 280 {19680000, 2822400, 0x05, 0x66, 0x13, 0}, /* MCLK=19.68Mhz */ 281 {19800000, 2822400, 0x01, 0xAE, 0x13, 0}, /* MCLK=19.8Mhz */ 282 }; 283 284 enum clk_src { 285 DA9055_CLKSRC_MCLK 286 }; 287 288 /* Gain and Volume */ 289 290 static const unsigned int aux_vol_tlv[] = { 291 TLV_DB_RANGE_HEAD(2), 292 0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0), 293 /* -54dB to 15dB */ 294 0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0) 295 }; 296 297 static const unsigned int digital_gain_tlv[] = { 298 TLV_DB_RANGE_HEAD(2), 299 0x0, 0x07, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 300 /* -78dB to 12dB */ 301 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0) 302 }; 303 304 static const unsigned int alc_analog_gain_tlv[] = { 305 TLV_DB_RANGE_HEAD(2), 306 0x0, 0x0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1), 307 /* 0dB to 36dB */ 308 0x01, 0x07, TLV_DB_SCALE_ITEM(0, 600, 0) 309 }; 310 311 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0); 312 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0); 313 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0); 314 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0); 315 static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0); 316 static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0); 317 static const DECLARE_TLV_DB_SCALE(alc_gain_tlv, 0, 600, 0); 318 319 /* ADC and DAC high pass filter cutoff value */ 320 static const char * const da9055_hpf_cutoff_txt[] = { 321 "Fs/24000", "Fs/12000", "Fs/6000", "Fs/3000" 322 }; 323 324 static const struct soc_enum da9055_dac_hpf_cutoff = 325 SOC_ENUM_SINGLE(DA9055_DAC_FILTERS1, 4, 4, da9055_hpf_cutoff_txt); 326 327 static const struct soc_enum da9055_adc_hpf_cutoff = 328 SOC_ENUM_SINGLE(DA9055_ADC_FILTERS1, 4, 4, da9055_hpf_cutoff_txt); 329 330 /* ADC and DAC voice mode (8kHz) high pass cutoff value */ 331 static const char * const da9055_vf_cutoff_txt[] = { 332 "2.5Hz", "25Hz", "50Hz", "100Hz", "150Hz", "200Hz", "300Hz", "400Hz" 333 }; 334 335 static const struct soc_enum da9055_dac_vf_cutoff = 336 SOC_ENUM_SINGLE(DA9055_DAC_FILTERS1, 0, 8, da9055_vf_cutoff_txt); 337 338 static const struct soc_enum da9055_adc_vf_cutoff = 339 SOC_ENUM_SINGLE(DA9055_ADC_FILTERS1, 0, 8, da9055_vf_cutoff_txt); 340 341 /* Gain ramping rate value */ 342 static const char * const da9055_gain_ramping_txt[] = { 343 "nominal rate", "nominal rate * 4", "nominal rate * 8", 344 "nominal rate / 8" 345 }; 346 347 static const struct soc_enum da9055_gain_ramping_rate = 348 SOC_ENUM_SINGLE(DA9055_GAIN_RAMP_CTRL, 0, 4, da9055_gain_ramping_txt); 349 350 /* DAC noise gate setup time value */ 351 static const char * const da9055_dac_ng_setup_time_txt[] = { 352 "256 samples", "512 samples", "1024 samples", "2048 samples" 353 }; 354 355 static const struct soc_enum da9055_dac_ng_setup_time = 356 SOC_ENUM_SINGLE(DA9055_DAC_NG_SETUP_TIME, 0, 4, 357 da9055_dac_ng_setup_time_txt); 358 359 /* DAC noise gate rampup rate value */ 360 static const char * const da9055_dac_ng_rampup_txt[] = { 361 "0.02 ms/dB", "0.16 ms/dB" 362 }; 363 364 static const struct soc_enum da9055_dac_ng_rampup_rate = 365 SOC_ENUM_SINGLE(DA9055_DAC_NG_SETUP_TIME, 2, 2, 366 da9055_dac_ng_rampup_txt); 367 368 /* DAC noise gate rampdown rate value */ 369 static const char * const da9055_dac_ng_rampdown_txt[] = { 370 "0.64 ms/dB", "20.48 ms/dB" 371 }; 372 373 static const struct soc_enum da9055_dac_ng_rampdown_rate = 374 SOC_ENUM_SINGLE(DA9055_DAC_NG_SETUP_TIME, 3, 2, 375 da9055_dac_ng_rampdown_txt); 376 377 /* DAC soft mute rate value */ 378 static const char * const da9055_dac_soft_mute_rate_txt[] = { 379 "1", "2", "4", "8", "16", "32", "64" 380 }; 381 382 static const struct soc_enum da9055_dac_soft_mute_rate = 383 SOC_ENUM_SINGLE(DA9055_DAC_FILTERS5, 4, 7, 384 da9055_dac_soft_mute_rate_txt); 385 386 /* DAC routing select */ 387 static const char * const da9055_dac_src_txt[] = { 388 "ADC output left", "ADC output right", "AIF input left", 389 "AIF input right" 390 }; 391 392 static const struct soc_enum da9055_dac_l_src = 393 SOC_ENUM_SINGLE(DA9055_DIG_ROUTING_DAC, 0, 4, da9055_dac_src_txt); 394 395 static const struct soc_enum da9055_dac_r_src = 396 SOC_ENUM_SINGLE(DA9055_DIG_ROUTING_DAC, 4, 4, da9055_dac_src_txt); 397 398 /* MIC PGA Left source select */ 399 static const char * const da9055_mic_l_src_txt[] = { 400 "MIC1_P_N", "MIC1_P", "MIC1_N", "MIC2_L" 401 }; 402 403 static const struct soc_enum da9055_mic_l_src = 404 SOC_ENUM_SINGLE(DA9055_MIXIN_L_SELECT, 4, 4, da9055_mic_l_src_txt); 405 406 /* MIC PGA Right source select */ 407 static const char * const da9055_mic_r_src_txt[] = { 408 "MIC2_R_L", "MIC2_R", "MIC2_L" 409 }; 410 411 static const struct soc_enum da9055_mic_r_src = 412 SOC_ENUM_SINGLE(DA9055_MIXIN_R_SELECT, 4, 3, da9055_mic_r_src_txt); 413 414 /* ALC Input Signal Tracking rate select */ 415 static const char * const da9055_signal_tracking_rate_txt[] = { 416 "1/4", "1/16", "1/256", "1/65536" 417 }; 418 419 static const struct soc_enum da9055_integ_attack_rate = 420 SOC_ENUM_SINGLE(DA9055_ALC_CTRL3, 4, 4, 421 da9055_signal_tracking_rate_txt); 422 423 static const struct soc_enum da9055_integ_release_rate = 424 SOC_ENUM_SINGLE(DA9055_ALC_CTRL3, 6, 4, 425 da9055_signal_tracking_rate_txt); 426 427 /* ALC Attack Rate select */ 428 static const char * const da9055_attack_rate_txt[] = { 429 "44/fs", "88/fs", "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", 430 "5632/fs", "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs" 431 }; 432 433 static const struct soc_enum da9055_attack_rate = 434 SOC_ENUM_SINGLE(DA9055_ALC_CTRL2, 0, 13, da9055_attack_rate_txt); 435 436 /* ALC Release Rate select */ 437 static const char * const da9055_release_rate_txt[] = { 438 "176/fs", "352/fs", "704/fs", "1408/fs", "2816/fs", "5632/fs", 439 "11264/fs", "22528/fs", "45056/fs", "90112/fs", "180224/fs" 440 }; 441 442 static const struct soc_enum da9055_release_rate = 443 SOC_ENUM_SINGLE(DA9055_ALC_CTRL2, 4, 11, da9055_release_rate_txt); 444 445 /* ALC Hold Time select */ 446 static const char * const da9055_hold_time_txt[] = { 447 "62/fs", "124/fs", "248/fs", "496/fs", "992/fs", "1984/fs", "3968/fs", 448 "7936/fs", "15872/fs", "31744/fs", "63488/fs", "126976/fs", 449 "253952/fs", "507904/fs", "1015808/fs", "2031616/fs" 450 }; 451 452 static const struct soc_enum da9055_hold_time = 453 SOC_ENUM_SINGLE(DA9055_ALC_CTRL3, 0, 16, da9055_hold_time_txt); 454 455 static int da9055_get_alc_data(struct snd_soc_codec *codec, u8 reg_val) 456 { 457 int mid_data, top_data; 458 int sum = 0; 459 u8 iteration; 460 461 for (iteration = 0; iteration < DA9055_ALC_AVG_ITERATIONS; 462 iteration++) { 463 /* Select the left or right channel and capture data */ 464 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL, reg_val); 465 466 /* Select middle 8 bits for read back from data register */ 467 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL, 468 reg_val | DA9055_ALC_DATA_MIDDLE); 469 mid_data = snd_soc_read(codec, DA9055_ALC_CIC_OP_LVL_DATA); 470 471 /* Select top 8 bits for read back from data register */ 472 snd_soc_write(codec, DA9055_ALC_CIC_OP_LVL_CTRL, 473 reg_val | DA9055_ALC_DATA_TOP); 474 top_data = snd_soc_read(codec, DA9055_ALC_CIC_OP_LVL_DATA); 475 476 sum += ((mid_data << 8) | (top_data << 16)); 477 } 478 479 return sum / DA9055_ALC_AVG_ITERATIONS; 480 } 481 482 static int da9055_put_alc_sw(struct snd_kcontrol *kcontrol, 483 struct snd_ctl_elem_value *ucontrol) 484 { 485 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol); 486 u8 reg_val, adc_left, adc_right, mic_left, mic_right; 487 int avg_left_data, avg_right_data, offset_l, offset_r; 488 489 if (ucontrol->value.integer.value[0]) { 490 /* 491 * While enabling ALC (or ALC sync mode), calibration of the DC 492 * offsets must be done first 493 */ 494 495 /* Save current values from Mic control registers */ 496 mic_left = snd_soc_read(codec, DA9055_MIC_L_CTRL); 497 mic_right = snd_soc_read(codec, DA9055_MIC_R_CTRL); 498 499 /* Mute Mic PGA Left and Right */ 500 snd_soc_update_bits(codec, DA9055_MIC_L_CTRL, 501 DA9055_MIC_L_MUTE_EN, DA9055_MIC_L_MUTE_EN); 502 snd_soc_update_bits(codec, DA9055_MIC_R_CTRL, 503 DA9055_MIC_R_MUTE_EN, DA9055_MIC_R_MUTE_EN); 504 505 /* Save current values from ADC control registers */ 506 adc_left = snd_soc_read(codec, DA9055_ADC_L_CTRL); 507 adc_right = snd_soc_read(codec, DA9055_ADC_R_CTRL); 508 509 /* Enable ADC Left and Right */ 510 snd_soc_update_bits(codec, DA9055_ADC_L_CTRL, 511 DA9055_ADC_L_EN, DA9055_ADC_L_EN); 512 snd_soc_update_bits(codec, DA9055_ADC_R_CTRL, 513 DA9055_ADC_R_EN, DA9055_ADC_R_EN); 514 515 /* Calculate average for Left and Right data */ 516 /* Left Data */ 517 avg_left_data = da9055_get_alc_data(codec, 518 DA9055_ALC_CIC_OP_CHANNEL_LEFT); 519 /* Right Data */ 520 avg_right_data = da9055_get_alc_data(codec, 521 DA9055_ALC_CIC_OP_CHANNEL_RIGHT); 522 523 /* Calculate DC offset */ 524 offset_l = -avg_left_data; 525 offset_r = -avg_right_data; 526 527 reg_val = (offset_l & DA9055_ALC_OFFSET_15_8) >> 8; 528 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2M_L, reg_val); 529 reg_val = (offset_l & DA9055_ALC_OFFSET_17_16) >> 16; 530 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2U_L, reg_val); 531 532 reg_val = (offset_r & DA9055_ALC_OFFSET_15_8) >> 8; 533 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2M_R, reg_val); 534 reg_val = (offset_r & DA9055_ALC_OFFSET_17_16) >> 16; 535 snd_soc_write(codec, DA9055_ALC_OFFSET_OP2U_R, reg_val); 536 537 /* Restore original values of ADC control registers */ 538 snd_soc_write(codec, DA9055_ADC_L_CTRL, adc_left); 539 snd_soc_write(codec, DA9055_ADC_R_CTRL, adc_right); 540 541 /* Restore original values of Mic control registers */ 542 snd_soc_write(codec, DA9055_MIC_L_CTRL, mic_left); 543 snd_soc_write(codec, DA9055_MIC_R_CTRL, mic_right); 544 } 545 546 return snd_soc_put_volsw(kcontrol, ucontrol); 547 } 548 549 static const struct snd_kcontrol_new da9055_snd_controls[] = { 550 551 /* Volume controls */ 552 SOC_DOUBLE_R_TLV("Mic Volume", 553 DA9055_MIC_L_GAIN, DA9055_MIC_R_GAIN, 554 0, 0x7, 0, mic_vol_tlv), 555 SOC_DOUBLE_R_TLV("Aux Volume", 556 DA9055_AUX_L_GAIN, DA9055_AUX_R_GAIN, 557 0, 0x3f, 0, aux_vol_tlv), 558 SOC_DOUBLE_R_TLV("Mixin PGA Volume", 559 DA9055_MIXIN_L_GAIN, DA9055_MIXIN_R_GAIN, 560 0, 0xf, 0, mixin_gain_tlv), 561 SOC_DOUBLE_R_TLV("ADC Volume", 562 DA9055_ADC_L_GAIN, DA9055_ADC_R_GAIN, 563 0, 0x7f, 0, digital_gain_tlv), 564 565 SOC_DOUBLE_R_TLV("DAC Volume", 566 DA9055_DAC_L_GAIN, DA9055_DAC_R_GAIN, 567 0, 0x7f, 0, digital_gain_tlv), 568 SOC_DOUBLE_R_TLV("Headphone Volume", 569 DA9055_HP_L_GAIN, DA9055_HP_R_GAIN, 570 0, 0x3f, 0, hp_vol_tlv), 571 SOC_SINGLE_TLV("Lineout Volume", DA9055_LINE_GAIN, 0, 0x3f, 0, 572 lineout_vol_tlv), 573 574 /* DAC Equalizer controls */ 575 SOC_SINGLE("DAC EQ Switch", DA9055_DAC_FILTERS4, 7, 1, 0), 576 SOC_SINGLE_TLV("DAC EQ1 Volume", DA9055_DAC_FILTERS2, 0, 0xf, 0, 577 eq_gain_tlv), 578 SOC_SINGLE_TLV("DAC EQ2 Volume", DA9055_DAC_FILTERS2, 4, 0xf, 0, 579 eq_gain_tlv), 580 SOC_SINGLE_TLV("DAC EQ3 Volume", DA9055_DAC_FILTERS3, 0, 0xf, 0, 581 eq_gain_tlv), 582 SOC_SINGLE_TLV("DAC EQ4 Volume", DA9055_DAC_FILTERS3, 4, 0xf, 0, 583 eq_gain_tlv), 584 SOC_SINGLE_TLV("DAC EQ5 Volume", DA9055_DAC_FILTERS4, 0, 0xf, 0, 585 eq_gain_tlv), 586 587 /* High Pass Filter and Voice Mode controls */ 588 SOC_SINGLE("ADC HPF Switch", DA9055_ADC_FILTERS1, 7, 1, 0), 589 SOC_ENUM("ADC HPF Cutoff", da9055_adc_hpf_cutoff), 590 SOC_SINGLE("ADC Voice Mode Switch", DA9055_ADC_FILTERS1, 3, 1, 0), 591 SOC_ENUM("ADC Voice Cutoff", da9055_adc_vf_cutoff), 592 593 SOC_SINGLE("DAC HPF Switch", DA9055_DAC_FILTERS1, 7, 1, 0), 594 SOC_ENUM("DAC HPF Cutoff", da9055_dac_hpf_cutoff), 595 SOC_SINGLE("DAC Voice Mode Switch", DA9055_DAC_FILTERS1, 3, 1, 0), 596 SOC_ENUM("DAC Voice Cutoff", da9055_dac_vf_cutoff), 597 598 /* Mute controls */ 599 SOC_DOUBLE_R("Mic Switch", DA9055_MIC_L_CTRL, 600 DA9055_MIC_R_CTRL, 6, 1, 0), 601 SOC_DOUBLE_R("Aux Switch", DA9055_AUX_L_CTRL, 602 DA9055_AUX_R_CTRL, 6, 1, 0), 603 SOC_DOUBLE_R("Mixin PGA Switch", DA9055_MIXIN_L_CTRL, 604 DA9055_MIXIN_R_CTRL, 6, 1, 0), 605 SOC_DOUBLE_R("ADC Switch", DA9055_ADC_L_CTRL, 606 DA9055_ADC_R_CTRL, 6, 1, 0), 607 SOC_DOUBLE_R("Headphone Switch", DA9055_HP_L_CTRL, 608 DA9055_HP_R_CTRL, 6, 1, 0), 609 SOC_SINGLE("Lineout Switch", DA9055_LINE_CTRL, 6, 1, 0), 610 SOC_SINGLE("DAC Soft Mute Switch", DA9055_DAC_FILTERS5, 7, 1, 0), 611 SOC_ENUM("DAC Soft Mute Rate", da9055_dac_soft_mute_rate), 612 613 /* Zero Cross controls */ 614 SOC_DOUBLE_R("Aux ZC Switch", DA9055_AUX_L_CTRL, 615 DA9055_AUX_R_CTRL, 4, 1, 0), 616 SOC_DOUBLE_R("Mixin PGA ZC Switch", DA9055_MIXIN_L_CTRL, 617 DA9055_MIXIN_R_CTRL, 4, 1, 0), 618 SOC_DOUBLE_R("Headphone ZC Switch", DA9055_HP_L_CTRL, 619 DA9055_HP_R_CTRL, 4, 1, 0), 620 SOC_SINGLE("Lineout ZC Switch", DA9055_LINE_CTRL, 4, 1, 0), 621 622 /* Gain Ramping controls */ 623 SOC_DOUBLE_R("Aux Gain Ramping Switch", DA9055_AUX_L_CTRL, 624 DA9055_AUX_R_CTRL, 5, 1, 0), 625 SOC_DOUBLE_R("Mixin Gain Ramping Switch", DA9055_MIXIN_L_CTRL, 626 DA9055_MIXIN_R_CTRL, 5, 1, 0), 627 SOC_DOUBLE_R("ADC Gain Ramping Switch", DA9055_ADC_L_CTRL, 628 DA9055_ADC_R_CTRL, 5, 1, 0), 629 SOC_DOUBLE_R("DAC Gain Ramping Switch", DA9055_DAC_L_CTRL, 630 DA9055_DAC_R_CTRL, 5, 1, 0), 631 SOC_DOUBLE_R("Headphone Gain Ramping Switch", DA9055_HP_L_CTRL, 632 DA9055_HP_R_CTRL, 5, 1, 0), 633 SOC_SINGLE("Lineout Gain Ramping Switch", DA9055_LINE_CTRL, 5, 1, 0), 634 SOC_ENUM("Gain Ramping Rate", da9055_gain_ramping_rate), 635 636 /* DAC Noise Gate controls */ 637 SOC_SINGLE("DAC NG Switch", DA9055_DAC_NG_CTRL, 7, 1, 0), 638 SOC_SINGLE("DAC NG ON Threshold", DA9055_DAC_NG_ON_THRESHOLD, 639 0, 0x7, 0), 640 SOC_SINGLE("DAC NG OFF Threshold", DA9055_DAC_NG_OFF_THRESHOLD, 641 0, 0x7, 0), 642 SOC_ENUM("DAC NG Setup Time", da9055_dac_ng_setup_time), 643 SOC_ENUM("DAC NG Rampup Rate", da9055_dac_ng_rampup_rate), 644 SOC_ENUM("DAC NG Rampdown Rate", da9055_dac_ng_rampdown_rate), 645 646 /* DAC Invertion control */ 647 SOC_SINGLE("DAC Left Invert", DA9055_DIG_CTRL, 3, 1, 0), 648 SOC_SINGLE("DAC Right Invert", DA9055_DIG_CTRL, 7, 1, 0), 649 650 /* DMIC controls */ 651 SOC_DOUBLE_R("DMIC Switch", DA9055_MIXIN_L_SELECT, 652 DA9055_MIXIN_R_SELECT, 7, 1, 0), 653 654 /* ALC Controls */ 655 SOC_DOUBLE_EXT("ALC Switch", DA9055_ALC_CTRL1, 3, 7, 1, 0, 656 snd_soc_get_volsw, da9055_put_alc_sw), 657 SOC_SINGLE_EXT("ALC Sync Mode Switch", DA9055_ALC_CTRL1, 1, 1, 0, 658 snd_soc_get_volsw, da9055_put_alc_sw), 659 SOC_SINGLE("ALC Offset Switch", DA9055_ALC_CTRL1, 0, 1, 0), 660 SOC_SINGLE("ALC Anticlip Mode Switch", DA9055_ALC_ANTICLIP_CTRL, 661 7, 1, 0), 662 SOC_SINGLE("ALC Anticlip Level", DA9055_ALC_ANTICLIP_LEVEL, 663 0, 0x7f, 0), 664 SOC_SINGLE_TLV("ALC Min Threshold Volume", DA9055_ALC_TARGET_MIN, 665 0, 0x3f, 1, alc_threshold_tlv), 666 SOC_SINGLE_TLV("ALC Max Threshold Volume", DA9055_ALC_TARGET_MAX, 667 0, 0x3f, 1, alc_threshold_tlv), 668 SOC_SINGLE_TLV("ALC Noise Threshold Volume", DA9055_ALC_NOISE, 669 0, 0x3f, 1, alc_threshold_tlv), 670 SOC_SINGLE_TLV("ALC Max Gain Volume", DA9055_ALC_GAIN_LIMITS, 671 4, 0xf, 0, alc_gain_tlv), 672 SOC_SINGLE_TLV("ALC Max Attenuation Volume", DA9055_ALC_GAIN_LIMITS, 673 0, 0xf, 0, alc_gain_tlv), 674 SOC_SINGLE_TLV("ALC Min Analog Gain Volume", 675 DA9055_ALC_ANA_GAIN_LIMITS, 676 0, 0x7, 0, alc_analog_gain_tlv), 677 SOC_SINGLE_TLV("ALC Max Analog Gain Volume", 678 DA9055_ALC_ANA_GAIN_LIMITS, 679 4, 0x7, 0, alc_analog_gain_tlv), 680 SOC_ENUM("ALC Attack Rate", da9055_attack_rate), 681 SOC_ENUM("ALC Release Rate", da9055_release_rate), 682 SOC_ENUM("ALC Hold Time", da9055_hold_time), 683 /* 684 * Rate at which input signal envelope is tracked as the signal gets 685 * larger 686 */ 687 SOC_ENUM("ALC Integ Attack Rate", da9055_integ_attack_rate), 688 /* 689 * Rate at which input signal envelope is tracked as the signal gets 690 * smaller 691 */ 692 SOC_ENUM("ALC Integ Release Rate", da9055_integ_release_rate), 693 }; 694 695 /* DAPM Controls */ 696 697 /* Mic PGA Left Source */ 698 static const struct snd_kcontrol_new da9055_mic_l_mux_controls = 699 SOC_DAPM_ENUM("Route", da9055_mic_l_src); 700 701 /* Mic PGA Right Source */ 702 static const struct snd_kcontrol_new da9055_mic_r_mux_controls = 703 SOC_DAPM_ENUM("Route", da9055_mic_r_src); 704 705 /* In Mixer Left */ 706 static const struct snd_kcontrol_new da9055_dapm_mixinl_controls[] = { 707 SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXIN_L_SELECT, 0, 1, 0), 708 SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_L_SELECT, 1, 1, 0), 709 SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_L_SELECT, 2, 1, 0), 710 }; 711 712 /* In Mixer Right */ 713 static const struct snd_kcontrol_new da9055_dapm_mixinr_controls[] = { 714 SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXIN_R_SELECT, 0, 1, 0), 715 SOC_DAPM_SINGLE("Mic Right Switch", DA9055_MIXIN_R_SELECT, 1, 1, 0), 716 SOC_DAPM_SINGLE("Mic Left Switch", DA9055_MIXIN_R_SELECT, 2, 1, 0), 717 SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXIN_R_SELECT, 3, 1, 0), 718 }; 719 720 /* DAC Left Source */ 721 static const struct snd_kcontrol_new da9055_dac_l_mux_controls = 722 SOC_DAPM_ENUM("Route", da9055_dac_l_src); 723 724 /* DAC Right Source */ 725 static const struct snd_kcontrol_new da9055_dac_r_mux_controls = 726 SOC_DAPM_ENUM("Route", da9055_dac_r_src); 727 728 /* Out Mixer Left */ 729 static const struct snd_kcontrol_new da9055_dapm_mixoutl_controls[] = { 730 SOC_DAPM_SINGLE("Aux Left Switch", DA9055_MIXOUT_L_SELECT, 0, 1, 0), 731 SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_L_SELECT, 1, 1, 0), 732 SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_L_SELECT, 2, 1, 0), 733 SOC_DAPM_SINGLE("DAC Left Switch", DA9055_MIXOUT_L_SELECT, 3, 1, 0), 734 SOC_DAPM_SINGLE("Aux Left Invert Switch", DA9055_MIXOUT_L_SELECT, 735 4, 1, 0), 736 SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_L_SELECT, 737 5, 1, 0), 738 SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_L_SELECT, 739 6, 1, 0), 740 }; 741 742 /* Out Mixer Right */ 743 static const struct snd_kcontrol_new da9055_dapm_mixoutr_controls[] = { 744 SOC_DAPM_SINGLE("Aux Right Switch", DA9055_MIXOUT_R_SELECT, 0, 1, 0), 745 SOC_DAPM_SINGLE("Mixin Right Switch", DA9055_MIXOUT_R_SELECT, 1, 1, 0), 746 SOC_DAPM_SINGLE("Mixin Left Switch", DA9055_MIXOUT_R_SELECT, 2, 1, 0), 747 SOC_DAPM_SINGLE("DAC Right Switch", DA9055_MIXOUT_R_SELECT, 3, 1, 0), 748 SOC_DAPM_SINGLE("Aux Right Invert Switch", DA9055_MIXOUT_R_SELECT, 749 4, 1, 0), 750 SOC_DAPM_SINGLE("Mixin Right Invert Switch", DA9055_MIXOUT_R_SELECT, 751 5, 1, 0), 752 SOC_DAPM_SINGLE("Mixin Left Invert Switch", DA9055_MIXOUT_R_SELECT, 753 6, 1, 0), 754 }; 755 756 /* Headphone Output Enable */ 757 static const struct snd_kcontrol_new da9055_dapm_hp_l_control = 758 SOC_DAPM_SINGLE("Switch", DA9055_HP_L_CTRL, 3, 1, 0); 759 760 static const struct snd_kcontrol_new da9055_dapm_hp_r_control = 761 SOC_DAPM_SINGLE("Switch", DA9055_HP_R_CTRL, 3, 1, 0); 762 763 /* Lineout Output Enable */ 764 static const struct snd_kcontrol_new da9055_dapm_lineout_control = 765 SOC_DAPM_SINGLE("Switch", DA9055_LINE_CTRL, 3, 1, 0); 766 767 /* DAPM widgets */ 768 static const struct snd_soc_dapm_widget da9055_dapm_widgets[] = { 769 /* Input Side */ 770 771 /* Input Lines */ 772 SND_SOC_DAPM_INPUT("MIC1"), 773 SND_SOC_DAPM_INPUT("MIC2"), 774 SND_SOC_DAPM_INPUT("AUXL"), 775 SND_SOC_DAPM_INPUT("AUXR"), 776 777 /* MUXs for Mic PGA source selection */ 778 SND_SOC_DAPM_MUX("Mic Left Source", SND_SOC_NOPM, 0, 0, 779 &da9055_mic_l_mux_controls), 780 SND_SOC_DAPM_MUX("Mic Right Source", SND_SOC_NOPM, 0, 0, 781 &da9055_mic_r_mux_controls), 782 783 /* Input PGAs */ 784 SND_SOC_DAPM_PGA("Mic Left", DA9055_MIC_L_CTRL, 7, 0, NULL, 0), 785 SND_SOC_DAPM_PGA("Mic Right", DA9055_MIC_R_CTRL, 7, 0, NULL, 0), 786 SND_SOC_DAPM_PGA("Aux Left", DA9055_AUX_L_CTRL, 7, 0, NULL, 0), 787 SND_SOC_DAPM_PGA("Aux Right", DA9055_AUX_R_CTRL, 7, 0, NULL, 0), 788 SND_SOC_DAPM_PGA("MIXIN Left", DA9055_MIXIN_L_CTRL, 7, 0, NULL, 0), 789 SND_SOC_DAPM_PGA("MIXIN Right", DA9055_MIXIN_R_CTRL, 7, 0, NULL, 0), 790 791 SND_SOC_DAPM_SUPPLY("Mic Bias", DA9055_MIC_BIAS_CTRL, 7, 0, NULL, 0), 792 SND_SOC_DAPM_SUPPLY("AIF", DA9055_AIF_CTRL, 7, 0, NULL, 0), 793 SND_SOC_DAPM_SUPPLY("Charge Pump", DA9055_CP_CTRL, 7, 0, NULL, 0), 794 795 /* Input Mixers */ 796 SND_SOC_DAPM_MIXER("In Mixer Left", SND_SOC_NOPM, 0, 0, 797 &da9055_dapm_mixinl_controls[0], 798 ARRAY_SIZE(da9055_dapm_mixinl_controls)), 799 SND_SOC_DAPM_MIXER("In Mixer Right", SND_SOC_NOPM, 0, 0, 800 &da9055_dapm_mixinr_controls[0], 801 ARRAY_SIZE(da9055_dapm_mixinr_controls)), 802 803 /* ADCs */ 804 SND_SOC_DAPM_ADC("ADC Left", "Capture", DA9055_ADC_L_CTRL, 7, 0), 805 SND_SOC_DAPM_ADC("ADC Right", "Capture", DA9055_ADC_R_CTRL, 7, 0), 806 807 /* Output Side */ 808 809 /* MUXs for DAC source selection */ 810 SND_SOC_DAPM_MUX("DAC Left Source", SND_SOC_NOPM, 0, 0, 811 &da9055_dac_l_mux_controls), 812 SND_SOC_DAPM_MUX("DAC Right Source", SND_SOC_NOPM, 0, 0, 813 &da9055_dac_r_mux_controls), 814 815 /* AIF input */ 816 SND_SOC_DAPM_AIF_IN("AIFIN Left", "Playback", 0, SND_SOC_NOPM, 0, 0), 817 SND_SOC_DAPM_AIF_IN("AIFIN Right", "Playback", 0, SND_SOC_NOPM, 0, 0), 818 819 /* DACs */ 820 SND_SOC_DAPM_DAC("DAC Left", "Playback", DA9055_DAC_L_CTRL, 7, 0), 821 SND_SOC_DAPM_DAC("DAC Right", "Playback", DA9055_DAC_R_CTRL, 7, 0), 822 823 /* Output Mixers */ 824 SND_SOC_DAPM_MIXER("Out Mixer Left", SND_SOC_NOPM, 0, 0, 825 &da9055_dapm_mixoutl_controls[0], 826 ARRAY_SIZE(da9055_dapm_mixoutl_controls)), 827 SND_SOC_DAPM_MIXER("Out Mixer Right", SND_SOC_NOPM, 0, 0, 828 &da9055_dapm_mixoutr_controls[0], 829 ARRAY_SIZE(da9055_dapm_mixoutr_controls)), 830 831 /* Output Enable Switches */ 832 SND_SOC_DAPM_SWITCH("Headphone Left Enable", SND_SOC_NOPM, 0, 0, 833 &da9055_dapm_hp_l_control), 834 SND_SOC_DAPM_SWITCH("Headphone Right Enable", SND_SOC_NOPM, 0, 0, 835 &da9055_dapm_hp_r_control), 836 SND_SOC_DAPM_SWITCH("Lineout Enable", SND_SOC_NOPM, 0, 0, 837 &da9055_dapm_lineout_control), 838 839 /* Output PGAs */ 840 SND_SOC_DAPM_PGA("MIXOUT Left", DA9055_MIXOUT_L_CTRL, 7, 0, NULL, 0), 841 SND_SOC_DAPM_PGA("MIXOUT Right", DA9055_MIXOUT_R_CTRL, 7, 0, NULL, 0), 842 SND_SOC_DAPM_PGA("Lineout", DA9055_LINE_CTRL, 7, 0, NULL, 0), 843 SND_SOC_DAPM_PGA("Headphone Left", DA9055_HP_L_CTRL, 7, 0, NULL, 0), 844 SND_SOC_DAPM_PGA("Headphone Right", DA9055_HP_R_CTRL, 7, 0, NULL, 0), 845 846 /* Output Lines */ 847 SND_SOC_DAPM_OUTPUT("HPL"), 848 SND_SOC_DAPM_OUTPUT("HPR"), 849 SND_SOC_DAPM_OUTPUT("LINE"), 850 }; 851 852 /* DAPM audio route definition */ 853 static const struct snd_soc_dapm_route da9055_audio_map[] = { 854 /* Dest Connecting Widget source */ 855 856 /* Input path */ 857 {"Mic Left Source", "MIC1_P_N", "MIC1"}, 858 {"Mic Left Source", "MIC1_P", "MIC1"}, 859 {"Mic Left Source", "MIC1_N", "MIC1"}, 860 {"Mic Left Source", "MIC2_L", "MIC2"}, 861 862 {"Mic Right Source", "MIC2_R_L", "MIC2"}, 863 {"Mic Right Source", "MIC2_R", "MIC2"}, 864 {"Mic Right Source", "MIC2_L", "MIC2"}, 865 866 {"Mic Left", NULL, "Mic Left Source"}, 867 {"Mic Right", NULL, "Mic Right Source"}, 868 869 {"Aux Left", NULL, "AUXL"}, 870 {"Aux Right", NULL, "AUXR"}, 871 872 {"In Mixer Left", "Mic Left Switch", "Mic Left"}, 873 {"In Mixer Left", "Mic Right Switch", "Mic Right"}, 874 {"In Mixer Left", "Aux Left Switch", "Aux Left"}, 875 876 {"In Mixer Right", "Mic Right Switch", "Mic Right"}, 877 {"In Mixer Right", "Mic Left Switch", "Mic Left"}, 878 {"In Mixer Right", "Aux Right Switch", "Aux Right"}, 879 {"In Mixer Right", "Mixin Left Switch", "MIXIN Left"}, 880 881 {"MIXIN Left", NULL, "In Mixer Left"}, 882 {"ADC Left", NULL, "MIXIN Left"}, 883 884 {"MIXIN Right", NULL, "In Mixer Right"}, 885 {"ADC Right", NULL, "MIXIN Right"}, 886 887 {"ADC Left", NULL, "AIF"}, 888 {"ADC Right", NULL, "AIF"}, 889 890 /* Output path */ 891 {"AIFIN Left", NULL, "AIF"}, 892 {"AIFIN Right", NULL, "AIF"}, 893 894 {"DAC Left Source", "ADC output left", "ADC Left"}, 895 {"DAC Left Source", "ADC output right", "ADC Right"}, 896 {"DAC Left Source", "AIF input left", "AIFIN Left"}, 897 {"DAC Left Source", "AIF input right", "AIFIN Right"}, 898 899 {"DAC Right Source", "ADC output left", "ADC Left"}, 900 {"DAC Right Source", "ADC output right", "ADC Right"}, 901 {"DAC Right Source", "AIF input left", "AIFIN Left"}, 902 {"DAC Right Source", "AIF input right", "AIFIN Right"}, 903 904 {"DAC Left", NULL, "DAC Left Source"}, 905 {"DAC Right", NULL, "DAC Right Source"}, 906 907 {"Out Mixer Left", "Aux Left Switch", "Aux Left"}, 908 {"Out Mixer Left", "Mixin Left Switch", "MIXIN Left"}, 909 {"Out Mixer Left", "Mixin Right Switch", "MIXIN Right"}, 910 {"Out Mixer Left", "Aux Left Invert Switch", "Aux Left"}, 911 {"Out Mixer Left", "Mixin Left Invert Switch", "MIXIN Left"}, 912 {"Out Mixer Left", "Mixin Right Invert Switch", "MIXIN Right"}, 913 {"Out Mixer Left", "DAC Left Switch", "DAC Left"}, 914 915 {"Out Mixer Right", "Aux Right Switch", "Aux Right"}, 916 {"Out Mixer Right", "Mixin Right Switch", "MIXIN Right"}, 917 {"Out Mixer Right", "Mixin Left Switch", "MIXIN Left"}, 918 {"Out Mixer Right", "Aux Right Invert Switch", "Aux Right"}, 919 {"Out Mixer Right", "Mixin Right Invert Switch", "MIXIN Right"}, 920 {"Out Mixer Right", "Mixin Left Invert Switch", "MIXIN Left"}, 921 {"Out Mixer Right", "DAC Right Switch", "DAC Right"}, 922 923 {"MIXOUT Left", NULL, "Out Mixer Left"}, 924 {"Headphone Left Enable", "Switch", "MIXOUT Left"}, 925 {"Headphone Left", NULL, "Headphone Left Enable"}, 926 {"Headphone Left", NULL, "Charge Pump"}, 927 {"HPL", NULL, "Headphone Left"}, 928 929 {"MIXOUT Right", NULL, "Out Mixer Right"}, 930 {"Headphone Right Enable", "Switch", "MIXOUT Right"}, 931 {"Headphone Right", NULL, "Headphone Right Enable"}, 932 {"Headphone Right", NULL, "Charge Pump"}, 933 {"HPR", NULL, "Headphone Right"}, 934 935 {"MIXOUT Right", NULL, "Out Mixer Right"}, 936 {"Lineout Enable", "Switch", "MIXOUT Right"}, 937 {"Lineout", NULL, "Lineout Enable"}, 938 {"LINE", NULL, "Lineout"}, 939 }; 940 941 /* Codec private data */ 942 struct da9055_priv { 943 struct regmap *regmap; 944 unsigned int mclk_rate; 945 int master; 946 struct da9055_platform_data *pdata; 947 }; 948 949 static struct reg_default da9055_reg_defaults[] = { 950 { 0x21, 0x10 }, 951 { 0x22, 0x0A }, 952 { 0x23, 0x00 }, 953 { 0x24, 0x00 }, 954 { 0x25, 0x00 }, 955 { 0x26, 0x00 }, 956 { 0x27, 0x0C }, 957 { 0x28, 0x01 }, 958 { 0x29, 0x08 }, 959 { 0x2A, 0x32 }, 960 { 0x2B, 0x00 }, 961 { 0x30, 0x35 }, 962 { 0x31, 0x35 }, 963 { 0x32, 0x00 }, 964 { 0x33, 0x00 }, 965 { 0x34, 0x03 }, 966 { 0x35, 0x03 }, 967 { 0x36, 0x6F }, 968 { 0x37, 0x6F }, 969 { 0x38, 0x80 }, 970 { 0x39, 0x01 }, 971 { 0x3A, 0x01 }, 972 { 0x40, 0x00 }, 973 { 0x41, 0x88 }, 974 { 0x42, 0x88 }, 975 { 0x43, 0x08 }, 976 { 0x44, 0x80 }, 977 { 0x45, 0x6F }, 978 { 0x46, 0x6F }, 979 { 0x47, 0x61 }, 980 { 0x48, 0x35 }, 981 { 0x49, 0x35 }, 982 { 0x4A, 0x35 }, 983 { 0x4B, 0x00 }, 984 { 0x4C, 0x00 }, 985 { 0x60, 0x44 }, 986 { 0x61, 0x44 }, 987 { 0x62, 0x00 }, 988 { 0x63, 0x40 }, 989 { 0x64, 0x40 }, 990 { 0x65, 0x40 }, 991 { 0x66, 0x40 }, 992 { 0x67, 0x40 }, 993 { 0x68, 0x40 }, 994 { 0x69, 0x48 }, 995 { 0x6A, 0x40 }, 996 { 0x6B, 0x41 }, 997 { 0x6C, 0x40 }, 998 { 0x6D, 0x40 }, 999 { 0x6E, 0x10 }, 1000 { 0x6F, 0x10 }, 1001 { 0x90, 0x80 }, 1002 { 0x92, 0x02 }, 1003 { 0x93, 0x00 }, 1004 { 0x99, 0x00 }, 1005 { 0x9A, 0x00 }, 1006 { 0x9B, 0x00 }, 1007 { 0x9C, 0x3F }, 1008 { 0x9D, 0x00 }, 1009 { 0x9E, 0x3F }, 1010 { 0x9F, 0xFF }, 1011 { 0xA0, 0x71 }, 1012 { 0xA1, 0x00 }, 1013 { 0xA2, 0x00 }, 1014 { 0xA6, 0x00 }, 1015 { 0xA7, 0x00 }, 1016 { 0xAB, 0x00 }, 1017 { 0xAC, 0x00 }, 1018 { 0xAD, 0x00 }, 1019 { 0xAF, 0x08 }, 1020 { 0xB0, 0x00 }, 1021 { 0xB1, 0x00 }, 1022 { 0xB2, 0x00 }, 1023 }; 1024 1025 static bool da9055_volatile_register(struct device *dev, 1026 unsigned int reg) 1027 { 1028 switch (reg) { 1029 case DA9055_STATUS1: 1030 case DA9055_PLL_STATUS: 1031 case DA9055_AUX_L_GAIN_STATUS: 1032 case DA9055_AUX_R_GAIN_STATUS: 1033 case DA9055_MIC_L_GAIN_STATUS: 1034 case DA9055_MIC_R_GAIN_STATUS: 1035 case DA9055_MIXIN_L_GAIN_STATUS: 1036 case DA9055_MIXIN_R_GAIN_STATUS: 1037 case DA9055_ADC_L_GAIN_STATUS: 1038 case DA9055_ADC_R_GAIN_STATUS: 1039 case DA9055_DAC_L_GAIN_STATUS: 1040 case DA9055_DAC_R_GAIN_STATUS: 1041 case DA9055_HP_L_GAIN_STATUS: 1042 case DA9055_HP_R_GAIN_STATUS: 1043 case DA9055_LINE_GAIN_STATUS: 1044 case DA9055_ALC_CIC_OP_LVL_DATA: 1045 return 1; 1046 default: 1047 return 0; 1048 } 1049 } 1050 1051 /* Set DAI word length */ 1052 static int da9055_hw_params(struct snd_pcm_substream *substream, 1053 struct snd_pcm_hw_params *params, 1054 struct snd_soc_dai *dai) 1055 { 1056 struct snd_soc_codec *codec = dai->codec; 1057 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec); 1058 u8 aif_ctrl, fs; 1059 u32 sysclk; 1060 1061 switch (params_format(params)) { 1062 case SNDRV_PCM_FORMAT_S16_LE: 1063 aif_ctrl = DA9055_AIF_WORD_S16_LE; 1064 break; 1065 case SNDRV_PCM_FORMAT_S20_3LE: 1066 aif_ctrl = DA9055_AIF_WORD_S20_3LE; 1067 break; 1068 case SNDRV_PCM_FORMAT_S24_LE: 1069 aif_ctrl = DA9055_AIF_WORD_S24_LE; 1070 break; 1071 case SNDRV_PCM_FORMAT_S32_LE: 1072 aif_ctrl = DA9055_AIF_WORD_S32_LE; 1073 break; 1074 default: 1075 return -EINVAL; 1076 } 1077 1078 /* Set AIF format */ 1079 snd_soc_update_bits(codec, DA9055_AIF_CTRL, DA9055_AIF_WORD_LENGTH_MASK, 1080 aif_ctrl); 1081 1082 switch (params_rate(params)) { 1083 case 8000: 1084 fs = DA9055_SR_8000; 1085 sysclk = 3072000; 1086 break; 1087 case 11025: 1088 fs = DA9055_SR_11025; 1089 sysclk = 2822400; 1090 break; 1091 case 12000: 1092 fs = DA9055_SR_12000; 1093 sysclk = 3072000; 1094 break; 1095 case 16000: 1096 fs = DA9055_SR_16000; 1097 sysclk = 3072000; 1098 break; 1099 case 22050: 1100 fs = DA9055_SR_22050; 1101 sysclk = 2822400; 1102 break; 1103 case 32000: 1104 fs = DA9055_SR_32000; 1105 sysclk = 3072000; 1106 break; 1107 case 44100: 1108 fs = DA9055_SR_44100; 1109 sysclk = 2822400; 1110 break; 1111 case 48000: 1112 fs = DA9055_SR_48000; 1113 sysclk = 3072000; 1114 break; 1115 case 88200: 1116 fs = DA9055_SR_88200; 1117 sysclk = 2822400; 1118 break; 1119 case 96000: 1120 fs = DA9055_SR_96000; 1121 sysclk = 3072000; 1122 break; 1123 default: 1124 return -EINVAL; 1125 } 1126 1127 if (da9055->mclk_rate) { 1128 /* PLL Mode, Write actual FS */ 1129 snd_soc_write(codec, DA9055_SR, fs); 1130 } else { 1131 /* 1132 * Non-PLL Mode 1133 * When PLL is bypassed, chip assumes constant MCLK of 1134 * 12.288MHz and uses sample rate value to divide this MCLK 1135 * to derive its sys clk. As sys clk has to be 256 * Fs, we 1136 * need to write constant sample rate i.e. 48KHz. 1137 */ 1138 snd_soc_write(codec, DA9055_SR, DA9055_SR_48000); 1139 } 1140 1141 if (da9055->mclk_rate && (da9055->mclk_rate != sysclk)) { 1142 /* PLL Mode */ 1143 if (!da9055->master) { 1144 /* PLL slave mode, enable PLL and also SRM */ 1145 snd_soc_update_bits(codec, DA9055_PLL_CTRL, 1146 DA9055_PLL_EN | DA9055_PLL_SRM_EN, 1147 DA9055_PLL_EN | DA9055_PLL_SRM_EN); 1148 } else { 1149 /* PLL master mode, only enable PLL */ 1150 snd_soc_update_bits(codec, DA9055_PLL_CTRL, 1151 DA9055_PLL_EN, DA9055_PLL_EN); 1152 } 1153 } else { 1154 /* Non PLL Mode, disable PLL */ 1155 snd_soc_update_bits(codec, DA9055_PLL_CTRL, DA9055_PLL_EN, 0); 1156 } 1157 1158 return 0; 1159 } 1160 1161 /* Set DAI mode and Format */ 1162 static int da9055_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt) 1163 { 1164 struct snd_soc_codec *codec = codec_dai->codec; 1165 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec); 1166 u8 aif_clk_mode, aif_ctrl, mode; 1167 1168 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1169 case SND_SOC_DAIFMT_CBM_CFM: 1170 /* DA9055 in I2S Master Mode */ 1171 mode = 1; 1172 aif_clk_mode = DA9055_AIF_CLK_EN_MASTER_MODE; 1173 break; 1174 case SND_SOC_DAIFMT_CBS_CFS: 1175 /* DA9055 in I2S Slave Mode */ 1176 mode = 0; 1177 aif_clk_mode = DA9055_AIF_CLK_EN_SLAVE_MODE; 1178 break; 1179 default: 1180 return -EINVAL; 1181 } 1182 1183 /* Don't allow change of mode if PLL is enabled */ 1184 if ((snd_soc_read(codec, DA9055_PLL_CTRL) & DA9055_PLL_EN) && 1185 (da9055->master != mode)) 1186 return -EINVAL; 1187 1188 da9055->master = mode; 1189 1190 /* Only I2S is supported */ 1191 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1192 case SND_SOC_DAIFMT_I2S: 1193 aif_ctrl = DA9055_AIF_FORMAT_I2S_MODE; 1194 break; 1195 case SND_SOC_DAIFMT_LEFT_J: 1196 aif_ctrl = DA9055_AIF_FORMAT_LEFT_J; 1197 break; 1198 case SND_SOC_DAIFMT_RIGHT_J: 1199 aif_ctrl = DA9055_AIF_FORMAT_RIGHT_J; 1200 break; 1201 case SND_SOC_DAIFMT_DSP_A: 1202 aif_ctrl = DA9055_AIF_FORMAT_DSP; 1203 break; 1204 default: 1205 return -EINVAL; 1206 } 1207 1208 /* By default only 32 BCLK per WCLK is supported */ 1209 aif_clk_mode |= DA9055_AIF_BCLKS_PER_WCLK_32; 1210 1211 snd_soc_update_bits(codec, DA9055_AIF_CLK_MODE, 1212 (DA9055_AIF_CLK_MODE_MASK | DA9055_AIF_BCLK_MASK), 1213 aif_clk_mode); 1214 snd_soc_update_bits(codec, DA9055_AIF_CTRL, DA9055_AIF_FORMAT_MASK, 1215 aif_ctrl); 1216 return 0; 1217 } 1218 1219 static int da9055_mute(struct snd_soc_dai *dai, int mute) 1220 { 1221 struct snd_soc_codec *codec = dai->codec; 1222 1223 if (mute) { 1224 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL, 1225 DA9055_DAC_L_MUTE_EN, DA9055_DAC_L_MUTE_EN); 1226 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL, 1227 DA9055_DAC_R_MUTE_EN, DA9055_DAC_R_MUTE_EN); 1228 } else { 1229 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL, 1230 DA9055_DAC_L_MUTE_EN, 0); 1231 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL, 1232 DA9055_DAC_R_MUTE_EN, 0); 1233 } 1234 1235 return 0; 1236 } 1237 1238 #define DA9055_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\ 1239 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE) 1240 1241 static int da9055_set_dai_sysclk(struct snd_soc_dai *codec_dai, 1242 int clk_id, unsigned int freq, int dir) 1243 { 1244 struct snd_soc_codec *codec = codec_dai->codec; 1245 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec); 1246 1247 switch (clk_id) { 1248 case DA9055_CLKSRC_MCLK: 1249 switch (freq) { 1250 case 11289600: 1251 case 12000000: 1252 case 12288000: 1253 case 13000000: 1254 case 13500000: 1255 case 14400000: 1256 case 19200000: 1257 case 19680000: 1258 case 19800000: 1259 da9055->mclk_rate = freq; 1260 return 0; 1261 default: 1262 dev_err(codec_dai->dev, "Unsupported MCLK value %d\n", 1263 freq); 1264 return -EINVAL; 1265 } 1266 break; 1267 default: 1268 dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id); 1269 return -EINVAL; 1270 } 1271 } 1272 1273 /* 1274 * da9055_set_dai_pll : Configure the codec PLL 1275 * @param codec_dai : Pointer to codec DAI 1276 * @param pll_id : da9055 has only one pll, so pll_id is always zero 1277 * @param fref : Input MCLK frequency 1278 * @param fout : FsDM value 1279 * @return int : Zero for success, negative error code for error 1280 * 1281 * Note: Supported PLL input frequencies are 11.2896MHz, 12MHz, 12.288MHz, 1282 * 13MHz, 13.5MHz, 14.4MHz, 19.2MHz, 19.6MHz and 19.8MHz 1283 */ 1284 static int da9055_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id, 1285 int source, unsigned int fref, unsigned int fout) 1286 { 1287 struct snd_soc_codec *codec = codec_dai->codec; 1288 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec); 1289 1290 u8 pll_frac_top, pll_frac_bot, pll_integer, cnt; 1291 1292 /* Disable PLL before setting the divisors */ 1293 snd_soc_update_bits(codec, DA9055_PLL_CTRL, DA9055_PLL_EN, 0); 1294 1295 /* In slave mode, there is only one set of divisors */ 1296 if (!da9055->master && (fout != 2822400)) 1297 goto pll_err; 1298 1299 /* Search pll div array for correct divisors */ 1300 for (cnt = 0; cnt < ARRAY_SIZE(da9055_pll_div); cnt++) { 1301 /* Check fref, mode and fout */ 1302 if ((fref == da9055_pll_div[cnt].fref) && 1303 (da9055->master == da9055_pll_div[cnt].mode) && 1304 (fout == da9055_pll_div[cnt].fout)) { 1305 /* All match, pick up divisors */ 1306 pll_frac_top = da9055_pll_div[cnt].frac_top; 1307 pll_frac_bot = da9055_pll_div[cnt].frac_bot; 1308 pll_integer = da9055_pll_div[cnt].integer; 1309 break; 1310 } 1311 } 1312 if (cnt >= ARRAY_SIZE(da9055_pll_div)) 1313 goto pll_err; 1314 1315 /* Write PLL dividers */ 1316 snd_soc_write(codec, DA9055_PLL_FRAC_TOP, pll_frac_top); 1317 snd_soc_write(codec, DA9055_PLL_FRAC_BOT, pll_frac_bot); 1318 snd_soc_write(codec, DA9055_PLL_INTEGER, pll_integer); 1319 1320 return 0; 1321 pll_err: 1322 dev_err(codec_dai->dev, "Error in setting up PLL\n"); 1323 return -EINVAL; 1324 } 1325 1326 /* DAI operations */ 1327 static const struct snd_soc_dai_ops da9055_dai_ops = { 1328 .hw_params = da9055_hw_params, 1329 .set_fmt = da9055_set_dai_fmt, 1330 .set_sysclk = da9055_set_dai_sysclk, 1331 .set_pll = da9055_set_dai_pll, 1332 .digital_mute = da9055_mute, 1333 }; 1334 1335 static struct snd_soc_dai_driver da9055_dai = { 1336 .name = "da9055-hifi", 1337 /* Playback Capabilities */ 1338 .playback = { 1339 .stream_name = "Playback", 1340 .channels_min = 1, 1341 .channels_max = 2, 1342 .rates = SNDRV_PCM_RATE_8000_96000, 1343 .formats = DA9055_FORMATS, 1344 }, 1345 /* Capture Capabilities */ 1346 .capture = { 1347 .stream_name = "Capture", 1348 .channels_min = 1, 1349 .channels_max = 2, 1350 .rates = SNDRV_PCM_RATE_8000_96000, 1351 .formats = DA9055_FORMATS, 1352 }, 1353 .ops = &da9055_dai_ops, 1354 .symmetric_rates = 1, 1355 }; 1356 1357 static int da9055_set_bias_level(struct snd_soc_codec *codec, 1358 enum snd_soc_bias_level level) 1359 { 1360 switch (level) { 1361 case SND_SOC_BIAS_ON: 1362 case SND_SOC_BIAS_PREPARE: 1363 break; 1364 case SND_SOC_BIAS_STANDBY: 1365 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { 1366 /* Enable VMID reference & master bias */ 1367 snd_soc_update_bits(codec, DA9055_REFERENCES, 1368 DA9055_VMID_EN | DA9055_BIAS_EN, 1369 DA9055_VMID_EN | DA9055_BIAS_EN); 1370 } 1371 break; 1372 case SND_SOC_BIAS_OFF: 1373 /* Disable VMID reference & master bias */ 1374 snd_soc_update_bits(codec, DA9055_REFERENCES, 1375 DA9055_VMID_EN | DA9055_BIAS_EN, 0); 1376 break; 1377 } 1378 codec->dapm.bias_level = level; 1379 return 0; 1380 } 1381 1382 static int da9055_probe(struct snd_soc_codec *codec) 1383 { 1384 int ret; 1385 struct da9055_priv *da9055 = snd_soc_codec_get_drvdata(codec); 1386 1387 codec->control_data = da9055->regmap; 1388 ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_REGMAP); 1389 if (ret < 0) { 1390 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret); 1391 return ret; 1392 } 1393 1394 /* Enable all Gain Ramps */ 1395 snd_soc_update_bits(codec, DA9055_AUX_L_CTRL, 1396 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1397 snd_soc_update_bits(codec, DA9055_AUX_R_CTRL, 1398 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1399 snd_soc_update_bits(codec, DA9055_MIXIN_L_CTRL, 1400 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1401 snd_soc_update_bits(codec, DA9055_MIXIN_R_CTRL, 1402 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1403 snd_soc_update_bits(codec, DA9055_ADC_L_CTRL, 1404 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1405 snd_soc_update_bits(codec, DA9055_ADC_R_CTRL, 1406 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1407 snd_soc_update_bits(codec, DA9055_DAC_L_CTRL, 1408 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1409 snd_soc_update_bits(codec, DA9055_DAC_R_CTRL, 1410 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1411 snd_soc_update_bits(codec, DA9055_HP_L_CTRL, 1412 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1413 snd_soc_update_bits(codec, DA9055_HP_R_CTRL, 1414 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1415 snd_soc_update_bits(codec, DA9055_LINE_CTRL, 1416 DA9055_GAIN_RAMPING_EN, DA9055_GAIN_RAMPING_EN); 1417 1418 /* 1419 * There are two separate control bits for input and output mixers. 1420 * One to enable corresponding amplifier and other to enable its 1421 * output. As amplifier bits are related to power control, they are 1422 * being managed by DAPM while other (non power related) bits are 1423 * enabled here 1424 */ 1425 snd_soc_update_bits(codec, DA9055_MIXIN_L_CTRL, 1426 DA9055_MIXIN_L_MIX_EN, DA9055_MIXIN_L_MIX_EN); 1427 snd_soc_update_bits(codec, DA9055_MIXIN_R_CTRL, 1428 DA9055_MIXIN_R_MIX_EN, DA9055_MIXIN_R_MIX_EN); 1429 1430 snd_soc_update_bits(codec, DA9055_MIXOUT_L_CTRL, 1431 DA9055_MIXOUT_L_MIX_EN, DA9055_MIXOUT_L_MIX_EN); 1432 snd_soc_update_bits(codec, DA9055_MIXOUT_R_CTRL, 1433 DA9055_MIXOUT_R_MIX_EN, DA9055_MIXOUT_R_MIX_EN); 1434 1435 /* Set this as per your system configuration */ 1436 snd_soc_write(codec, DA9055_PLL_CTRL, DA9055_PLL_INDIV_10_20_MHZ); 1437 1438 /* Set platform data values */ 1439 if (da9055->pdata) { 1440 /* set mic bias source */ 1441 if (da9055->pdata->micbias_source) { 1442 snd_soc_update_bits(codec, DA9055_MIXIN_R_SELECT, 1443 DA9055_MICBIAS2_EN, 1444 DA9055_MICBIAS2_EN); 1445 } else { 1446 snd_soc_update_bits(codec, DA9055_MIXIN_R_SELECT, 1447 DA9055_MICBIAS2_EN, 0); 1448 } 1449 /* set mic bias voltage */ 1450 switch (da9055->pdata->micbias) { 1451 case DA9055_MICBIAS_2_2V: 1452 case DA9055_MICBIAS_2_1V: 1453 case DA9055_MICBIAS_1_8V: 1454 case DA9055_MICBIAS_1_6V: 1455 snd_soc_update_bits(codec, DA9055_MIC_CONFIG, 1456 DA9055_MICBIAS_LEVEL_MASK, 1457 (da9055->pdata->micbias) << 4); 1458 break; 1459 } 1460 } 1461 return 0; 1462 } 1463 1464 static struct snd_soc_codec_driver soc_codec_dev_da9055 = { 1465 .probe = da9055_probe, 1466 .set_bias_level = da9055_set_bias_level, 1467 1468 .controls = da9055_snd_controls, 1469 .num_controls = ARRAY_SIZE(da9055_snd_controls), 1470 1471 .dapm_widgets = da9055_dapm_widgets, 1472 .num_dapm_widgets = ARRAY_SIZE(da9055_dapm_widgets), 1473 .dapm_routes = da9055_audio_map, 1474 .num_dapm_routes = ARRAY_SIZE(da9055_audio_map), 1475 }; 1476 1477 static const struct regmap_config da9055_regmap_config = { 1478 .reg_bits = 8, 1479 .val_bits = 8, 1480 1481 .reg_defaults = da9055_reg_defaults, 1482 .num_reg_defaults = ARRAY_SIZE(da9055_reg_defaults), 1483 .volatile_reg = da9055_volatile_register, 1484 .cache_type = REGCACHE_RBTREE, 1485 }; 1486 1487 static int da9055_i2c_probe(struct i2c_client *i2c, 1488 const struct i2c_device_id *id) 1489 { 1490 struct da9055_priv *da9055; 1491 struct da9055_platform_data *pdata = dev_get_platdata(&i2c->dev); 1492 int ret; 1493 1494 da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055_priv), 1495 GFP_KERNEL); 1496 if (!da9055) 1497 return -ENOMEM; 1498 1499 if (pdata) 1500 da9055->pdata = pdata; 1501 1502 i2c_set_clientdata(i2c, da9055); 1503 1504 da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config); 1505 if (IS_ERR(da9055->regmap)) { 1506 ret = PTR_ERR(da9055->regmap); 1507 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret); 1508 return ret; 1509 } 1510 1511 ret = snd_soc_register_codec(&i2c->dev, 1512 &soc_codec_dev_da9055, &da9055_dai, 1); 1513 if (ret < 0) { 1514 dev_err(&i2c->dev, "Failed to register da9055 codec: %d\n", 1515 ret); 1516 } 1517 return ret; 1518 } 1519 1520 static int da9055_remove(struct i2c_client *client) 1521 { 1522 snd_soc_unregister_codec(&client->dev); 1523 return 0; 1524 } 1525 1526 static const struct i2c_device_id da9055_i2c_id[] = { 1527 { "da9055", 0 }, 1528 { } 1529 }; 1530 MODULE_DEVICE_TABLE(i2c, da9055_i2c_id); 1531 1532 /* I2C codec control layer */ 1533 static struct i2c_driver da9055_i2c_driver = { 1534 .driver = { 1535 .name = "da9055", 1536 .owner = THIS_MODULE, 1537 }, 1538 .probe = da9055_i2c_probe, 1539 .remove = da9055_remove, 1540 .id_table = da9055_i2c_id, 1541 }; 1542 1543 module_i2c_driver(da9055_i2c_driver); 1544 1545 MODULE_DESCRIPTION("ASoC DA9055 Codec driver"); 1546 MODULE_AUTHOR("David Chen, Ashish Chavan"); 1547 MODULE_LICENSE("GPL"); 1548