1a497a436SSimon Ho /* SPDX-License-Identifier: GPL-2.0 */ 2a497a436SSimon Ho /* 3a497a436SSimon Ho * ALSA SoC CX20721/CX20723 codec driver 4a497a436SSimon Ho * 5a497a436SSimon Ho * Copyright: (C) 2017 Conexant Systems, Inc. 6a497a436SSimon Ho * Author: Simon Ho, <Simon.ho@conexant.com> 7a497a436SSimon Ho */ 8a497a436SSimon Ho 9a497a436SSimon Ho #ifndef __CX2072X_H__ 10a497a436SSimon Ho #define __CX2072X_H__ 11a497a436SSimon Ho 12a497a436SSimon Ho #define CX2072X_MCLK_PLL 1 13a497a436SSimon Ho #define CX2072X_MCLK_EXTERNAL_PLL 1 14a497a436SSimon Ho #define CX2072X_MCLK_INTERNAL_OSC 2 15a497a436SSimon Ho 16a497a436SSimon Ho /*#define CX2072X_RATES SNDRV_PCM_RATE_8000_192000*/ 17a497a436SSimon Ho #define CX2072X_RATES_DSP SNDRV_PCM_RATE_48000 18a497a436SSimon Ho 19a497a436SSimon Ho #define CX2072X_REG_MAX 0x8a3c 20a497a436SSimon Ho 21a497a436SSimon Ho #define CX2072X_VENDOR_ID 0x0200 22a497a436SSimon Ho #define CX2072X_REVISION_ID 0x0208 23a497a436SSimon Ho #define CX2072X_CURRENT_BCLK_FREQUENCY 0x00dc 24a497a436SSimon Ho #define CX2072X_AFG_POWER_STATE 0x0414 25a497a436SSimon Ho #define CX2072X_UM_RESPONSE 0x0420 26a497a436SSimon Ho #define CX2072X_GPIO_DATA 0x0454 27a497a436SSimon Ho #define CX2072X_GPIO_ENABLE 0x0458 28a497a436SSimon Ho #define CX2072X_GPIO_DIRECTION 0x045c 29a497a436SSimon Ho #define CX2072X_GPIO_WAKE 0x0460 30a497a436SSimon Ho #define CX2072X_GPIO_UM_ENABLE 0x0464 31a497a436SSimon Ho #define CX2072X_GPIO_STICKY_MASK 0x0468 32a497a436SSimon Ho #define CX2072X_AFG_FUNCTION_RESET 0x07fc 33a497a436SSimon Ho #define CX2072X_DAC1_CONVERTER_FORMAT 0x43c8 34a497a436SSimon Ho #define CX2072X_DAC1_AMP_GAIN_RIGHT 0x41c0 35a497a436SSimon Ho #define CX2072X_DAC1_AMP_GAIN_LEFT 0x41e0 36a497a436SSimon Ho #define CX2072X_DAC1_POWER_STATE 0x4014 37a497a436SSimon Ho #define CX2072X_DAC1_CONVERTER_STREAM_CHANNEL 0x4018 38a497a436SSimon Ho #define CX2072X_DAC1_EAPD_ENABLE 0x4030 39a497a436SSimon Ho #define CX2072X_DAC2_CONVERTER_FORMAT 0x47c8 40a497a436SSimon Ho #define CX2072X_DAC2_AMP_GAIN_RIGHT 0x45c0 41a497a436SSimon Ho #define CX2072X_DAC2_AMP_GAIN_LEFT 0x45e0 42a497a436SSimon Ho #define CX2072X_DAC2_POWER_STATE 0x4414 43a497a436SSimon Ho #define CX2072X_DAC2_CONVERTER_STREAM_CHANNEL 0x4418 44a497a436SSimon Ho #define CX2072X_ADC1_CONVERTER_FORMAT 0x4fc8 45a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_RIGHT_0 0x4d80 46a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_LEFT_0 0x4da0 47a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_RIGHT_1 0x4d84 48a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_LEFT_1 0x4da4 49a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_RIGHT_2 0x4d88 50a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_LEFT_2 0x4da8 51a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_RIGHT_3 0x4d8c 52a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_LEFT_3 0x4dac 53a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_RIGHT_4 0x4d90 54a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_LEFT_4 0x4db0 55a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_RIGHT_5 0x4d94 56a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_LEFT_5 0x4db4 57a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_RIGHT_6 0x4d98 58a497a436SSimon Ho #define CX2072X_ADC1_AMP_GAIN_LEFT_6 0x4db8 59a497a436SSimon Ho #define CX2072X_ADC1_CONNECTION_SELECT_CONTROL 0x4c04 60a497a436SSimon Ho #define CX2072X_ADC1_POWER_STATE 0x4c14 61a497a436SSimon Ho #define CX2072X_ADC1_CONVERTER_STREAM_CHANNEL 0x4c18 62a497a436SSimon Ho #define CX2072X_ADC2_CONVERTER_FORMAT 0x53c8 63a497a436SSimon Ho #define CX2072X_ADC2_AMP_GAIN_RIGHT_0 0x5180 64a497a436SSimon Ho #define CX2072X_ADC2_AMP_GAIN_LEFT_0 0x51a0 65a497a436SSimon Ho #define CX2072X_ADC2_AMP_GAIN_RIGHT_1 0x5184 66a497a436SSimon Ho #define CX2072X_ADC2_AMP_GAIN_LEFT_1 0x51a4 67a497a436SSimon Ho #define CX2072X_ADC2_AMP_GAIN_RIGHT_2 0x5188 68a497a436SSimon Ho #define CX2072X_ADC2_AMP_GAIN_LEFT_2 0x51a8 69a497a436SSimon Ho #define CX2072X_ADC2_CONNECTION_SELECT_CONTROL 0x5004 70a497a436SSimon Ho #define CX2072X_ADC2_POWER_STATE 0x5014 71a497a436SSimon Ho #define CX2072X_ADC2_CONVERTER_STREAM_CHANNEL 0x5018 72a497a436SSimon Ho #define CX2072X_PORTA_CONNECTION_SELECT_CTRL 0x5804 73a497a436SSimon Ho #define CX2072X_PORTA_POWER_STATE 0x5814 74a497a436SSimon Ho #define CX2072X_PORTA_PIN_CTRL 0x581c 75a497a436SSimon Ho #define CX2072X_PORTA_UNSOLICITED_RESPONSE 0x5820 76a497a436SSimon Ho #define CX2072X_PORTA_PIN_SENSE 0x5824 77a497a436SSimon Ho #define CX2072X_PORTA_EAPD_BTL 0x5830 78a497a436SSimon Ho #define CX2072X_PORTB_POWER_STATE 0x6014 79a497a436SSimon Ho #define CX2072X_PORTB_PIN_CTRL 0x601c 80a497a436SSimon Ho #define CX2072X_PORTB_UNSOLICITED_RESPONSE 0x6020 81a497a436SSimon Ho #define CX2072X_PORTB_PIN_SENSE 0x6024 82a497a436SSimon Ho #define CX2072X_PORTB_EAPD_BTL 0x6030 83a497a436SSimon Ho #define CX2072X_PORTB_GAIN_RIGHT 0x6180 84a497a436SSimon Ho #define CX2072X_PORTB_GAIN_LEFT 0x61a0 85a497a436SSimon Ho #define CX2072X_PORTC_POWER_STATE 0x6814 86a497a436SSimon Ho #define CX2072X_PORTC_PIN_CTRL 0x681c 87a497a436SSimon Ho #define CX2072X_PORTC_GAIN_RIGHT 0x6980 88a497a436SSimon Ho #define CX2072X_PORTC_GAIN_LEFT 0x69a0 89a497a436SSimon Ho #define CX2072X_PORTD_POWER_STATE 0x6414 90a497a436SSimon Ho #define CX2072X_PORTD_PIN_CTRL 0x641c 91a497a436SSimon Ho #define CX2072X_PORTD_UNSOLICITED_RESPONSE 0x6420 92a497a436SSimon Ho #define CX2072X_PORTD_PIN_SENSE 0x6424 93a497a436SSimon Ho #define CX2072X_PORTD_GAIN_RIGHT 0x6580 94a497a436SSimon Ho #define CX2072X_PORTD_GAIN_LEFT 0x65a0 95a497a436SSimon Ho #define CX2072X_PORTE_CONNECTION_SELECT_CTRL 0x7404 96a497a436SSimon Ho #define CX2072X_PORTE_POWER_STATE 0x7414 97a497a436SSimon Ho #define CX2072X_PORTE_PIN_CTRL 0x741c 98a497a436SSimon Ho #define CX2072X_PORTE_UNSOLICITED_RESPONSE 0x7420 99a497a436SSimon Ho #define CX2072X_PORTE_PIN_SENSE 0x7424 100a497a436SSimon Ho #define CX2072X_PORTE_EAPD_BTL 0x7430 101a497a436SSimon Ho #define CX2072X_PORTE_GAIN_RIGHT 0x7580 102a497a436SSimon Ho #define CX2072X_PORTE_GAIN_LEFT 0x75a0 103a497a436SSimon Ho #define CX2072X_PORTF_POWER_STATE 0x7814 104a497a436SSimon Ho #define CX2072X_PORTF_PIN_CTRL 0x781c 105a497a436SSimon Ho #define CX2072X_PORTF_UNSOLICITED_RESPONSE 0x7820 106a497a436SSimon Ho #define CX2072X_PORTF_PIN_SENSE 0x7824 107a497a436SSimon Ho #define CX2072X_PORTF_GAIN_RIGHT 0x7980 108a497a436SSimon Ho #define CX2072X_PORTF_GAIN_LEFT 0x79a0 109a497a436SSimon Ho #define CX2072X_PORTG_POWER_STATE 0x5c14 110a497a436SSimon Ho #define CX2072X_PORTG_PIN_CTRL 0x5c1c 111a497a436SSimon Ho #define CX2072X_PORTG_CONNECTION_SELECT_CTRL 0x5c04 112a497a436SSimon Ho #define CX2072X_PORTG_EAPD_BTL 0x5c30 113a497a436SSimon Ho #define CX2072X_PORTM_POWER_STATE 0x8814 114a497a436SSimon Ho #define CX2072X_PORTM_PIN_CTRL 0x881c 115a497a436SSimon Ho #define CX2072X_PORTM_CONNECTION_SELECT_CTRL 0x8804 116a497a436SSimon Ho #define CX2072X_PORTM_EAPD_BTL 0x8830 117a497a436SSimon Ho #define CX2072X_MIXER_POWER_STATE 0x5414 118a497a436SSimon Ho #define CX2072X_MIXER_GAIN_RIGHT_0 0x5580 119a497a436SSimon Ho #define CX2072X_MIXER_GAIN_LEFT_0 0x55a0 120a497a436SSimon Ho #define CX2072X_MIXER_GAIN_RIGHT_1 0x5584 121a497a436SSimon Ho #define CX2072X_MIXER_GAIN_LEFT_1 0x55a4 122a497a436SSimon Ho #define CX2072X_EQ_ENABLE_BYPASS 0x6d00 123a497a436SSimon Ho #define CX2072X_EQ_B0_COEFF 0x6d02 124a497a436SSimon Ho #define CX2072X_EQ_B1_COEFF 0x6d04 125a497a436SSimon Ho #define CX2072X_EQ_B2_COEFF 0x6d06 126a497a436SSimon Ho #define CX2072X_EQ_A1_COEFF 0x6d08 127a497a436SSimon Ho #define CX2072X_EQ_A2_COEFF 0x6d0a 128a497a436SSimon Ho #define CX2072X_EQ_G_COEFF 0x6d0c 129a497a436SSimon Ho #define CX2072X_EQ_BAND 0x6d0d 130a497a436SSimon Ho #define CX2072X_SPKR_DRC_ENABLE_STEP 0x6d10 131a497a436SSimon Ho #define CX2072X_SPKR_DRC_CONTROL 0x6d14 132a497a436SSimon Ho #define CX2072X_SPKR_DRC_TEST 0x6d18 133a497a436SSimon Ho #define CX2072X_DIGITAL_BIOS_TEST0 0x6d80 134a497a436SSimon Ho #define CX2072X_DIGITAL_BIOS_TEST2 0x6d84 135a497a436SSimon Ho #define CX2072X_I2SPCM_CONTROL1 0x6e00 136a497a436SSimon Ho #define CX2072X_I2SPCM_CONTROL2 0x6e04 137a497a436SSimon Ho #define CX2072X_I2SPCM_CONTROL3 0x6e08 138a497a436SSimon Ho #define CX2072X_I2SPCM_CONTROL4 0x6e0c 139a497a436SSimon Ho #define CX2072X_I2SPCM_CONTROL5 0x6e10 140a497a436SSimon Ho #define CX2072X_I2SPCM_CONTROL6 0x6e18 141a497a436SSimon Ho #define CX2072X_UM_INTERRUPT_CRTL_E 0x6e14 142a497a436SSimon Ho #define CX2072X_CODEC_TEST2 0x7108 143a497a436SSimon Ho #define CX2072X_CODEC_TEST9 0x7124 144a497a436SSimon Ho #define CX2072X_CODEC_TESTXX 0x7290 145a497a436SSimon Ho #define CX2072X_CODEC_TEST20 0x7310 146a497a436SSimon Ho #define CX2072X_CODEC_TEST24 0x731c 147a497a436SSimon Ho #define CX2072X_CODEC_TEST26 0x7328 148a497a436SSimon Ho #define CX2072X_ANALOG_TEST3 0x718c 149a497a436SSimon Ho #define CX2072X_ANALOG_TEST4 0x7190 150a497a436SSimon Ho #define CX2072X_ANALOG_TEST5 0x7194 151a497a436SSimon Ho #define CX2072X_ANALOG_TEST6 0x7198 152a497a436SSimon Ho #define CX2072X_ANALOG_TEST7 0x719c 153a497a436SSimon Ho #define CX2072X_ANALOG_TEST8 0x71a0 154a497a436SSimon Ho #define CX2072X_ANALOG_TEST9 0x71a4 155a497a436SSimon Ho #define CX2072X_ANALOG_TEST10 0x71a8 156a497a436SSimon Ho #define CX2072X_ANALOG_TEST11 0x71ac 157a497a436SSimon Ho #define CX2072X_ANALOG_TEST12 0x71b0 158a497a436SSimon Ho #define CX2072X_ANALOG_TEST13 0x71b4 159a497a436SSimon Ho #define CX2072X_DIGITAL_TEST0 0x7200 160a497a436SSimon Ho #define CX2072X_DIGITAL_TEST1 0x7204 161a497a436SSimon Ho #define CX2072X_DIGITAL_TEST11 0x722c 162a497a436SSimon Ho #define CX2072X_DIGITAL_TEST12 0x7230 163a497a436SSimon Ho #define CX2072X_DIGITAL_TEST15 0x723c 164a497a436SSimon Ho #define CX2072X_DIGITAL_TEST16 0x7080 165a497a436SSimon Ho #define CX2072X_DIGITAL_TEST17 0x7084 166a497a436SSimon Ho #define CX2072X_DIGITAL_TEST18 0x7088 167a497a436SSimon Ho #define CX2072X_DIGITAL_TEST19 0x708c 168a497a436SSimon Ho #define CX2072X_DIGITAL_TEST20 0x7090 169a497a436SSimon Ho 170a497a436SSimon Ho /* not used in the current code, for future extensions (if any) */ 171a497a436SSimon Ho #define CX2072X_MAX_EQ_BAND 7 172a497a436SSimon Ho #define CX2072X_MAX_EQ_COEFF 11 173a497a436SSimon Ho #define CX2072X_MAX_DRC_REGS 9 174a497a436SSimon Ho #define CX2072X_MIC_EQ_COEFF 10 175a497a436SSimon Ho #define CX2072X_PLBK_EQ_BAND_NUM 7 176a497a436SSimon Ho #define CX2072X_PLBK_EQ_COEF_LEN 11 177a497a436SSimon Ho #define CX2072X_PLBK_DRC_PARM_LEN 9 178a497a436SSimon Ho #define CX2072X_CLASSD_AMP_LEN 6 179a497a436SSimon Ho 180a497a436SSimon Ho /* DAI interfae type */ 181a497a436SSimon Ho #define CX2072X_DAI_HIFI 1 182a497a436SSimon Ho #define CX2072X_DAI_DSP 2 183a497a436SSimon Ho #define CX2072X_DAI_DSP_PWM 3 /* 4 ch, including mic and AEC */ 184a497a436SSimon Ho 185a497a436SSimon Ho enum cx2072x_reg_sample_size { 186a497a436SSimon Ho CX2072X_SAMPLE_SIZE_8_BITS = 0, 187a497a436SSimon Ho CX2072X_SAMPLE_SIZE_16_BITS = 1, 188a497a436SSimon Ho CX2072X_SAMPLE_SIZE_24_BITS = 2, 189a497a436SSimon Ho CX2072X_SAMPLE_SIZE_RESERVED = 3, 190a497a436SSimon Ho }; 191a497a436SSimon Ho 192a497a436SSimon Ho union cx2072x_reg_i2spcm_ctrl_reg1 { 193a497a436SSimon Ho struct { 194a497a436SSimon Ho u32 rx_data_one_line:1; 195a497a436SSimon Ho u32 rx_ws_pol:1; 196a497a436SSimon Ho u32 rx_ws_wid:7; 197a497a436SSimon Ho u32 rx_frm_len:5; 198a497a436SSimon Ho u32 rx_sa_size:2; 199a497a436SSimon Ho u32 tx_data_one_line:1; 200a497a436SSimon Ho u32 tx_ws_pol:1; 201a497a436SSimon Ho u32 tx_ws_wid:7; 202a497a436SSimon Ho u32 tx_frm_len:5; 203a497a436SSimon Ho u32 tx_sa_size:2; 204a497a436SSimon Ho } r; 205a497a436SSimon Ho u32 ulval; 206a497a436SSimon Ho }; 207a497a436SSimon Ho 208a497a436SSimon Ho union cx2072x_reg_i2spcm_ctrl_reg2 { 209a497a436SSimon Ho struct { 210a497a436SSimon Ho u32 tx_en_ch1:1; 211a497a436SSimon Ho u32 tx_en_ch2:1; 212a497a436SSimon Ho u32 tx_en_ch3:1; 213a497a436SSimon Ho u32 tx_en_ch4:1; 214a497a436SSimon Ho u32 tx_en_ch5:1; 215a497a436SSimon Ho u32 tx_en_ch6:1; 216a497a436SSimon Ho u32 tx_slot_1:5; 217a497a436SSimon Ho u32 tx_slot_2:5; 218a497a436SSimon Ho u32 tx_slot_3:5; 219a497a436SSimon Ho u32 tx_slot_4:5; 220a497a436SSimon Ho u32 res:1; 221a497a436SSimon Ho u32 tx_data_neg_bclk:1; 222a497a436SSimon Ho u32 tx_master:1; 223a497a436SSimon Ho u32 tx_tri_n:1; 224a497a436SSimon Ho u32 tx_endian_sel:1; 225a497a436SSimon Ho u32 tx_dstart_dly:1; 226a497a436SSimon Ho } r; 227a497a436SSimon Ho u32 ulval; 228a497a436SSimon Ho }; 229a497a436SSimon Ho 230a497a436SSimon Ho union cx2072x_reg_i2spcm_ctrl_reg3 { 231a497a436SSimon Ho struct { 232a497a436SSimon Ho u32 rx_en_ch1:1; 233a497a436SSimon Ho u32 rx_en_ch2:1; 234a497a436SSimon Ho u32 rx_en_ch3:1; 235a497a436SSimon Ho u32 rx_en_ch4:1; 236a497a436SSimon Ho u32 rx_en_ch5:1; 237a497a436SSimon Ho u32 rx_en_ch6:1; 238a497a436SSimon Ho u32 rx_slot_1:5; 239a497a436SSimon Ho u32 rx_slot_2:5; 240a497a436SSimon Ho u32 rx_slot_3:5; 241a497a436SSimon Ho u32 rx_slot_4:5; 242a497a436SSimon Ho u32 res:1; 243a497a436SSimon Ho u32 rx_data_neg_bclk:1; 244a497a436SSimon Ho u32 rx_master:1; 245a497a436SSimon Ho u32 rx_tri_n:1; 246a497a436SSimon Ho u32 rx_endian_sel:1; 247a497a436SSimon Ho u32 rx_dstart_dly:1; 248a497a436SSimon Ho } r; 249a497a436SSimon Ho u32 ulval; 250a497a436SSimon Ho }; 251a497a436SSimon Ho 252a497a436SSimon Ho union cx2072x_reg_i2spcm_ctrl_reg4 { 253a497a436SSimon Ho struct { 254a497a436SSimon Ho u32 rx_mute:1; 255a497a436SSimon Ho u32 tx_mute:1; 256a497a436SSimon Ho u32 reserved:1; 257a497a436SSimon Ho u32 dac_34_independent:1; 258a497a436SSimon Ho u32 dac_bclk_lrck_share:1; 259a497a436SSimon Ho u32 bclk_lrck_share_en:1; 260a497a436SSimon Ho u32 reserved2:2; 261a497a436SSimon Ho u32 rx_last_dac_ch_en:1; 262a497a436SSimon Ho u32 rx_last_dac_ch:3; 263a497a436SSimon Ho u32 tx_last_adc_ch_en:1; 264a497a436SSimon Ho u32 tx_last_adc_ch:3; 265a497a436SSimon Ho u32 rx_slot_5:5; 266a497a436SSimon Ho u32 rx_slot_6:5; 267a497a436SSimon Ho u32 reserved3:6; 268a497a436SSimon Ho } r; 269a497a436SSimon Ho u32 ulval; 270a497a436SSimon Ho }; 271a497a436SSimon Ho 272a497a436SSimon Ho union cx2072x_reg_i2spcm_ctrl_reg5 { 273a497a436SSimon Ho struct { 274a497a436SSimon Ho u32 tx_slot_5:5; 275a497a436SSimon Ho u32 reserved:3; 276a497a436SSimon Ho u32 tx_slot_6:5; 277a497a436SSimon Ho u32 reserved2:3; 278a497a436SSimon Ho u32 reserved3:8; 279a497a436SSimon Ho u32 i2s_pcm_clk_div:7; 280a497a436SSimon Ho u32 i2s_pcm_clk_div_chan_en:1; 281a497a436SSimon Ho } r; 282a497a436SSimon Ho u32 ulval; 283a497a436SSimon Ho }; 284a497a436SSimon Ho 285a497a436SSimon Ho union cx2072x_reg_i2spcm_ctrl_reg6 { 286a497a436SSimon Ho struct { 287a497a436SSimon Ho u32 reserved:5; 288a497a436SSimon Ho u32 rx_pause_cycles:3; 289a497a436SSimon Ho u32 rx_pause_start_pos:8; 290a497a436SSimon Ho u32 reserved2:5; 291a497a436SSimon Ho u32 tx_pause_cycles:3; 292a497a436SSimon Ho u32 tx_pause_start_pos:8; 293a497a436SSimon Ho } r; 294a497a436SSimon Ho u32 ulval; 295a497a436SSimon Ho }; 296a497a436SSimon Ho 297a497a436SSimon Ho union cx2072x_reg_digital_bios_test2 { 298a497a436SSimon Ho struct { 299a497a436SSimon Ho u32 pull_down_eapd:2; 300a497a436SSimon Ho u32 input_en_eapd_pad:1; 301a497a436SSimon Ho u32 push_pull_mode:1; 302a497a436SSimon Ho u32 eapd_pad_output_driver:2; 303a497a436SSimon Ho u32 pll_source:1; 304a497a436SSimon Ho u32 i2s_bclk_en:1; 305a497a436SSimon Ho u32 i2s_bclk_invert:1; 306a497a436SSimon Ho u32 pll_ref_clock:1; 307a497a436SSimon Ho u32 class_d_shield_clk:1; 308a497a436SSimon Ho u32 audio_pll_bypass_mode:1; 309a497a436SSimon Ho u32 reserved:4; 310a497a436SSimon Ho } r; 311a497a436SSimon Ho u32 ulval; 312a497a436SSimon Ho }; 313a497a436SSimon Ho 314a497a436SSimon Ho #endif /* __CX2072X_H__ */ 315