1 /* 2 * ALSA SoC CS53L30 codec driver 3 * 4 * Copyright 2015 Cirrus Logic, Inc. 5 * 6 * Author: Paul Handrigan <Paul.Handrigan@cirrus.com>, 7 * Tim Howe <Tim.Howe@cirrus.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 */ 14 15 #ifndef __CS53L30_H__ 16 #define __CS53L30_H__ 17 18 /* I2C Registers */ 19 #define CS53L30_DEVID_AB 0x01 /* Device ID A & B [RO]. */ 20 #define CS53L30_DEVID_CD 0x02 /* Device ID C & D [RO]. */ 21 #define CS53L30_DEVID_E 0x03 /* Device ID E [RO]. */ 22 #define CS53L30_REVID 0x05 /* Revision ID [RO]. */ 23 #define CS53L30_PWRCTL 0x06 /* Power Control. */ 24 #define CS53L30_MCLKCTL 0x07 /* MCLK Control. */ 25 #define CS53L30_INT_SR_CTL 0x08 /* Internal Sample Rate Control. */ 26 #define CS53L30_MICBIAS_CTL 0x0A /* Mic Bias Control. */ 27 #define CS53L30_ASPCFG_CTL 0x0C /* ASP Config Control. */ 28 #define CS53L30_ASP_CTL1 0x0D /* ASP1 Control. */ 29 #define CS53L30_ASP_TDMTX_CTL1 0x0E /* ASP1 TDM TX Control 1 */ 30 #define CS53L30_ASP_TDMTX_CTL2 0x0F /* ASP1 TDM TX Control 2 */ 31 #define CS53L30_ASP_TDMTX_CTL3 0x10 /* ASP1 TDM TX Control 3 */ 32 #define CS53L30_ASP_TDMTX_CTL4 0x11 /* ASP1 TDM TX Control 4 */ 33 #define CS53L30_ASP_TDMTX_EN1 0x12 /* ASP1 TDM TX Enable 1 */ 34 #define CS53L30_ASP_TDMTX_EN2 0x13 /* ASP1 TDM TX Enable 2 */ 35 #define CS53L30_ASP_TDMTX_EN3 0x14 /* ASP1 TDM TX Enable 3 */ 36 #define CS53L30_ASP_TDMTX_EN4 0x15 /* ASP1 TDM TX Enable 4 */ 37 #define CS53L30_ASP_TDMTX_EN5 0x16 /* ASP1 TDM TX Enable 5 */ 38 #define CS53L30_ASP_TDMTX_EN6 0x17 /* ASP1 TDM TX Enable 6 */ 39 #define CS53L30_ASP_CTL2 0x18 /* ASP2 Control. */ 40 #define CS53L30_SFT_RAMP 0x1A /* Soft Ramp Control. */ 41 #define CS53L30_LRCK_CTL1 0x1B /* LRCK Control 1. */ 42 #define CS53L30_LRCK_CTL2 0x1C /* LRCK Control 2. */ 43 #define CS53L30_MUTEP_CTL1 0x1F /* Mute Pin Control 1. */ 44 #define CS53L30_MUTEP_CTL2 0x20 /* Mute Pin Control 2. */ 45 #define CS53L30_INBIAS_CTL1 0x21 /* Input Bias Control 1. */ 46 #define CS53L30_INBIAS_CTL2 0x22 /* Input Bias Control 2. */ 47 #define CS53L30_DMIC1_STR_CTL 0x23 /* DMIC1 Stereo Control. */ 48 #define CS53L30_DMIC2_STR_CTL 0x24 /* DMIC2 Stereo Control. */ 49 #define CS53L30_ADCDMIC1_CTL1 0x25 /* ADC1/DMIC1 Control 1. */ 50 #define CS53L30_ADCDMIC1_CTL2 0x26 /* ADC1/DMIC1 Control 2. */ 51 #define CS53L30_ADC1_CTL3 0x27 /* ADC1 Control 3. */ 52 #define CS53L30_ADC1_NG_CTL 0x28 /* ADC1 Noise Gate Control. */ 53 #define CS53L30_ADC1A_AFE_CTL 0x29 /* ADC1A AFE Control. */ 54 #define CS53L30_ADC1B_AFE_CTL 0x2A /* ADC1B AFE Control. */ 55 #define CS53L30_ADC1A_DIG_VOL 0x2B /* ADC1A Digital Volume. */ 56 #define CS53L30_ADC1B_DIG_VOL 0x2C /* ADC1B Digital Volume. */ 57 #define CS53L30_ADCDMIC2_CTL1 0x2D /* ADC2/DMIC2 Control 1. */ 58 #define CS53L30_ADCDMIC2_CTL2 0x2E /* ADC2/DMIC2 Control 2. */ 59 #define CS53L30_ADC2_CTL3 0x2F /* ADC2 Control 3. */ 60 #define CS53L30_ADC2_NG_CTL 0x30 /* ADC2 Noise Gate Control. */ 61 #define CS53L30_ADC2A_AFE_CTL 0x31 /* ADC2A AFE Control. */ 62 #define CS53L30_ADC2B_AFE_CTL 0x32 /* ADC2B AFE Control. */ 63 #define CS53L30_ADC2A_DIG_VOL 0x33 /* ADC2A Digital Volume. */ 64 #define CS53L30_ADC2B_DIG_VOL 0x34 /* ADC2B Digital Volume. */ 65 #define CS53L30_INT_MASK 0x35 /* Interrupt Mask. */ 66 #define CS53L30_IS 0x36 /* Interrupt Status. */ 67 #define CS53L30_MAX_REGISTER 0x36 68 69 #define CS53L30_TDM_SLOT_MAX 4 70 #define CS53L30_ASP_TDMTX_CTL(x) (CS53L30_ASP_TDMTX_CTL1 + (x)) 71 /* x : index for registers; n : index for slot; 8 slots per register */ 72 #define CS53L30_ASP_TDMTX_ENx(x) (CS53L30_ASP_TDMTX_EN6 - (x)) 73 #define CS53L30_ASP_TDMTX_ENn(n) CS53L30_ASP_TDMTX_ENx((n) >> 3) 74 #define CS53L30_ASP_TDMTX_ENx_MAX 6 75 76 /* Device ID */ 77 #define CS53L30_DEVID 0x53A30 78 79 /* PDN_DONE Poll Maximum 80 * If soft ramp is set it will take much longer to power down 81 * the system. 82 */ 83 #define CS53L30_PDN_POLL_MAX 90 84 85 /* Bitfield Definitions */ 86 87 /* R6 (0x06) CS53L30_PWRCTL - Power Control */ 88 #define CS53L30_PDN_ULP_SHIFT 7 89 #define CS53L30_PDN_ULP_MASK (1 << CS53L30_PDN_ULP_SHIFT) 90 #define CS53L30_PDN_ULP (1 << CS53L30_PDN_ULP_SHIFT) 91 #define CS53L30_PDN_LP_SHIFT 6 92 #define CS53L30_PDN_LP_MASK (1 << CS53L30_PDN_LP_SHIFT) 93 #define CS53L30_PDN_LP (1 << CS53L30_PDN_LP_SHIFT) 94 #define CS53L30_DISCHARGE_FILT_SHIFT 5 95 #define CS53L30_DISCHARGE_FILT_MASK (1 << CS53L30_DISCHARGE_FILT_SHIFT) 96 #define CS53L30_DISCHARGE_FILT (1 << CS53L30_DISCHARGE_FILT_SHIFT) 97 #define CS53L30_THMS_PDN_SHIFT 4 98 #define CS53L30_THMS_PDN_MASK (1 << CS53L30_THMS_PDN_SHIFT) 99 #define CS53L30_THMS_PDN (1 << CS53L30_THMS_PDN_SHIFT) 100 101 #define CS53L30_PWRCTL_DEFAULT (CS53L30_THMS_PDN) 102 103 /* R7 (0x07) CS53L30_MCLKCTL - MCLK Control */ 104 #define CS53L30_MCLK_DIS_SHIFT 7 105 #define CS53L30_MCLK_DIS_MASK (1 << CS53L30_MCLK_DIS_SHIFT) 106 #define CS53L30_MCLK_DIS (1 << CS53L30_MCLK_DIS_SHIFT) 107 #define CS53L30_MCLK_INT_SCALE_SHIFT 6 108 #define CS53L30_MCLK_INT_SCALE_MASK (1 << CS53L30_MCLK_INT_SCALE_SHIFT) 109 #define CS53L30_MCLK_INT_SCALE (1 << CS53L30_MCLK_INT_SCALE_SHIFT) 110 #define CS53L30_DMIC_DRIVE_SHIFT 5 111 #define CS53L30_DMIC_DRIVE_MASK (1 << CS53L30_DMIC_DRIVE_SHIFT) 112 #define CS53L30_DMIC_DRIVE (1 << CS53L30_DMIC_DRIVE_SHIFT) 113 #define CS53L30_MCLK_DIV_SHIFT 2 114 #define CS53L30_MCLK_DIV_WIDTH 2 115 #define CS53L30_MCLK_DIV_MASK (((1 << CS53L30_MCLK_DIV_WIDTH) - 1) << CS53L30_MCLK_DIV_SHIFT) 116 #define CS53L30_MCLK_DIV_BY_1 (0x0 << CS53L30_MCLK_DIV_SHIFT) 117 #define CS53L30_MCLK_DIV_BY_2 (0x1 << CS53L30_MCLK_DIV_SHIFT) 118 #define CS53L30_MCLK_DIV_BY_3 (0x2 << CS53L30_MCLK_DIV_SHIFT) 119 #define CS53L30_SYNC_EN_SHIFT 1 120 #define CS53L30_SYNC_EN_MASK (1 << CS53L30_SYNC_EN_SHIFT) 121 #define CS53L30_SYNC_EN (1 << CS53L30_SYNC_EN_SHIFT) 122 123 #define CS53L30_MCLKCTL_DEFAULT (CS53L30_MCLK_DIV_BY_2) 124 125 /* R8 (0x08) CS53L30_INT_SR_CTL - Internal Sample Rate Control */ 126 #define CS53L30_INTRNL_FS_RATIO_SHIFT 4 127 #define CS53L30_INTRNL_FS_RATIO_MASK (1 << CS53L30_INTRNL_FS_RATIO_SHIFT) 128 #define CS53L30_INTRNL_FS_RATIO (1 << CS53L30_INTRNL_FS_RATIO_SHIFT) 129 #define CS53L30_MCLK_19MHZ_EN_SHIFT 0 130 #define CS53L30_MCLK_19MHZ_EN_MASK (1 << CS53L30_MCLK_19MHZ_EN_SHIFT) 131 #define CS53L30_MCLK_19MHZ_EN (1 << CS53L30_MCLK_19MHZ_EN_SHIFT) 132 133 /* 0x6 << 1 is reserved bits */ 134 #define CS53L30_INT_SR_CTL_DEFAULT (CS53L30_INTRNL_FS_RATIO | 0x6 << 1) 135 136 /* R10 (0x0A) CS53L30_MICBIAS_CTL - Mic Bias Control */ 137 #define CS53L30_MIC4_BIAS_PDN_SHIFT 7 138 #define CS53L30_MIC4_BIAS_PDN_MASK (1 << CS53L30_MIC4_BIAS_PDN_SHIFT) 139 #define CS53L30_MIC4_BIAS_PDN (1 << CS53L30_MIC4_BIAS_PDN_SHIFT) 140 #define CS53L30_MIC3_BIAS_PDN_SHIFT 6 141 #define CS53L30_MIC3_BIAS_PDN_MASK (1 << CS53L30_MIC3_BIAS_PDN_SHIFT) 142 #define CS53L30_MIC3_BIAS_PDN (1 << CS53L30_MIC3_BIAS_PDN_SHIFT) 143 #define CS53L30_MIC2_BIAS_PDN_SHIFT 5 144 #define CS53L30_MIC2_BIAS_PDN_MASK (1 << CS53L30_MIC2_BIAS_PDN_SHIFT) 145 #define CS53L30_MIC2_BIAS_PDN (1 << CS53L30_MIC2_BIAS_PDN_SHIFT) 146 #define CS53L30_MIC1_BIAS_PDN_SHIFT 4 147 #define CS53L30_MIC1_BIAS_PDN_MASK (1 << CS53L30_MIC1_BIAS_PDN_SHIFT) 148 #define CS53L30_MIC1_BIAS_PDN (1 << CS53L30_MIC1_BIAS_PDN_SHIFT) 149 #define CS53L30_MICx_BIAS_PDN (0xf << CS53L30_MIC1_BIAS_PDN_SHIFT) 150 #define CS53L30_VP_MIN_SHIFT 2 151 #define CS53L30_VP_MIN_MASK (1 << CS53L30_VP_MIN_SHIFT) 152 #define CS53L30_VP_MIN (1 << CS53L30_VP_MIN_SHIFT) 153 #define CS53L30_MIC_BIAS_CTRL_SHIFT 0 154 #define CS53L30_MIC_BIAS_CTRL_WIDTH 2 155 #define CS53L30_MIC_BIAS_CTRL_MASK (((1 << CS53L30_MIC_BIAS_CTRL_WIDTH) - 1) << CS53L30_MIC_BIAS_CTRL_SHIFT) 156 #define CS53L30_MIC_BIAS_CTRL_HIZ (0 << CS53L30_MIC_BIAS_CTRL_SHIFT) 157 #define CS53L30_MIC_BIAS_CTRL_1V8 (1 << CS53L30_MIC_BIAS_CTRL_SHIFT) 158 #define CS53L30_MIC_BIAS_CTRL_2V75 (2 << CS53L30_MIC_BIAS_CTRL_SHIFT) 159 160 #define CS53L30_MICBIAS_CTL_DEFAULT (CS53L30_MICx_BIAS_PDN | CS53L30_VP_MIN) 161 162 /* R12 (0x0C) CS53L30_ASPCFG_CTL - ASP Configuration Control */ 163 #define CS53L30_ASP_MS_SHIFT 7 164 #define CS53L30_ASP_MS_MASK (1 << CS53L30_ASP_MS_SHIFT) 165 #define CS53L30_ASP_MS (1 << CS53L30_ASP_MS_SHIFT) 166 #define CS53L30_ASP_SCLK_INV_SHIFT 4 167 #define CS53L30_ASP_SCLK_INV_MASK (1 << CS53L30_ASP_SCLK_INV_SHIFT) 168 #define CS53L30_ASP_SCLK_INV (1 << CS53L30_ASP_SCLK_INV_SHIFT) 169 #define CS53L30_ASP_RATE_SHIFT 0 170 #define CS53L30_ASP_RATE_WIDTH 4 171 #define CS53L30_ASP_RATE_MASK (((1 << CS53L30_ASP_RATE_WIDTH) - 1) << CS53L30_ASP_RATE_SHIFT) 172 #define CS53L30_ASP_RATE_48K (0xc << CS53L30_ASP_RATE_SHIFT) 173 174 #define CS53L30_ASPCFG_CTL_DEFAULT (CS53L30_ASP_RATE_48K) 175 176 /* R13/R24 (0x0D/0x18) CS53L30_ASP_CTL1 & CS53L30_ASP_CTL2 - ASP Control 1~2 */ 177 #define CS53L30_ASP_TDM_PDN_SHIFT 7 178 #define CS53L30_ASP_TDM_PDN_MASK (1 << CS53L30_ASP_TDM_PDN_SHIFT) 179 #define CS53L30_ASP_TDM_PDN (1 << CS53L30_ASP_TDM_PDN_SHIFT) 180 #define CS53L30_ASP_SDOUTx_PDN_SHIFT 6 181 #define CS53L30_ASP_SDOUTx_PDN_MASK (1 << CS53L30_ASP_SDOUTx_PDN_SHIFT) 182 #define CS53L30_ASP_SDOUTx_PDN (1 << CS53L30_ASP_SDOUTx_PDN_SHIFT) 183 #define CS53L30_ASP_3ST_SHIFT 5 184 #define CS53L30_ASP_3ST_MASK (1 << CS53L30_ASP_3ST_SHIFT) 185 #define CS53L30_ASP_3ST (1 << CS53L30_ASP_3ST_SHIFT) 186 #define CS53L30_SHIFT_LEFT_SHIFT 4 187 #define CS53L30_SHIFT_LEFT_MASK (1 << CS53L30_SHIFT_LEFT_SHIFT) 188 #define CS53L30_SHIFT_LEFT (1 << CS53L30_SHIFT_LEFT_SHIFT) 189 #define CS53L30_ASP_SDOUTx_DRIVE_SHIFT 0 190 #define CS53L30_ASP_SDOUTx_DRIVE_MASK (1 << CS53L30_ASP_SDOUTx_DRIVE_SHIFT) 191 #define CS53L30_ASP_SDOUTx_DRIVE (1 << CS53L30_ASP_SDOUTx_DRIVE_SHIFT) 192 193 #define CS53L30_ASP_CTL1_DEFAULT (CS53L30_ASP_TDM_PDN) 194 #define CS53L30_ASP_CTL2_DEFAULT (0) 195 196 /* R14 (0x0E) ~ R17 (0x11) CS53L30_ASP_TDMTX_CTLx - ASP TDM TX Control 1~4 */ 197 #define CS53L30_ASP_CHx_TX_STATE_SHIFT 7 198 #define CS53L30_ASP_CHx_TX_STATE_MASK (1 << CS53L30_ASP_CHx_TX_STATE_SHIFT) 199 #define CS53L30_ASP_CHx_TX_STATE (1 << CS53L30_ASP_CHx_TX_STATE_SHIFT) 200 #define CS53L30_ASP_CHx_TX_LOC_SHIFT 0 201 #define CS53L30_ASP_CHx_TX_LOC_WIDTH 6 202 #define CS53L30_ASP_CHx_TX_LOC_MASK (((1 << CS53L30_ASP_CHx_TX_LOC_WIDTH) - 1) << CS53L30_ASP_CHx_TX_LOC_SHIFT) 203 #define CS53L30_ASP_CHx_TX_LOC_MAX (47 << CS53L30_ASP_CHx_TX_LOC_SHIFT) 204 #define CS53L30_ASP_CHx_TX_LOC(x) ((x) << CS53L30_ASP_CHx_TX_LOC_SHIFT) 205 206 #define CS53L30_ASP_TDMTX_CTLx_DEFAULT (CS53L30_ASP_CHx_TX_LOC_MAX) 207 208 /* R18 (0x12) ~ R23 (0x17) CS53L30_ASP_TDMTX_ENx - ASP TDM TX Enable 1~6 */ 209 #define CS53L30_ASP_TDMTX_ENx_DEFAULT (0) 210 211 /* R26 (0x1A) CS53L30_SFT_RAMP - Soft Ramp Control */ 212 #define CS53L30_DIGSFT_SHIFT 5 213 #define CS53L30_DIGSFT_MASK (1 << CS53L30_DIGSFT_SHIFT) 214 #define CS53L30_DIGSFT (1 << CS53L30_DIGSFT_SHIFT) 215 216 #define CS53L30_SFT_RMP_DEFAULT (0) 217 218 /* R28 (0x1C) CS53L30_LRCK_CTL2 - LRCK Control 2 */ 219 #define CS53L30_LRCK_50_NPW_SHIFT 3 220 #define CS53L30_LRCK_50_NPW_MASK (1 << CS53L30_LRCK_50_NPW_SHIFT) 221 #define CS53L30_LRCK_50_NPW (1 << CS53L30_LRCK_50_NPW_SHIFT) 222 #define CS53L30_LRCK_TPWH_SHIFT 0 223 #define CS53L30_LRCK_TPWH_WIDTH 3 224 #define CS53L30_LRCK_TPWH_MASK (((1 << CS53L30_LRCK_TPWH_WIDTH) - 1) << CS53L30_LRCK_TPWH_SHIFT) 225 #define CS53L30_LRCK_TPWH(x) (((x) << CS53L30_LRCK_TPWH_SHIFT) & CS53L30_LRCK_TPWH_MASK) 226 227 #define CS53L30_LRCK_CTLx_DEFAULT (0) 228 229 /* R31 (0x1F) CS53L30_MUTEP_CTL1 - MUTE Pin Control 1 */ 230 #define CS53L30_MUTE_PDN_ULP_SHIFT 7 231 #define CS53L30_MUTE_PDN_ULP_MASK (1 << CS53L30_MUTE_PDN_ULP_SHIFT) 232 #define CS53L30_MUTE_PDN_ULP (1 << CS53L30_MUTE_PDN_ULP_SHIFT) 233 #define CS53L30_MUTE_PDN_LP_SHIFT 6 234 #define CS53L30_MUTE_PDN_LP_MASK (1 << CS53L30_MUTE_PDN_LP_SHIFT) 235 #define CS53L30_MUTE_PDN_LP (1 << CS53L30_MUTE_PDN_LP_SHIFT) 236 #define CS53L30_MUTE_M4B_PDN_SHIFT 4 237 #define CS53L30_MUTE_M4B_PDN_MASK (1 << CS53L30_MUTE_M4B_PDN_SHIFT) 238 #define CS53L30_MUTE_M4B_PDN (1 << CS53L30_MUTE_M4B_PDN_SHIFT) 239 #define CS53L30_MUTE_M3B_PDN_SHIFT 3 240 #define CS53L30_MUTE_M3B_PDN_MASK (1 << CS53L30_MUTE_M3B_PDN_SHIFT) 241 #define CS53L30_MUTE_M3B_PDN (1 << CS53L30_MUTE_M3B_PDN_SHIFT) 242 #define CS53L30_MUTE_M2B_PDN_SHIFT 2 243 #define CS53L30_MUTE_M2B_PDN_MASK (1 << CS53L30_MUTE_M2B_PDN_SHIFT) 244 #define CS53L30_MUTE_M2B_PDN (1 << CS53L30_MUTE_M2B_PDN_SHIFT) 245 #define CS53L30_MUTE_M1B_PDN_SHIFT 1 246 #define CS53L30_MUTE_M1B_PDN_MASK (1 << CS53L30_MUTE_M1B_PDN_SHIFT) 247 #define CS53L30_MUTE_M1B_PDN (1 << CS53L30_MUTE_M1B_PDN_SHIFT) 248 /* Note: be careful - x starts from 0 */ 249 #define CS53L30_MUTE_MxB_PDN_SHIFT(x) (CS53L30_MUTE_M1B_PDN_SHIFT + (x)) 250 #define CS53L30_MUTE_MxB_PDN_MASK(x) (1 << CS53L30_MUTE_MxB_PDN_SHIFT(x)) 251 #define CS53L30_MUTE_MxB_PDN(x) (1 << CS53L30_MUTE_MxB_PDN_SHIFT(x)) 252 #define CS53L30_MUTE_MB_ALL_PDN_SHIFT 0 253 #define CS53L30_MUTE_MB_ALL_PDN_MASK (1 << CS53L30_MUTE_MB_ALL_PDN_SHIFT) 254 #define CS53L30_MUTE_MB_ALL_PDN (1 << CS53L30_MUTE_MB_ALL_PDN_SHIFT) 255 256 #define CS53L30_MUTEP_CTL1_MUTEALL (0xdf) 257 #define CS53L30_MUTEP_CTL1_DEFAULT (0) 258 259 /* R32 (0x20) CS53L30_MUTEP_CTL2 - MUTE Pin Control 2 */ 260 #define CS53L30_MUTE_PIN_POLARITY_SHIFT 7 261 #define CS53L30_MUTE_PIN_POLARITY_MASK (1 << CS53L30_MUTE_PIN_POLARITY_SHIFT) 262 #define CS53L30_MUTE_PIN_POLARITY (1 << CS53L30_MUTE_PIN_POLARITY_SHIFT) 263 #define CS53L30_MUTE_ASP_TDM_PDN_SHIFT 6 264 #define CS53L30_MUTE_ASP_TDM_PDN_MASK (1 << CS53L30_MUTE_ASP_TDM_PDN_SHIFT) 265 #define CS53L30_MUTE_ASP_TDM_PDN (1 << CS53L30_MUTE_ASP_TDM_PDN_SHIFT) 266 #define CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT 5 267 #define CS53L30_MUTE_ASP_SDOUT2_PDN_MASK (1 << CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT) 268 #define CS53L30_MUTE_ASP_SDOUT2_PDN (1 << CS53L30_MUTE_ASP_SDOUT2_PDN_SHIFT) 269 #define CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT 4 270 #define CS53L30_MUTE_ASP_SDOUT1_PDN_MASK (1 << CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT) 271 #define CS53L30_MUTE_ASP_SDOUT1_PDN (1 << CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT) 272 /* Note: be careful - x starts from 0 */ 273 #define CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x) ((x) + CS53L30_MUTE_ASP_SDOUT1_PDN_SHIFT) 274 #define CS53L30_MUTE_ASP_SDOUTx_PDN_MASK(x) (1 << CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x)) 275 #define CS53L30_MUTE_ASP_SDOUTx_PDN (1 << CS53L30_MUTE_ASP_SDOUTx_PDN_SHIFT(x)) 276 #define CS53L30_MUTE_ADC2B_PDN_SHIFT 3 277 #define CS53L30_MUTE_ADC2B_PDN_MASK (1 << CS53L30_MUTE_ADC2B_PDN_SHIFT) 278 #define CS53L30_MUTE_ADC2B_PDN (1 << CS53L30_MUTE_ADC2B_PDN_SHIFT) 279 #define CS53L30_MUTE_ADC2A_PDN_SHIFT 2 280 #define CS53L30_MUTE_ADC2A_PDN_MASK (1 << CS53L30_MUTE_ADC2A_PDN_SHIFT) 281 #define CS53L30_MUTE_ADC2A_PDN (1 << CS53L30_MUTE_ADC2A_PDN_SHIFT) 282 #define CS53L30_MUTE_ADC1B_PDN_SHIFT 1 283 #define CS53L30_MUTE_ADC1B_PDN_MASK (1 << CS53L30_MUTE_ADC1B_PDN_SHIFT) 284 #define CS53L30_MUTE_ADC1B_PDN (1 << CS53L30_MUTE_ADC1B_PDN_SHIFT) 285 #define CS53L30_MUTE_ADC1A_PDN_SHIFT 0 286 #define CS53L30_MUTE_ADC1A_PDN_MASK (1 << CS53L30_MUTE_ADC1A_PDN_SHIFT) 287 #define CS53L30_MUTE_ADC1A_PDN (1 << CS53L30_MUTE_ADC1A_PDN_SHIFT) 288 289 #define CS53L30_MUTEP_CTL2_DEFAULT (CS53L30_MUTE_PIN_POLARITY) 290 291 /* R33 (0x21) CS53L30_INBIAS_CTL1 - Input Bias Control 1 */ 292 #define CS53L30_IN4M_BIAS_SHIFT 6 293 #define CS53L30_IN4M_BIAS_WIDTH 2 294 #define CS53L30_IN4M_BIAS_MASK (((1 << CS53L30_IN4M_BIAS_WIDTH) - 1) << CS53L30_IN4M_BIAS_SHIFT) 295 #define CS53L30_IN4M_BIAS_OPEN (0 << CS53L30_IN4M_BIAS_SHIFT) 296 #define CS53L30_IN4M_BIAS_PULL_DOWN (1 << CS53L30_IN4M_BIAS_SHIFT) 297 #define CS53L30_IN4M_BIAS_VCM (2 << CS53L30_IN4M_BIAS_SHIFT) 298 #define CS53L30_IN4P_BIAS_SHIFT 4 299 #define CS53L30_IN4P_BIAS_WIDTH 2 300 #define CS53L30_IN4P_BIAS_MASK (((1 << CS53L30_IN4P_BIAS_WIDTH) - 1) << CS53L30_IN4P_BIAS_SHIFT) 301 #define CS53L30_IN4P_BIAS_OPEN (0 << CS53L30_IN4P_BIAS_SHIFT) 302 #define CS53L30_IN4P_BIAS_PULL_DOWN (1 << CS53L30_IN4P_BIAS_SHIFT) 303 #define CS53L30_IN4P_BIAS_VCM (2 << CS53L30_IN4P_BIAS_SHIFT) 304 #define CS53L30_IN3M_BIAS_SHIFT 2 305 #define CS53L30_IN3M_BIAS_WIDTH 2 306 #define CS53L30_IN3M_BIAS_MASK (((1 << CS53L30_IN3M_BIAS_WIDTH) - 1) << CS53L30_IN4M_BIAS_SHIFT) 307 #define CS53L30_IN3M_BIAS_OPEN (0 << CS53L30_IN3M_BIAS_SHIFT) 308 #define CS53L30_IN3M_BIAS_PULL_DOWN (1 << CS53L30_IN3M_BIAS_SHIFT) 309 #define CS53L30_IN3M_BIAS_VCM (2 << CS53L30_IN3M_BIAS_SHIFT) 310 #define CS53L30_IN3P_BIAS_SHIFT 0 311 #define CS53L30_IN3P_BIAS_WIDTH 2 312 #define CS53L30_IN3P_BIAS_MASK (((1 << CS53L30_IN3P_BIAS_WIDTH) - 1) << CS53L30_IN3P_BIAS_SHIFT) 313 #define CS53L30_IN3P_BIAS_OPEN (0 << CS53L30_IN3P_BIAS_SHIFT) 314 #define CS53L30_IN3P_BIAS_PULL_DOWN (1 << CS53L30_IN3P_BIAS_SHIFT) 315 #define CS53L30_IN3P_BIAS_VCM (2 << CS53L30_IN3P_BIAS_SHIFT) 316 317 #define CS53L30_INBIAS_CTL1_DEFAULT (CS53L30_IN4M_BIAS_VCM | CS53L30_IN4P_BIAS_VCM |\ 318 CS53L30_IN3M_BIAS_VCM | CS53L30_IN3P_BIAS_VCM) 319 320 /* R34 (0x22) CS53L30_INBIAS_CTL2 - Input Bias Control 2 */ 321 #define CS53L30_IN2M_BIAS_SHIFT 6 322 #define CS53L30_IN2M_BIAS_WIDTH 2 323 #define CS53L30_IN2M_BIAS_MASK (((1 << CS53L30_IN2M_BIAS_WIDTH) - 1) << CS53L30_IN2M_BIAS_SHIFT) 324 #define CS53L30_IN2M_BIAS_OPEN (0 << CS53L30_IN2M_BIAS_SHIFT) 325 #define CS53L30_IN2M_BIAS_PULL_DOWN (1 << CS53L30_IN2M_BIAS_SHIFT) 326 #define CS53L30_IN2M_BIAS_VCM (2 << CS53L30_IN2M_BIAS_SHIFT) 327 #define CS53L30_IN2P_BIAS_SHIFT 4 328 #define CS53L30_IN2P_BIAS_WIDTH 2 329 #define CS53L30_IN2P_BIAS_MASK (((1 << CS53L30_IN2P_BIAS_WIDTH) - 1) << CS53L30_IN2P_BIAS_SHIFT) 330 #define CS53L30_IN2P_BIAS_OPEN (0 << CS53L30_IN2P_BIAS_SHIFT) 331 #define CS53L30_IN2P_BIAS_PULL_DOWN (1 << CS53L30_IN2P_BIAS_SHIFT) 332 #define CS53L30_IN2P_BIAS_VCM (2 << CS53L30_IN2P_BIAS_SHIFT) 333 #define CS53L30_IN1M_BIAS_SHIFT 2 334 #define CS53L30_IN1M_BIAS_WIDTH 2 335 #define CS53L30_IN1M_BIAS_MASK (((1 << CS53L30_IN1M_BIAS_WIDTH) - 1) << CS53L30_IN1M_BIAS_SHIFT) 336 #define CS53L30_IN1M_BIAS_OPEN (0 << CS53L30_IN1M_BIAS_SHIFT) 337 #define CS53L30_IN1M_BIAS_PULL_DOWN (1 << CS53L30_IN1M_BIAS_SHIFT) 338 #define CS53L30_IN1M_BIAS_VCM (2 << CS53L30_IN1M_BIAS_SHIFT) 339 #define CS53L30_IN1P_BIAS_SHIFT 0 340 #define CS53L30_IN1P_BIAS_WIDTH 2 341 #define CS53L30_IN1P_BIAS_MASK (((1 << CS53L30_IN1P_BIAS_WIDTH) - 1) << CS53L30_IN1P_BIAS_SHIFT) 342 #define CS53L30_IN1P_BIAS_OPEN (0 << CS53L30_IN1P_BIAS_SHIFT) 343 #define CS53L30_IN1P_BIAS_PULL_DOWN (1 << CS53L30_IN1P_BIAS_SHIFT) 344 #define CS53L30_IN1P_BIAS_VCM (2 << CS53L30_IN1P_BIAS_SHIFT) 345 346 #define CS53L30_INBIAS_CTL2_DEFAULT (CS53L30_IN2M_BIAS_VCM | CS53L30_IN2P_BIAS_VCM |\ 347 CS53L30_IN1M_BIAS_VCM | CS53L30_IN1P_BIAS_VCM) 348 349 /* R35 (0x23) & R36 (0x24) CS53L30_DMICx_STR_CTL - DMIC1 & DMIC2 Stereo Control */ 350 #define CS53L30_DMICx_STEREO_ENB_SHIFT 5 351 #define CS53L30_DMICx_STEREO_ENB_MASK (1 << CS53L30_DMICx_STEREO_ENB_SHIFT) 352 #define CS53L30_DMICx_STEREO_ENB (1 << CS53L30_DMICx_STEREO_ENB_SHIFT) 353 354 /* 0x88 and 0xCC are reserved bits */ 355 #define CS53L30_DMIC1_STR_CTL_DEFAULT (CS53L30_DMICx_STEREO_ENB | 0x88) 356 #define CS53L30_DMIC2_STR_CTL_DEFAULT (CS53L30_DMICx_STEREO_ENB | 0xCC) 357 358 /* R37/R45 (0x25/0x2D) CS53L30_ADCDMICx_CTL1 - ADC1/DMIC1 & ADC2/DMIC2 Control 1 */ 359 #define CS53L30_ADCxB_PDN_SHIFT 7 360 #define CS53L30_ADCxB_PDN_MASK (1 << CS53L30_ADCxB_PDN_SHIFT) 361 #define CS53L30_ADCxB_PDN (1 << CS53L30_ADCxB_PDN_SHIFT) 362 #define CS53L30_ADCxA_PDN_SHIFT 6 363 #define CS53L30_ADCxA_PDN_MASK (1 << CS53L30_ADCxA_PDN_SHIFT) 364 #define CS53L30_ADCxA_PDN (1 << CS53L30_ADCxA_PDN_SHIFT) 365 #define CS53L30_DMICx_PDN_SHIFT 2 366 #define CS53L30_DMICx_PDN_MASK (1 << CS53L30_DMICx_PDN_SHIFT) 367 #define CS53L30_DMICx_PDN (1 << CS53L30_DMICx_PDN_SHIFT) 368 #define CS53L30_DMICx_SCLK_DIV_SHIFT 1 369 #define CS53L30_DMICx_SCLK_DIV_MASK (1 << CS53L30_DMICx_SCLK_DIV_SHIFT) 370 #define CS53L30_DMICx_SCLK_DIV (1 << CS53L30_DMICx_SCLK_DIV_SHIFT) 371 #define CS53L30_CH_TYPE_SHIFT 0 372 #define CS53L30_CH_TYPE_MASK (1 << CS53L30_CH_TYPE_SHIFT) 373 #define CS53L30_CH_TYPE (1 << CS53L30_CH_TYPE_SHIFT) 374 375 #define CS53L30_ADCDMICx_PDN_MASK 0xFF 376 #define CS53L30_ADCDMICx_CTL1_DEFAULT (CS53L30_DMICx_PDN) 377 378 /* R38/R46 (0x26/0x2E) CS53L30_ADCDMICx_CTL2 - ADC1/DMIC1 & ADC2/DMIC2 Control 2 */ 379 #define CS53L30_ADCx_NOTCH_DIS_SHIFT 7 380 #define CS53L30_ADCx_NOTCH_DIS_MASK (1 << CS53L30_ADCx_NOTCH_DIS_SHIFT) 381 #define CS53L30_ADCx_NOTCH_DIS (1 << CS53L30_ADCx_NOTCH_DIS_SHIFT) 382 #define CS53L30_ADCxB_INV_SHIFT 5 383 #define CS53L30_ADCxB_INV_MASK (1 << CS53L30_ADCxB_INV_SHIFT) 384 #define CS53L30_ADCxB_INV (1 << CS53L30_ADCxB_INV_SHIFT) 385 #define CS53L30_ADCxA_INV_SHIFT 4 386 #define CS53L30_ADCxA_INV_MASK (1 << CS53L30_ADCxA_INV_SHIFT) 387 #define CS53L30_ADCxA_INV (1 << CS53L30_ADCxA_INV_SHIFT) 388 #define CS53L30_ADCxB_DIG_BOOST_SHIFT 1 389 #define CS53L30_ADCxB_DIG_BOOST_MASK (1 << CS53L30_ADCxB_DIG_BOOST_SHIFT) 390 #define CS53L30_ADCxB_DIG_BOOST (1 << CS53L30_ADCxB_DIG_BOOST_SHIFT) 391 #define CS53L30_ADCxA_DIG_BOOST_SHIFT 0 392 #define CS53L30_ADCxA_DIG_BOOST_MASK (1 << CS53L30_ADCxA_DIG_BOOST_SHIFT) 393 #define CS53L30_ADCxA_DIG_BOOST (1 << CS53L30_ADCxA_DIG_BOOST_SHIFT) 394 395 #define CS53L30_ADCDMIC1_CTL2_DEFAULT (0) 396 397 /* R39/R47 (0x27/0x2F) CS53L30_ADCx_CTL3 - ADC1/ADC2 Control 3 */ 398 #define CS53L30_ADCx_HPF_EN_SHIFT 3 399 #define CS53L30_ADCx_HPF_EN_MASK (1 << CS53L30_ADCx_HPF_EN_SHIFT) 400 #define CS53L30_ADCx_HPF_EN (1 << CS53L30_ADCx_HPF_EN_SHIFT) 401 #define CS53L30_ADCx_HPF_CF_SHIFT 1 402 #define CS53L30_ADCx_HPF_CF_WIDTH 2 403 #define CS53L30_ADCx_HPF_CF_MASK (((1 << CS53L30_ADCx_HPF_CF_WIDTH) - 1) << CS53L30_ADCx_HPF_CF_SHIFT) 404 #define CS53L30_ADCx_HPF_CF_1HZ86 (0 << CS53L30_ADCx_HPF_CF_SHIFT) 405 #define CS53L30_ADCx_HPF_CF_120HZ (1 << CS53L30_ADCx_HPF_CF_SHIFT) 406 #define CS53L30_ADCx_HPF_CF_235HZ (2 << CS53L30_ADCx_HPF_CF_SHIFT) 407 #define CS53L30_ADCx_HPF_CF_466HZ (3 << CS53L30_ADCx_HPF_CF_SHIFT) 408 #define CS53L30_ADCx_NG_ALL_SHIFT 0 409 #define CS53L30_ADCx_NG_ALL_MASK (1 << CS53L30_ADCx_NG_ALL_SHIFT) 410 #define CS53L30_ADCx_NG_ALL (1 << CS53L30_ADCx_NG_ALL_SHIFT) 411 412 #define CS53L30_ADCx_CTL3_DEFAULT (CS53L30_ADCx_HPF_EN) 413 414 /* R40/R48 (0x28/0x30) CS53L30_ADCx_NG_CTL - ADC1/ADC2 Noise Gate Control */ 415 #define CS53L30_ADCxB_NG_SHIFT 7 416 #define CS53L30_ADCxB_NG_MASK (1 << CS53L30_ADCxB_NG_SHIFT) 417 #define CS53L30_ADCxB_NG (1 << CS53L30_ADCxB_NG_SHIFT) 418 #define CS53L30_ADCxA_NG_SHIFT 6 419 #define CS53L30_ADCxA_NG_MASK (1 << CS53L30_ADCxA_NG_SHIFT) 420 #define CS53L30_ADCxA_NG (1 << CS53L30_ADCxA_NG_SHIFT) 421 #define CS53L30_ADCx_NG_BOOST_SHIFT 5 422 #define CS53L30_ADCx_NG_BOOST_MASK (1 << CS53L30_ADCx_NG_BOOST_SHIFT) 423 #define CS53L30_ADCx_NG_BOOST (1 << CS53L30_ADCx_NG_BOOST_SHIFT) 424 #define CS53L30_ADCx_NG_THRESH_SHIFT 2 425 #define CS53L30_ADCx_NG_THRESH_WIDTH 3 426 #define CS53L30_ADCx_NG_THRESH_MASK (((1 << CS53L30_ADCx_NG_THRESH_WIDTH) - 1) << CS53L30_ADCx_NG_THRESH_SHIFT) 427 #define CS53L30_ADCx_NG_DELAY_SHIFT 0 428 #define CS53L30_ADCx_NG_DELAY_WIDTH 2 429 #define CS53L30_ADCx_NG_DELAY_MASK (((1 << CS53L30_ADCx_NG_DELAY_WIDTH) - 1) << CS53L30_ADCx_NG_DELAY_SHIFT) 430 431 #define CS53L30_ADCx_NG_CTL_DEFAULT (0) 432 433 /* R41/R42/R49/R50 (0x29/0x2A/0x31/0x32) CS53L30_ADCxy_AFE_CTL - ADC1A/1B/2A/2B AFE Control */ 434 #define CS53L30_ADCxy_PREAMP_SHIFT 6 435 #define CS53L30_ADCxy_PREAMP_WIDTH 2 436 #define CS53L30_ADCxy_PREAMP_MASK (((1 << CS53L30_ADCxy_PREAMP_WIDTH) - 1) << CS53L30_ADCxy_PREAMP_SHIFT) 437 #define CS53L30_ADCxy_PGA_VOL_SHIFT 0 438 #define CS53L30_ADCxy_PGA_VOL_WIDTH 6 439 #define CS53L30_ADCxy_PGA_VOL_MASK (((1 << CS53L30_ADCxy_PGA_VOL_WIDTH) - 1) << CS53L30_ADCxy_PGA_VOL_SHIFT) 440 441 #define CS53L30_ADCxy_AFE_CTL_DEFAULT (0) 442 443 /* R43/R44/R51/R52 (0x2B/0x2C/0x33/0x34) CS53L30_ADCxy_DIG_VOL - ADC1A/1B/2A/2B Digital Volume */ 444 #define CS53L30_ADCxy_VOL_MUTE (0x80) 445 446 #define CS53L30_ADCxy_DIG_VOL_DEFAULT (0x0) 447 448 /* CS53L30_INT */ 449 #define CS53L30_PDN_DONE (1 << 7) 450 #define CS53L30_THMS_TRIP (1 << 6) 451 #define CS53L30_SYNC_DONE (1 << 5) 452 #define CS53L30_ADC2B_OVFL (1 << 4) 453 #define CS53L30_ADC2A_OVFL (1 << 3) 454 #define CS53L30_ADC1B_OVFL (1 << 2) 455 #define CS53L30_ADC1A_OVFL (1 << 1) 456 #define CS53L30_MUTE_PIN (1 << 0) 457 #define CS53L30_DEVICE_INT_MASK 0xFF 458 459 #endif /* __CS53L30_H__ */ 460